arch/x86/kernel/apic/summit_32.c

   1 /*
   2  * IBM Summit-Specific Code
   3  *
   4  * Written By: Matthew Dobson, IBM Corporation
   5  *
   6  * Copyright (c) 2003 IBM Corp.
   7  *
   8  * All rights reserved.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or (at
  13  * your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful, but
  16  * WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  18  * NON INFRINGEMENT.  See the GNU General Public License for more
  19  * details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  24  *
  25  * Send feedback to <colpatch@us.ibm.com>
  26  *
  27  */
  28
  29 #include <linux/mm.h>
  30 #include <linux/init.h>
  31 #include <asm/io.h>
  32 #include <asm/bios_ebda.h>
  33
  34 /*
  35  * APIC driver for the IBM "Summit" chipset.
  36  */
  37 #include <linux/threads.h>
  38 #include <linux/cpumask.h>
  39 #include <asm/mpspec.h>
  40 #include <asm/apic.h>
  41 #include <asm/smp.h>
  42 #include <asm/fixmap.h>
  43 #include <asm/apicdef.h>
  44 #include <asm/ipi.h>
  45 #include <linux/kernel.h>
  46 #include <linux/string.h>
  47 #include <linux/init.h>
  48 #include <linux/gfp.h>
  49 #include <linux/smp.h>
  50
  51 static inline unsigned summit_get_apic_id(unsigned long x)
  52 {
  53         return (x >> 24) & 0xFF;
  54 }
  55
  56 static inline void summit_send_IPI_mask(const cpumask_t *mask, int vector)
  57 {
  58         default_send_IPI_mask_sequence_logical(mask, vector);
  59 }
  60
  61 static inline void summit_send_IPI_allbutself(int vector)
  62 {
  63         cpumask_t mask = cpu_online_map;
  64         cpu_clear(smp_processor_id(), mask);
  65
  66         if (!cpus_empty(mask))
  67                 summit_send_IPI_mask(&mask, vector);
  68 }
  69
  70 static inline void summit_send_IPI_all(int vector)
  71 {
  72         summit_send_IPI_mask(&cpu_online_map, vector);
  73 }
  74
  75 #include <asm/tsc.h>
  76
  77 extern int use_cyclone;
  78
  79 #ifdef CONFIG_X86_SUMMIT_NUMA
  80 extern void setup_summit(void);
  81 #else
  82 #define setup_summit()  {}
  83 #endif
  84
  85 static inline int
  86 summit_mps_oem_check(struct mpc_table *mpc, char *oem, char *productid)
  87 {
  88         if (!strncmp(oem, "IBM ENSW", 8) &&
  89                         (!strncmp(productid, "VIGIL SMP", 9)
  90                          || !strncmp(productid, "EXA", 3)
  91                          || !strncmp(productid, "RUTHLESS SMP", 12))){
  92                 mark_tsc_unstable("Summit based system");
  93                 use_cyclone = 1; /*enable cyclone-timer*/
  94                 setup_summit();
  95                 return 1;
  96         }
  97         return 0;
  98 }
  99
 100 /* Hook from generic ACPI tables.c */
 101 static inline int summit_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
 102 {
 103         if (!strncmp(oem_id, "IBM", 3) &&
 104             (!strncmp(oem_table_id, "SERVIGIL", 8)
 105              || !strncmp(oem_table_id, "EXA", 3))){
 106                 mark_tsc_unstable("Summit based system");
 107                 use_cyclone = 1; /*enable cyclone-timer*/
 108                 setup_summit();
 109                 return 1;
 110         }
 111         return 0;
 112 }
 113
 114 struct rio_table_hdr {
 115         unsigned char version;      /* Version number of this data structure           */
 116                                     /* Version 3 adds chassis_num & WP_index           */
 117         unsigned char num_scal_dev; /* # of Scalability devices (Twisters for Vigil)   */
 118         unsigned char num_rio_dev;  /* # of RIO I/O devices (Cyclones and Winnipegs)   */
 119 } __attribute__((packed));
 120
 121 struct scal_detail {
 122         unsigned char node_id;      /* Scalability Node ID                             */
 123         unsigned long CBAR;         /* Address of 1MB register space                   */
 124         unsigned char port0node;    /* Node ID port connected to: 0xFF=None            */
 125         unsigned char port0port;    /* Port num port connected to: 0,1,2, or 0xFF=None */
 126         unsigned char port1node;    /* Node ID port connected to: 0xFF = None          */
 127         unsigned char port1port;    /* Port num port connected to: 0,1,2, or 0xFF=None */
 128         unsigned char port2node;    /* Node ID port connected to: 0xFF = None          */
 129         unsigned char port2port;    /* Port num port connected to: 0,1,2, or 0xFF=None */
 130         unsigned char chassis_num;  /* 1 based Chassis number (1 = boot node)          */
 131 } __attribute__((packed));
 132
 133 struct rio_detail {
 134         unsigned char node_id;      /* RIO Node ID                                     */
 135         unsigned long BBAR;         /* Address of 1MB register space                   */
 136         unsigned char type;         /* Type of device                                  */
 137         unsigned char owner_id;     /* For WPEG: Node ID of Cyclone that owns this WPEG*/
 138                                     /* For CYC:  Node ID of Twister that owns this CYC */
 139         unsigned char port0node;    /* Node ID port connected to: 0xFF=None            */
 140         unsigned char port0port;    /* Port num port connected to: 0,1,2, or 0xFF=None */
 141         unsigned char port1node;    /* Node ID port connected to: 0xFF=None            */
 142         unsigned char port1port;    /* Port num port connected to: 0,1,2, or 0xFF=None */
 143         unsigned char first_slot;   /* For WPEG: Lowest slot number below this WPEG    */
 144                                     /* For CYC:  0                                     */
 145         unsigned char status;       /* For WPEG: Bit 0 = 1 : the XAPIC is used         */
 146                                     /*                 = 0 : the XAPIC is not used, ie:*/
 147                                     /*                     ints fwded to another XAPIC */
 148                                     /*           Bits1:7 Reserved                      */
 149                                     /* For CYC:  Bits0:7 Reserved                      */
 150         unsigned char WP_index;     /* For WPEG: WPEG instance index - lower ones have */
 151                                     /*           lower slot numbers/PCI bus numbers    */
 152                                     /* For CYC:  No meaning                            */
 153         unsigned char chassis_num;  /* 1 based Chassis number                          */
 154                                     /* For LookOut WPEGs this field indicates the      */
 155                                     /* Expansion Chassis #, enumerated from Boot       */
 156                                     /* Node WPEG external port, then Boot Node CYC     */
 157                                     /* external port, then Next Vigil chassis WPEG     */
 158                                     /* external port, etc.                             */
 159                                     /* Shared Lookouts have only 1 chassis number (the */
 160                                     /* first one assigned)                             */
 161 } __attribute__((packed));
 162
 163
 164 typedef enum {
 165         CompatTwister = 0,  /* Compatibility Twister               */
 166         AltTwister    = 1,  /* Alternate Twister of internal 8-way */
 167         CompatCyclone = 2,  /* Compatibility Cyclone               */
 168         AltCyclone    = 3,  /* Alternate Cyclone of internal 8-way */
 169         CompatWPEG    = 4,  /* Compatibility WPEG                  */
 170         AltWPEG       = 5,  /* Second Planar WPEG                  */
 171         LookOutAWPEG  = 6,  /* LookOut WPEG                        */
 172         LookOutBWPEG  = 7,  /* LookOut WPEG                        */
 173 } node_type;
 174
 175 static inline int is_WPEG(struct rio_detail *rio){
 176         return (rio->type == CompatWPEG || rio->type == AltWPEG ||
 177                 rio->type == LookOutAWPEG || rio->type == LookOutBWPEG);
 178 }
 179
 180
 181 /* In clustered mode, the high nibble of APIC ID is a cluster number.
 182  * The low nibble is a 4-bit bitmap. */
 183 #define XAPIC_DEST_CPUS_SHIFT   4
 184 #define XAPIC_DEST_CPUS_MASK    ((1u << XAPIC_DEST_CPUS_SHIFT) - 1)
 185 #define XAPIC_DEST_CLUSTER_MASK (XAPIC_DEST_CPUS_MASK << XAPIC_DEST_CPUS_SHIFT)
 186
 187 #define SUMMIT_APIC_DFR_VALUE   (APIC_DFR_CLUSTER)
 188
 189 static inline const cpumask_t *summit_target_cpus(void)
 190 {
 191         /* CPU_MASK_ALL (0xff) has undefined behaviour with
 192          * dest_LowestPrio mode logical clustered apic interrupt routing
 193          * Just start on cpu 0.  IRQ balancing will spread load
 194          */
 195         return &cpumask_of_cpu(0);
 196 }
 197
 198 static inline unsigned long
 199 summit_check_apicid_used(physid_mask_t bitmap, int apicid)
 200 {
 201         return 0;
 202 }
 203
 204 /* we don't use the phys_cpu_present_map to indicate apicid presence */
 205 static inline unsigned long summit_check_apicid_present(int bit)
 206 {
 207         return 1;
 208 }
 209
 210 static inline void summit_init_apic_ldr(void)
 211 {
 212         unsigned long val, id;
 213         int count = 0;
 214         u8 my_id = (u8)hard_smp_processor_id();
 215         u8 my_cluster = APIC_CLUSTER(my_id);
 216 #ifdef CONFIG_SMP
 217         u8 lid;
 218         int i;
 219
 220         /* Create logical APIC IDs by counting CPUs already in cluster. */
 221         for (count = 0, i = nr_cpu_ids; --i >= 0; ) {
 222                 lid = cpu_2_logical_apicid[i];
 223                 if (lid != BAD_APICID && APIC_CLUSTER(lid) == my_cluster)
 224                         ++count;
 225         }
 226 #endif
 227         /* We only have a 4 wide bitmap in cluster mode.  If a deranged
 228          * BIOS puts 5 CPUs in one APIC cluster, we're hosed. */
 229         BUG_ON(count >= XAPIC_DEST_CPUS_SHIFT);
 230         id = my_cluster | (1UL << count);
 231         apic_write(APIC_DFR, SUMMIT_APIC_DFR_VALUE);
 232         val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
 233         val |= SET_APIC_LOGICAL_ID(id);
 234         apic_write(APIC_LDR, val);
 235 }
 236
 237 static inline int summit_apic_id_registered(void)
 238 {
 239         return 1;
 240 }
 241
 242 static inline void summit_setup_apic_routing(void)
 243 {
 244         printk("Enabling APIC mode:  Summit.  Using %d I/O APICs\n",
 245                                                 nr_ioapics);
 246 }
 247
 248 static inline int summit_apicid_to_node(int logical_apicid)
 249 {
 250 #ifdef CONFIG_SMP
 251         return apicid_2_node[hard_smp_processor_id()];
 252 #else
 253         return 0;
 254 #endif
 255 }
 256
 257 /* Mapping from cpu number to logical apicid */
 258 static inline int summit_cpu_to_logical_apicid(int cpu)
 259 {
 260 #ifdef CONFIG_SMP
 261         if (cpu >= nr_cpu_ids)
 262                 return BAD_APICID;
 263         return cpu_2_logical_apicid[cpu];
 264 #else
 265         return logical_smp_processor_id();
 266 #endif
 267 }
 268
 269 static inline int summit_cpu_present_to_apicid(int mps_cpu)
 270 {
 271         if (mps_cpu < nr_cpu_ids)
 272                 return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu);
 273         else
 274                 return BAD_APICID;
 275 }
 276
 277 static inline physid_mask_t
 278 summit_ioapic_phys_id_map(physid_mask_t phys_id_map)
 279 {
 280         /* For clustered we don't have a good way to do this yet - hack */
 281         return physids_promote(0x0F);
 282 }
 283
 284 static inline physid_mask_t summit_apicid_to_cpu_present(int apicid)
 285 {
 286         return physid_mask_of_physid(0);
 287 }
 288
 289 static inline void summit_setup_portio_remap(void)
 290 {
 291 }
 292
 293 static inline int summit_check_phys_apicid_present(int boot_cpu_physical_apicid)
 294 {
 295         return 1;
 296 }
 297
 298 static inline unsigned int summit_cpu_mask_to_apicid(const cpumask_t *cpumask)
 299 {
 300         int cpus_found = 0;
 301         int num_bits_set;
 302         int apicid;
 303         int cpu;
 304
 305         num_bits_set = cpus_weight(*cpumask);
 306         /* Return id to all */
 307         if (num_bits_set >= nr_cpu_ids)
 308                 return 0xFF;
 309         /*
 310          * The cpus in the mask must all be on the apic cluster.  If are not
 311          * on the same apicid cluster return default value of target_cpus():
 312          */
 313         cpu = first_cpu(*cpumask);
 314         apicid = summit_cpu_to_logical_apicid(cpu);
 315
 316         while (cpus_found < num_bits_set) {
 317                 if (cpu_isset(cpu, *cpumask)) {
 318                         int new_apicid = summit_cpu_to_logical_apicid(cpu);
 319
 320                         if (APIC_CLUSTER(apicid) != APIC_CLUSTER(new_apicid)) {
 321                                 printk ("%s: Not a valid mask!\n", __func__);
 322
 323                                 return 0xFF;
 324                         }
 325                         apicid = apicid | new_apicid;
 326                         cpus_found++;
 327                 }
 328                 cpu++;
 329         }
 330         return apicid;
 331 }
 332
 333 static inline unsigned int
 334 summit_cpu_mask_to_apicid_and(const struct cpumask *inmask,
 335                               const struct cpumask *andmask)
 336 {
 337         int apicid = summit_cpu_to_logical_apicid(0);
 338         cpumask_var_t cpumask;
 339
 340         if (!alloc_cpumask_var(&cpumask, GFP_ATOMIC))
 341                 return apicid;
 342
 343         cpumask_and(cpumask, inmask, andmask);
 344         cpumask_and(cpumask, cpumask, cpu_online_mask);
 345         apicid = summit_cpu_mask_to_apicid(cpumask);
 346
 347         free_cpumask_var(cpumask);
 348
 349         return apicid;
 350 }
 351
 352 /*
 353  * cpuid returns the value latched in the HW at reset, not the APIC ID
 354  * register's value.  For any box whose BIOS changes APIC IDs, like
 355  * clustered APIC systems, we must use hard_smp_processor_id.
 356  *
 357  * See Intel's IA-32 SW Dev's Manual Vol2 under CPUID.
 358  */
 359 static inline int summit_phys_pkg_id(int cpuid_apic, int index_msb)
 360 {
 361         return hard_smp_processor_id() >> index_msb;
 362 }
 363
 364 static int probe_summit(void)
 365 {
 366         /* probed later in mptable/ACPI hooks */
 367         return 0;
 368 }
 369
 370 static void summit_vector_allocation_domain(int cpu, cpumask_t *retmask)
 371 {
 372         /* Careful. Some cpus do not strictly honor the set of cpus
 373          * specified in the interrupt destination when using lowest
 374          * priority interrupt delivery mode.
 375          *
 376          * In particular there was a hyperthreading cpu observed to
 377          * deliver interrupts to the wrong hyperthread when only one
 378          * hyperthread was specified in the interrupt desitination.
 379          */
 380         *retmask = (cpumask_t){ { [0] = APIC_ALL_CPUS, } };
 381 }
 382
 383 #ifdef CONFIG_X86_SUMMIT_NUMA
 384 static struct rio_table_hdr *rio_table_hdr __initdata;
 385 static struct scal_detail   *scal_devs[MAX_NUMNODES] __initdata;
 386 static struct rio_detail    *rio_devs[MAX_NUMNODES*4] __initdata;
 387
 388 #ifndef CONFIG_X86_NUMAQ
 389 static int mp_bus_id_to_node[MAX_MP_BUSSES] __initdata;
 390 #endif
 391
 392 static int __init setup_pci_node_map_for_wpeg(int wpeg_num, int last_bus)
 393 {
 394         int twister = 0, node = 0;
 395         int i, bus, num_buses;
 396
 397         for (i = 0; i < rio_table_hdr->num_rio_dev; i++) {
 398                 if (rio_devs[i]->node_id == rio_devs[wpeg_num]->owner_id) {
 399                         twister = rio_devs[i]->owner_id;
 400                         break;
 401                 }
 402         }
 403         if (i == rio_table_hdr->num_rio_dev) {
 404                 printk(KERN_ERR "%s: Couldn't find owner Cyclone for Winnipeg!\n", __func__);
 405                 return last_bus;
 406         }
 407
 408         for (i = 0; i < rio_table_hdr->num_scal_dev; i++) {
 409                 if (scal_devs[i]->node_id == twister) {
 410                         node = scal_devs[i]->node_id;
 411                         break;
 412                 }
 413         }
 414         if (i == rio_table_hdr->num_scal_dev) {
 415                 printk(KERN_ERR "%s: Couldn't find owner Twister for Cyclone!\n", __func__);
 416                 return last_bus;
 417         }
 418
 419         switch (rio_devs[wpeg_num]->type) {
 420         case CompatWPEG:
 421                 /*
 422                  * The Compatibility Winnipeg controls the 2 legacy buses,
 423                  * the 66MHz PCI bus [2 slots] and the 2 "extra" buses in case
 424                  * a PCI-PCI bridge card is used in either slot: total 5 buses.
 425                  */
 426                 num_buses = 5;
 427                 break;
 428         case AltWPEG:
 429                 /*
 430                  * The Alternate Winnipeg controls the 2 133MHz buses [1 slot
 431                  * each], their 2 "extra" buses, the 100MHz bus [2 slots] and
 432                  * the "extra" buses for each of those slots: total 7 buses.
 433                  */
 434                 num_buses = 7;
 435                 break;
 436         case LookOutAWPEG:
 437         case LookOutBWPEG:
 438                 /*
 439                  * A Lookout Winnipeg controls 3 100MHz buses [2 slots each]
 440                  * & the "extra" buses for each of those slots: total 9 buses.
 441                  */
 442                 num_buses = 9;
 443                 break;
 444         default:
 445                 printk(KERN_INFO "%s: Unsupported Winnipeg type!\n", __func__);
 446                 return last_bus;
 447         }
 448
 449         for (bus = last_bus; bus < last_bus + num_buses; bus++)
 450                 mp_bus_id_to_node[bus] = node;
 451         return bus;
 452 }
 453
 454 static int __init build_detail_arrays(void)
 455 {
 456         unsigned long ptr;
 457         int i, scal_detail_size, rio_detail_size;
 458
 459         if (rio_table_hdr->num_scal_dev > MAX_NUMNODES) {
 460                 printk(KERN_WARNING "%s: MAX_NUMNODES too low!  Defined as %d, but system has %d nodes.\n", __func__, MAX_NUMNODES, rio_table_hdr->num_scal_dev);
 461                 return 0;
 462         }
 463
 464         switch (rio_table_hdr->version) {
 465         default:
 466                 printk(KERN_WARNING "%s: Invalid Rio Grande Table Version: %d\n", __func__, rio_table_hdr->version);
 467                 return 0;
 468         case 2:
 469                 scal_detail_size = 11;
 470                 rio_detail_size = 13;
 471                 break;
 472         case 3:
 473                 scal_detail_size = 12;
 474                 rio_detail_size = 15;
 475                 break;
 476         }
 477
 478         ptr = (unsigned long)rio_table_hdr + 3;
 479         for (i = 0; i < rio_table_hdr->num_scal_dev; i++, ptr += scal_detail_size)
 480                 scal_devs[i] = (struct scal_detail *)ptr;
 481
 482         for (i = 0; i < rio_table_hdr->num_rio_dev; i++, ptr += rio_detail_size)
 483                 rio_devs[i] = (struct rio_detail *)ptr;
 484
 485         return 1;
 486 }
 487
 488 void __init setup_summit(void)
 489 {
 490         unsigned long           ptr;
 491         unsigned short          offset;
 492         int                     i, next_wpeg, next_bus = 0;
 493
 494         /* The pointer to the EBDA is stored in the word @ phys 0x40E(40:0E) */
 495         ptr = get_bios_ebda();
 496         ptr = (unsigned long)phys_to_virt(ptr);
 497
 498         rio_table_hdr = NULL;
 499         offset = 0x180;
 500         while (offset) {
 501                 /* The block id is stored in the 2nd word */
 502                 if (*((unsigned short *)(ptr + offset + 2)) == 0x4752) {
 503                         /* set the pointer past the offset & block id */
 504                         rio_table_hdr = (struct rio_table_hdr *)(ptr + offset + 4);
 505                         break;
 506                 }
 507                 /* The next offset is stored in the 1st word.  0 means no more */
 508                 offset = *((unsigned short *)(ptr + offset));
 509         }
 510         if (!rio_table_hdr) {
 511                 printk(KERN_ERR "%s: Unable to locate Rio Grande Table in EBDA - bailing!\n", __func__);
 512                 return;
 513         }
 514
 515         if (!build_detail_arrays())
 516                 return;
 517
 518         /* The first Winnipeg we're looking for has an index of 0 */
 519         next_wpeg = 0;
 520         do {
 521                 for (i = 0; i < rio_table_hdr->num_rio_dev; i++) {
 522                         if (is_WPEG(rio_devs[i]) && rio_devs[i]->WP_index == next_wpeg) {
 523                                 /* It's the Winnipeg we're looking for! */
 524                                 next_bus = setup_pci_node_map_for_wpeg(i, next_bus);
 525                                 next_wpeg++;
 526                                 break;
 527                         }
 528                 }
 529                 /*
 530                  * If we go through all Rio devices and don't find one with
 531                  * the next index, it means we've found all the Winnipegs,
 532                  * and thus all the PCI buses.
 533                  */
 534                 if (i == rio_table_hdr->num_rio_dev)
 535                         next_wpeg = 0;
 536         } while (next_wpeg != 0);
 537 }
 538 #endif
 539
 540 struct apic apic_summit = {
 541
 542         .name                           = "summit",
 543         .probe                          = probe_summit,
 544         .acpi_madt_oem_check            = summit_acpi_madt_oem_check,
 545         .apic_id_registered             = summit_apic_id_registered,
 546
 547         .irq_delivery_mode              = dest_LowestPrio,
 548         /* logical delivery broadcast to all CPUs: */
 549         .irq_dest_mode                  = 1,
 550
 551         .target_cpus                    = summit_target_cpus,
 552         .disable_esr                    = 1,
 553         .dest_logical                   = APIC_DEST_LOGICAL,
 554         .check_apicid_used              = summit_check_apicid_used,
 555         .check_apicid_present           = summit_check_apicid_present,
 556
 557         .vector_allocation_domain       = summit_vector_allocation_domain,
 558         .init_apic_ldr                  = summit_init_apic_ldr,
 559
 560         .ioapic_phys_id_map             = summit_ioapic_phys_id_map,
 561         .setup_apic_routing             = summit_setup_apic_routing,
 562         .multi_timer_check              = NULL,
 563         .apicid_to_node                 = summit_apicid_to_node,
 564         .cpu_to_logical_apicid          = summit_cpu_to_logical_apicid,
 565         .cpu_present_to_apicid          = summit_cpu_present_to_apicid,
 566         .apicid_to_cpu_present          = summit_apicid_to_cpu_present,
 567         .setup_portio_remap             = NULL,
 568         .check_phys_apicid_present      = summit_check_phys_apicid_present,
 569         .enable_apic_mode               = NULL,
 570         .phys_pkg_id                    = summit_phys_pkg_id,
 571         .mps_oem_check                  = summit_mps_oem_check,
 572
 573         .get_apic_id                    = summit_get_apic_id,
 574         .set_apic_id                    = NULL,
 575         .apic_id_mask                   = 0xFF << 24,
 576
 577         .cpu_mask_to_apicid             = summit_cpu_mask_to_apicid,
 578         .cpu_mask_to_apicid_and         = summit_cpu_mask_to_apicid_and,
 579
 580         .send_IPI_mask                  = summit_send_IPI_mask,
 581         .send_IPI_mask_allbutself       = NULL,
 582         .send_IPI_allbutself            = summit_send_IPI_allbutself,
 583         .send_IPI_all                   = summit_send_IPI_all,
 584         .send_IPI_self                  = default_send_IPI_self,
 585
 586         .wakeup_cpu                     = NULL,
 587         .trampoline_phys_low            = DEFAULT_TRAMPOLINE_PHYS_LOW,
 588         .trampoline_phys_high           = DEFAULT_TRAMPOLINE_PHYS_HIGH,
 589
 590         .wait_for_init_deassert         = default_wait_for_init_deassert,
 591
 592         .smp_callin_clear_local_apic    = NULL,
 593         .inquire_remote_apic            = default_inquire_remote_apic,
 594
 595         .read                           = native_apic_mem_read,
 596         .write                          = native_apic_mem_write,
 597         .icr_read                       = native_apic_icr_read,
 598         .icr_write                      = native_apic_icr_write,
 599         .wait_icr_idle                  = native_apic_wait_icr_idle,
 600         .safe_wait_icr_idle             = native_safe_apic_wait_icr_idle,
 601 };