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mm: fix dubious code in __count_immobile_pages()
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / r8169.c
blobef2133b16f8c615759506a2023f803cccd0bcfaf
1 /*
2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
9 */
10
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
21 #include <linux/in.h>
22 #include <linux/ip.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/firmware.h>
28
29 #include <asm/system.h>
30 #include <asm/io.h>
31 #include <asm/irq.h>
32
33 #define RTL8169_VERSION "2.3LK-NAPI"
34 #define MODULENAME "r8169"
35 #define PFX MODULENAME ": "
36
37 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
38 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
39
40 #ifdef RTL8169_DEBUG
41 #define assert(expr) \
42 if (!(expr)) { \
43 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
44 #expr,__FILE__,__func__,__LINE__); \
45 }
46 #define dprintk(fmt, args...) \
47 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
48 #else
49 #define assert(expr) do {} while (0)
50 #define dprintk(fmt, args...) do {} while (0)
51 #endif /* RTL8169_DEBUG */
52
53 #define R8169_MSG_DEFAULT \
54 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
55
56 #define TX_BUFFS_AVAIL(tp) \
57 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
58
59 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
60 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
61 static const int multicast_filter_limit = 32;
62
63 /* MAC address length */
64 #define MAC_ADDR_LEN 6
65
66 #define MAX_READ_REQUEST_SHIFT 12
67 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
68 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
69 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
70 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
71 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
72
73 #define R8169_REGS_SIZE 256
74 #define R8169_NAPI_WEIGHT 64
75 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
76 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
77 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
78 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
79 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
80
81 #define RTL8169_TX_TIMEOUT (6*HZ)
82 #define RTL8169_PHY_TIMEOUT (10*HZ)
83
84 #define RTL_EEPROM_SIG cpu_to_le32(0x8129)
85 #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
86 #define RTL_EEPROM_SIG_ADDR 0x0000
87
88 /* write/read MMIO register */
89 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
90 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
91 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
92 #define RTL_R8(reg) readb (ioaddr + (reg))
93 #define RTL_R16(reg) readw (ioaddr + (reg))
94 #define RTL_R32(reg) readl (ioaddr + (reg))
95
96 enum mac_version {
97 RTL_GIGA_MAC_NONE = 0x00,
98 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
99 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
100 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
101 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
102 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
103 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
104 RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
105 RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
106 RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
107 RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
108 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
109 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
110 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
111 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
112 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
113 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
114 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
115 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
116 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
117 RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
118 RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
119 RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
120 RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP
121 RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP
122 RTL_GIGA_MAC_VER_25 = 0x19, // 8168D
123 RTL_GIGA_MAC_VER_26 = 0x1a, // 8168D
124 RTL_GIGA_MAC_VER_27 = 0x1b, // 8168DP
125 RTL_GIGA_MAC_VER_28 = 0x1c, // 8168DP
126 };
127
128 #define _R(NAME,MAC,MASK) \
129 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
130
131 static const struct {
132 const char *name;
133 u8 mac_version;
134 u32 RxConfigMask; /* Clears the bits supported by this chip */
135 } rtl_chip_info[] = {
136 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
137 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
138 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
139 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
140 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
141 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
142 _R("RTL8102e", RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
143 _R("RTL8102e", RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
144 _R("RTL8102e", RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
145 _R("RTL8101e", RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
146 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
147 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
148 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
149 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
150 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
151 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
152 _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
153 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
154 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
155 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E
156 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E
157 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E
158 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E
159 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E
160 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25, 0xff7e1880), // PCI-E
161 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_26, 0xff7e1880), // PCI-E
162 _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_27, 0xff7e1880), // PCI-E
163 _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_28, 0xff7e1880) // PCI-E
164 };
165 #undef _R
166
167 enum cfg_version {
168 RTL_CFG_0 = 0x00,
169 RTL_CFG_1,
170 RTL_CFG_2
171 };
172
173 static void rtl_hw_start_8169(struct net_device *);
174 static void rtl_hw_start_8168(struct net_device *);
175 static void rtl_hw_start_8101(struct net_device *);
176
177 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
178 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
179 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
180 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
181 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
182 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
183 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
184 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
185 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
186 { PCI_VENDOR_ID_LINKSYS, 0x1032,
187 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
188 { 0x0001, 0x8168,
189 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
190 {0,},
191 };
192
193 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
194
195 static int rx_buf_sz = 16383;
196 static int use_dac;
197 static struct {
198 u32 msg_enable;
199 } debug = { -1 };
200
201 enum rtl_registers {
202 MAC0 = 0, /* Ethernet hardware address. */
203 MAC4 = 4,
204 MAR0 = 8, /* Multicast filter. */
205 CounterAddrLow = 0x10,
206 CounterAddrHigh = 0x14,
207 TxDescStartAddrLow = 0x20,
208 TxDescStartAddrHigh = 0x24,
209 TxHDescStartAddrLow = 0x28,
210 TxHDescStartAddrHigh = 0x2c,
211 FLASH = 0x30,
212 ERSR = 0x36,
213 ChipCmd = 0x37,
214 TxPoll = 0x38,
215 IntrMask = 0x3c,
216 IntrStatus = 0x3e,
217 TxConfig = 0x40,
218 RxConfig = 0x44,
219 RxMissed = 0x4c,
220 Cfg9346 = 0x50,
221 Config0 = 0x51,
222 Config1 = 0x52,
223 Config2 = 0x53,
224 Config3 = 0x54,
225 Config4 = 0x55,
226 Config5 = 0x56,
227 MultiIntr = 0x5c,
228 PHYAR = 0x60,
229 PHYstatus = 0x6c,
230 RxMaxSize = 0xda,
231 CPlusCmd = 0xe0,
232 IntrMitigate = 0xe2,
233 RxDescAddrLow = 0xe4,
234 RxDescAddrHigh = 0xe8,
235 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
236
237 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
238
239 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
240
241 #define TxPacketMax (8064 >> 7)
242
243 FuncEvent = 0xf0,
244 FuncEventMask = 0xf4,
245 FuncPresetState = 0xf8,
246 FuncForceEvent = 0xfc,
247 };
248
249 enum rtl8110_registers {
250 TBICSR = 0x64,
251 TBI_ANAR = 0x68,
252 TBI_LPAR = 0x6a,
253 };
254
255 enum rtl8168_8101_registers {
256 CSIDR = 0x64,
257 CSIAR = 0x68,
258 #define CSIAR_FLAG 0x80000000
259 #define CSIAR_WRITE_CMD 0x80000000
260 #define CSIAR_BYTE_ENABLE 0x0f
261 #define CSIAR_BYTE_ENABLE_SHIFT 12
262 #define CSIAR_ADDR_MASK 0x0fff
263 PMCH = 0x6f,
264 EPHYAR = 0x80,
265 #define EPHYAR_FLAG 0x80000000
266 #define EPHYAR_WRITE_CMD 0x80000000
267 #define EPHYAR_REG_MASK 0x1f
268 #define EPHYAR_REG_SHIFT 16
269 #define EPHYAR_DATA_MASK 0xffff
270 DBG_REG = 0xd1,
271 #define FIX_NAK_1 (1 << 4)
272 #define FIX_NAK_2 (1 << 3)
273 EFUSEAR = 0xdc,
274 #define EFUSEAR_FLAG 0x80000000
275 #define EFUSEAR_WRITE_CMD 0x80000000
276 #define EFUSEAR_READ_CMD 0x00000000
277 #define EFUSEAR_REG_MASK 0x03ff
278 #define EFUSEAR_REG_SHIFT 8
279 #define EFUSEAR_DATA_MASK 0xff
280 };
281
282 enum rtl8168_registers {
283 ERIDR = 0x70,
284 ERIAR = 0x74,
285 #define ERIAR_FLAG 0x80000000
286 #define ERIAR_WRITE_CMD 0x80000000
287 #define ERIAR_READ_CMD 0x00000000
288 #define ERIAR_ADDR_BYTE_ALIGN 4
289 #define ERIAR_EXGMAC 0
290 #define ERIAR_MSIX 1
291 #define ERIAR_ASF 2
292 #define ERIAR_TYPE_SHIFT 16
293 #define ERIAR_BYTEEN 0x0f
294 #define ERIAR_BYTEEN_SHIFT 12
295 EPHY_RXER_NUM = 0x7c,
296 OCPDR = 0xb0, /* OCP GPHY access */
297 #define OCPDR_WRITE_CMD 0x80000000
298 #define OCPDR_READ_CMD 0x00000000
299 #define OCPDR_REG_MASK 0x7f
300 #define OCPDR_GPHY_REG_SHIFT 16
301 #define OCPDR_DATA_MASK 0xffff
302 OCPAR = 0xb4,
303 #define OCPAR_FLAG 0x80000000
304 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
305 #define OCPAR_GPHY_READ_CMD 0x0000f060
306 RDSAR1 = 0xd0 /* 8168c only. Undocumented on 8168dp */
307 };
308
309 enum rtl_register_content {
310 /* InterruptStatusBits */
311 SYSErr = 0x8000,
312 PCSTimeout = 0x4000,
313 SWInt = 0x0100,
314 TxDescUnavail = 0x0080,
315 RxFIFOOver = 0x0040,
316 LinkChg = 0x0020,
317 RxOverflow = 0x0010,
318 TxErr = 0x0008,
319 TxOK = 0x0004,
320 RxErr = 0x0002,
321 RxOK = 0x0001,
322
323 /* RxStatusDesc */
324 RxFOVF = (1 << 23),
325 RxRWT = (1 << 22),
326 RxRES = (1 << 21),
327 RxRUNT = (1 << 20),
328 RxCRC = (1 << 19),
329
330 /* ChipCmdBits */
331 CmdReset = 0x10,
332 CmdRxEnb = 0x08,
333 CmdTxEnb = 0x04,
334 RxBufEmpty = 0x01,
335
336 /* TXPoll register p.5 */
337 HPQ = 0x80, /* Poll cmd on the high prio queue */
338 NPQ = 0x40, /* Poll cmd on the low prio queue */
339 FSWInt = 0x01, /* Forced software interrupt */
340
341 /* Cfg9346Bits */
342 Cfg9346_Lock = 0x00,
343 Cfg9346_Unlock = 0xc0,
344
345 /* rx_mode_bits */
346 AcceptErr = 0x20,
347 AcceptRunt = 0x10,
348 AcceptBroadcast = 0x08,
349 AcceptMulticast = 0x04,
350 AcceptMyPhys = 0x02,
351 AcceptAllPhys = 0x01,
352
353 /* RxConfigBits */
354 RxCfgFIFOShift = 13,
355 RxCfgDMAShift = 8,
356
357 /* TxConfigBits */
358 TxInterFrameGapShift = 24,
359 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
360
361 /* Config1 register p.24 */
362 LEDS1 = (1 << 7),
363 LEDS0 = (1 << 6),
364 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
365 Speed_down = (1 << 4),
366 MEMMAP = (1 << 3),
367 IOMAP = (1 << 2),
368 VPD = (1 << 1),
369 PMEnable = (1 << 0), /* Power Management Enable */
370
371 /* Config2 register p. 25 */
372 PCI_Clock_66MHz = 0x01,
373 PCI_Clock_33MHz = 0x00,
374
375 /* Config3 register p.25 */
376 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
377 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
378 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
379
380 /* Config5 register p.27 */
381 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
382 MWF = (1 << 5), /* Accept Multicast wakeup frame */
383 UWF = (1 << 4), /* Accept Unicast wakeup frame */
384 LanWake = (1 << 1), /* LanWake enable/disable */
385 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
386
387 /* TBICSR p.28 */
388 TBIReset = 0x80000000,
389 TBILoopback = 0x40000000,
390 TBINwEnable = 0x20000000,
391 TBINwRestart = 0x10000000,
392 TBILinkOk = 0x02000000,
393 TBINwComplete = 0x01000000,
394
395 /* CPlusCmd p.31 */
396 EnableBist = (1 << 15), // 8168 8101
397 Mac_dbgo_oe = (1 << 14), // 8168 8101
398 Normal_mode = (1 << 13), // unused
399 Force_half_dup = (1 << 12), // 8168 8101
400 Force_rxflow_en = (1 << 11), // 8168 8101
401 Force_txflow_en = (1 << 10), // 8168 8101
402 Cxpl_dbg_sel = (1 << 9), // 8168 8101
403 ASF = (1 << 8), // 8168 8101
404 PktCntrDisable = (1 << 7), // 8168 8101
405 Mac_dbgo_sel = 0x001c, // 8168
406 RxVlan = (1 << 6),
407 RxChkSum = (1 << 5),
408 PCIDAC = (1 << 4),
409 PCIMulRW = (1 << 3),
410 INTT_0 = 0x0000, // 8168
411 INTT_1 = 0x0001, // 8168
412 INTT_2 = 0x0002, // 8168
413 INTT_3 = 0x0003, // 8168
414
415 /* rtl8169_PHYstatus */
416 TBI_Enable = 0x80,
417 TxFlowCtrl = 0x40,
418 RxFlowCtrl = 0x20,
419 _1000bpsF = 0x10,
420 _100bps = 0x08,
421 _10bps = 0x04,
422 LinkStatus = 0x02,
423 FullDup = 0x01,
424
425 /* _TBICSRBit */
426 TBILinkOK = 0x02000000,
427
428 /* DumpCounterCommand */
429 CounterDump = 0x8,
430 };
431
432 enum desc_status_bit {
433 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
434 RingEnd = (1 << 30), /* End of descriptor ring */
435 FirstFrag = (1 << 29), /* First segment of a packet */
436 LastFrag = (1 << 28), /* Final segment of a packet */
437
438 /* Tx private */
439 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
440 MSSShift = 16, /* MSS value position */
441 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
442 IPCS = (1 << 18), /* Calculate IP checksum */
443 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
444 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
445 TxVlanTag = (1 << 17), /* Add VLAN tag */
446
447 /* Rx private */
448 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
449 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
450
451 #define RxProtoUDP (PID1)
452 #define RxProtoTCP (PID0)
453 #define RxProtoIP (PID1 | PID0)
454 #define RxProtoMask RxProtoIP
455
456 IPFail = (1 << 16), /* IP checksum failed */
457 UDPFail = (1 << 15), /* UDP/IP checksum failed */
458 TCPFail = (1 << 14), /* TCP/IP checksum failed */
459 RxVlanTag = (1 << 16), /* VLAN tag available */
460 };
461
462 #define RsvdMask 0x3fffc000
463
464 struct TxDesc {
465 __le32 opts1;
466 __le32 opts2;
467 __le64 addr;
468 };
469
470 struct RxDesc {
471 __le32 opts1;
472 __le32 opts2;
473 __le64 addr;
474 };
475
476 struct ring_info {
477 struct sk_buff *skb;
478 u32 len;
479 u8 __pad[sizeof(void *) - sizeof(u32)];
480 };
481
482 enum features {
483 RTL_FEATURE_WOL = (1 << 0),
484 RTL_FEATURE_MSI = (1 << 1),
485 RTL_FEATURE_GMII = (1 << 2),
486 };
487
488 struct rtl8169_counters {
489 __le64 tx_packets;
490 __le64 rx_packets;
491 __le64 tx_errors;
492 __le32 rx_errors;
493 __le16 rx_missed;
494 __le16 align_errors;
495 __le32 tx_one_collision;
496 __le32 tx_multi_collision;
497 __le64 rx_unicast;
498 __le64 rx_broadcast;
499 __le32 rx_multicast;
500 __le16 tx_aborted;
501 __le16 tx_underun;
502 };
503
504 struct rtl8169_private {
505 void __iomem *mmio_addr; /* memory map physical address */
506 struct pci_dev *pci_dev; /* Index of PCI device */
507 struct net_device *dev;
508 struct napi_struct napi;
509 spinlock_t lock; /* spin lock flag */
510 u32 msg_enable;
511 int chipset;
512 int mac_version;
513 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
514 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
515 u32 dirty_rx;
516 u32 dirty_tx;
517 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
518 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
519 dma_addr_t TxPhyAddr;
520 dma_addr_t RxPhyAddr;
521 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
522 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
523 struct timer_list timer;
524 u16 cp_cmd;
525 u16 intr_event;
526 u16 napi_event;
527 u16 intr_mask;
528 int phy_1000_ctrl_reg;
529 #ifdef CONFIG_R8169_VLAN
530 struct vlan_group *vlgrp;
531 #endif
532
533 struct mdio_ops {
534 void (*write)(void __iomem *, int, int);
535 int (*read)(void __iomem *, int);
536 } mdio_ops;
537
538 struct pll_power_ops {
539 void (*down)(struct rtl8169_private *);
540 void (*up)(struct rtl8169_private *);
541 } pll_power_ops;
542
543 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
544 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
545 void (*phy_reset_enable)(struct rtl8169_private *tp);
546 void (*hw_start)(struct net_device *);
547 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
548 unsigned int (*link_ok)(void __iomem *);
549 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
550 int pcie_cap;
551 struct delayed_work task;
552 unsigned features;
553
554 struct mii_if_info mii;
555 struct rtl8169_counters counters;
556 u32 saved_wolopts;
557
558 const struct firmware *fw;
559 };
560
561 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
562 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
563 module_param(use_dac, int, 0);
564 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
565 module_param_named(debug, debug.msg_enable, int, 0);
566 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
567 MODULE_LICENSE("GPL");
568 MODULE_VERSION(RTL8169_VERSION);
569 MODULE_FIRMWARE(FIRMWARE_8168D_1);
570 MODULE_FIRMWARE(FIRMWARE_8168D_2);
571
572 static int rtl8169_open(struct net_device *dev);
573 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
574 struct net_device *dev);
575 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
576 static int rtl8169_init_ring(struct net_device *dev);
577 static void rtl_hw_start(struct net_device *dev);
578 static int rtl8169_close(struct net_device *dev);
579 static void rtl_set_rx_mode(struct net_device *dev);
580 static void rtl8169_tx_timeout(struct net_device *dev);
581 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
582 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
583 void __iomem *, u32 budget);
584 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
585 static void rtl8169_down(struct net_device *dev);
586 static void rtl8169_rx_clear(struct rtl8169_private *tp);
587 static int rtl8169_poll(struct napi_struct *napi, int budget);
588
589 static const unsigned int rtl8169_rx_config =
590 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
591
592 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
593 {
594 void __iomem *ioaddr = tp->mmio_addr;
595 int i;
596
597 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
598 for (i = 0; i < 20; i++) {
599 udelay(100);
600 if (RTL_R32(OCPAR) & OCPAR_FLAG)
601 break;
602 }
603 return RTL_R32(OCPDR);
604 }
605
606 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
607 {
608 void __iomem *ioaddr = tp->mmio_addr;
609 int i;
610
611 RTL_W32(OCPDR, data);
612 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
613 for (i = 0; i < 20; i++) {
614 udelay(100);
615 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
616 break;
617 }
618 }
619
620 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
621 {
622 void __iomem *ioaddr = tp->mmio_addr;
623 int i;
624
625 RTL_W8(ERIDR, cmd);
626 RTL_W32(ERIAR, 0x800010e8);
627 msleep(2);
628 for (i = 0; i < 5; i++) {
629 udelay(100);
630 if (!(RTL_R32(ERIDR) & ERIAR_FLAG))
631 break;
632 }
633
634 ocp_write(tp, 0x1, 0x30, 0x00000001);
635 }
636
637 #define OOB_CMD_RESET 0x00
638 #define OOB_CMD_DRIVER_START 0x05
639 #define OOB_CMD_DRIVER_STOP 0x06
640
641 static void rtl8168_driver_start(struct rtl8169_private *tp)
642 {
643 int i;
644
645 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
646
647 for (i = 0; i < 10; i++) {
648 msleep(10);
649 if (ocp_read(tp, 0x0f, 0x0010) & 0x00000800)
650 break;
651 }
652 }
653
654 static void rtl8168_driver_stop(struct rtl8169_private *tp)
655 {
656 int i;
657
658 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
659
660 for (i = 0; i < 10; i++) {
661 msleep(10);
662 if ((ocp_read(tp, 0x0f, 0x0010) & 0x00000800) == 0)
663 break;
664 }
665 }
666
667
668 static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
669 {
670 int i;
671
672 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
673
674 for (i = 20; i > 0; i--) {
675 /*
676 * Check if the RTL8169 has completed writing to the specified
677 * MII register.
678 */
679 if (!(RTL_R32(PHYAR) & 0x80000000))
680 break;
681 udelay(25);
682 }
683 /*
684 * According to hardware specs a 20us delay is required after write
685 * complete indication, but before sending next command.
686 */
687 udelay(20);
688 }
689
690 static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
691 {
692 int i, value = -1;
693
694 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
695
696 for (i = 20; i > 0; i--) {
697 /*
698 * Check if the RTL8169 has completed retrieving data from
699 * the specified MII register.
700 */
701 if (RTL_R32(PHYAR) & 0x80000000) {
702 value = RTL_R32(PHYAR) & 0xffff;
703 break;
704 }
705 udelay(25);
706 }
707 /*
708 * According to hardware specs a 20us delay is required after read
709 * complete indication, but before sending next command.
710 */
711 udelay(20);
712
713 return value;
714 }
715
716 static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
717 {
718 int i;
719
720 RTL_W32(OCPDR, data |
721 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
722 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
723 RTL_W32(EPHY_RXER_NUM, 0);
724
725 for (i = 0; i < 100; i++) {
726 mdelay(1);
727 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
728 break;
729 }
730 }
731
732 static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
733 {
734 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
735 (value & OCPDR_DATA_MASK));
736 }
737
738 static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
739 {
740 int i;
741
742 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
743
744 mdelay(1);
745 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
746 RTL_W32(EPHY_RXER_NUM, 0);
747
748 for (i = 0; i < 100; i++) {
749 mdelay(1);
750 if (RTL_R32(OCPAR) & OCPAR_FLAG)
751 break;
752 }
753
754 return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
755 }
756
757 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
758
759 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
760 {
761 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
762 }
763
764 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
765 {
766 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
767 }
768
769 static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
770 {
771 r8168dp_2_mdio_start(ioaddr);
772
773 r8169_mdio_write(ioaddr, reg_addr, value);
774
775 r8168dp_2_mdio_stop(ioaddr);
776 }
777
778 static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
779 {
780 int value;
781
782 r8168dp_2_mdio_start(ioaddr);
783
784 value = r8169_mdio_read(ioaddr, reg_addr);
785
786 r8168dp_2_mdio_stop(ioaddr);
787
788 return value;
789 }
790
791 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
792 {
793 tp->mdio_ops.write(tp->mmio_addr, location, val);
794 }
795
796 static int rtl_readphy(struct rtl8169_private *tp, int location)
797 {
798 return tp->mdio_ops.read(tp->mmio_addr, location);
799 }
800
801 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
802 {
803 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
804 }
805
806 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
807 {
808 int val;
809
810 val = rtl_readphy(tp, reg_addr);
811 rtl_writephy(tp, reg_addr, (val | p) & ~m);
812 }
813
814 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
815 int val)
816 {
817 struct rtl8169_private *tp = netdev_priv(dev);
818
819 rtl_writephy(tp, location, val);
820 }
821
822 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
823 {
824 struct rtl8169_private *tp = netdev_priv(dev);
825
826 return rtl_readphy(tp, location);
827 }
828
829 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
830 {
831 unsigned int i;
832
833 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
834 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
835
836 for (i = 0; i < 100; i++) {
837 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
838 break;
839 udelay(10);
840 }
841 }
842
843 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
844 {
845 u16 value = 0xffff;
846 unsigned int i;
847
848 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
849
850 for (i = 0; i < 100; i++) {
851 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
852 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
853 break;
854 }
855 udelay(10);
856 }
857
858 return value;
859 }
860
861 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
862 {
863 unsigned int i;
864
865 RTL_W32(CSIDR, value);
866 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
867 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
868
869 for (i = 0; i < 100; i++) {
870 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
871 break;
872 udelay(10);
873 }
874 }
875
876 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
877 {
878 u32 value = ~0x00;
879 unsigned int i;
880
881 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
882 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
883
884 for (i = 0; i < 100; i++) {
885 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
886 value = RTL_R32(CSIDR);
887 break;
888 }
889 udelay(10);
890 }
891
892 return value;
893 }
894
895 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
896 {
897 u8 value = 0xff;
898 unsigned int i;
899
900 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
901
902 for (i = 0; i < 300; i++) {
903 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
904 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
905 break;
906 }
907 udelay(100);
908 }
909
910 return value;
911 }
912
913 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
914 {
915 RTL_W16(IntrMask, 0x0000);
916
917 RTL_W16(IntrStatus, 0xffff);
918 }
919
920 static void rtl8169_asic_down(void __iomem *ioaddr)
921 {
922 RTL_W8(ChipCmd, 0x00);
923 rtl8169_irq_mask_and_ack(ioaddr);
924 RTL_R16(CPlusCmd);
925 }
926
927 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
928 {
929 void __iomem *ioaddr = tp->mmio_addr;
930
931 return RTL_R32(TBICSR) & TBIReset;
932 }
933
934 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
935 {
936 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
937 }
938
939 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
940 {
941 return RTL_R32(TBICSR) & TBILinkOk;
942 }
943
944 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
945 {
946 return RTL_R8(PHYstatus) & LinkStatus;
947 }
948
949 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
950 {
951 void __iomem *ioaddr = tp->mmio_addr;
952
953 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
954 }
955
956 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
957 {
958 unsigned int val;
959
960 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
961 rtl_writephy(tp, MII_BMCR, val & 0xffff);
962 }
963
964 static void __rtl8169_check_link_status(struct net_device *dev,
965 struct rtl8169_private *tp,
966 void __iomem *ioaddr,
967 bool pm)
968 {
969 unsigned long flags;
970
971 spin_lock_irqsave(&tp->lock, flags);
972 if (tp->link_ok(ioaddr)) {
973 /* This is to cancel a scheduled suspend if there's one. */
974 if (pm)
975 pm_request_resume(&tp->pci_dev->dev);
976 netif_carrier_on(dev);
977 if (net_ratelimit())
978 netif_info(tp, ifup, dev, "link up\n");
979 } else {
980 netif_carrier_off(dev);
981 netif_info(tp, ifdown, dev, "link down\n");
982 if (pm)
983 pm_schedule_suspend(&tp->pci_dev->dev, 100);
984 }
985 spin_unlock_irqrestore(&tp->lock, flags);
986 }
987
988 static void rtl8169_check_link_status(struct net_device *dev,
989 struct rtl8169_private *tp,
990 void __iomem *ioaddr)
991 {
992 __rtl8169_check_link_status(dev, tp, ioaddr, false);
993 }
994
995 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
996
997 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
998 {
999 void __iomem *ioaddr = tp->mmio_addr;
1000 u8 options;
1001 u32 wolopts = 0;
1002
1003 options = RTL_R8(Config1);
1004 if (!(options & PMEnable))
1005 return 0;
1006
1007 options = RTL_R8(Config3);
1008 if (options & LinkUp)
1009 wolopts |= WAKE_PHY;
1010 if (options & MagicPacket)
1011 wolopts |= WAKE_MAGIC;
1012
1013 options = RTL_R8(Config5);
1014 if (options & UWF)
1015 wolopts |= WAKE_UCAST;
1016 if (options & BWF)
1017 wolopts |= WAKE_BCAST;
1018 if (options & MWF)
1019 wolopts |= WAKE_MCAST;
1020
1021 return wolopts;
1022 }
1023
1024 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1025 {
1026 struct rtl8169_private *tp = netdev_priv(dev);
1027
1028 spin_lock_irq(&tp->lock);
1029
1030 wol->supported = WAKE_ANY;
1031 wol->wolopts = __rtl8169_get_wol(tp);
1032
1033 spin_unlock_irq(&tp->lock);
1034 }
1035
1036 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1037 {
1038 void __iomem *ioaddr = tp->mmio_addr;
1039 unsigned int i;
1040 static const struct {
1041 u32 opt;
1042 u16 reg;
1043 u8 mask;
1044 } cfg[] = {
1045 { WAKE_ANY, Config1, PMEnable },
1046 { WAKE_PHY, Config3, LinkUp },
1047 { WAKE_MAGIC, Config3, MagicPacket },
1048 { WAKE_UCAST, Config5, UWF },
1049 { WAKE_BCAST, Config5, BWF },
1050 { WAKE_MCAST, Config5, MWF },
1051 { WAKE_ANY, Config5, LanWake }
1052 };
1053
1054 RTL_W8(Cfg9346, Cfg9346_Unlock);
1055
1056 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1057 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1058 if (wolopts & cfg[i].opt)
1059 options |= cfg[i].mask;
1060 RTL_W8(cfg[i].reg, options);
1061 }
1062
1063 RTL_W8(Cfg9346, Cfg9346_Lock);
1064 }
1065
1066 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1067 {
1068 struct rtl8169_private *tp = netdev_priv(dev);
1069
1070 spin_lock_irq(&tp->lock);
1071
1072 if (wol->wolopts)
1073 tp->features |= RTL_FEATURE_WOL;
1074 else
1075 tp->features &= ~RTL_FEATURE_WOL;
1076 __rtl8169_set_wol(tp, wol->wolopts);
1077 spin_unlock_irq(&tp->lock);
1078
1079 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1080
1081 return 0;
1082 }
1083
1084 static void rtl8169_get_drvinfo(struct net_device *dev,
1085 struct ethtool_drvinfo *info)
1086 {
1087 struct rtl8169_private *tp = netdev_priv(dev);
1088
1089 strcpy(info->driver, MODULENAME);
1090 strcpy(info->version, RTL8169_VERSION);
1091 strcpy(info->bus_info, pci_name(tp->pci_dev));
1092 }
1093
1094 static int rtl8169_get_regs_len(struct net_device *dev)
1095 {
1096 return R8169_REGS_SIZE;
1097 }
1098
1099 static int rtl8169_set_speed_tbi(struct net_device *dev,
1100 u8 autoneg, u16 speed, u8 duplex)
1101 {
1102 struct rtl8169_private *tp = netdev_priv(dev);
1103 void __iomem *ioaddr = tp->mmio_addr;
1104 int ret = 0;
1105 u32 reg;
1106
1107 reg = RTL_R32(TBICSR);
1108 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1109 (duplex == DUPLEX_FULL)) {
1110 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1111 } else if (autoneg == AUTONEG_ENABLE)
1112 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1113 else {
1114 netif_warn(tp, link, dev,
1115 "incorrect speed setting refused in TBI mode\n");
1116 ret = -EOPNOTSUPP;
1117 }
1118
1119 return ret;
1120 }
1121
1122 static int rtl8169_set_speed_xmii(struct net_device *dev,
1123 u8 autoneg, u16 speed, u8 duplex)
1124 {
1125 struct rtl8169_private *tp = netdev_priv(dev);
1126 int giga_ctrl, bmcr;
1127
1128 if (autoneg == AUTONEG_ENABLE) {
1129 int auto_nego;
1130
1131 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1132 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
1133 ADVERTISE_100HALF | ADVERTISE_100FULL);
1134 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1135
1136 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1137 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1138
1139 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1140 if ((tp->mac_version != RTL_GIGA_MAC_VER_07) &&
1141 (tp->mac_version != RTL_GIGA_MAC_VER_08) &&
1142 (tp->mac_version != RTL_GIGA_MAC_VER_09) &&
1143 (tp->mac_version != RTL_GIGA_MAC_VER_10) &&
1144 (tp->mac_version != RTL_GIGA_MAC_VER_13) &&
1145 (tp->mac_version != RTL_GIGA_MAC_VER_14) &&
1146 (tp->mac_version != RTL_GIGA_MAC_VER_15) &&
1147 (tp->mac_version != RTL_GIGA_MAC_VER_16)) {
1148 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
1149 } else {
1150 netif_info(tp, link, dev,
1151 "PHY does not support 1000Mbps\n");
1152 }
1153
1154 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1155
1156 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
1157 (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
1158 (tp->mac_version >= RTL_GIGA_MAC_VER_17)) {
1159 /*
1160 * Wake up the PHY.
1161 * Vendor specific (0x1f) and reserved (0x0e) MII
1162 * registers.
1163 */
1164 rtl_writephy(tp, 0x1f, 0x0000);
1165 rtl_writephy(tp, 0x0e, 0x0000);
1166 }
1167
1168 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1169 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1170 } else {
1171 giga_ctrl = 0;
1172
1173 if (speed == SPEED_10)
1174 bmcr = 0;
1175 else if (speed == SPEED_100)
1176 bmcr = BMCR_SPEED100;
1177 else
1178 return -EINVAL;
1179
1180 if (duplex == DUPLEX_FULL)
1181 bmcr |= BMCR_FULLDPLX;
1182
1183 rtl_writephy(tp, 0x1f, 0x0000);
1184 }
1185
1186 tp->phy_1000_ctrl_reg = giga_ctrl;
1187
1188 rtl_writephy(tp, MII_BMCR, bmcr);
1189
1190 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1191 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
1192 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1193 rtl_writephy(tp, 0x17, 0x2138);
1194 rtl_writephy(tp, 0x0e, 0x0260);
1195 } else {
1196 rtl_writephy(tp, 0x17, 0x2108);
1197 rtl_writephy(tp, 0x0e, 0x0000);
1198 }
1199 }
1200
1201 return 0;
1202 }
1203
1204 static int rtl8169_set_speed(struct net_device *dev,
1205 u8 autoneg, u16 speed, u8 duplex)
1206 {
1207 struct rtl8169_private *tp = netdev_priv(dev);
1208 int ret;
1209
1210 ret = tp->set_speed(dev, autoneg, speed, duplex);
1211
1212 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1213 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1214
1215 return ret;
1216 }
1217
1218 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1219 {
1220 struct rtl8169_private *tp = netdev_priv(dev);
1221 unsigned long flags;
1222 int ret;
1223
1224 spin_lock_irqsave(&tp->lock, flags);
1225 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
1226 spin_unlock_irqrestore(&tp->lock, flags);
1227
1228 return ret;
1229 }
1230
1231 static u32 rtl8169_get_rx_csum(struct net_device *dev)
1232 {
1233 struct rtl8169_private *tp = netdev_priv(dev);
1234
1235 return tp->cp_cmd & RxChkSum;
1236 }
1237
1238 static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
1239 {
1240 struct rtl8169_private *tp = netdev_priv(dev);
1241 void __iomem *ioaddr = tp->mmio_addr;
1242 unsigned long flags;
1243
1244 spin_lock_irqsave(&tp->lock, flags);
1245
1246 if (data)
1247 tp->cp_cmd |= RxChkSum;
1248 else
1249 tp->cp_cmd &= ~RxChkSum;
1250
1251 RTL_W16(CPlusCmd, tp->cp_cmd);
1252 RTL_R16(CPlusCmd);
1253
1254 spin_unlock_irqrestore(&tp->lock, flags);
1255
1256 return 0;
1257 }
1258
1259 #ifdef CONFIG_R8169_VLAN
1260
1261 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1262 struct sk_buff *skb)
1263 {
1264 return (vlan_tx_tag_present(skb)) ?
1265 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1266 }
1267
1268 static void rtl8169_vlan_rx_register(struct net_device *dev,
1269 struct vlan_group *grp)
1270 {
1271 struct rtl8169_private *tp = netdev_priv(dev);
1272 void __iomem *ioaddr = tp->mmio_addr;
1273 unsigned long flags;
1274
1275 spin_lock_irqsave(&tp->lock, flags);
1276 tp->vlgrp = grp;
1277 /*
1278 * Do not disable RxVlan on 8110SCd.
1279 */
1280 if (tp->vlgrp || (tp->mac_version == RTL_GIGA_MAC_VER_05))
1281 tp->cp_cmd |= RxVlan;
1282 else
1283 tp->cp_cmd &= ~RxVlan;
1284 RTL_W16(CPlusCmd, tp->cp_cmd);
1285 RTL_R16(CPlusCmd);
1286 spin_unlock_irqrestore(&tp->lock, flags);
1287 }
1288
1289 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1290 struct sk_buff *skb, int polling)
1291 {
1292 u32 opts2 = le32_to_cpu(desc->opts2);
1293 struct vlan_group *vlgrp = tp->vlgrp;
1294 int ret;
1295
1296 if (vlgrp && (opts2 & RxVlanTag)) {
1297 u16 vtag = swab16(opts2 & 0xffff);
1298
1299 if (likely(polling))
1300 vlan_gro_receive(&tp->napi, vlgrp, vtag, skb);
1301 else
1302 __vlan_hwaccel_rx(skb, vlgrp, vtag, polling);
1303 ret = 0;
1304 } else
1305 ret = -1;
1306 desc->opts2 = 0;
1307 return ret;
1308 }
1309
1310 #else /* !CONFIG_R8169_VLAN */
1311
1312 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1313 struct sk_buff *skb)
1314 {
1315 return 0;
1316 }
1317
1318 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1319 struct sk_buff *skb, int polling)
1320 {
1321 return -1;
1322 }
1323
1324 #endif
1325
1326 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1327 {
1328 struct rtl8169_private *tp = netdev_priv(dev);
1329 void __iomem *ioaddr = tp->mmio_addr;
1330 u32 status;
1331
1332 cmd->supported =
1333 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1334 cmd->port = PORT_FIBRE;
1335 cmd->transceiver = XCVR_INTERNAL;
1336
1337 status = RTL_R32(TBICSR);
1338 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1339 cmd->autoneg = !!(status & TBINwEnable);
1340
1341 cmd->speed = SPEED_1000;
1342 cmd->duplex = DUPLEX_FULL; /* Always set */
1343
1344 return 0;
1345 }
1346
1347 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1348 {
1349 struct rtl8169_private *tp = netdev_priv(dev);
1350
1351 return mii_ethtool_gset(&tp->mii, cmd);
1352 }
1353
1354 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1355 {
1356 struct rtl8169_private *tp = netdev_priv(dev);
1357 unsigned long flags;
1358 int rc;
1359
1360 spin_lock_irqsave(&tp->lock, flags);
1361
1362 rc = tp->get_settings(dev, cmd);
1363
1364 spin_unlock_irqrestore(&tp->lock, flags);
1365 return rc;
1366 }
1367
1368 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1369 void *p)
1370 {
1371 struct rtl8169_private *tp = netdev_priv(dev);
1372 unsigned long flags;
1373
1374 if (regs->len > R8169_REGS_SIZE)
1375 regs->len = R8169_REGS_SIZE;
1376
1377 spin_lock_irqsave(&tp->lock, flags);
1378 memcpy_fromio(p, tp->mmio_addr, regs->len);
1379 spin_unlock_irqrestore(&tp->lock, flags);
1380 }
1381
1382 static u32 rtl8169_get_msglevel(struct net_device *dev)
1383 {
1384 struct rtl8169_private *tp = netdev_priv(dev);
1385
1386 return tp->msg_enable;
1387 }
1388
1389 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1390 {
1391 struct rtl8169_private *tp = netdev_priv(dev);
1392
1393 tp->msg_enable = value;
1394 }
1395
1396 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1397 "tx_packets",
1398 "rx_packets",
1399 "tx_errors",
1400 "rx_errors",
1401 "rx_missed",
1402 "align_errors",
1403 "tx_single_collisions",
1404 "tx_multi_collisions",
1405 "unicast",
1406 "broadcast",
1407 "multicast",
1408 "tx_aborted",
1409 "tx_underrun",
1410 };
1411
1412 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1413 {
1414 switch (sset) {
1415 case ETH_SS_STATS:
1416 return ARRAY_SIZE(rtl8169_gstrings);
1417 default:
1418 return -EOPNOTSUPP;
1419 }
1420 }
1421
1422 static void rtl8169_update_counters(struct net_device *dev)
1423 {
1424 struct rtl8169_private *tp = netdev_priv(dev);
1425 void __iomem *ioaddr = tp->mmio_addr;
1426 struct rtl8169_counters *counters;
1427 dma_addr_t paddr;
1428 u32 cmd;
1429 int wait = 1000;
1430 struct device *d = &tp->pci_dev->dev;
1431
1432 /*
1433 * Some chips are unable to dump tally counters when the receiver
1434 * is disabled.
1435 */
1436 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1437 return;
1438
1439 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1440 if (!counters)
1441 return;
1442
1443 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1444 cmd = (u64)paddr & DMA_BIT_MASK(32);
1445 RTL_W32(CounterAddrLow, cmd);
1446 RTL_W32(CounterAddrLow, cmd | CounterDump);
1447
1448 while (wait--) {
1449 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1450 /* copy updated counters */
1451 memcpy(&tp->counters, counters, sizeof(*counters));
1452 break;
1453 }
1454 udelay(10);
1455 }
1456
1457 RTL_W32(CounterAddrLow, 0);
1458 RTL_W32(CounterAddrHigh, 0);
1459
1460 dma_free_coherent(d, sizeof(*counters), counters, paddr);
1461 }
1462
1463 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1464 struct ethtool_stats *stats, u64 *data)
1465 {
1466 struct rtl8169_private *tp = netdev_priv(dev);
1467
1468 ASSERT_RTNL();
1469
1470 rtl8169_update_counters(dev);
1471
1472 data[0] = le64_to_cpu(tp->counters.tx_packets);
1473 data[1] = le64_to_cpu(tp->counters.rx_packets);
1474 data[2] = le64_to_cpu(tp->counters.tx_errors);
1475 data[3] = le32_to_cpu(tp->counters.rx_errors);
1476 data[4] = le16_to_cpu(tp->counters.rx_missed);
1477 data[5] = le16_to_cpu(tp->counters.align_errors);
1478 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1479 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1480 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1481 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1482 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1483 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1484 data[12] = le16_to_cpu(tp->counters.tx_underun);
1485 }
1486
1487 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1488 {
1489 switch(stringset) {
1490 case ETH_SS_STATS:
1491 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1492 break;
1493 }
1494 }
1495
1496 static const struct ethtool_ops rtl8169_ethtool_ops = {
1497 .get_drvinfo = rtl8169_get_drvinfo,
1498 .get_regs_len = rtl8169_get_regs_len,
1499 .get_link = ethtool_op_get_link,
1500 .get_settings = rtl8169_get_settings,
1501 .set_settings = rtl8169_set_settings,
1502 .get_msglevel = rtl8169_get_msglevel,
1503 .set_msglevel = rtl8169_set_msglevel,
1504 .get_rx_csum = rtl8169_get_rx_csum,
1505 .set_rx_csum = rtl8169_set_rx_csum,
1506 .set_tx_csum = ethtool_op_set_tx_csum,
1507 .set_sg = ethtool_op_set_sg,
1508 .set_tso = ethtool_op_set_tso,
1509 .get_regs = rtl8169_get_regs,
1510 .get_wol = rtl8169_get_wol,
1511 .set_wol = rtl8169_set_wol,
1512 .get_strings = rtl8169_get_strings,
1513 .get_sset_count = rtl8169_get_sset_count,
1514 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1515 };
1516
1517 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1518 void __iomem *ioaddr)
1519 {
1520 /*
1521 * The driver currently handles the 8168Bf and the 8168Be identically
1522 * but they can be identified more specifically through the test below
1523 * if needed:
1524 *
1525 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1526 *
1527 * Same thing for the 8101Eb and the 8101Ec:
1528 *
1529 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1530 */
1531 static const struct {
1532 u32 mask;
1533 u32 val;
1534 int mac_version;
1535 } mac_info[] = {
1536 /* 8168D family. */
1537 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
1538 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
1539 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
1540
1541 /* 8168DP family. */
1542 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
1543 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
1544
1545 /* 8168C family. */
1546 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
1547 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
1548 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
1549 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
1550 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1551 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
1552 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
1553 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
1554 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
1555
1556 /* 8168B family. */
1557 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1558 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1559 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1560 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1561
1562 /* 8101 family. */
1563 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1564 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1565 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1566 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1567 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1568 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
1569 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
1570 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
1571 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
1572 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1573 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
1574 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1575 /* FIXME: where did these entries come from ? -- FR */
1576 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1577 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1578
1579 /* 8110 family. */
1580 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1581 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1582 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1583 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1584 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1585 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1586
1587 /* Catch-all */
1588 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
1589 }, *p = mac_info;
1590 u32 reg;
1591
1592 reg = RTL_R32(TxConfig);
1593 while ((reg & p->mask) != p->val)
1594 p++;
1595 tp->mac_version = p->mac_version;
1596 }
1597
1598 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1599 {
1600 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1601 }
1602
1603 struct phy_reg {
1604 u16 reg;
1605 u16 val;
1606 };
1607
1608 static void rtl_writephy_batch(struct rtl8169_private *tp,
1609 const struct phy_reg *regs, int len)
1610 {
1611 while (len-- > 0) {
1612 rtl_writephy(tp, regs->reg, regs->val);
1613 regs++;
1614 }
1615 }
1616
1617 #define PHY_READ 0x00000000
1618 #define PHY_DATA_OR 0x10000000
1619 #define PHY_DATA_AND 0x20000000
1620 #define PHY_BJMPN 0x30000000
1621 #define PHY_READ_EFUSE 0x40000000
1622 #define PHY_READ_MAC_BYTE 0x50000000
1623 #define PHY_WRITE_MAC_BYTE 0x60000000
1624 #define PHY_CLEAR_READCOUNT 0x70000000
1625 #define PHY_WRITE 0x80000000
1626 #define PHY_READCOUNT_EQ_SKIP 0x90000000
1627 #define PHY_COMP_EQ_SKIPN 0xa0000000
1628 #define PHY_COMP_NEQ_SKIPN 0xb0000000
1629 #define PHY_WRITE_PREVIOUS 0xc0000000
1630 #define PHY_SKIPN 0xd0000000
1631 #define PHY_DELAY_MS 0xe0000000
1632 #define PHY_WRITE_ERI_WORD 0xf0000000
1633
1634 static void
1635 rtl_phy_write_fw(struct rtl8169_private *tp, const struct firmware *fw)
1636 {
1637 __le32 *phytable = (__le32 *)fw->data;
1638 struct net_device *dev = tp->dev;
1639 size_t index, fw_size = fw->size / sizeof(*phytable);
1640 u32 predata, count;
1641
1642 if (fw->size % sizeof(*phytable)) {
1643 netif_err(tp, probe, dev, "odd sized firmware %zd\n", fw->size);
1644 return;
1645 }
1646
1647 for (index = 0; index < fw_size; index++) {
1648 u32 action = le32_to_cpu(phytable[index]);
1649 u32 regno = (action & 0x0fff0000) >> 16;
1650
1651 switch(action & 0xf0000000) {
1652 case PHY_READ:
1653 case PHY_DATA_OR:
1654 case PHY_DATA_AND:
1655 case PHY_READ_EFUSE:
1656 case PHY_CLEAR_READCOUNT:
1657 case PHY_WRITE:
1658 case PHY_WRITE_PREVIOUS:
1659 case PHY_DELAY_MS:
1660 break;
1661
1662 case PHY_BJMPN:
1663 if (regno > index) {
1664 netif_err(tp, probe, tp->dev,
1665 "Out of range of firmware\n");
1666 return;
1667 }
1668 break;
1669 case PHY_READCOUNT_EQ_SKIP:
1670 if (index + 2 >= fw_size) {
1671 netif_err(tp, probe, tp->dev,
1672 "Out of range of firmware\n");
1673 return;
1674 }
1675 break;
1676 case PHY_COMP_EQ_SKIPN:
1677 case PHY_COMP_NEQ_SKIPN:
1678 case PHY_SKIPN:
1679 if (index + 1 + regno >= fw_size) {
1680 netif_err(tp, probe, tp->dev,
1681 "Out of range of firmware\n");
1682 return;
1683 }
1684 break;
1685
1686 case PHY_READ_MAC_BYTE:
1687 case PHY_WRITE_MAC_BYTE:
1688 case PHY_WRITE_ERI_WORD:
1689 default:
1690 netif_err(tp, probe, tp->dev,
1691 "Invalid action 0x%08x\n", action);
1692 return;
1693 }
1694 }
1695
1696 predata = 0;
1697 count = 0;
1698
1699 for (index = 0; index < fw_size; ) {
1700 u32 action = le32_to_cpu(phytable[index]);
1701 u32 data = action & 0x0000ffff;
1702 u32 regno = (action & 0x0fff0000) >> 16;
1703
1704 if (!action)
1705 break;
1706
1707 switch(action & 0xf0000000) {
1708 case PHY_READ:
1709 predata = rtl_readphy(tp, regno);
1710 count++;
1711 index++;
1712 break;
1713 case PHY_DATA_OR:
1714 predata |= data;
1715 index++;
1716 break;
1717 case PHY_DATA_AND:
1718 predata &= data;
1719 index++;
1720 break;
1721 case PHY_BJMPN:
1722 index -= regno;
1723 break;
1724 case PHY_READ_EFUSE:
1725 predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
1726 index++;
1727 break;
1728 case PHY_CLEAR_READCOUNT:
1729 count = 0;
1730 index++;
1731 break;
1732 case PHY_WRITE:
1733 rtl_writephy(tp, regno, data);
1734 index++;
1735 break;
1736 case PHY_READCOUNT_EQ_SKIP:
1737 if (count == data)
1738 index += 2;
1739 else
1740 index += 1;
1741 break;
1742 case PHY_COMP_EQ_SKIPN:
1743 if (predata == data)
1744 index += regno;
1745 index++;
1746 break;
1747 case PHY_COMP_NEQ_SKIPN:
1748 if (predata != data)
1749 index += regno;
1750 index++;
1751 break;
1752 case PHY_WRITE_PREVIOUS:
1753 rtl_writephy(tp, regno, predata);
1754 index++;
1755 break;
1756 case PHY_SKIPN:
1757 index += regno + 1;
1758 break;
1759 case PHY_DELAY_MS:
1760 mdelay(data);
1761 index++;
1762 break;
1763
1764 case PHY_READ_MAC_BYTE:
1765 case PHY_WRITE_MAC_BYTE:
1766 case PHY_WRITE_ERI_WORD:
1767 default:
1768 BUG();
1769 }
1770 }
1771 }
1772
1773 static void rtl_release_firmware(struct rtl8169_private *tp)
1774 {
1775 release_firmware(tp->fw);
1776 tp->fw = NULL;
1777 }
1778
1779 static int rtl_apply_firmware(struct rtl8169_private *tp, const char *fw_name)
1780 {
1781 const struct firmware **fw = &tp->fw;
1782 int rc = !*fw;
1783
1784 if (rc) {
1785 rc = request_firmware(fw, fw_name, &tp->pci_dev->dev);
1786 if (rc < 0)
1787 goto out;
1788 }
1789
1790 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
1791 rtl_phy_write_fw(tp, *fw);
1792 out:
1793 return rc;
1794 }
1795
1796 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1797 {
1798 static const struct phy_reg phy_reg_init[] = {
1799 { 0x1f, 0x0001 },
1800 { 0x06, 0x006e },
1801 { 0x08, 0x0708 },
1802 { 0x15, 0x4000 },
1803 { 0x18, 0x65c7 },
1804
1805 { 0x1f, 0x0001 },
1806 { 0x03, 0x00a1 },
1807 { 0x02, 0x0008 },
1808 { 0x01, 0x0120 },
1809 { 0x00, 0x1000 },
1810 { 0x04, 0x0800 },
1811 { 0x04, 0x0000 },
1812
1813 { 0x03, 0xff41 },
1814 { 0x02, 0xdf60 },
1815 { 0x01, 0x0140 },
1816 { 0x00, 0x0077 },
1817 { 0x04, 0x7800 },
1818 { 0x04, 0x7000 },
1819
1820 { 0x03, 0x802f },
1821 { 0x02, 0x4f02 },
1822 { 0x01, 0x0409 },
1823 { 0x00, 0xf0f9 },
1824 { 0x04, 0x9800 },
1825 { 0x04, 0x9000 },
1826
1827 { 0x03, 0xdf01 },
1828 { 0x02, 0xdf20 },
1829 { 0x01, 0xff95 },
1830 { 0x00, 0xba00 },
1831 { 0x04, 0xa800 },
1832 { 0x04, 0xa000 },
1833
1834 { 0x03, 0xff41 },
1835 { 0x02, 0xdf20 },
1836 { 0x01, 0x0140 },
1837 { 0x00, 0x00bb },
1838 { 0x04, 0xb800 },
1839 { 0x04, 0xb000 },
1840
1841 { 0x03, 0xdf41 },
1842 { 0x02, 0xdc60 },
1843 { 0x01, 0x6340 },
1844 { 0x00, 0x007d },
1845 { 0x04, 0xd800 },
1846 { 0x04, 0xd000 },
1847
1848 { 0x03, 0xdf01 },
1849 { 0x02, 0xdf20 },
1850 { 0x01, 0x100a },
1851 { 0x00, 0xa0ff },
1852 { 0x04, 0xf800 },
1853 { 0x04, 0xf000 },
1854
1855 { 0x1f, 0x0000 },
1856 { 0x0b, 0x0000 },
1857 { 0x00, 0x9200 }
1858 };
1859
1860 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1861 }
1862
1863 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
1864 {
1865 static const struct phy_reg phy_reg_init[] = {
1866 { 0x1f, 0x0002 },
1867 { 0x01, 0x90d0 },
1868 { 0x1f, 0x0000 }
1869 };
1870
1871 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1872 }
1873
1874 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
1875 {
1876 struct pci_dev *pdev = tp->pci_dev;
1877 u16 vendor_id, device_id;
1878
1879 pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
1880 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
1881
1882 if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
1883 return;
1884
1885 rtl_writephy(tp, 0x1f, 0x0001);
1886 rtl_writephy(tp, 0x10, 0xf01b);
1887 rtl_writephy(tp, 0x1f, 0x0000);
1888 }
1889
1890 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
1891 {
1892 static const struct phy_reg phy_reg_init[] = {
1893 { 0x1f, 0x0001 },
1894 { 0x04, 0x0000 },
1895 { 0x03, 0x00a1 },
1896 { 0x02, 0x0008 },
1897 { 0x01, 0x0120 },
1898 { 0x00, 0x1000 },
1899 { 0x04, 0x0800 },
1900 { 0x04, 0x9000 },
1901 { 0x03, 0x802f },
1902 { 0x02, 0x4f02 },
1903 { 0x01, 0x0409 },
1904 { 0x00, 0xf099 },
1905 { 0x04, 0x9800 },
1906 { 0x04, 0xa000 },
1907 { 0x03, 0xdf01 },
1908 { 0x02, 0xdf20 },
1909 { 0x01, 0xff95 },
1910 { 0x00, 0xba00 },
1911 { 0x04, 0xa800 },
1912 { 0x04, 0xf000 },
1913 { 0x03, 0xdf01 },
1914 { 0x02, 0xdf20 },
1915 { 0x01, 0x101a },
1916 { 0x00, 0xa0ff },
1917 { 0x04, 0xf800 },
1918 { 0x04, 0x0000 },
1919 { 0x1f, 0x0000 },
1920
1921 { 0x1f, 0x0001 },
1922 { 0x10, 0xf41b },
1923 { 0x14, 0xfb54 },
1924 { 0x18, 0xf5c7 },
1925 { 0x1f, 0x0000 },
1926
1927 { 0x1f, 0x0001 },
1928 { 0x17, 0x0cc0 },
1929 { 0x1f, 0x0000 }
1930 };
1931
1932 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1933
1934 rtl8169scd_hw_phy_config_quirk(tp);
1935 }
1936
1937 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
1938 {
1939 static const struct phy_reg phy_reg_init[] = {
1940 { 0x1f, 0x0001 },
1941 { 0x04, 0x0000 },
1942 { 0x03, 0x00a1 },
1943 { 0x02, 0x0008 },
1944 { 0x01, 0x0120 },
1945 { 0x00, 0x1000 },
1946 { 0x04, 0x0800 },
1947 { 0x04, 0x9000 },
1948 { 0x03, 0x802f },
1949 { 0x02, 0x4f02 },
1950 { 0x01, 0x0409 },
1951 { 0x00, 0xf099 },
1952 { 0x04, 0x9800 },
1953 { 0x04, 0xa000 },
1954 { 0x03, 0xdf01 },
1955 { 0x02, 0xdf20 },
1956 { 0x01, 0xff95 },
1957 { 0x00, 0xba00 },
1958 { 0x04, 0xa800 },
1959 { 0x04, 0xf000 },
1960 { 0x03, 0xdf01 },
1961 { 0x02, 0xdf20 },
1962 { 0x01, 0x101a },
1963 { 0x00, 0xa0ff },
1964 { 0x04, 0xf800 },
1965 { 0x04, 0x0000 },
1966 { 0x1f, 0x0000 },
1967
1968 { 0x1f, 0x0001 },
1969 { 0x0b, 0x8480 },
1970 { 0x1f, 0x0000 },
1971
1972 { 0x1f, 0x0001 },
1973 { 0x18, 0x67c7 },
1974 { 0x04, 0x2000 },
1975 { 0x03, 0x002f },
1976 { 0x02, 0x4360 },
1977 { 0x01, 0x0109 },
1978 { 0x00, 0x3022 },
1979 { 0x04, 0x2800 },
1980 { 0x1f, 0x0000 },
1981
1982 { 0x1f, 0x0001 },
1983 { 0x17, 0x0cc0 },
1984 { 0x1f, 0x0000 }
1985 };
1986
1987 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1988 }
1989
1990 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
1991 {
1992 static const struct phy_reg phy_reg_init[] = {
1993 { 0x10, 0xf41b },
1994 { 0x1f, 0x0000 }
1995 };
1996
1997 rtl_writephy(tp, 0x1f, 0x0001);
1998 rtl_patchphy(tp, 0x16, 1 << 0);
1999
2000 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2001 }
2002
2003 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2004 {
2005 static const struct phy_reg phy_reg_init[] = {
2006 { 0x1f, 0x0001 },
2007 { 0x10, 0xf41b },
2008 { 0x1f, 0x0000 }
2009 };
2010
2011 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2012 }
2013
2014 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2015 {
2016 static const struct phy_reg phy_reg_init[] = {
2017 { 0x1f, 0x0000 },
2018 { 0x1d, 0x0f00 },
2019 { 0x1f, 0x0002 },
2020 { 0x0c, 0x1ec8 },
2021 { 0x1f, 0x0000 }
2022 };
2023
2024 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2025 }
2026
2027 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2028 {
2029 static const struct phy_reg phy_reg_init[] = {
2030 { 0x1f, 0x0001 },
2031 { 0x1d, 0x3d98 },
2032 { 0x1f, 0x0000 }
2033 };
2034
2035 rtl_writephy(tp, 0x1f, 0x0000);
2036 rtl_patchphy(tp, 0x14, 1 << 5);
2037 rtl_patchphy(tp, 0x0d, 1 << 5);
2038
2039 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2040 }
2041
2042 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2043 {
2044 static const struct phy_reg phy_reg_init[] = {
2045 { 0x1f, 0x0001 },
2046 { 0x12, 0x2300 },
2047 { 0x1f, 0x0002 },
2048 { 0x00, 0x88d4 },
2049 { 0x01, 0x82b1 },
2050 { 0x03, 0x7002 },
2051 { 0x08, 0x9e30 },
2052 { 0x09, 0x01f0 },
2053 { 0x0a, 0x5500 },
2054 { 0x0c, 0x00c8 },
2055 { 0x1f, 0x0003 },
2056 { 0x12, 0xc096 },
2057 { 0x16, 0x000a },
2058 { 0x1f, 0x0000 },
2059 { 0x1f, 0x0000 },
2060 { 0x09, 0x2000 },
2061 { 0x09, 0x0000 }
2062 };
2063
2064 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2065
2066 rtl_patchphy(tp, 0x14, 1 << 5);
2067 rtl_patchphy(tp, 0x0d, 1 << 5);
2068 rtl_writephy(tp, 0x1f, 0x0000);
2069 }
2070
2071 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2072 {
2073 static const struct phy_reg phy_reg_init[] = {
2074 { 0x1f, 0x0001 },
2075 { 0x12, 0x2300 },
2076 { 0x03, 0x802f },
2077 { 0x02, 0x4f02 },
2078 { 0x01, 0x0409 },
2079 { 0x00, 0xf099 },
2080 { 0x04, 0x9800 },
2081 { 0x04, 0x9000 },
2082 { 0x1d, 0x3d98 },
2083 { 0x1f, 0x0002 },
2084 { 0x0c, 0x7eb8 },
2085 { 0x06, 0x0761 },
2086 { 0x1f, 0x0003 },
2087 { 0x16, 0x0f0a },
2088 { 0x1f, 0x0000 }
2089 };
2090
2091 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2092
2093 rtl_patchphy(tp, 0x16, 1 << 0);
2094 rtl_patchphy(tp, 0x14, 1 << 5);
2095 rtl_patchphy(tp, 0x0d, 1 << 5);
2096 rtl_writephy(tp, 0x1f, 0x0000);
2097 }
2098
2099 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2100 {
2101 static const struct phy_reg phy_reg_init[] = {
2102 { 0x1f, 0x0001 },
2103 { 0x12, 0x2300 },
2104 { 0x1d, 0x3d98 },
2105 { 0x1f, 0x0002 },
2106 { 0x0c, 0x7eb8 },
2107 { 0x06, 0x5461 },
2108 { 0x1f, 0x0003 },
2109 { 0x16, 0x0f0a },
2110 { 0x1f, 0x0000 }
2111 };
2112
2113 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2114
2115 rtl_patchphy(tp, 0x16, 1 << 0);
2116 rtl_patchphy(tp, 0x14, 1 << 5);
2117 rtl_patchphy(tp, 0x0d, 1 << 5);
2118 rtl_writephy(tp, 0x1f, 0x0000);
2119 }
2120
2121 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2122 {
2123 rtl8168c_3_hw_phy_config(tp);
2124 }
2125
2126 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2127 {
2128 static const struct phy_reg phy_reg_init_0[] = {
2129 /* Channel Estimation */
2130 { 0x1f, 0x0001 },
2131 { 0x06, 0x4064 },
2132 { 0x07, 0x2863 },
2133 { 0x08, 0x059c },
2134 { 0x09, 0x26b4 },
2135 { 0x0a, 0x6a19 },
2136 { 0x0b, 0xdcc8 },
2137 { 0x10, 0xf06d },
2138 { 0x14, 0x7f68 },
2139 { 0x18, 0x7fd9 },
2140 { 0x1c, 0xf0ff },
2141 { 0x1d, 0x3d9c },
2142 { 0x1f, 0x0003 },
2143 { 0x12, 0xf49f },
2144 { 0x13, 0x070b },
2145 { 0x1a, 0x05ad },
2146 { 0x14, 0x94c0 },
2147
2148 /*
2149 * Tx Error Issue
2150 * enhance line driver power
2151 */
2152 { 0x1f, 0x0002 },
2153 { 0x06, 0x5561 },
2154 { 0x1f, 0x0005 },
2155 { 0x05, 0x8332 },
2156 { 0x06, 0x5561 },
2157
2158 /*
2159 * Can not link to 1Gbps with bad cable
2160 * Decrease SNR threshold form 21.07dB to 19.04dB
2161 */
2162 { 0x1f, 0x0001 },
2163 { 0x17, 0x0cc0 },
2164
2165 { 0x1f, 0x0000 },
2166 { 0x0d, 0xf880 }
2167 };
2168 void __iomem *ioaddr = tp->mmio_addr;
2169
2170 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2171
2172 /*
2173 * Rx Error Issue
2174 * Fine Tune Switching regulator parameter
2175 */
2176 rtl_writephy(tp, 0x1f, 0x0002);
2177 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2178 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2179
2180 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2181 static const struct phy_reg phy_reg_init[] = {
2182 { 0x1f, 0x0002 },
2183 { 0x05, 0x669a },
2184 { 0x1f, 0x0005 },
2185 { 0x05, 0x8330 },
2186 { 0x06, 0x669a },
2187 { 0x1f, 0x0002 }
2188 };
2189 int val;
2190
2191 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2192
2193 val = rtl_readphy(tp, 0x0d);
2194
2195 if ((val & 0x00ff) != 0x006c) {
2196 static const u32 set[] = {
2197 0x0065, 0x0066, 0x0067, 0x0068,
2198 0x0069, 0x006a, 0x006b, 0x006c
2199 };
2200 int i;
2201
2202 rtl_writephy(tp, 0x1f, 0x0002);
2203
2204 val &= 0xff00;
2205 for (i = 0; i < ARRAY_SIZE(set); i++)
2206 rtl_writephy(tp, 0x0d, val | set[i]);
2207 }
2208 } else {
2209 static const struct phy_reg phy_reg_init[] = {
2210 { 0x1f, 0x0002 },
2211 { 0x05, 0x6662 },
2212 { 0x1f, 0x0005 },
2213 { 0x05, 0x8330 },
2214 { 0x06, 0x6662 }
2215 };
2216
2217 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2218 }
2219
2220 /* RSET couple improve */
2221 rtl_writephy(tp, 0x1f, 0x0002);
2222 rtl_patchphy(tp, 0x0d, 0x0300);
2223 rtl_patchphy(tp, 0x0f, 0x0010);
2224
2225 /* Fine tune PLL performance */
2226 rtl_writephy(tp, 0x1f, 0x0002);
2227 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2228 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2229
2230 rtl_writephy(tp, 0x1f, 0x0005);
2231 rtl_writephy(tp, 0x05, 0x001b);
2232 if ((rtl_readphy(tp, 0x06) != 0xbf00) ||
2233 (rtl_apply_firmware(tp, FIRMWARE_8168D_1) < 0)) {
2234 netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n");
2235 }
2236
2237 rtl_writephy(tp, 0x1f, 0x0000);
2238 }
2239
2240 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2241 {
2242 static const struct phy_reg phy_reg_init_0[] = {
2243 /* Channel Estimation */
2244 { 0x1f, 0x0001 },
2245 { 0x06, 0x4064 },
2246 { 0x07, 0x2863 },
2247 { 0x08, 0x059c },
2248 { 0x09, 0x26b4 },
2249 { 0x0a, 0x6a19 },
2250 { 0x0b, 0xdcc8 },
2251 { 0x10, 0xf06d },
2252 { 0x14, 0x7f68 },
2253 { 0x18, 0x7fd9 },
2254 { 0x1c, 0xf0ff },
2255 { 0x1d, 0x3d9c },
2256 { 0x1f, 0x0003 },
2257 { 0x12, 0xf49f },
2258 { 0x13, 0x070b },
2259 { 0x1a, 0x05ad },
2260 { 0x14, 0x94c0 },
2261
2262 /*
2263 * Tx Error Issue
2264 * enhance line driver power
2265 */
2266 { 0x1f, 0x0002 },
2267 { 0x06, 0x5561 },
2268 { 0x1f, 0x0005 },
2269 { 0x05, 0x8332 },
2270 { 0x06, 0x5561 },
2271
2272 /*
2273 * Can not link to 1Gbps with bad cable
2274 * Decrease SNR threshold form 21.07dB to 19.04dB
2275 */
2276 { 0x1f, 0x0001 },
2277 { 0x17, 0x0cc0 },
2278
2279 { 0x1f, 0x0000 },
2280 { 0x0d, 0xf880 }
2281 };
2282 void __iomem *ioaddr = tp->mmio_addr;
2283
2284 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2285
2286 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2287 static const struct phy_reg phy_reg_init[] = {
2288 { 0x1f, 0x0002 },
2289 { 0x05, 0x669a },
2290 { 0x1f, 0x0005 },
2291 { 0x05, 0x8330 },
2292 { 0x06, 0x669a },
2293
2294 { 0x1f, 0x0002 }
2295 };
2296 int val;
2297
2298 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2299
2300 val = rtl_readphy(tp, 0x0d);
2301 if ((val & 0x00ff) != 0x006c) {
2302 static const u32 set[] = {
2303 0x0065, 0x0066, 0x0067, 0x0068,
2304 0x0069, 0x006a, 0x006b, 0x006c
2305 };
2306 int i;
2307
2308 rtl_writephy(tp, 0x1f, 0x0002);
2309
2310 val &= 0xff00;
2311 for (i = 0; i < ARRAY_SIZE(set); i++)
2312 rtl_writephy(tp, 0x0d, val | set[i]);
2313 }
2314 } else {
2315 static const struct phy_reg phy_reg_init[] = {
2316 { 0x1f, 0x0002 },
2317 { 0x05, 0x2642 },
2318 { 0x1f, 0x0005 },
2319 { 0x05, 0x8330 },
2320 { 0x06, 0x2642 }
2321 };
2322
2323 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2324 }
2325
2326 /* Fine tune PLL performance */
2327 rtl_writephy(tp, 0x1f, 0x0002);
2328 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2329 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2330
2331 /* Switching regulator Slew rate */
2332 rtl_writephy(tp, 0x1f, 0x0002);
2333 rtl_patchphy(tp, 0x0f, 0x0017);
2334
2335 rtl_writephy(tp, 0x1f, 0x0005);
2336 rtl_writephy(tp, 0x05, 0x001b);
2337 if ((rtl_readphy(tp, 0x06) != 0xb300) ||
2338 (rtl_apply_firmware(tp, FIRMWARE_8168D_2) < 0)) {
2339 netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n");
2340 }
2341
2342 rtl_writephy(tp, 0x1f, 0x0000);
2343 }
2344
2345 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2346 {
2347 static const struct phy_reg phy_reg_init[] = {
2348 { 0x1f, 0x0002 },
2349 { 0x10, 0x0008 },
2350 { 0x0d, 0x006c },
2351
2352 { 0x1f, 0x0000 },
2353 { 0x0d, 0xf880 },
2354
2355 { 0x1f, 0x0001 },
2356 { 0x17, 0x0cc0 },
2357
2358 { 0x1f, 0x0001 },
2359 { 0x0b, 0xa4d8 },
2360 { 0x09, 0x281c },
2361 { 0x07, 0x2883 },
2362 { 0x0a, 0x6b35 },
2363 { 0x1d, 0x3da4 },
2364 { 0x1c, 0xeffd },
2365 { 0x14, 0x7f52 },
2366 { 0x18, 0x7fc6 },
2367 { 0x08, 0x0601 },
2368 { 0x06, 0x4063 },
2369 { 0x10, 0xf074 },
2370 { 0x1f, 0x0003 },
2371 { 0x13, 0x0789 },
2372 { 0x12, 0xf4bd },
2373 { 0x1a, 0x04fd },
2374 { 0x14, 0x84b0 },
2375 { 0x1f, 0x0000 },
2376 { 0x00, 0x9200 },
2377
2378 { 0x1f, 0x0005 },
2379 { 0x01, 0x0340 },
2380 { 0x1f, 0x0001 },
2381 { 0x04, 0x4000 },
2382 { 0x03, 0x1d21 },
2383 { 0x02, 0x0c32 },
2384 { 0x01, 0x0200 },
2385 { 0x00, 0x5554 },
2386 { 0x04, 0x4800 },
2387 { 0x04, 0x4000 },
2388 { 0x04, 0xf000 },
2389 { 0x03, 0xdf01 },
2390 { 0x02, 0xdf20 },
2391 { 0x01, 0x101a },
2392 { 0x00, 0xa0ff },
2393 { 0x04, 0xf800 },
2394 { 0x04, 0xf000 },
2395 { 0x1f, 0x0000 },
2396
2397 { 0x1f, 0x0007 },
2398 { 0x1e, 0x0023 },
2399 { 0x16, 0x0000 },
2400 { 0x1f, 0x0000 }
2401 };
2402
2403 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2404 }
2405
2406 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2407 {
2408 static const struct phy_reg phy_reg_init[] = {
2409 { 0x1f, 0x0001 },
2410 { 0x17, 0x0cc0 },
2411
2412 { 0x1f, 0x0007 },
2413 { 0x1e, 0x002d },
2414 { 0x18, 0x0040 },
2415 { 0x1f, 0x0000 }
2416 };
2417
2418 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2419 rtl_patchphy(tp, 0x0d, 1 << 5);
2420 }
2421
2422 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2423 {
2424 static const struct phy_reg phy_reg_init[] = {
2425 { 0x1f, 0x0003 },
2426 { 0x08, 0x441d },
2427 { 0x01, 0x9100 },
2428 { 0x1f, 0x0000 }
2429 };
2430
2431 rtl_writephy(tp, 0x1f, 0x0000);
2432 rtl_patchphy(tp, 0x11, 1 << 12);
2433 rtl_patchphy(tp, 0x19, 1 << 13);
2434 rtl_patchphy(tp, 0x10, 1 << 15);
2435
2436 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2437 }
2438
2439 static void rtl_hw_phy_config(struct net_device *dev)
2440 {
2441 struct rtl8169_private *tp = netdev_priv(dev);
2442
2443 rtl8169_print_mac_version(tp);
2444
2445 switch (tp->mac_version) {
2446 case RTL_GIGA_MAC_VER_01:
2447 break;
2448 case RTL_GIGA_MAC_VER_02:
2449 case RTL_GIGA_MAC_VER_03:
2450 rtl8169s_hw_phy_config(tp);
2451 break;
2452 case RTL_GIGA_MAC_VER_04:
2453 rtl8169sb_hw_phy_config(tp);
2454 break;
2455 case RTL_GIGA_MAC_VER_05:
2456 rtl8169scd_hw_phy_config(tp);
2457 break;
2458 case RTL_GIGA_MAC_VER_06:
2459 rtl8169sce_hw_phy_config(tp);
2460 break;
2461 case RTL_GIGA_MAC_VER_07:
2462 case RTL_GIGA_MAC_VER_08:
2463 case RTL_GIGA_MAC_VER_09:
2464 rtl8102e_hw_phy_config(tp);
2465 break;
2466 case RTL_GIGA_MAC_VER_11:
2467 rtl8168bb_hw_phy_config(tp);
2468 break;
2469 case RTL_GIGA_MAC_VER_12:
2470 rtl8168bef_hw_phy_config(tp);
2471 break;
2472 case RTL_GIGA_MAC_VER_17:
2473 rtl8168bef_hw_phy_config(tp);
2474 break;
2475 case RTL_GIGA_MAC_VER_18:
2476 rtl8168cp_1_hw_phy_config(tp);
2477 break;
2478 case RTL_GIGA_MAC_VER_19:
2479 rtl8168c_1_hw_phy_config(tp);
2480 break;
2481 case RTL_GIGA_MAC_VER_20:
2482 rtl8168c_2_hw_phy_config(tp);
2483 break;
2484 case RTL_GIGA_MAC_VER_21:
2485 rtl8168c_3_hw_phy_config(tp);
2486 break;
2487 case RTL_GIGA_MAC_VER_22:
2488 rtl8168c_4_hw_phy_config(tp);
2489 break;
2490 case RTL_GIGA_MAC_VER_23:
2491 case RTL_GIGA_MAC_VER_24:
2492 rtl8168cp_2_hw_phy_config(tp);
2493 break;
2494 case RTL_GIGA_MAC_VER_25:
2495 rtl8168d_1_hw_phy_config(tp);
2496 break;
2497 case RTL_GIGA_MAC_VER_26:
2498 rtl8168d_2_hw_phy_config(tp);
2499 break;
2500 case RTL_GIGA_MAC_VER_27:
2501 rtl8168d_3_hw_phy_config(tp);
2502 break;
2503 case RTL_GIGA_MAC_VER_28:
2504 rtl8168d_4_hw_phy_config(tp);
2505 break;
2506
2507 default:
2508 break;
2509 }
2510 }
2511
2512 static void rtl8169_phy_timer(unsigned long __opaque)
2513 {
2514 struct net_device *dev = (struct net_device *)__opaque;
2515 struct rtl8169_private *tp = netdev_priv(dev);
2516 struct timer_list *timer = &tp->timer;
2517 void __iomem *ioaddr = tp->mmio_addr;
2518 unsigned long timeout = RTL8169_PHY_TIMEOUT;
2519
2520 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
2521
2522 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
2523 return;
2524
2525 spin_lock_irq(&tp->lock);
2526
2527 if (tp->phy_reset_pending(tp)) {
2528 /*
2529 * A busy loop could burn quite a few cycles on nowadays CPU.
2530 * Let's delay the execution of the timer for a few ticks.
2531 */
2532 timeout = HZ/10;
2533 goto out_mod_timer;
2534 }
2535
2536 if (tp->link_ok(ioaddr))
2537 goto out_unlock;
2538
2539 netif_warn(tp, link, dev, "PHY reset until link up\n");
2540
2541 tp->phy_reset_enable(tp);
2542
2543 out_mod_timer:
2544 mod_timer(timer, jiffies + timeout);
2545 out_unlock:
2546 spin_unlock_irq(&tp->lock);
2547 }
2548
2549 static inline void rtl8169_delete_timer(struct net_device *dev)
2550 {
2551 struct rtl8169_private *tp = netdev_priv(dev);
2552 struct timer_list *timer = &tp->timer;
2553
2554 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
2555 return;
2556
2557 del_timer_sync(timer);
2558 }
2559
2560 static inline void rtl8169_request_timer(struct net_device *dev)
2561 {
2562 struct rtl8169_private *tp = netdev_priv(dev);
2563 struct timer_list *timer = &tp->timer;
2564
2565 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
2566 return;
2567
2568 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
2569 }
2570
2571 #ifdef CONFIG_NET_POLL_CONTROLLER
2572 /*
2573 * Polling 'interrupt' - used by things like netconsole to send skbs
2574 * without having to re-enable interrupts. It's not called while
2575 * the interrupt routine is executing.
2576 */
2577 static void rtl8169_netpoll(struct net_device *dev)
2578 {
2579 struct rtl8169_private *tp = netdev_priv(dev);
2580 struct pci_dev *pdev = tp->pci_dev;
2581
2582 disable_irq(pdev->irq);
2583 rtl8169_interrupt(pdev->irq, dev);
2584 enable_irq(pdev->irq);
2585 }
2586 #endif
2587
2588 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
2589 void __iomem *ioaddr)
2590 {
2591 iounmap(ioaddr);
2592 pci_release_regions(pdev);
2593 pci_clear_mwi(pdev);
2594 pci_disable_device(pdev);
2595 free_netdev(dev);
2596 }
2597
2598 static void rtl8169_phy_reset(struct net_device *dev,
2599 struct rtl8169_private *tp)
2600 {
2601 unsigned int i;
2602
2603 tp->phy_reset_enable(tp);
2604 for (i = 0; i < 100; i++) {
2605 if (!tp->phy_reset_pending(tp))
2606 return;
2607 msleep(1);
2608 }
2609 netif_err(tp, link, dev, "PHY reset failed\n");
2610 }
2611
2612 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
2613 {
2614 void __iomem *ioaddr = tp->mmio_addr;
2615
2616 rtl_hw_phy_config(dev);
2617
2618 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2619 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2620 RTL_W8(0x82, 0x01);
2621 }
2622
2623 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2624
2625 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
2626 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
2627
2628 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
2629 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2630 RTL_W8(0x82, 0x01);
2631 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
2632 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
2633 }
2634
2635 rtl8169_phy_reset(dev, tp);
2636
2637 /*
2638 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
2639 * only 8101. Don't panic.
2640 */
2641 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
2642
2643 if (RTL_R8(PHYstatus) & TBI_Enable)
2644 netif_info(tp, link, dev, "TBI auto-negotiating\n");
2645 }
2646
2647 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2648 {
2649 void __iomem *ioaddr = tp->mmio_addr;
2650 u32 high;
2651 u32 low;
2652
2653 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
2654 high = addr[4] | (addr[5] << 8);
2655
2656 spin_lock_irq(&tp->lock);
2657
2658 RTL_W8(Cfg9346, Cfg9346_Unlock);
2659
2660 RTL_W32(MAC4, high);
2661 RTL_R32(MAC4);
2662
2663 RTL_W32(MAC0, low);
2664 RTL_R32(MAC0);
2665
2666 RTL_W8(Cfg9346, Cfg9346_Lock);
2667
2668 spin_unlock_irq(&tp->lock);
2669 }
2670
2671 static int rtl_set_mac_address(struct net_device *dev, void *p)
2672 {
2673 struct rtl8169_private *tp = netdev_priv(dev);
2674 struct sockaddr *addr = p;
2675
2676 if (!is_valid_ether_addr(addr->sa_data))
2677 return -EADDRNOTAVAIL;
2678
2679 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2680
2681 rtl_rar_set(tp, dev->dev_addr);
2682
2683 return 0;
2684 }
2685
2686 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2687 {
2688 struct rtl8169_private *tp = netdev_priv(dev);
2689 struct mii_ioctl_data *data = if_mii(ifr);
2690
2691 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
2692 }
2693
2694 static int rtl_xmii_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2695 {
2696 switch (cmd) {
2697 case SIOCGMIIPHY:
2698 data->phy_id = 32; /* Internal PHY */
2699 return 0;
2700
2701 case SIOCGMIIREG:
2702 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
2703 return 0;
2704
2705 case SIOCSMIIREG:
2706 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
2707 return 0;
2708 }
2709 return -EOPNOTSUPP;
2710 }
2711
2712 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2713 {
2714 return -EOPNOTSUPP;
2715 }
2716
2717 static const struct rtl_cfg_info {
2718 void (*hw_start)(struct net_device *);
2719 unsigned int region;
2720 unsigned int align;
2721 u16 intr_event;
2722 u16 napi_event;
2723 unsigned features;
2724 u8 default_ver;
2725 } rtl_cfg_infos [] = {
2726 [RTL_CFG_0] = {
2727 .hw_start = rtl_hw_start_8169,
2728 .region = 1,
2729 .align = 0,
2730 .intr_event = SYSErr | LinkChg | RxOverflow |
2731 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2732 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2733 .features = RTL_FEATURE_GMII,
2734 .default_ver = RTL_GIGA_MAC_VER_01,
2735 },
2736 [RTL_CFG_1] = {
2737 .hw_start = rtl_hw_start_8168,
2738 .region = 2,
2739 .align = 8,
2740 .intr_event = SYSErr | LinkChg | RxOverflow |
2741 TxErr | TxOK | RxOK | RxErr,
2742 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
2743 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
2744 .default_ver = RTL_GIGA_MAC_VER_11,
2745 },
2746 [RTL_CFG_2] = {
2747 .hw_start = rtl_hw_start_8101,
2748 .region = 2,
2749 .align = 8,
2750 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
2751 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2752 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2753 .features = RTL_FEATURE_MSI,
2754 .default_ver = RTL_GIGA_MAC_VER_13,
2755 }
2756 };
2757
2758 /* Cfg9346_Unlock assumed. */
2759 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
2760 const struct rtl_cfg_info *cfg)
2761 {
2762 unsigned msi = 0;
2763 u8 cfg2;
2764
2765 cfg2 = RTL_R8(Config2) & ~MSIEnable;
2766 if (cfg->features & RTL_FEATURE_MSI) {
2767 if (pci_enable_msi(pdev)) {
2768 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
2769 } else {
2770 cfg2 |= MSIEnable;
2771 msi = RTL_FEATURE_MSI;
2772 }
2773 }
2774 RTL_W8(Config2, cfg2);
2775 return msi;
2776 }
2777
2778 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
2779 {
2780 if (tp->features & RTL_FEATURE_MSI) {
2781 pci_disable_msi(pdev);
2782 tp->features &= ~RTL_FEATURE_MSI;
2783 }
2784 }
2785
2786 static const struct net_device_ops rtl8169_netdev_ops = {
2787 .ndo_open = rtl8169_open,
2788 .ndo_stop = rtl8169_close,
2789 .ndo_get_stats = rtl8169_get_stats,
2790 .ndo_start_xmit = rtl8169_start_xmit,
2791 .ndo_tx_timeout = rtl8169_tx_timeout,
2792 .ndo_validate_addr = eth_validate_addr,
2793 .ndo_change_mtu = rtl8169_change_mtu,
2794 .ndo_set_mac_address = rtl_set_mac_address,
2795 .ndo_do_ioctl = rtl8169_ioctl,
2796 .ndo_set_multicast_list = rtl_set_rx_mode,
2797 #ifdef CONFIG_R8169_VLAN
2798 .ndo_vlan_rx_register = rtl8169_vlan_rx_register,
2799 #endif
2800 #ifdef CONFIG_NET_POLL_CONTROLLER
2801 .ndo_poll_controller = rtl8169_netpoll,
2802 #endif
2803
2804 };
2805
2806 static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
2807 {
2808 struct mdio_ops *ops = &tp->mdio_ops;
2809
2810 switch (tp->mac_version) {
2811 case RTL_GIGA_MAC_VER_27:
2812 ops->write = r8168dp_1_mdio_write;
2813 ops->read = r8168dp_1_mdio_read;
2814 break;
2815 case RTL_GIGA_MAC_VER_28:
2816 ops->write = r8168dp_2_mdio_write;
2817 ops->read = r8168dp_2_mdio_read;
2818 break;
2819 default:
2820 ops->write = r8169_mdio_write;
2821 ops->read = r8169_mdio_read;
2822 break;
2823 }
2824 }
2825
2826 static void r810x_phy_power_down(struct rtl8169_private *tp)
2827 {
2828 rtl_writephy(tp, 0x1f, 0x0000);
2829 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
2830 }
2831
2832 static void r810x_phy_power_up(struct rtl8169_private *tp)
2833 {
2834 rtl_writephy(tp, 0x1f, 0x0000);
2835 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
2836 }
2837
2838 static void r810x_pll_power_down(struct rtl8169_private *tp)
2839 {
2840 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
2841 rtl_writephy(tp, 0x1f, 0x0000);
2842 rtl_writephy(tp, MII_BMCR, 0x0000);
2843 return;
2844 }
2845
2846 r810x_phy_power_down(tp);
2847 }
2848
2849 static void r810x_pll_power_up(struct rtl8169_private *tp)
2850 {
2851 r810x_phy_power_up(tp);
2852 }
2853
2854 static void r8168_phy_power_up(struct rtl8169_private *tp)
2855 {
2856 rtl_writephy(tp, 0x1f, 0x0000);
2857 rtl_writephy(tp, 0x0e, 0x0000);
2858 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
2859 }
2860
2861 static void r8168_phy_power_down(struct rtl8169_private *tp)
2862 {
2863 rtl_writephy(tp, 0x1f, 0x0000);
2864 rtl_writephy(tp, 0x0e, 0x0200);
2865 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
2866 }
2867
2868 static void r8168_pll_power_down(struct rtl8169_private *tp)
2869 {
2870 void __iomem *ioaddr = tp->mmio_addr;
2871
2872 if (((tp->mac_version == RTL_GIGA_MAC_VER_27) ||
2873 (tp->mac_version == RTL_GIGA_MAC_VER_28)) &&
2874 (ocp_read(tp, 0x0f, 0x0010) & 0x00008000)) {
2875 return;
2876 }
2877
2878 if (((tp->mac_version == RTL_GIGA_MAC_VER_23) ||
2879 (tp->mac_version == RTL_GIGA_MAC_VER_24)) &&
2880 (RTL_R16(CPlusCmd) & ASF)) {
2881 return;
2882 }
2883
2884 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
2885 rtl_writephy(tp, 0x1f, 0x0000);
2886 rtl_writephy(tp, MII_BMCR, 0x0000);
2887
2888 RTL_W32(RxConfig, RTL_R32(RxConfig) |
2889 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
2890 return;
2891 }
2892
2893 r8168_phy_power_down(tp);
2894
2895 switch (tp->mac_version) {
2896 case RTL_GIGA_MAC_VER_25:
2897 case RTL_GIGA_MAC_VER_26:
2898 case RTL_GIGA_MAC_VER_27:
2899 case RTL_GIGA_MAC_VER_28:
2900 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
2901 break;
2902 }
2903 }
2904
2905 static void r8168_pll_power_up(struct rtl8169_private *tp)
2906 {
2907 void __iomem *ioaddr = tp->mmio_addr;
2908
2909 if (((tp->mac_version == RTL_GIGA_MAC_VER_27) ||
2910 (tp->mac_version == RTL_GIGA_MAC_VER_28)) &&
2911 (ocp_read(tp, 0x0f, 0x0010) & 0x00008000)) {
2912 return;
2913 }
2914
2915 switch (tp->mac_version) {
2916 case RTL_GIGA_MAC_VER_25:
2917 case RTL_GIGA_MAC_VER_26:
2918 case RTL_GIGA_MAC_VER_27:
2919 case RTL_GIGA_MAC_VER_28:
2920 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
2921 break;
2922 }
2923
2924 r8168_phy_power_up(tp);
2925 }
2926
2927 static void rtl_pll_power_op(struct rtl8169_private *tp,
2928 void (*op)(struct rtl8169_private *))
2929 {
2930 if (op)
2931 op(tp);
2932 }
2933
2934 static void rtl_pll_power_down(struct rtl8169_private *tp)
2935 {
2936 rtl_pll_power_op(tp, tp->pll_power_ops.down);
2937 }
2938
2939 static void rtl_pll_power_up(struct rtl8169_private *tp)
2940 {
2941 rtl_pll_power_op(tp, tp->pll_power_ops.up);
2942 }
2943
2944 static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
2945 {
2946 struct pll_power_ops *ops = &tp->pll_power_ops;
2947
2948 switch (tp->mac_version) {
2949 case RTL_GIGA_MAC_VER_07:
2950 case RTL_GIGA_MAC_VER_08:
2951 case RTL_GIGA_MAC_VER_09:
2952 case RTL_GIGA_MAC_VER_10:
2953 case RTL_GIGA_MAC_VER_16:
2954 ops->down = r810x_pll_power_down;
2955 ops->up = r810x_pll_power_up;
2956 break;
2957
2958 case RTL_GIGA_MAC_VER_11:
2959 case RTL_GIGA_MAC_VER_12:
2960 case RTL_GIGA_MAC_VER_17:
2961 case RTL_GIGA_MAC_VER_18:
2962 case RTL_GIGA_MAC_VER_19:
2963 case RTL_GIGA_MAC_VER_20:
2964 case RTL_GIGA_MAC_VER_21:
2965 case RTL_GIGA_MAC_VER_22:
2966 case RTL_GIGA_MAC_VER_23:
2967 case RTL_GIGA_MAC_VER_24:
2968 case RTL_GIGA_MAC_VER_25:
2969 case RTL_GIGA_MAC_VER_26:
2970 case RTL_GIGA_MAC_VER_27:
2971 case RTL_GIGA_MAC_VER_28:
2972 ops->down = r8168_pll_power_down;
2973 ops->up = r8168_pll_power_up;
2974 break;
2975
2976 default:
2977 ops->down = NULL;
2978 ops->up = NULL;
2979 break;
2980 }
2981 }
2982
2983 static int __devinit
2984 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2985 {
2986 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
2987 const unsigned int region = cfg->region;
2988 struct rtl8169_private *tp;
2989 struct mii_if_info *mii;
2990 struct net_device *dev;
2991 void __iomem *ioaddr;
2992 unsigned int i;
2993 int rc;
2994
2995 if (netif_msg_drv(&debug)) {
2996 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
2997 MODULENAME, RTL8169_VERSION);
2998 }
2999
3000 dev = alloc_etherdev(sizeof (*tp));
3001 if (!dev) {
3002 if (netif_msg_drv(&debug))
3003 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
3004 rc = -ENOMEM;
3005 goto out;
3006 }
3007
3008 SET_NETDEV_DEV(dev, &pdev->dev);
3009 dev->netdev_ops = &rtl8169_netdev_ops;
3010 tp = netdev_priv(dev);
3011 tp->dev = dev;
3012 tp->pci_dev = pdev;
3013 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
3014
3015 mii = &tp->mii;
3016 mii->dev = dev;
3017 mii->mdio_read = rtl_mdio_read;
3018 mii->mdio_write = rtl_mdio_write;
3019 mii->phy_id_mask = 0x1f;
3020 mii->reg_num_mask = 0x1f;
3021 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3022
3023 /* enable device (incl. PCI PM wakeup and hotplug setup) */
3024 rc = pci_enable_device(pdev);
3025 if (rc < 0) {
3026 netif_err(tp, probe, dev, "enable failure\n");
3027 goto err_out_free_dev_1;
3028 }
3029
3030 if (pci_set_mwi(pdev) < 0)
3031 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
3032
3033 /* make sure PCI base addr 1 is MMIO */
3034 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
3035 netif_err(tp, probe, dev,
3036 "region #%d not an MMIO resource, aborting\n",
3037 region);
3038 rc = -ENODEV;
3039 goto err_out_mwi_2;
3040 }
3041
3042 /* check for weird/broken PCI region reporting */
3043 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
3044 netif_err(tp, probe, dev,
3045 "Invalid PCI region size(s), aborting\n");
3046 rc = -ENODEV;
3047 goto err_out_mwi_2;
3048 }
3049
3050 rc = pci_request_regions(pdev, MODULENAME);
3051 if (rc < 0) {
3052 netif_err(tp, probe, dev, "could not request regions\n");
3053 goto err_out_mwi_2;
3054 }
3055
3056 tp->cp_cmd = RxChkSum;
3057
3058 if ((sizeof(dma_addr_t) > 4) &&
3059 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
3060 tp->cp_cmd |= PCIDAC;
3061 dev->features |= NETIF_F_HIGHDMA;
3062 } else {
3063 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3064 if (rc < 0) {
3065 netif_err(tp, probe, dev, "DMA configuration failed\n");
3066 goto err_out_free_res_3;
3067 }
3068 }
3069
3070 /* ioremap MMIO region */
3071 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
3072 if (!ioaddr) {
3073 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
3074 rc = -EIO;
3075 goto err_out_free_res_3;
3076 }
3077
3078 tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3079 if (!tp->pcie_cap)
3080 netif_info(tp, probe, dev, "no PCI Express capability\n");
3081
3082 RTL_W16(IntrMask, 0x0000);
3083
3084 /* Soft reset the chip. */
3085 RTL_W8(ChipCmd, CmdReset);
3086
3087 /* Check that the chip has finished the reset. */
3088 for (i = 0; i < 100; i++) {
3089 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3090 break;
3091 msleep_interruptible(1);
3092 }
3093
3094 RTL_W16(IntrStatus, 0xffff);
3095
3096 pci_set_master(pdev);
3097
3098 /* Identify chip attached to board */
3099 rtl8169_get_mac_version(tp, ioaddr);
3100
3101 rtl_init_mdio_ops(tp);
3102 rtl_init_pll_power_ops(tp);
3103
3104 /* Use appropriate default if unknown */
3105 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
3106 netif_notice(tp, probe, dev,
3107 "unknown MAC, using family default\n");
3108 tp->mac_version = cfg->default_ver;
3109 }
3110
3111 rtl8169_print_mac_version(tp);
3112
3113 for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
3114 if (tp->mac_version == rtl_chip_info[i].mac_version)
3115 break;
3116 }
3117 if (i == ARRAY_SIZE(rtl_chip_info)) {
3118 dev_err(&pdev->dev,
3119 "driver bug, MAC version not found in rtl_chip_info\n");
3120 goto err_out_msi_4;
3121 }
3122 tp->chipset = i;
3123
3124 RTL_W8(Cfg9346, Cfg9346_Unlock);
3125 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
3126 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
3127 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3128 tp->features |= RTL_FEATURE_WOL;
3129 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3130 tp->features |= RTL_FEATURE_WOL;
3131 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
3132 RTL_W8(Cfg9346, Cfg9346_Lock);
3133
3134 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
3135 (RTL_R8(PHYstatus) & TBI_Enable)) {
3136 tp->set_speed = rtl8169_set_speed_tbi;
3137 tp->get_settings = rtl8169_gset_tbi;
3138 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3139 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3140 tp->link_ok = rtl8169_tbi_link_ok;
3141 tp->do_ioctl = rtl_tbi_ioctl;
3142
3143 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
3144 } else {
3145 tp->set_speed = rtl8169_set_speed_xmii;
3146 tp->get_settings = rtl8169_gset_xmii;
3147 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3148 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3149 tp->link_ok = rtl8169_xmii_link_ok;
3150 tp->do_ioctl = rtl_xmii_ioctl;
3151 }
3152
3153 spin_lock_init(&tp->lock);
3154
3155 tp->mmio_addr = ioaddr;
3156
3157 /* Get MAC address */
3158 for (i = 0; i < MAC_ADDR_LEN; i++)
3159 dev->dev_addr[i] = RTL_R8(MAC0 + i);
3160 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3161
3162 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
3163 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3164 dev->irq = pdev->irq;
3165 dev->base_addr = (unsigned long) ioaddr;
3166
3167 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
3168
3169 #ifdef CONFIG_R8169_VLAN
3170 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3171 #endif
3172 dev->features |= NETIF_F_GRO;
3173
3174 tp->intr_mask = 0xffff;
3175 tp->hw_start = cfg->hw_start;
3176 tp->intr_event = cfg->intr_event;
3177 tp->napi_event = cfg->napi_event;
3178
3179 init_timer(&tp->timer);
3180 tp->timer.data = (unsigned long) dev;
3181 tp->timer.function = rtl8169_phy_timer;
3182
3183 rc = register_netdev(dev);
3184 if (rc < 0)
3185 goto err_out_msi_4;
3186
3187 pci_set_drvdata(pdev, dev);
3188
3189 netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
3190 rtl_chip_info[tp->chipset].name,
3191 dev->base_addr, dev->dev_addr,
3192 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
3193
3194 if ((tp->mac_version == RTL_GIGA_MAC_VER_27) ||
3195 (tp->mac_version == RTL_GIGA_MAC_VER_28)) {
3196 rtl8168_driver_start(tp);
3197 }
3198
3199 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
3200
3201 if (pci_dev_run_wake(pdev))
3202 pm_runtime_put_noidle(&pdev->dev);
3203
3204 netif_carrier_off(dev);
3205
3206 out:
3207 return rc;
3208
3209 err_out_msi_4:
3210 rtl_disable_msi(pdev, tp);
3211 iounmap(ioaddr);
3212 err_out_free_res_3:
3213 pci_release_regions(pdev);
3214 err_out_mwi_2:
3215 pci_clear_mwi(pdev);
3216 pci_disable_device(pdev);
3217 err_out_free_dev_1:
3218 free_netdev(dev);
3219 goto out;
3220 }
3221
3222 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
3223 {
3224 struct net_device *dev = pci_get_drvdata(pdev);
3225 struct rtl8169_private *tp = netdev_priv(dev);
3226
3227 if ((tp->mac_version == RTL_GIGA_MAC_VER_27) ||
3228 (tp->mac_version == RTL_GIGA_MAC_VER_28)) {
3229 rtl8168_driver_stop(tp);
3230 }
3231
3232 cancel_delayed_work_sync(&tp->task);
3233
3234 rtl_release_firmware(tp);
3235
3236 unregister_netdev(dev);
3237
3238 if (pci_dev_run_wake(pdev))
3239 pm_runtime_get_noresume(&pdev->dev);
3240
3241 /* restore original MAC address */
3242 rtl_rar_set(tp, dev->perm_addr);
3243
3244 rtl_disable_msi(pdev, tp);
3245 rtl8169_release_board(pdev, dev, tp->mmio_addr);
3246 pci_set_drvdata(pdev, NULL);
3247 }
3248
3249 static int rtl8169_open(struct net_device *dev)
3250 {
3251 struct rtl8169_private *tp = netdev_priv(dev);
3252 void __iomem *ioaddr = tp->mmio_addr;
3253 struct pci_dev *pdev = tp->pci_dev;
3254 int retval = -ENOMEM;
3255
3256 pm_runtime_get_sync(&pdev->dev);
3257
3258 /*
3259 * Rx and Tx desscriptors needs 256 bytes alignment.
3260 * dma_alloc_coherent provides more.
3261 */
3262 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
3263 &tp->TxPhyAddr, GFP_KERNEL);
3264 if (!tp->TxDescArray)
3265 goto err_pm_runtime_put;
3266
3267 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
3268 &tp->RxPhyAddr, GFP_KERNEL);
3269 if (!tp->RxDescArray)
3270 goto err_free_tx_0;
3271
3272 retval = rtl8169_init_ring(dev);
3273 if (retval < 0)
3274 goto err_free_rx_1;
3275
3276 INIT_DELAYED_WORK(&tp->task, NULL);
3277
3278 smp_mb();
3279
3280 retval = request_irq(dev->irq, rtl8169_interrupt,
3281 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
3282 dev->name, dev);
3283 if (retval < 0)
3284 goto err_release_ring_2;
3285
3286 napi_enable(&tp->napi);
3287
3288 rtl8169_init_phy(dev, tp);
3289
3290 /*
3291 * Pretend we are using VLANs; This bypasses a nasty bug where
3292 * Interrupts stop flowing on high load on 8110SCd controllers.
3293 */
3294 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3295 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | RxVlan);
3296
3297 rtl_pll_power_up(tp);
3298
3299 rtl_hw_start(dev);
3300
3301 rtl8169_request_timer(dev);
3302
3303 tp->saved_wolopts = 0;
3304 pm_runtime_put_noidle(&pdev->dev);
3305
3306 rtl8169_check_link_status(dev, tp, ioaddr);
3307 out:
3308 return retval;
3309
3310 err_release_ring_2:
3311 rtl8169_rx_clear(tp);
3312 err_free_rx_1:
3313 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
3314 tp->RxPhyAddr);
3315 tp->RxDescArray = NULL;
3316 err_free_tx_0:
3317 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
3318 tp->TxPhyAddr);
3319 tp->TxDescArray = NULL;
3320 err_pm_runtime_put:
3321 pm_runtime_put_noidle(&pdev->dev);
3322 goto out;
3323 }
3324
3325 static void rtl8169_hw_reset(struct rtl8169_private *tp)
3326 {
3327 void __iomem *ioaddr = tp->mmio_addr;
3328
3329 /* Disable interrupts */
3330 rtl8169_irq_mask_and_ack(ioaddr);
3331
3332 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3333 tp->mac_version == RTL_GIGA_MAC_VER_28) {
3334 while (RTL_R8(TxPoll) & NPQ)
3335 udelay(20);
3336
3337 }
3338
3339 /* Reset the chipset */
3340 RTL_W8(ChipCmd, CmdReset);
3341
3342 /* PCI commit */
3343 RTL_R8(ChipCmd);
3344 }
3345
3346 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
3347 {
3348 void __iomem *ioaddr = tp->mmio_addr;
3349 u32 cfg = rtl8169_rx_config;
3350
3351 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3352 RTL_W32(RxConfig, cfg);
3353
3354 /* Set DMA burst size and Interframe Gap Time */
3355 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3356 (InterFrameGap << TxInterFrameGapShift));
3357 }
3358
3359 static void rtl_hw_start(struct net_device *dev)
3360 {
3361 struct rtl8169_private *tp = netdev_priv(dev);
3362 void __iomem *ioaddr = tp->mmio_addr;
3363 unsigned int i;
3364
3365 /* Soft reset the chip. */
3366 RTL_W8(ChipCmd, CmdReset);
3367
3368 /* Check that the chip has finished the reset. */
3369 for (i = 0; i < 100; i++) {
3370 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3371 break;
3372 msleep_interruptible(1);
3373 }
3374
3375 tp->hw_start(dev);
3376
3377 netif_start_queue(dev);
3378 }
3379
3380
3381 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
3382 void __iomem *ioaddr)
3383 {
3384 /*
3385 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3386 * register to be written before TxDescAddrLow to work.
3387 * Switching from MMIO to I/O access fixes the issue as well.
3388 */
3389 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
3390 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
3391 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
3392 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
3393 }
3394
3395 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
3396 {
3397 u16 cmd;
3398
3399 cmd = RTL_R16(CPlusCmd);
3400 RTL_W16(CPlusCmd, cmd);
3401 return cmd;
3402 }
3403
3404 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
3405 {
3406 /* Low hurts. Let's disable the filtering. */
3407 RTL_W16(RxMaxSize, rx_buf_sz + 1);
3408 }
3409
3410 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
3411 {
3412 static const struct {
3413 u32 mac_version;
3414 u32 clk;
3415 u32 val;
3416 } cfg2_info [] = {
3417 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
3418 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
3419 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
3420 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3421 }, *p = cfg2_info;
3422 unsigned int i;
3423 u32 clk;
3424
3425 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
3426 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
3427 if ((p->mac_version == mac_version) && (p->clk == clk)) {
3428 RTL_W32(0x7c, p->val);
3429 break;
3430 }
3431 }
3432 }
3433
3434 static void rtl_hw_start_8169(struct net_device *dev)
3435 {
3436 struct rtl8169_private *tp = netdev_priv(dev);
3437 void __iomem *ioaddr = tp->mmio_addr;
3438 struct pci_dev *pdev = tp->pci_dev;
3439
3440 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
3441 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
3442 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
3443 }
3444
3445 RTL_W8(Cfg9346, Cfg9346_Unlock);
3446 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3447 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3448 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3449 (tp->mac_version == RTL_GIGA_MAC_VER_04))
3450 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3451
3452 RTL_W8(EarlyTxThres, NoEarlyTx);
3453
3454 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
3455
3456 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3457 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3458 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3459 (tp->mac_version == RTL_GIGA_MAC_VER_04))
3460 rtl_set_rx_tx_config_registers(tp);
3461
3462 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3463
3464 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3465 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
3466 dprintk("Set MAC Reg C+CR Offset 0xE0. "
3467 "Bit-3 and bit-14 MUST be 1\n");
3468 tp->cp_cmd |= (1 << 14);
3469 }
3470
3471 RTL_W16(CPlusCmd, tp->cp_cmd);
3472
3473 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
3474
3475 /*
3476 * Undocumented corner. Supposedly:
3477 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3478 */
3479 RTL_W16(IntrMitigate, 0x0000);
3480
3481 rtl_set_rx_tx_desc_registers(tp, ioaddr);
3482
3483 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
3484 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
3485 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
3486 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
3487 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3488 rtl_set_rx_tx_config_registers(tp);
3489 }
3490
3491 RTL_W8(Cfg9346, Cfg9346_Lock);
3492
3493 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3494 RTL_R8(IntrMask);
3495
3496 RTL_W32(RxMissed, 0);
3497
3498 rtl_set_rx_mode(dev);
3499
3500 /* no early-rx interrupts */
3501 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
3502
3503 /* Enable all known interrupts by setting the interrupt mask. */
3504 RTL_W16(IntrMask, tp->intr_event);
3505 }
3506
3507 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
3508 {
3509 struct net_device *dev = pci_get_drvdata(pdev);
3510 struct rtl8169_private *tp = netdev_priv(dev);
3511 int cap = tp->pcie_cap;
3512
3513 if (cap) {
3514 u16 ctl;
3515
3516 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
3517 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
3518 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
3519 }
3520 }
3521
3522 static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
3523 {
3524 u32 csi;
3525
3526 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
3527 rtl_csi_write(ioaddr, 0x070c, csi | bits);
3528 }
3529
3530 static void rtl_csi_access_enable_1(void __iomem *ioaddr)
3531 {
3532 rtl_csi_access_enable(ioaddr, 0x17000000);
3533 }
3534
3535 static void rtl_csi_access_enable_2(void __iomem *ioaddr)
3536 {
3537 rtl_csi_access_enable(ioaddr, 0x27000000);
3538 }
3539
3540 struct ephy_info {
3541 unsigned int offset;
3542 u16 mask;
3543 u16 bits;
3544 };
3545
3546 static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
3547 {
3548 u16 w;
3549
3550 while (len-- > 0) {
3551 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
3552 rtl_ephy_write(ioaddr, e->offset, w);
3553 e++;
3554 }
3555 }
3556
3557 static void rtl_disable_clock_request(struct pci_dev *pdev)
3558 {
3559 struct net_device *dev = pci_get_drvdata(pdev);
3560 struct rtl8169_private *tp = netdev_priv(dev);
3561 int cap = tp->pcie_cap;
3562
3563 if (cap) {
3564 u16 ctl;
3565
3566 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3567 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
3568 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3569 }
3570 }
3571
3572 static void rtl_enable_clock_request(struct pci_dev *pdev)
3573 {
3574 struct net_device *dev = pci_get_drvdata(pdev);
3575 struct rtl8169_private *tp = netdev_priv(dev);
3576 int cap = tp->pcie_cap;
3577
3578 if (cap) {
3579 u16 ctl;
3580
3581 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3582 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
3583 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3584 }
3585 }
3586
3587 #define R8168_CPCMD_QUIRK_MASK (\
3588 EnableBist | \
3589 Mac_dbgo_oe | \
3590 Force_half_dup | \
3591 Force_rxflow_en | \
3592 Force_txflow_en | \
3593 Cxpl_dbg_sel | \
3594 ASF | \
3595 PktCntrDisable | \
3596 Mac_dbgo_sel)
3597
3598 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
3599 {
3600 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3601
3602 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3603
3604 rtl_tx_performance_tweak(pdev,
3605 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3606 }
3607
3608 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
3609 {
3610 rtl_hw_start_8168bb(ioaddr, pdev);
3611
3612 RTL_W8(MaxTxPacketSize, TxPacketMax);
3613
3614 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
3615 }
3616
3617 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
3618 {
3619 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
3620
3621 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3622
3623 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3624
3625 rtl_disable_clock_request(pdev);
3626
3627 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3628 }
3629
3630 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
3631 {
3632 static const struct ephy_info e_info_8168cp[] = {
3633 { 0x01, 0, 0x0001 },
3634 { 0x02, 0x0800, 0x1000 },
3635 { 0x03, 0, 0x0042 },
3636 { 0x06, 0x0080, 0x0000 },
3637 { 0x07, 0, 0x2000 }
3638 };
3639
3640 rtl_csi_access_enable_2(ioaddr);
3641
3642 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
3643
3644 __rtl_hw_start_8168cp(ioaddr, pdev);
3645 }
3646
3647 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
3648 {
3649 rtl_csi_access_enable_2(ioaddr);
3650
3651 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3652
3653 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3654
3655 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3656 }
3657
3658 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
3659 {
3660 rtl_csi_access_enable_2(ioaddr);
3661
3662 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3663
3664 /* Magic. */
3665 RTL_W8(DBG_REG, 0x20);
3666
3667 RTL_W8(MaxTxPacketSize, TxPacketMax);
3668
3669 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3670
3671 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3672 }
3673
3674 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
3675 {
3676 static const struct ephy_info e_info_8168c_1[] = {
3677 { 0x02, 0x0800, 0x1000 },
3678 { 0x03, 0, 0x0002 },
3679 { 0x06, 0x0080, 0x0000 }
3680 };
3681
3682 rtl_csi_access_enable_2(ioaddr);
3683
3684 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
3685
3686 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
3687
3688 __rtl_hw_start_8168cp(ioaddr, pdev);
3689 }
3690
3691 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
3692 {
3693 static const struct ephy_info e_info_8168c_2[] = {
3694 { 0x01, 0, 0x0001 },
3695 { 0x03, 0x0400, 0x0220 }
3696 };
3697
3698 rtl_csi_access_enable_2(ioaddr);
3699
3700 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
3701
3702 __rtl_hw_start_8168cp(ioaddr, pdev);
3703 }
3704
3705 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
3706 {
3707 rtl_hw_start_8168c_2(ioaddr, pdev);
3708 }
3709
3710 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
3711 {
3712 rtl_csi_access_enable_2(ioaddr);
3713
3714 __rtl_hw_start_8168cp(ioaddr, pdev);
3715 }
3716
3717 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
3718 {
3719 rtl_csi_access_enable_2(ioaddr);
3720
3721 rtl_disable_clock_request(pdev);
3722
3723 RTL_W8(MaxTxPacketSize, TxPacketMax);
3724
3725 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3726
3727 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3728 }
3729
3730 static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
3731 {
3732 static const struct ephy_info e_info_8168d_4[] = {
3733 { 0x0b, ~0, 0x48 },
3734 { 0x19, 0x20, 0x50 },
3735 { 0x0c, ~0, 0x20 }
3736 };
3737 int i;
3738
3739 rtl_csi_access_enable_1(ioaddr);
3740
3741 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3742
3743 RTL_W8(MaxTxPacketSize, TxPacketMax);
3744
3745 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
3746 const struct ephy_info *e = e_info_8168d_4 + i;
3747 u16 w;
3748
3749 w = rtl_ephy_read(ioaddr, e->offset);
3750 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
3751 }
3752
3753 rtl_enable_clock_request(pdev);
3754 }
3755
3756 static void rtl_hw_start_8168(struct net_device *dev)
3757 {
3758 struct rtl8169_private *tp = netdev_priv(dev);
3759 void __iomem *ioaddr = tp->mmio_addr;
3760 struct pci_dev *pdev = tp->pci_dev;
3761
3762 RTL_W8(Cfg9346, Cfg9346_Unlock);
3763
3764 RTL_W8(MaxTxPacketSize, TxPacketMax);
3765
3766 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
3767
3768 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
3769
3770 RTL_W16(CPlusCmd, tp->cp_cmd);
3771
3772 RTL_W16(IntrMitigate, 0x5151);
3773
3774 /* Work around for RxFIFO overflow. */
3775 if (tp->mac_version == RTL_GIGA_MAC_VER_11 ||
3776 tp->mac_version == RTL_GIGA_MAC_VER_22) {
3777 tp->intr_event |= RxFIFOOver | PCSTimeout;
3778 tp->intr_event &= ~RxOverflow;
3779 }
3780
3781 rtl_set_rx_tx_desc_registers(tp, ioaddr);
3782
3783 rtl_set_rx_mode(dev);
3784
3785 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3786 (InterFrameGap << TxInterFrameGapShift));
3787
3788 RTL_R8(IntrMask);
3789
3790 switch (tp->mac_version) {
3791 case RTL_GIGA_MAC_VER_11:
3792 rtl_hw_start_8168bb(ioaddr, pdev);
3793 break;
3794
3795 case RTL_GIGA_MAC_VER_12:
3796 case RTL_GIGA_MAC_VER_17:
3797 rtl_hw_start_8168bef(ioaddr, pdev);
3798 break;
3799
3800 case RTL_GIGA_MAC_VER_18:
3801 rtl_hw_start_8168cp_1(ioaddr, pdev);
3802 break;
3803
3804 case RTL_GIGA_MAC_VER_19:
3805 rtl_hw_start_8168c_1(ioaddr, pdev);
3806 break;
3807
3808 case RTL_GIGA_MAC_VER_20:
3809 rtl_hw_start_8168c_2(ioaddr, pdev);
3810 break;
3811
3812 case RTL_GIGA_MAC_VER_21:
3813 rtl_hw_start_8168c_3(ioaddr, pdev);
3814 break;
3815
3816 case RTL_GIGA_MAC_VER_22:
3817 rtl_hw_start_8168c_4(ioaddr, pdev);
3818 break;
3819
3820 case RTL_GIGA_MAC_VER_23:
3821 rtl_hw_start_8168cp_2(ioaddr, pdev);
3822 break;
3823
3824 case RTL_GIGA_MAC_VER_24:
3825 rtl_hw_start_8168cp_3(ioaddr, pdev);
3826 break;
3827
3828 case RTL_GIGA_MAC_VER_25:
3829 case RTL_GIGA_MAC_VER_26:
3830 case RTL_GIGA_MAC_VER_27:
3831 rtl_hw_start_8168d(ioaddr, pdev);
3832 break;
3833
3834 case RTL_GIGA_MAC_VER_28:
3835 rtl_hw_start_8168d_4(ioaddr, pdev);
3836 break;
3837
3838 default:
3839 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
3840 dev->name, tp->mac_version);
3841 break;
3842 }
3843
3844 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3845
3846 RTL_W8(Cfg9346, Cfg9346_Lock);
3847
3848 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
3849
3850 RTL_W16(IntrMask, tp->intr_event);
3851 }
3852
3853 #define R810X_CPCMD_QUIRK_MASK (\
3854 EnableBist | \
3855 Mac_dbgo_oe | \
3856 Force_half_dup | \
3857 Force_rxflow_en | \
3858 Force_txflow_en | \
3859 Cxpl_dbg_sel | \
3860 ASF | \
3861 PktCntrDisable | \
3862 Mac_dbgo_sel)
3863
3864 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
3865 {
3866 static const struct ephy_info e_info_8102e_1[] = {
3867 { 0x01, 0, 0x6e65 },
3868 { 0x02, 0, 0x091f },
3869 { 0x03, 0, 0xc2f9 },
3870 { 0x06, 0, 0xafb5 },
3871 { 0x07, 0, 0x0e00 },
3872 { 0x19, 0, 0xec80 },
3873 { 0x01, 0, 0x2e65 },
3874 { 0x01, 0, 0x6e65 }
3875 };
3876 u8 cfg1;
3877
3878 rtl_csi_access_enable_2(ioaddr);
3879
3880 RTL_W8(DBG_REG, FIX_NAK_1);
3881
3882 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3883
3884 RTL_W8(Config1,
3885 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
3886 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3887
3888 cfg1 = RTL_R8(Config1);
3889 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
3890 RTL_W8(Config1, cfg1 & ~LEDS0);
3891
3892 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
3893 }
3894
3895 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
3896 {
3897 rtl_csi_access_enable_2(ioaddr);
3898
3899 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3900
3901 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
3902 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3903 }
3904
3905 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
3906 {
3907 rtl_hw_start_8102e_2(ioaddr, pdev);
3908
3909 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
3910 }
3911
3912 static void rtl_hw_start_8101(struct net_device *dev)
3913 {
3914 struct rtl8169_private *tp = netdev_priv(dev);
3915 void __iomem *ioaddr = tp->mmio_addr;
3916 struct pci_dev *pdev = tp->pci_dev;
3917
3918 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
3919 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
3920 int cap = tp->pcie_cap;
3921
3922 if (cap) {
3923 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
3924 PCI_EXP_DEVCTL_NOSNOOP_EN);
3925 }
3926 }
3927
3928 RTL_W8(Cfg9346, Cfg9346_Unlock);
3929
3930 switch (tp->mac_version) {
3931 case RTL_GIGA_MAC_VER_07:
3932 rtl_hw_start_8102e_1(ioaddr, pdev);
3933 break;
3934
3935 case RTL_GIGA_MAC_VER_08:
3936 rtl_hw_start_8102e_3(ioaddr, pdev);
3937 break;
3938
3939 case RTL_GIGA_MAC_VER_09:
3940 rtl_hw_start_8102e_2(ioaddr, pdev);
3941 break;
3942 }
3943
3944 RTL_W8(Cfg9346, Cfg9346_Lock);
3945
3946 RTL_W8(MaxTxPacketSize, TxPacketMax);
3947
3948 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
3949
3950 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
3951 RTL_W16(CPlusCmd, tp->cp_cmd);
3952
3953 RTL_W16(IntrMitigate, 0x0000);
3954
3955 rtl_set_rx_tx_desc_registers(tp, ioaddr);
3956
3957 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3958 rtl_set_rx_tx_config_registers(tp);
3959
3960 RTL_R8(IntrMask);
3961
3962 rtl_set_rx_mode(dev);
3963
3964 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
3965
3966 RTL_W16(IntrMask, tp->intr_event);
3967 }
3968
3969 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
3970 {
3971 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
3972 return -EINVAL;
3973
3974 dev->mtu = new_mtu;
3975 return 0;
3976 }
3977
3978 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
3979 {
3980 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
3981 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
3982 }
3983
3984 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
3985 void **data_buff, struct RxDesc *desc)
3986 {
3987 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
3988 DMA_FROM_DEVICE);
3989
3990 kfree(*data_buff);
3991 *data_buff = NULL;
3992 rtl8169_make_unusable_by_asic(desc);
3993 }
3994
3995 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
3996 {
3997 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
3998
3999 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
4000 }
4001
4002 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
4003 u32 rx_buf_sz)
4004 {
4005 desc->addr = cpu_to_le64(mapping);
4006 wmb();
4007 rtl8169_mark_to_asic(desc, rx_buf_sz);
4008 }
4009
4010 static inline void *rtl8169_align(void *data)
4011 {
4012 return (void *)ALIGN((long)data, 16);
4013 }
4014
4015 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
4016 struct RxDesc *desc)
4017 {
4018 void *data;
4019 dma_addr_t mapping;
4020 struct device *d = &tp->pci_dev->dev;
4021 struct net_device *dev = tp->dev;
4022 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
4023
4024 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
4025 if (!data)
4026 return NULL;
4027
4028 if (rtl8169_align(data) != data) {
4029 kfree(data);
4030 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
4031 if (!data)
4032 return NULL;
4033 }
4034
4035 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
4036 DMA_FROM_DEVICE);
4037 if (unlikely(dma_mapping_error(d, mapping))) {
4038 if (net_ratelimit())
4039 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
4040 goto err_out;
4041 }
4042
4043 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
4044 return data;
4045
4046 err_out:
4047 kfree(data);
4048 return NULL;
4049 }
4050
4051 static void rtl8169_rx_clear(struct rtl8169_private *tp)
4052 {
4053 unsigned int i;
4054
4055 for (i = 0; i < NUM_RX_DESC; i++) {
4056 if (tp->Rx_databuff[i]) {
4057 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
4058 tp->RxDescArray + i);
4059 }
4060 }
4061 }
4062
4063 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
4064 {
4065 desc->opts1 |= cpu_to_le32(RingEnd);
4066 }
4067
4068 static int rtl8169_rx_fill(struct rtl8169_private *tp)
4069 {
4070 unsigned int i;
4071
4072 for (i = 0; i < NUM_RX_DESC; i++) {
4073 void *data;
4074
4075 if (tp->Rx_databuff[i])
4076 continue;
4077
4078 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
4079 if (!data) {
4080 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
4081 goto err_out;
4082 }
4083 tp->Rx_databuff[i] = data;
4084 }
4085
4086 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4087 return 0;
4088
4089 err_out:
4090 rtl8169_rx_clear(tp);
4091 return -ENOMEM;
4092 }
4093
4094 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4095 {
4096 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
4097 }
4098
4099 static int rtl8169_init_ring(struct net_device *dev)
4100 {
4101 struct rtl8169_private *tp = netdev_priv(dev);
4102
4103 rtl8169_init_ring_indexes(tp);
4104
4105 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
4106 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
4107
4108 return rtl8169_rx_fill(tp);
4109 }
4110
4111 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
4112 struct TxDesc *desc)
4113 {
4114 unsigned int len = tx_skb->len;
4115
4116 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
4117
4118 desc->opts1 = 0x00;
4119 desc->opts2 = 0x00;
4120 desc->addr = 0x00;
4121 tx_skb->len = 0;
4122 }
4123
4124 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4125 unsigned int n)
4126 {
4127 unsigned int i;
4128
4129 for (i = 0; i < n; i++) {
4130 unsigned int entry = (start + i) % NUM_TX_DESC;
4131 struct ring_info *tx_skb = tp->tx_skb + entry;
4132 unsigned int len = tx_skb->len;
4133
4134 if (len) {
4135 struct sk_buff *skb = tx_skb->skb;
4136
4137 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4138 tp->TxDescArray + entry);
4139 if (skb) {
4140 tp->dev->stats.tx_dropped++;
4141 dev_kfree_skb(skb);
4142 tx_skb->skb = NULL;
4143 }
4144 }
4145 }
4146 }
4147
4148 static void rtl8169_tx_clear(struct rtl8169_private *tp)
4149 {
4150 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
4151 tp->cur_tx = tp->dirty_tx = 0;
4152 }
4153
4154 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
4155 {
4156 struct rtl8169_private *tp = netdev_priv(dev);
4157
4158 PREPARE_DELAYED_WORK(&tp->task, task);
4159 schedule_delayed_work(&tp->task, 4);
4160 }
4161
4162 static void rtl8169_wait_for_quiescence(struct net_device *dev)
4163 {
4164 struct rtl8169_private *tp = netdev_priv(dev);
4165 void __iomem *ioaddr = tp->mmio_addr;
4166
4167 synchronize_irq(dev->irq);
4168
4169 /* Wait for any pending NAPI task to complete */
4170 napi_disable(&tp->napi);
4171
4172 rtl8169_irq_mask_and_ack(ioaddr);
4173
4174 tp->intr_mask = 0xffff;
4175 RTL_W16(IntrMask, tp->intr_event);
4176 napi_enable(&tp->napi);
4177 }
4178
4179 static void rtl8169_reinit_task(struct work_struct *work)
4180 {
4181 struct rtl8169_private *tp =
4182 container_of(work, struct rtl8169_private, task.work);
4183 struct net_device *dev = tp->dev;
4184 int ret;
4185
4186 rtnl_lock();
4187
4188 if (!netif_running(dev))
4189 goto out_unlock;
4190
4191 rtl8169_wait_for_quiescence(dev);
4192 rtl8169_close(dev);
4193
4194 ret = rtl8169_open(dev);
4195 if (unlikely(ret < 0)) {
4196 if (net_ratelimit())
4197 netif_err(tp, drv, dev,
4198 "reinit failure (status = %d). Rescheduling\n",
4199 ret);
4200 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4201 }
4202
4203 out_unlock:
4204 rtnl_unlock();
4205 }
4206
4207 static void rtl8169_reset_task(struct work_struct *work)
4208 {
4209 struct rtl8169_private *tp =
4210 container_of(work, struct rtl8169_private, task.work);
4211 struct net_device *dev = tp->dev;
4212
4213 rtnl_lock();
4214
4215 if (!netif_running(dev))
4216 goto out_unlock;
4217
4218 rtl8169_wait_for_quiescence(dev);
4219
4220 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
4221 rtl8169_tx_clear(tp);
4222
4223 if (tp->dirty_rx == tp->cur_rx) {
4224 rtl8169_init_ring_indexes(tp);
4225 rtl_hw_start(dev);
4226 netif_wake_queue(dev);
4227 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
4228 } else {
4229 if (net_ratelimit())
4230 netif_emerg(tp, intr, dev, "Rx buffers shortage\n");
4231 rtl8169_schedule_work(dev, rtl8169_reset_task);
4232 }
4233
4234 out_unlock:
4235 rtnl_unlock();
4236 }
4237
4238 static void rtl8169_tx_timeout(struct net_device *dev)
4239 {
4240 struct rtl8169_private *tp = netdev_priv(dev);
4241
4242 rtl8169_hw_reset(tp);
4243
4244 /* Let's wait a bit while any (async) irq lands on */
4245 rtl8169_schedule_work(dev, rtl8169_reset_task);
4246 }
4247
4248 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4249 u32 opts1)
4250 {
4251 struct skb_shared_info *info = skb_shinfo(skb);
4252 unsigned int cur_frag, entry;
4253 struct TxDesc * uninitialized_var(txd);
4254 struct device *d = &tp->pci_dev->dev;
4255
4256 entry = tp->cur_tx;
4257 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4258 skb_frag_t *frag = info->frags + cur_frag;
4259 dma_addr_t mapping;
4260 u32 status, len;
4261 void *addr;
4262
4263 entry = (entry + 1) % NUM_TX_DESC;
4264
4265 txd = tp->TxDescArray + entry;
4266 len = frag->size;
4267 addr = ((void *) page_address(frag->page)) + frag->page_offset;
4268 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
4269 if (unlikely(dma_mapping_error(d, mapping))) {
4270 if (net_ratelimit())
4271 netif_err(tp, drv, tp->dev,
4272 "Failed to map TX fragments DMA!\n");
4273 goto err_out;
4274 }
4275
4276 /* anti gcc 2.95.3 bugware (sic) */
4277 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4278
4279 txd->opts1 = cpu_to_le32(status);
4280 txd->addr = cpu_to_le64(mapping);
4281
4282 tp->tx_skb[entry].len = len;
4283 }
4284
4285 if (cur_frag) {
4286 tp->tx_skb[entry].skb = skb;
4287 txd->opts1 |= cpu_to_le32(LastFrag);
4288 }
4289
4290 return cur_frag;
4291
4292 err_out:
4293 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4294 return -EIO;
4295 }
4296
4297 static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
4298 {
4299 if (dev->features & NETIF_F_TSO) {
4300 u32 mss = skb_shinfo(skb)->gso_size;
4301
4302 if (mss)
4303 return LargeSend | ((mss & MSSMask) << MSSShift);
4304 }
4305 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4306 const struct iphdr *ip = ip_hdr(skb);
4307
4308 if (ip->protocol == IPPROTO_TCP)
4309 return IPCS | TCPCS;
4310 else if (ip->protocol == IPPROTO_UDP)
4311 return IPCS | UDPCS;
4312 WARN_ON(1); /* we need a WARN() */
4313 }
4314 return 0;
4315 }
4316
4317 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4318 struct net_device *dev)
4319 {
4320 struct rtl8169_private *tp = netdev_priv(dev);
4321 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
4322 struct TxDesc *txd = tp->TxDescArray + entry;
4323 void __iomem *ioaddr = tp->mmio_addr;
4324 struct device *d = &tp->pci_dev->dev;
4325 dma_addr_t mapping;
4326 u32 status, len;
4327 u32 opts1;
4328 int frags;
4329
4330 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
4331 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
4332 goto err_stop_0;
4333 }
4334
4335 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
4336 goto err_stop_0;
4337
4338 len = skb_headlen(skb);
4339 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
4340 if (unlikely(dma_mapping_error(d, mapping))) {
4341 if (net_ratelimit())
4342 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
4343 goto err_dma_0;
4344 }
4345
4346 tp->tx_skb[entry].len = len;
4347 txd->addr = cpu_to_le64(mapping);
4348 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
4349
4350 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
4351
4352 frags = rtl8169_xmit_frags(tp, skb, opts1);
4353 if (frags < 0)
4354 goto err_dma_1;
4355 else if (frags)
4356 opts1 |= FirstFrag;
4357 else {
4358 opts1 |= FirstFrag | LastFrag;
4359 tp->tx_skb[entry].skb = skb;
4360 }
4361
4362 wmb();
4363
4364 /* anti gcc 2.95.3 bugware (sic) */
4365 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4366 txd->opts1 = cpu_to_le32(status);
4367
4368 tp->cur_tx += frags + 1;
4369
4370 wmb();
4371
4372 RTL_W8(TxPoll, NPQ); /* set polling bit */
4373
4374 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
4375 netif_stop_queue(dev);
4376 smp_rmb();
4377 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
4378 netif_wake_queue(dev);
4379 }
4380
4381 return NETDEV_TX_OK;
4382
4383 err_dma_1:
4384 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
4385 err_dma_0:
4386 dev_kfree_skb(skb);
4387 dev->stats.tx_dropped++;
4388 return NETDEV_TX_OK;
4389
4390 err_stop_0:
4391 netif_stop_queue(dev);
4392 dev->stats.tx_dropped++;
4393 return NETDEV_TX_BUSY;
4394 }
4395
4396 static void rtl8169_pcierr_interrupt(struct net_device *dev)
4397 {
4398 struct rtl8169_private *tp = netdev_priv(dev);
4399 struct pci_dev *pdev = tp->pci_dev;
4400 u16 pci_status, pci_cmd;
4401
4402 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4403 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
4404
4405 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
4406 pci_cmd, pci_status);
4407
4408 /*
4409 * The recovery sequence below admits a very elaborated explanation:
4410 * - it seems to work;
4411 * - I did not see what else could be done;
4412 * - it makes iop3xx happy.
4413 *
4414 * Feel free to adjust to your needs.
4415 */
4416 if (pdev->broken_parity_status)
4417 pci_cmd &= ~PCI_COMMAND_PARITY;
4418 else
4419 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
4420
4421 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
4422
4423 pci_write_config_word(pdev, PCI_STATUS,
4424 pci_status & (PCI_STATUS_DETECTED_PARITY |
4425 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
4426 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
4427
4428 /* The infamous DAC f*ckup only happens at boot time */
4429 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
4430 void __iomem *ioaddr = tp->mmio_addr;
4431
4432 netif_info(tp, intr, dev, "disabling PCI DAC\n");
4433 tp->cp_cmd &= ~PCIDAC;
4434 RTL_W16(CPlusCmd, tp->cp_cmd);
4435 dev->features &= ~NETIF_F_HIGHDMA;
4436 }
4437
4438 rtl8169_hw_reset(tp);
4439
4440 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4441 }
4442
4443 static void rtl8169_tx_interrupt(struct net_device *dev,
4444 struct rtl8169_private *tp,
4445 void __iomem *ioaddr)
4446 {
4447 unsigned int dirty_tx, tx_left;
4448
4449 dirty_tx = tp->dirty_tx;
4450 smp_rmb();
4451 tx_left = tp->cur_tx - dirty_tx;
4452
4453 while (tx_left > 0) {
4454 unsigned int entry = dirty_tx % NUM_TX_DESC;
4455 struct ring_info *tx_skb = tp->tx_skb + entry;
4456 u32 status;
4457
4458 rmb();
4459 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4460 if (status & DescOwn)
4461 break;
4462
4463 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4464 tp->TxDescArray + entry);
4465 if (status & LastFrag) {
4466 dev->stats.tx_packets++;
4467 dev->stats.tx_bytes += tx_skb->skb->len;
4468 dev_kfree_skb(tx_skb->skb);
4469 tx_skb->skb = NULL;
4470 }
4471 dirty_tx++;
4472 tx_left--;
4473 }
4474
4475 if (tp->dirty_tx != dirty_tx) {
4476 tp->dirty_tx = dirty_tx;
4477 smp_wmb();
4478 if (netif_queue_stopped(dev) &&
4479 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
4480 netif_wake_queue(dev);
4481 }
4482 /*
4483 * 8168 hack: TxPoll requests are lost when the Tx packets are
4484 * too close. Let's kick an extra TxPoll request when a burst
4485 * of start_xmit activity is detected (if it is not detected,
4486 * it is slow enough). -- FR
4487 */
4488 smp_rmb();
4489 if (tp->cur_tx != dirty_tx)
4490 RTL_W8(TxPoll, NPQ);
4491 }
4492 }
4493
4494 static inline int rtl8169_fragmented_frame(u32 status)
4495 {
4496 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4497 }
4498
4499 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
4500 {
4501 u32 status = opts1 & RxProtoMask;
4502
4503 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
4504 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
4505 skb->ip_summed = CHECKSUM_UNNECESSARY;
4506 else
4507 skb_checksum_none_assert(skb);
4508 }
4509
4510 static struct sk_buff *rtl8169_try_rx_copy(void *data,
4511 struct rtl8169_private *tp,
4512 int pkt_size,
4513 dma_addr_t addr)
4514 {
4515 struct sk_buff *skb;
4516 struct device *d = &tp->pci_dev->dev;
4517
4518 data = rtl8169_align(data);
4519 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
4520 prefetch(data);
4521 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
4522 if (skb)
4523 memcpy(skb->data, data, pkt_size);
4524 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
4525
4526 return skb;
4527 }
4528
4529 /*
4530 * Warning : rtl8169_rx_interrupt() might be called :
4531 * 1) from NAPI (softirq) context
4532 * (polling = 1 : we should call netif_receive_skb())
4533 * 2) from process context (rtl8169_reset_task())
4534 * (polling = 0 : we must call netif_rx() instead)
4535 */
4536 static int rtl8169_rx_interrupt(struct net_device *dev,
4537 struct rtl8169_private *tp,
4538 void __iomem *ioaddr, u32 budget)
4539 {
4540 unsigned int cur_rx, rx_left;
4541 unsigned int count;
4542 int polling = (budget != ~(u32)0) ? 1 : 0;
4543
4544 cur_rx = tp->cur_rx;
4545 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
4546 rx_left = min(rx_left, budget);
4547
4548 for (; rx_left > 0; rx_left--, cur_rx++) {
4549 unsigned int entry = cur_rx % NUM_RX_DESC;
4550 struct RxDesc *desc = tp->RxDescArray + entry;
4551 u32 status;
4552
4553 rmb();
4554 status = le32_to_cpu(desc->opts1);
4555
4556 if (status & DescOwn)
4557 break;
4558 if (unlikely(status & RxRES)) {
4559 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
4560 status);
4561 dev->stats.rx_errors++;
4562 if (status & (RxRWT | RxRUNT))
4563 dev->stats.rx_length_errors++;
4564 if (status & RxCRC)
4565 dev->stats.rx_crc_errors++;
4566 if (status & RxFOVF) {
4567 rtl8169_schedule_work(dev, rtl8169_reset_task);
4568 dev->stats.rx_fifo_errors++;
4569 }
4570 rtl8169_mark_to_asic(desc, rx_buf_sz);
4571 } else {
4572 struct sk_buff *skb;
4573 dma_addr_t addr = le64_to_cpu(desc->addr);
4574 int pkt_size = (status & 0x00001FFF) - 4;
4575
4576 /*
4577 * The driver does not support incoming fragmented
4578 * frames. They are seen as a symptom of over-mtu
4579 * sized frames.
4580 */
4581 if (unlikely(rtl8169_fragmented_frame(status))) {
4582 dev->stats.rx_dropped++;
4583 dev->stats.rx_length_errors++;
4584 rtl8169_mark_to_asic(desc, rx_buf_sz);
4585 continue;
4586 }
4587
4588 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
4589 tp, pkt_size, addr);
4590 rtl8169_mark_to_asic(desc, rx_buf_sz);
4591 if (!skb) {
4592 dev->stats.rx_dropped++;
4593 continue;
4594 }
4595
4596 rtl8169_rx_csum(skb, status);
4597 skb_put(skb, pkt_size);
4598 skb->protocol = eth_type_trans(skb, dev);
4599
4600 if (rtl8169_rx_vlan_skb(tp, desc, skb, polling) < 0) {
4601 if (likely(polling))
4602 napi_gro_receive(&tp->napi, skb);
4603 else
4604 netif_rx(skb);
4605 }
4606
4607 dev->stats.rx_bytes += pkt_size;
4608 dev->stats.rx_packets++;
4609 }
4610
4611 /* Work around for AMD plateform. */
4612 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
4613 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
4614 desc->opts2 = 0;
4615 cur_rx++;
4616 }
4617 }
4618
4619 count = cur_rx - tp->cur_rx;
4620 tp->cur_rx = cur_rx;
4621
4622 tp->dirty_rx += count;
4623
4624 return count;
4625 }
4626
4627 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
4628 {
4629 struct net_device *dev = dev_instance;
4630 struct rtl8169_private *tp = netdev_priv(dev);
4631 void __iomem *ioaddr = tp->mmio_addr;
4632 int handled = 0;
4633 int status;
4634
4635 /* loop handling interrupts until we have no new ones or
4636 * we hit a invalid/hotplug case.
4637 */
4638 status = RTL_R16(IntrStatus);
4639 while (status && status != 0xffff) {
4640 handled = 1;
4641
4642 /* Handle all of the error cases first. These will reset
4643 * the chip, so just exit the loop.
4644 */
4645 if (unlikely(!netif_running(dev))) {
4646 rtl8169_asic_down(ioaddr);
4647 break;
4648 }
4649
4650 if (unlikely(status & RxFIFOOver)) {
4651 switch (tp->mac_version) {
4652 /* Work around for rx fifo overflow */
4653 case RTL_GIGA_MAC_VER_11:
4654 case RTL_GIGA_MAC_VER_22:
4655 case RTL_GIGA_MAC_VER_26:
4656 netif_stop_queue(dev);
4657 rtl8169_tx_timeout(dev);
4658 goto done;
4659 /* Testers needed. */
4660 case RTL_GIGA_MAC_VER_17:
4661 case RTL_GIGA_MAC_VER_19:
4662 case RTL_GIGA_MAC_VER_20:
4663 case RTL_GIGA_MAC_VER_21:
4664 case RTL_GIGA_MAC_VER_23:
4665 case RTL_GIGA_MAC_VER_24:
4666 case RTL_GIGA_MAC_VER_27:
4667 case RTL_GIGA_MAC_VER_28:
4668 /* Experimental science. Pktgen proof. */
4669 case RTL_GIGA_MAC_VER_12:
4670 case RTL_GIGA_MAC_VER_25:
4671 if (status == RxFIFOOver)
4672 goto done;
4673 break;
4674 default:
4675 break;
4676 }
4677 }
4678
4679 if (unlikely(status & SYSErr)) {
4680 rtl8169_pcierr_interrupt(dev);
4681 break;
4682 }
4683
4684 if (status & LinkChg)
4685 __rtl8169_check_link_status(dev, tp, ioaddr, true);
4686
4687 /* We need to see the lastest version of tp->intr_mask to
4688 * avoid ignoring an MSI interrupt and having to wait for
4689 * another event which may never come.
4690 */
4691 smp_rmb();
4692 if (status & tp->intr_mask & tp->napi_event) {
4693 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
4694 tp->intr_mask = ~tp->napi_event;
4695
4696 if (likely(napi_schedule_prep(&tp->napi)))
4697 __napi_schedule(&tp->napi);
4698 else
4699 netif_info(tp, intr, dev,
4700 "interrupt %04x in poll\n", status);
4701 }
4702
4703 /* We only get a new MSI interrupt when all active irq
4704 * sources on the chip have been acknowledged. So, ack
4705 * everything we've seen and check if new sources have become
4706 * active to avoid blocking all interrupts from the chip.
4707 */
4708 RTL_W16(IntrStatus,
4709 (status & RxFIFOOver) ? (status | RxOverflow) : status);
4710 status = RTL_R16(IntrStatus);
4711 }
4712 done:
4713 return IRQ_RETVAL(handled);
4714 }
4715
4716 static int rtl8169_poll(struct napi_struct *napi, int budget)
4717 {
4718 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
4719 struct net_device *dev = tp->dev;
4720 void __iomem *ioaddr = tp->mmio_addr;
4721 int work_done;
4722
4723 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
4724 rtl8169_tx_interrupt(dev, tp, ioaddr);
4725
4726 if (work_done < budget) {
4727 napi_complete(napi);
4728
4729 /* We need for force the visibility of tp->intr_mask
4730 * for other CPUs, as we can loose an MSI interrupt
4731 * and potentially wait for a retransmit timeout if we don't.
4732 * The posted write to IntrMask is safe, as it will
4733 * eventually make it to the chip and we won't loose anything
4734 * until it does.
4735 */
4736 tp->intr_mask = 0xffff;
4737 wmb();
4738 RTL_W16(IntrMask, tp->intr_event);
4739 }
4740
4741 return work_done;
4742 }
4743
4744 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
4745 {
4746 struct rtl8169_private *tp = netdev_priv(dev);
4747
4748 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
4749 return;
4750
4751 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
4752 RTL_W32(RxMissed, 0);
4753 }
4754
4755 static void rtl8169_down(struct net_device *dev)
4756 {
4757 struct rtl8169_private *tp = netdev_priv(dev);
4758 void __iomem *ioaddr = tp->mmio_addr;
4759
4760 rtl8169_delete_timer(dev);
4761
4762 netif_stop_queue(dev);
4763
4764 napi_disable(&tp->napi);
4765
4766 spin_lock_irq(&tp->lock);
4767
4768 rtl8169_asic_down(ioaddr);
4769 /*
4770 * At this point device interrupts can not be enabled in any function,
4771 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
4772 * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
4773 */
4774 rtl8169_rx_missed(dev, ioaddr);
4775
4776 spin_unlock_irq(&tp->lock);
4777
4778 synchronize_irq(dev->irq);
4779
4780 /* Give a racing hard_start_xmit a few cycles to complete. */
4781 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
4782
4783 rtl8169_tx_clear(tp);
4784
4785 rtl8169_rx_clear(tp);
4786
4787 rtl_pll_power_down(tp);
4788 }
4789
4790 static int rtl8169_close(struct net_device *dev)
4791 {
4792 struct rtl8169_private *tp = netdev_priv(dev);
4793 struct pci_dev *pdev = tp->pci_dev;
4794
4795 pm_runtime_get_sync(&pdev->dev);
4796
4797 /* update counters before going down */
4798 rtl8169_update_counters(dev);
4799
4800 rtl8169_down(dev);
4801
4802 free_irq(dev->irq, dev);
4803
4804 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4805 tp->RxPhyAddr);
4806 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4807 tp->TxPhyAddr);
4808 tp->TxDescArray = NULL;
4809 tp->RxDescArray = NULL;
4810
4811 pm_runtime_put_sync(&pdev->dev);
4812
4813 return 0;
4814 }
4815
4816 static void rtl_set_rx_mode(struct net_device *dev)
4817 {
4818 struct rtl8169_private *tp = netdev_priv(dev);
4819 void __iomem *ioaddr = tp->mmio_addr;
4820 unsigned long flags;
4821 u32 mc_filter[2]; /* Multicast hash filter */
4822 int rx_mode;
4823 u32 tmp = 0;
4824
4825 if (dev->flags & IFF_PROMISC) {
4826 /* Unconditionally log net taps. */
4827 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4828 rx_mode =
4829 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4830 AcceptAllPhys;
4831 mc_filter[1] = mc_filter[0] = 0xffffffff;
4832 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4833 (dev->flags & IFF_ALLMULTI)) {
4834 /* Too many to filter perfectly -- accept all multicasts. */
4835 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4836 mc_filter[1] = mc_filter[0] = 0xffffffff;
4837 } else {
4838 struct netdev_hw_addr *ha;
4839
4840 rx_mode = AcceptBroadcast | AcceptMyPhys;
4841 mc_filter[1] = mc_filter[0] = 0;
4842 netdev_for_each_mc_addr(ha, dev) {
4843 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4844 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4845 rx_mode |= AcceptMulticast;
4846 }
4847 }
4848
4849 spin_lock_irqsave(&tp->lock, flags);
4850
4851 tmp = rtl8169_rx_config | rx_mode |
4852 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
4853
4854 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4855 u32 data = mc_filter[0];
4856
4857 mc_filter[0] = swab32(mc_filter[1]);
4858 mc_filter[1] = swab32(data);
4859 }
4860
4861 RTL_W32(MAR0 + 4, mc_filter[1]);
4862 RTL_W32(MAR0 + 0, mc_filter[0]);
4863
4864 RTL_W32(RxConfig, tmp);
4865
4866 spin_unlock_irqrestore(&tp->lock, flags);
4867 }
4868
4869 /**
4870 * rtl8169_get_stats - Get rtl8169 read/write statistics
4871 * @dev: The Ethernet Device to get statistics for
4872 *
4873 * Get TX/RX statistics for rtl8169
4874 */
4875 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
4876 {
4877 struct rtl8169_private *tp = netdev_priv(dev);
4878 void __iomem *ioaddr = tp->mmio_addr;
4879 unsigned long flags;
4880
4881 if (netif_running(dev)) {
4882 spin_lock_irqsave(&tp->lock, flags);
4883 rtl8169_rx_missed(dev, ioaddr);
4884 spin_unlock_irqrestore(&tp->lock, flags);
4885 }
4886
4887 return &dev->stats;
4888 }
4889
4890 static void rtl8169_net_suspend(struct net_device *dev)
4891 {
4892 struct rtl8169_private *tp = netdev_priv(dev);
4893
4894 if (!netif_running(dev))
4895 return;
4896
4897 rtl_pll_power_down(tp);
4898
4899 netif_device_detach(dev);
4900 netif_stop_queue(dev);
4901 }
4902
4903 #ifdef CONFIG_PM
4904
4905 static int rtl8169_suspend(struct device *device)
4906 {
4907 struct pci_dev *pdev = to_pci_dev(device);
4908 struct net_device *dev = pci_get_drvdata(pdev);
4909
4910 rtl8169_net_suspend(dev);
4911
4912 return 0;
4913 }
4914
4915 static void __rtl8169_resume(struct net_device *dev)
4916 {
4917 struct rtl8169_private *tp = netdev_priv(dev);
4918
4919 netif_device_attach(dev);
4920
4921 rtl_pll_power_up(tp);
4922
4923 rtl8169_schedule_work(dev, rtl8169_reset_task);
4924 }
4925
4926 static int rtl8169_resume(struct device *device)
4927 {
4928 struct pci_dev *pdev = to_pci_dev(device);
4929 struct net_device *dev = pci_get_drvdata(pdev);
4930 struct rtl8169_private *tp = netdev_priv(dev);
4931
4932 rtl8169_init_phy(dev, tp);
4933
4934 if (netif_running(dev))
4935 __rtl8169_resume(dev);
4936
4937 return 0;
4938 }
4939
4940 static int rtl8169_runtime_suspend(struct device *device)
4941 {
4942 struct pci_dev *pdev = to_pci_dev(device);
4943 struct net_device *dev = pci_get_drvdata(pdev);
4944 struct rtl8169_private *tp = netdev_priv(dev);
4945
4946 if (!tp->TxDescArray)
4947 return 0;
4948
4949 spin_lock_irq(&tp->lock);
4950 tp->saved_wolopts = __rtl8169_get_wol(tp);
4951 __rtl8169_set_wol(tp, WAKE_ANY);
4952 spin_unlock_irq(&tp->lock);
4953
4954 rtl8169_net_suspend(dev);
4955
4956 return 0;
4957 }
4958
4959 static int rtl8169_runtime_resume(struct device *device)
4960 {
4961 struct pci_dev *pdev = to_pci_dev(device);
4962 struct net_device *dev = pci_get_drvdata(pdev);
4963 struct rtl8169_private *tp = netdev_priv(dev);
4964
4965 if (!tp->TxDescArray)
4966 return 0;
4967
4968 spin_lock_irq(&tp->lock);
4969 __rtl8169_set_wol(tp, tp->saved_wolopts);
4970 tp->saved_wolopts = 0;
4971 spin_unlock_irq(&tp->lock);
4972
4973 rtl8169_init_phy(dev, tp);
4974
4975 __rtl8169_resume(dev);
4976
4977 return 0;
4978 }
4979
4980 static int rtl8169_runtime_idle(struct device *device)
4981 {
4982 struct pci_dev *pdev = to_pci_dev(device);
4983 struct net_device *dev = pci_get_drvdata(pdev);
4984 struct rtl8169_private *tp = netdev_priv(dev);
4985
4986 return tp->TxDescArray ? -EBUSY : 0;
4987 }
4988
4989 static const struct dev_pm_ops rtl8169_pm_ops = {
4990 .suspend = rtl8169_suspend,
4991 .resume = rtl8169_resume,
4992 .freeze = rtl8169_suspend,
4993 .thaw = rtl8169_resume,
4994 .poweroff = rtl8169_suspend,
4995 .restore = rtl8169_resume,
4996 .runtime_suspend = rtl8169_runtime_suspend,
4997 .runtime_resume = rtl8169_runtime_resume,
4998 .runtime_idle = rtl8169_runtime_idle,
4999 };
5000
5001 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
5002
5003 #else /* !CONFIG_PM */
5004
5005 #define RTL8169_PM_OPS NULL
5006
5007 #endif /* !CONFIG_PM */
5008
5009 static void rtl_shutdown(struct pci_dev *pdev)
5010 {
5011 struct net_device *dev = pci_get_drvdata(pdev);
5012 struct rtl8169_private *tp = netdev_priv(dev);
5013 void __iomem *ioaddr = tp->mmio_addr;
5014
5015 rtl8169_net_suspend(dev);
5016
5017 /* restore original MAC address */
5018 rtl_rar_set(tp, dev->perm_addr);
5019
5020 spin_lock_irq(&tp->lock);
5021
5022 rtl8169_asic_down(ioaddr);
5023
5024 spin_unlock_irq(&tp->lock);
5025
5026 if (system_state == SYSTEM_POWER_OFF) {
5027 /* WoL fails with some 8168 when the receiver is disabled. */
5028 if (tp->features & RTL_FEATURE_WOL) {
5029 pci_clear_master(pdev);
5030
5031 RTL_W8(ChipCmd, CmdRxEnb);
5032 /* PCI commit */
5033 RTL_R8(ChipCmd);
5034 }
5035
5036 pci_wake_from_d3(pdev, true);
5037 pci_set_power_state(pdev, PCI_D3hot);
5038 }
5039 }
5040
5041 static struct pci_driver rtl8169_pci_driver = {
5042 .name = MODULENAME,
5043 .id_table = rtl8169_pci_tbl,
5044 .probe = rtl8169_init_one,
5045 .remove = __devexit_p(rtl8169_remove_one),
5046 .shutdown = rtl_shutdown,
5047 .driver.pm = RTL8169_PM_OPS,
5048 };
5049
5050 static int __init rtl8169_init_module(void)
5051 {
5052 return pci_register_driver(&rtl8169_pci_driver);
5053 }
5054
5055 static void __exit rtl8169_cleanup_module(void)
5056 {
5057 pci_unregister_driver(&rtl8169_pci_driver);
5058 }
5059
5060 module_init(rtl8169_init_module);
5061 module_exit(rtl8169_cleanup_module);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree