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KVM: x86 emulator: drop vcpu argument from intercept callback
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / arch / x86 / kvm / x86.c
blob4f7248ea6cafe60e08da7961c4b6a98ffca6a529
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
22 #include <linux/kvm_host.h>
23 #include "irq.h"
24 #include "mmu.h"
25 #include "i8254.h"
26 #include "tss.h"
27 #include "kvm_cache_regs.h"
28 #include "x86.h"
29
30 #include <linux/clocksource.h>
31 #include <linux/interrupt.h>
32 #include <linux/kvm.h>
33 #include <linux/fs.h>
34 #include <linux/vmalloc.h>
35 #include <linux/module.h>
36 #include <linux/mman.h>
37 #include <linux/highmem.h>
38 #include <linux/iommu.h>
39 #include <linux/intel-iommu.h>
40 #include <linux/cpufreq.h>
41 #include <linux/user-return-notifier.h>
42 #include <linux/srcu.h>
43 #include <linux/slab.h>
44 #include <linux/perf_event.h>
45 #include <linux/uaccess.h>
46 #include <linux/hash.h>
47 #include <trace/events/kvm.h>
48
49 #define CREATE_TRACE_POINTS
50 #include "trace.h"
51
52 #include <asm/debugreg.h>
53 #include <asm/msr.h>
54 #include <asm/desc.h>
55 #include <asm/mtrr.h>
56 #include <asm/mce.h>
57 #include <asm/i387.h>
58 #include <asm/xcr.h>
59 #include <asm/pvclock.h>
60 #include <asm/div64.h>
61
62 #define MAX_IO_MSRS 256
63 #define KVM_MAX_MCE_BANKS 32
64 #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
65
66 #define emul_to_vcpu(ctxt) \
67 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
68
69 /* EFER defaults:
70 * - enable syscall per default because its emulated by KVM
71 * - enable LME and LMA per default on 64 bit KVM
72 */
73 #ifdef CONFIG_X86_64
74 static
75 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
76 #else
77 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
78 #endif
79
80 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
81 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
82
83 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
84 static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
85 struct kvm_cpuid_entry2 __user *entries);
86
87 struct kvm_x86_ops *kvm_x86_ops;
88 EXPORT_SYMBOL_GPL(kvm_x86_ops);
89
90 int ignore_msrs = 0;
91 module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
92
93 bool kvm_has_tsc_control;
94 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
95 u32 kvm_max_guest_tsc_khz;
96 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
97
98 #define KVM_NR_SHARED_MSRS 16
99
100 struct kvm_shared_msrs_global {
101 int nr;
102 u32 msrs[KVM_NR_SHARED_MSRS];
103 };
104
105 struct kvm_shared_msrs {
106 struct user_return_notifier urn;
107 bool registered;
108 struct kvm_shared_msr_values {
109 u64 host;
110 u64 curr;
111 } values[KVM_NR_SHARED_MSRS];
112 };
113
114 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
115 static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
116
117 struct kvm_stats_debugfs_item debugfs_entries[] = {
118 { "pf_fixed", VCPU_STAT(pf_fixed) },
119 { "pf_guest", VCPU_STAT(pf_guest) },
120 { "tlb_flush", VCPU_STAT(tlb_flush) },
121 { "invlpg", VCPU_STAT(invlpg) },
122 { "exits", VCPU_STAT(exits) },
123 { "io_exits", VCPU_STAT(io_exits) },
124 { "mmio_exits", VCPU_STAT(mmio_exits) },
125 { "signal_exits", VCPU_STAT(signal_exits) },
126 { "irq_window", VCPU_STAT(irq_window_exits) },
127 { "nmi_window", VCPU_STAT(nmi_window_exits) },
128 { "halt_exits", VCPU_STAT(halt_exits) },
129 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
130 { "hypercalls", VCPU_STAT(hypercalls) },
131 { "request_irq", VCPU_STAT(request_irq_exits) },
132 { "irq_exits", VCPU_STAT(irq_exits) },
133 { "host_state_reload", VCPU_STAT(host_state_reload) },
134 { "efer_reload", VCPU_STAT(efer_reload) },
135 { "fpu_reload", VCPU_STAT(fpu_reload) },
136 { "insn_emulation", VCPU_STAT(insn_emulation) },
137 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
138 { "irq_injections", VCPU_STAT(irq_injections) },
139 { "nmi_injections", VCPU_STAT(nmi_injections) },
140 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
141 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
142 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
143 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
144 { "mmu_flooded", VM_STAT(mmu_flooded) },
145 { "mmu_recycled", VM_STAT(mmu_recycled) },
146 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
147 { "mmu_unsync", VM_STAT(mmu_unsync) },
148 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
149 { "largepages", VM_STAT(lpages) },
150 { NULL }
151 };
152
153 u64 __read_mostly host_xcr0;
154
155 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
156 {
157 int i;
158 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
159 vcpu->arch.apf.gfns[i] = ~0;
160 }
161
162 static void kvm_on_user_return(struct user_return_notifier *urn)
163 {
164 unsigned slot;
165 struct kvm_shared_msrs *locals
166 = container_of(urn, struct kvm_shared_msrs, urn);
167 struct kvm_shared_msr_values *values;
168
169 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
170 values = &locals->values[slot];
171 if (values->host != values->curr) {
172 wrmsrl(shared_msrs_global.msrs[slot], values->host);
173 values->curr = values->host;
174 }
175 }
176 locals->registered = false;
177 user_return_notifier_unregister(urn);
178 }
179
180 static void shared_msr_update(unsigned slot, u32 msr)
181 {
182 struct kvm_shared_msrs *smsr;
183 u64 value;
184
185 smsr = &__get_cpu_var(shared_msrs);
186 /* only read, and nobody should modify it at this time,
187 * so don't need lock */
188 if (slot >= shared_msrs_global.nr) {
189 printk(KERN_ERR "kvm: invalid MSR slot!");
190 return;
191 }
192 rdmsrl_safe(msr, &value);
193 smsr->values[slot].host = value;
194 smsr->values[slot].curr = value;
195 }
196
197 void kvm_define_shared_msr(unsigned slot, u32 msr)
198 {
199 if (slot >= shared_msrs_global.nr)
200 shared_msrs_global.nr = slot + 1;
201 shared_msrs_global.msrs[slot] = msr;
202 /* we need ensured the shared_msr_global have been updated */
203 smp_wmb();
204 }
205 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
206
207 static void kvm_shared_msr_cpu_online(void)
208 {
209 unsigned i;
210
211 for (i = 0; i < shared_msrs_global.nr; ++i)
212 shared_msr_update(i, shared_msrs_global.msrs[i]);
213 }
214
215 void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
216 {
217 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
218
219 if (((value ^ smsr->values[slot].curr) & mask) == 0)
220 return;
221 smsr->values[slot].curr = value;
222 wrmsrl(shared_msrs_global.msrs[slot], value);
223 if (!smsr->registered) {
224 smsr->urn.on_user_return = kvm_on_user_return;
225 user_return_notifier_register(&smsr->urn);
226 smsr->registered = true;
227 }
228 }
229 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
230
231 static void drop_user_return_notifiers(void *ignore)
232 {
233 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
234
235 if (smsr->registered)
236 kvm_on_user_return(&smsr->urn);
237 }
238
239 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
240 {
241 if (irqchip_in_kernel(vcpu->kvm))
242 return vcpu->arch.apic_base;
243 else
244 return vcpu->arch.apic_base;
245 }
246 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
247
248 void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
249 {
250 /* TODO: reserve bits check */
251 if (irqchip_in_kernel(vcpu->kvm))
252 kvm_lapic_set_base(vcpu, data);
253 else
254 vcpu->arch.apic_base = data;
255 }
256 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
257
258 #define EXCPT_BENIGN 0
259 #define EXCPT_CONTRIBUTORY 1
260 #define EXCPT_PF 2
261
262 static int exception_class(int vector)
263 {
264 switch (vector) {
265 case PF_VECTOR:
266 return EXCPT_PF;
267 case DE_VECTOR:
268 case TS_VECTOR:
269 case NP_VECTOR:
270 case SS_VECTOR:
271 case GP_VECTOR:
272 return EXCPT_CONTRIBUTORY;
273 default:
274 break;
275 }
276 return EXCPT_BENIGN;
277 }
278
279 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
280 unsigned nr, bool has_error, u32 error_code,
281 bool reinject)
282 {
283 u32 prev_nr;
284 int class1, class2;
285
286 kvm_make_request(KVM_REQ_EVENT, vcpu);
287
288 if (!vcpu->arch.exception.pending) {
289 queue:
290 vcpu->arch.exception.pending = true;
291 vcpu->arch.exception.has_error_code = has_error;
292 vcpu->arch.exception.nr = nr;
293 vcpu->arch.exception.error_code = error_code;
294 vcpu->arch.exception.reinject = reinject;
295 return;
296 }
297
298 /* to check exception */
299 prev_nr = vcpu->arch.exception.nr;
300 if (prev_nr == DF_VECTOR) {
301 /* triple fault -> shutdown */
302 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
303 return;
304 }
305 class1 = exception_class(prev_nr);
306 class2 = exception_class(nr);
307 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
308 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
309 /* generate double fault per SDM Table 5-5 */
310 vcpu->arch.exception.pending = true;
311 vcpu->arch.exception.has_error_code = true;
312 vcpu->arch.exception.nr = DF_VECTOR;
313 vcpu->arch.exception.error_code = 0;
314 } else
315 /* replace previous exception with a new one in a hope
316 that instruction re-execution will regenerate lost
317 exception */
318 goto queue;
319 }
320
321 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
322 {
323 kvm_multiple_exception(vcpu, nr, false, 0, false);
324 }
325 EXPORT_SYMBOL_GPL(kvm_queue_exception);
326
327 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
328 {
329 kvm_multiple_exception(vcpu, nr, false, 0, true);
330 }
331 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
332
333 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
334 {
335 if (err)
336 kvm_inject_gp(vcpu, 0);
337 else
338 kvm_x86_ops->skip_emulated_instruction(vcpu);
339 }
340 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
341
342 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
343 {
344 ++vcpu->stat.pf_guest;
345 vcpu->arch.cr2 = fault->address;
346 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
347 }
348
349 void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
350 {
351 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
352 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
353 else
354 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
355 }
356
357 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
358 {
359 kvm_make_request(KVM_REQ_EVENT, vcpu);
360 vcpu->arch.nmi_pending = 1;
361 }
362 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
363
364 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
365 {
366 kvm_multiple_exception(vcpu, nr, true, error_code, false);
367 }
368 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
369
370 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
371 {
372 kvm_multiple_exception(vcpu, nr, true, error_code, true);
373 }
374 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
375
376 /*
377 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
378 * a #GP and return false.
379 */
380 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
381 {
382 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
383 return true;
384 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
385 return false;
386 }
387 EXPORT_SYMBOL_GPL(kvm_require_cpl);
388
389 /*
390 * This function will be used to read from the physical memory of the currently
391 * running guest. The difference to kvm_read_guest_page is that this function
392 * can read from guest physical or from the guest's guest physical memory.
393 */
394 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
395 gfn_t ngfn, void *data, int offset, int len,
396 u32 access)
397 {
398 gfn_t real_gfn;
399 gpa_t ngpa;
400
401 ngpa = gfn_to_gpa(ngfn);
402 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
403 if (real_gfn == UNMAPPED_GVA)
404 return -EFAULT;
405
406 real_gfn = gpa_to_gfn(real_gfn);
407
408 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
409 }
410 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
411
412 int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
413 void *data, int offset, int len, u32 access)
414 {
415 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
416 data, offset, len, access);
417 }
418
419 /*
420 * Load the pae pdptrs. Return true is they are all valid.
421 */
422 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
423 {
424 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
425 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
426 int i;
427 int ret;
428 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
429
430 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
431 offset * sizeof(u64), sizeof(pdpte),
432 PFERR_USER_MASK|PFERR_WRITE_MASK);
433 if (ret < 0) {
434 ret = 0;
435 goto out;
436 }
437 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
438 if (is_present_gpte(pdpte[i]) &&
439 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
440 ret = 0;
441 goto out;
442 }
443 }
444 ret = 1;
445
446 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
447 __set_bit(VCPU_EXREG_PDPTR,
448 (unsigned long *)&vcpu->arch.regs_avail);
449 __set_bit(VCPU_EXREG_PDPTR,
450 (unsigned long *)&vcpu->arch.regs_dirty);
451 out:
452
453 return ret;
454 }
455 EXPORT_SYMBOL_GPL(load_pdptrs);
456
457 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
458 {
459 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
460 bool changed = true;
461 int offset;
462 gfn_t gfn;
463 int r;
464
465 if (is_long_mode(vcpu) || !is_pae(vcpu))
466 return false;
467
468 if (!test_bit(VCPU_EXREG_PDPTR,
469 (unsigned long *)&vcpu->arch.regs_avail))
470 return true;
471
472 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
473 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
474 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
475 PFERR_USER_MASK | PFERR_WRITE_MASK);
476 if (r < 0)
477 goto out;
478 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
479 out:
480
481 return changed;
482 }
483
484 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
485 {
486 unsigned long old_cr0 = kvm_read_cr0(vcpu);
487 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
488 X86_CR0_CD | X86_CR0_NW;
489
490 cr0 |= X86_CR0_ET;
491
492 #ifdef CONFIG_X86_64
493 if (cr0 & 0xffffffff00000000UL)
494 return 1;
495 #endif
496
497 cr0 &= ~CR0_RESERVED_BITS;
498
499 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
500 return 1;
501
502 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
503 return 1;
504
505 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
506 #ifdef CONFIG_X86_64
507 if ((vcpu->arch.efer & EFER_LME)) {
508 int cs_db, cs_l;
509
510 if (!is_pae(vcpu))
511 return 1;
512 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
513 if (cs_l)
514 return 1;
515 } else
516 #endif
517 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
518 kvm_read_cr3(vcpu)))
519 return 1;
520 }
521
522 kvm_x86_ops->set_cr0(vcpu, cr0);
523
524 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
525 kvm_clear_async_pf_completion_queue(vcpu);
526 kvm_async_pf_hash_reset(vcpu);
527 }
528
529 if ((cr0 ^ old_cr0) & update_bits)
530 kvm_mmu_reset_context(vcpu);
531 return 0;
532 }
533 EXPORT_SYMBOL_GPL(kvm_set_cr0);
534
535 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
536 {
537 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
538 }
539 EXPORT_SYMBOL_GPL(kvm_lmsw);
540
541 int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
542 {
543 u64 xcr0;
544
545 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
546 if (index != XCR_XFEATURE_ENABLED_MASK)
547 return 1;
548 xcr0 = xcr;
549 if (kvm_x86_ops->get_cpl(vcpu) != 0)
550 return 1;
551 if (!(xcr0 & XSTATE_FP))
552 return 1;
553 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
554 return 1;
555 if (xcr0 & ~host_xcr0)
556 return 1;
557 vcpu->arch.xcr0 = xcr0;
558 vcpu->guest_xcr0_loaded = 0;
559 return 0;
560 }
561
562 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
563 {
564 if (__kvm_set_xcr(vcpu, index, xcr)) {
565 kvm_inject_gp(vcpu, 0);
566 return 1;
567 }
568 return 0;
569 }
570 EXPORT_SYMBOL_GPL(kvm_set_xcr);
571
572 static bool guest_cpuid_has_xsave(struct kvm_vcpu *vcpu)
573 {
574 struct kvm_cpuid_entry2 *best;
575
576 best = kvm_find_cpuid_entry(vcpu, 1, 0);
577 return best && (best->ecx & bit(X86_FEATURE_XSAVE));
578 }
579
580 static void update_cpuid(struct kvm_vcpu *vcpu)
581 {
582 struct kvm_cpuid_entry2 *best;
583
584 best = kvm_find_cpuid_entry(vcpu, 1, 0);
585 if (!best)
586 return;
587
588 /* Update OSXSAVE bit */
589 if (cpu_has_xsave && best->function == 0x1) {
590 best->ecx &= ~(bit(X86_FEATURE_OSXSAVE));
591 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE))
592 best->ecx |= bit(X86_FEATURE_OSXSAVE);
593 }
594 }
595
596 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
597 {
598 unsigned long old_cr4 = kvm_read_cr4(vcpu);
599 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
600
601 if (cr4 & CR4_RESERVED_BITS)
602 return 1;
603
604 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
605 return 1;
606
607 if (is_long_mode(vcpu)) {
608 if (!(cr4 & X86_CR4_PAE))
609 return 1;
610 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
611 && ((cr4 ^ old_cr4) & pdptr_bits)
612 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
613 kvm_read_cr3(vcpu)))
614 return 1;
615
616 if (cr4 & X86_CR4_VMXE)
617 return 1;
618
619 kvm_x86_ops->set_cr4(vcpu, cr4);
620
621 if ((cr4 ^ old_cr4) & pdptr_bits)
622 kvm_mmu_reset_context(vcpu);
623
624 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
625 update_cpuid(vcpu);
626
627 return 0;
628 }
629 EXPORT_SYMBOL_GPL(kvm_set_cr4);
630
631 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
632 {
633 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
634 kvm_mmu_sync_roots(vcpu);
635 kvm_mmu_flush_tlb(vcpu);
636 return 0;
637 }
638
639 if (is_long_mode(vcpu)) {
640 if (cr3 & CR3_L_MODE_RESERVED_BITS)
641 return 1;
642 } else {
643 if (is_pae(vcpu)) {
644 if (cr3 & CR3_PAE_RESERVED_BITS)
645 return 1;
646 if (is_paging(vcpu) &&
647 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
648 return 1;
649 }
650 /*
651 * We don't check reserved bits in nonpae mode, because
652 * this isn't enforced, and VMware depends on this.
653 */
654 }
655
656 /*
657 * Does the new cr3 value map to physical memory? (Note, we
658 * catch an invalid cr3 even in real-mode, because it would
659 * cause trouble later on when we turn on paging anyway.)
660 *
661 * A real CPU would silently accept an invalid cr3 and would
662 * attempt to use it - with largely undefined (and often hard
663 * to debug) behavior on the guest side.
664 */
665 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
666 return 1;
667 vcpu->arch.cr3 = cr3;
668 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
669 vcpu->arch.mmu.new_cr3(vcpu);
670 return 0;
671 }
672 EXPORT_SYMBOL_GPL(kvm_set_cr3);
673
674 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
675 {
676 if (cr8 & CR8_RESERVED_BITS)
677 return 1;
678 if (irqchip_in_kernel(vcpu->kvm))
679 kvm_lapic_set_tpr(vcpu, cr8);
680 else
681 vcpu->arch.cr8 = cr8;
682 return 0;
683 }
684 EXPORT_SYMBOL_GPL(kvm_set_cr8);
685
686 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
687 {
688 if (irqchip_in_kernel(vcpu->kvm))
689 return kvm_lapic_get_cr8(vcpu);
690 else
691 return vcpu->arch.cr8;
692 }
693 EXPORT_SYMBOL_GPL(kvm_get_cr8);
694
695 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
696 {
697 switch (dr) {
698 case 0 ... 3:
699 vcpu->arch.db[dr] = val;
700 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
701 vcpu->arch.eff_db[dr] = val;
702 break;
703 case 4:
704 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
705 return 1; /* #UD */
706 /* fall through */
707 case 6:
708 if (val & 0xffffffff00000000ULL)
709 return -1; /* #GP */
710 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
711 break;
712 case 5:
713 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
714 return 1; /* #UD */
715 /* fall through */
716 default: /* 7 */
717 if (val & 0xffffffff00000000ULL)
718 return -1; /* #GP */
719 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
720 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
721 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
722 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
723 }
724 break;
725 }
726
727 return 0;
728 }
729
730 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
731 {
732 int res;
733
734 res = __kvm_set_dr(vcpu, dr, val);
735 if (res > 0)
736 kvm_queue_exception(vcpu, UD_VECTOR);
737 else if (res < 0)
738 kvm_inject_gp(vcpu, 0);
739
740 return res;
741 }
742 EXPORT_SYMBOL_GPL(kvm_set_dr);
743
744 static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
745 {
746 switch (dr) {
747 case 0 ... 3:
748 *val = vcpu->arch.db[dr];
749 break;
750 case 4:
751 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
752 return 1;
753 /* fall through */
754 case 6:
755 *val = vcpu->arch.dr6;
756 break;
757 case 5:
758 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
759 return 1;
760 /* fall through */
761 default: /* 7 */
762 *val = vcpu->arch.dr7;
763 break;
764 }
765
766 return 0;
767 }
768
769 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
770 {
771 if (_kvm_get_dr(vcpu, dr, val)) {
772 kvm_queue_exception(vcpu, UD_VECTOR);
773 return 1;
774 }
775 return 0;
776 }
777 EXPORT_SYMBOL_GPL(kvm_get_dr);
778
779 /*
780 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
781 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
782 *
783 * This list is modified at module load time to reflect the
784 * capabilities of the host cpu. This capabilities test skips MSRs that are
785 * kvm-specific. Those are put in the beginning of the list.
786 */
787
788 #define KVM_SAVE_MSRS_BEGIN 8
789 static u32 msrs_to_save[] = {
790 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
791 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
792 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
793 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN,
794 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
795 MSR_STAR,
796 #ifdef CONFIG_X86_64
797 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
798 #endif
799 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
800 };
801
802 static unsigned num_msrs_to_save;
803
804 static u32 emulated_msrs[] = {
805 MSR_IA32_MISC_ENABLE,
806 MSR_IA32_MCG_STATUS,
807 MSR_IA32_MCG_CTL,
808 };
809
810 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
811 {
812 u64 old_efer = vcpu->arch.efer;
813
814 if (efer & efer_reserved_bits)
815 return 1;
816
817 if (is_paging(vcpu)
818 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
819 return 1;
820
821 if (efer & EFER_FFXSR) {
822 struct kvm_cpuid_entry2 *feat;
823
824 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
825 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
826 return 1;
827 }
828
829 if (efer & EFER_SVME) {
830 struct kvm_cpuid_entry2 *feat;
831
832 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
833 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
834 return 1;
835 }
836
837 efer &= ~EFER_LMA;
838 efer |= vcpu->arch.efer & EFER_LMA;
839
840 kvm_x86_ops->set_efer(vcpu, efer);
841
842 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
843
844 /* Update reserved bits */
845 if ((efer ^ old_efer) & EFER_NX)
846 kvm_mmu_reset_context(vcpu);
847
848 return 0;
849 }
850
851 void kvm_enable_efer_bits(u64 mask)
852 {
853 efer_reserved_bits &= ~mask;
854 }
855 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
856
857
858 /*
859 * Writes msr value into into the appropriate "register".
860 * Returns 0 on success, non-0 otherwise.
861 * Assumes vcpu_load() was already called.
862 */
863 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
864 {
865 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
866 }
867
868 /*
869 * Adapt set_msr() to msr_io()'s calling convention
870 */
871 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
872 {
873 return kvm_set_msr(vcpu, index, *data);
874 }
875
876 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
877 {
878 int version;
879 int r;
880 struct pvclock_wall_clock wc;
881 struct timespec boot;
882
883 if (!wall_clock)
884 return;
885
886 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
887 if (r)
888 return;
889
890 if (version & 1)
891 ++version; /* first time write, random junk */
892
893 ++version;
894
895 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
896
897 /*
898 * The guest calculates current wall clock time by adding
899 * system time (updated by kvm_guest_time_update below) to the
900 * wall clock specified here. guest system time equals host
901 * system time for us, thus we must fill in host boot time here.
902 */
903 getboottime(&boot);
904
905 wc.sec = boot.tv_sec;
906 wc.nsec = boot.tv_nsec;
907 wc.version = version;
908
909 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
910
911 version++;
912 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
913 }
914
915 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
916 {
917 uint32_t quotient, remainder;
918
919 /* Don't try to replace with do_div(), this one calculates
920 * "(dividend << 32) / divisor" */
921 __asm__ ( "divl %4"
922 : "=a" (quotient), "=d" (remainder)
923 : "0" (0), "1" (dividend), "r" (divisor) );
924 return quotient;
925 }
926
927 static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
928 s8 *pshift, u32 *pmultiplier)
929 {
930 uint64_t scaled64;
931 int32_t shift = 0;
932 uint64_t tps64;
933 uint32_t tps32;
934
935 tps64 = base_khz * 1000LL;
936 scaled64 = scaled_khz * 1000LL;
937 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
938 tps64 >>= 1;
939 shift--;
940 }
941
942 tps32 = (uint32_t)tps64;
943 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
944 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
945 scaled64 >>= 1;
946 else
947 tps32 <<= 1;
948 shift++;
949 }
950
951 *pshift = shift;
952 *pmultiplier = div_frac(scaled64, tps32);
953
954 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
955 __func__, base_khz, scaled_khz, shift, *pmultiplier);
956 }
957
958 static inline u64 get_kernel_ns(void)
959 {
960 struct timespec ts;
961
962 WARN_ON(preemptible());
963 ktime_get_ts(&ts);
964 monotonic_to_bootbased(&ts);
965 return timespec_to_ns(&ts);
966 }
967
968 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
969 unsigned long max_tsc_khz;
970
971 static inline int kvm_tsc_changes_freq(void)
972 {
973 int cpu = get_cpu();
974 int ret = !boot_cpu_has(X86_FEATURE_CONSTANT_TSC) &&
975 cpufreq_quick_get(cpu) != 0;
976 put_cpu();
977 return ret;
978 }
979
980 static u64 vcpu_tsc_khz(struct kvm_vcpu *vcpu)
981 {
982 if (vcpu->arch.virtual_tsc_khz)
983 return vcpu->arch.virtual_tsc_khz;
984 else
985 return __this_cpu_read(cpu_tsc_khz);
986 }
987
988 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
989 {
990 u64 ret;
991
992 WARN_ON(preemptible());
993 if (kvm_tsc_changes_freq())
994 printk_once(KERN_WARNING
995 "kvm: unreliable cycle conversion on adjustable rate TSC\n");
996 ret = nsec * vcpu_tsc_khz(vcpu);
997 do_div(ret, USEC_PER_SEC);
998 return ret;
999 }
1000
1001 static void kvm_init_tsc_catchup(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
1002 {
1003 /* Compute a scale to convert nanoseconds in TSC cycles */
1004 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
1005 &vcpu->arch.tsc_catchup_shift,
1006 &vcpu->arch.tsc_catchup_mult);
1007 }
1008
1009 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1010 {
1011 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.last_tsc_nsec,
1012 vcpu->arch.tsc_catchup_mult,
1013 vcpu->arch.tsc_catchup_shift);
1014 tsc += vcpu->arch.last_tsc_write;
1015 return tsc;
1016 }
1017
1018 void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data)
1019 {
1020 struct kvm *kvm = vcpu->kvm;
1021 u64 offset, ns, elapsed;
1022 unsigned long flags;
1023 s64 sdiff;
1024
1025 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1026 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1027 ns = get_kernel_ns();
1028 elapsed = ns - kvm->arch.last_tsc_nsec;
1029 sdiff = data - kvm->arch.last_tsc_write;
1030 if (sdiff < 0)
1031 sdiff = -sdiff;
1032
1033 /*
1034 * Special case: close write to TSC within 5 seconds of
1035 * another CPU is interpreted as an attempt to synchronize
1036 * The 5 seconds is to accommodate host load / swapping as
1037 * well as any reset of TSC during the boot process.
1038 *
1039 * In that case, for a reliable TSC, we can match TSC offsets,
1040 * or make a best guest using elapsed value.
1041 */
1042 if (sdiff < nsec_to_cycles(vcpu, 5ULL * NSEC_PER_SEC) &&
1043 elapsed < 5ULL * NSEC_PER_SEC) {
1044 if (!check_tsc_unstable()) {
1045 offset = kvm->arch.last_tsc_offset;
1046 pr_debug("kvm: matched tsc offset for %llu\n", data);
1047 } else {
1048 u64 delta = nsec_to_cycles(vcpu, elapsed);
1049 offset += delta;
1050 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1051 }
1052 ns = kvm->arch.last_tsc_nsec;
1053 }
1054 kvm->arch.last_tsc_nsec = ns;
1055 kvm->arch.last_tsc_write = data;
1056 kvm->arch.last_tsc_offset = offset;
1057 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1058 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1059
1060 /* Reset of TSC must disable overshoot protection below */
1061 vcpu->arch.hv_clock.tsc_timestamp = 0;
1062 vcpu->arch.last_tsc_write = data;
1063 vcpu->arch.last_tsc_nsec = ns;
1064 }
1065 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1066
1067 static int kvm_guest_time_update(struct kvm_vcpu *v)
1068 {
1069 unsigned long flags;
1070 struct kvm_vcpu_arch *vcpu = &v->arch;
1071 void *shared_kaddr;
1072 unsigned long this_tsc_khz;
1073 s64 kernel_ns, max_kernel_ns;
1074 u64 tsc_timestamp;
1075
1076 /* Keep irq disabled to prevent changes to the clock */
1077 local_irq_save(flags);
1078 kvm_get_msr(v, MSR_IA32_TSC, &tsc_timestamp);
1079 kernel_ns = get_kernel_ns();
1080 this_tsc_khz = vcpu_tsc_khz(v);
1081 if (unlikely(this_tsc_khz == 0)) {
1082 local_irq_restore(flags);
1083 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1084 return 1;
1085 }
1086
1087 /*
1088 * We may have to catch up the TSC to match elapsed wall clock
1089 * time for two reasons, even if kvmclock is used.
1090 * 1) CPU could have been running below the maximum TSC rate
1091 * 2) Broken TSC compensation resets the base at each VCPU
1092 * entry to avoid unknown leaps of TSC even when running
1093 * again on the same CPU. This may cause apparent elapsed
1094 * time to disappear, and the guest to stand still or run
1095 * very slowly.
1096 */
1097 if (vcpu->tsc_catchup) {
1098 u64 tsc = compute_guest_tsc(v, kernel_ns);
1099 if (tsc > tsc_timestamp) {
1100 kvm_x86_ops->adjust_tsc_offset(v, tsc - tsc_timestamp);
1101 tsc_timestamp = tsc;
1102 }
1103 }
1104
1105 local_irq_restore(flags);
1106
1107 if (!vcpu->time_page)
1108 return 0;
1109
1110 /*
1111 * Time as measured by the TSC may go backwards when resetting the base
1112 * tsc_timestamp. The reason for this is that the TSC resolution is
1113 * higher than the resolution of the other clock scales. Thus, many
1114 * possible measurments of the TSC correspond to one measurement of any
1115 * other clock, and so a spread of values is possible. This is not a
1116 * problem for the computation of the nanosecond clock; with TSC rates
1117 * around 1GHZ, there can only be a few cycles which correspond to one
1118 * nanosecond value, and any path through this code will inevitably
1119 * take longer than that. However, with the kernel_ns value itself,
1120 * the precision may be much lower, down to HZ granularity. If the
1121 * first sampling of TSC against kernel_ns ends in the low part of the
1122 * range, and the second in the high end of the range, we can get:
1123 *
1124 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1125 *
1126 * As the sampling errors potentially range in the thousands of cycles,
1127 * it is possible such a time value has already been observed by the
1128 * guest. To protect against this, we must compute the system time as
1129 * observed by the guest and ensure the new system time is greater.
1130 */
1131 max_kernel_ns = 0;
1132 if (vcpu->hv_clock.tsc_timestamp && vcpu->last_guest_tsc) {
1133 max_kernel_ns = vcpu->last_guest_tsc -
1134 vcpu->hv_clock.tsc_timestamp;
1135 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1136 vcpu->hv_clock.tsc_to_system_mul,
1137 vcpu->hv_clock.tsc_shift);
1138 max_kernel_ns += vcpu->last_kernel_ns;
1139 }
1140
1141 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
1142 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1143 &vcpu->hv_clock.tsc_shift,
1144 &vcpu->hv_clock.tsc_to_system_mul);
1145 vcpu->hw_tsc_khz = this_tsc_khz;
1146 }
1147
1148 if (max_kernel_ns > kernel_ns)
1149 kernel_ns = max_kernel_ns;
1150
1151 /* With all the info we got, fill in the values */
1152 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1153 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1154 vcpu->last_kernel_ns = kernel_ns;
1155 vcpu->last_guest_tsc = tsc_timestamp;
1156 vcpu->hv_clock.flags = 0;
1157
1158 /*
1159 * The interface expects us to write an even number signaling that the
1160 * update is finished. Since the guest won't see the intermediate
1161 * state, we just increase by 2 at the end.
1162 */
1163 vcpu->hv_clock.version += 2;
1164
1165 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
1166
1167 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
1168 sizeof(vcpu->hv_clock));
1169
1170 kunmap_atomic(shared_kaddr, KM_USER0);
1171
1172 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
1173 return 0;
1174 }
1175
1176 static bool msr_mtrr_valid(unsigned msr)
1177 {
1178 switch (msr) {
1179 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1180 case MSR_MTRRfix64K_00000:
1181 case MSR_MTRRfix16K_80000:
1182 case MSR_MTRRfix16K_A0000:
1183 case MSR_MTRRfix4K_C0000:
1184 case MSR_MTRRfix4K_C8000:
1185 case MSR_MTRRfix4K_D0000:
1186 case MSR_MTRRfix4K_D8000:
1187 case MSR_MTRRfix4K_E0000:
1188 case MSR_MTRRfix4K_E8000:
1189 case MSR_MTRRfix4K_F0000:
1190 case MSR_MTRRfix4K_F8000:
1191 case MSR_MTRRdefType:
1192 case MSR_IA32_CR_PAT:
1193 return true;
1194 case 0x2f8:
1195 return true;
1196 }
1197 return false;
1198 }
1199
1200 static bool valid_pat_type(unsigned t)
1201 {
1202 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1203 }
1204
1205 static bool valid_mtrr_type(unsigned t)
1206 {
1207 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1208 }
1209
1210 static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1211 {
1212 int i;
1213
1214 if (!msr_mtrr_valid(msr))
1215 return false;
1216
1217 if (msr == MSR_IA32_CR_PAT) {
1218 for (i = 0; i < 8; i++)
1219 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1220 return false;
1221 return true;
1222 } else if (msr == MSR_MTRRdefType) {
1223 if (data & ~0xcff)
1224 return false;
1225 return valid_mtrr_type(data & 0xff);
1226 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1227 for (i = 0; i < 8 ; i++)
1228 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1229 return false;
1230 return true;
1231 }
1232
1233 /* variable MTRRs */
1234 return valid_mtrr_type(data & 0xff);
1235 }
1236
1237 static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1238 {
1239 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1240
1241 if (!mtrr_valid(vcpu, msr, data))
1242 return 1;
1243
1244 if (msr == MSR_MTRRdefType) {
1245 vcpu->arch.mtrr_state.def_type = data;
1246 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1247 } else if (msr == MSR_MTRRfix64K_00000)
1248 p[0] = data;
1249 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1250 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1251 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1252 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1253 else if (msr == MSR_IA32_CR_PAT)
1254 vcpu->arch.pat = data;
1255 else { /* Variable MTRRs */
1256 int idx, is_mtrr_mask;
1257 u64 *pt;
1258
1259 idx = (msr - 0x200) / 2;
1260 is_mtrr_mask = msr - 0x200 - 2 * idx;
1261 if (!is_mtrr_mask)
1262 pt =
1263 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1264 else
1265 pt =
1266 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1267 *pt = data;
1268 }
1269
1270 kvm_mmu_reset_context(vcpu);
1271 return 0;
1272 }
1273
1274 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1275 {
1276 u64 mcg_cap = vcpu->arch.mcg_cap;
1277 unsigned bank_num = mcg_cap & 0xff;
1278
1279 switch (msr) {
1280 case MSR_IA32_MCG_STATUS:
1281 vcpu->arch.mcg_status = data;
1282 break;
1283 case MSR_IA32_MCG_CTL:
1284 if (!(mcg_cap & MCG_CTL_P))
1285 return 1;
1286 if (data != 0 && data != ~(u64)0)
1287 return -1;
1288 vcpu->arch.mcg_ctl = data;
1289 break;
1290 default:
1291 if (msr >= MSR_IA32_MC0_CTL &&
1292 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1293 u32 offset = msr - MSR_IA32_MC0_CTL;
1294 /* only 0 or all 1s can be written to IA32_MCi_CTL
1295 * some Linux kernels though clear bit 10 in bank 4 to
1296 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1297 * this to avoid an uncatched #GP in the guest
1298 */
1299 if ((offset & 0x3) == 0 &&
1300 data != 0 && (data | (1 << 10)) != ~(u64)0)
1301 return -1;
1302 vcpu->arch.mce_banks[offset] = data;
1303 break;
1304 }
1305 return 1;
1306 }
1307 return 0;
1308 }
1309
1310 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1311 {
1312 struct kvm *kvm = vcpu->kvm;
1313 int lm = is_long_mode(vcpu);
1314 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1315 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1316 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1317 : kvm->arch.xen_hvm_config.blob_size_32;
1318 u32 page_num = data & ~PAGE_MASK;
1319 u64 page_addr = data & PAGE_MASK;
1320 u8 *page;
1321 int r;
1322
1323 r = -E2BIG;
1324 if (page_num >= blob_size)
1325 goto out;
1326 r = -ENOMEM;
1327 page = kzalloc(PAGE_SIZE, GFP_KERNEL);
1328 if (!page)
1329 goto out;
1330 r = -EFAULT;
1331 if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
1332 goto out_free;
1333 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1334 goto out_free;
1335 r = 0;
1336 out_free:
1337 kfree(page);
1338 out:
1339 return r;
1340 }
1341
1342 static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1343 {
1344 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1345 }
1346
1347 static bool kvm_hv_msr_partition_wide(u32 msr)
1348 {
1349 bool r = false;
1350 switch (msr) {
1351 case HV_X64_MSR_GUEST_OS_ID:
1352 case HV_X64_MSR_HYPERCALL:
1353 r = true;
1354 break;
1355 }
1356
1357 return r;
1358 }
1359
1360 static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1361 {
1362 struct kvm *kvm = vcpu->kvm;
1363
1364 switch (msr) {
1365 case HV_X64_MSR_GUEST_OS_ID:
1366 kvm->arch.hv_guest_os_id = data;
1367 /* setting guest os id to zero disables hypercall page */
1368 if (!kvm->arch.hv_guest_os_id)
1369 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1370 break;
1371 case HV_X64_MSR_HYPERCALL: {
1372 u64 gfn;
1373 unsigned long addr;
1374 u8 instructions[4];
1375
1376 /* if guest os id is not set hypercall should remain disabled */
1377 if (!kvm->arch.hv_guest_os_id)
1378 break;
1379 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1380 kvm->arch.hv_hypercall = data;
1381 break;
1382 }
1383 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1384 addr = gfn_to_hva(kvm, gfn);
1385 if (kvm_is_error_hva(addr))
1386 return 1;
1387 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1388 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1389 if (copy_to_user((void __user *)addr, instructions, 4))
1390 return 1;
1391 kvm->arch.hv_hypercall = data;
1392 break;
1393 }
1394 default:
1395 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1396 "data 0x%llx\n", msr, data);
1397 return 1;
1398 }
1399 return 0;
1400 }
1401
1402 static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1403 {
1404 switch (msr) {
1405 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1406 unsigned long addr;
1407
1408 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1409 vcpu->arch.hv_vapic = data;
1410 break;
1411 }
1412 addr = gfn_to_hva(vcpu->kvm, data >>
1413 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1414 if (kvm_is_error_hva(addr))
1415 return 1;
1416 if (clear_user((void __user *)addr, PAGE_SIZE))
1417 return 1;
1418 vcpu->arch.hv_vapic = data;
1419 break;
1420 }
1421 case HV_X64_MSR_EOI:
1422 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1423 case HV_X64_MSR_ICR:
1424 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1425 case HV_X64_MSR_TPR:
1426 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1427 default:
1428 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1429 "data 0x%llx\n", msr, data);
1430 return 1;
1431 }
1432
1433 return 0;
1434 }
1435
1436 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1437 {
1438 gpa_t gpa = data & ~0x3f;
1439
1440 /* Bits 2:5 are resrved, Should be zero */
1441 if (data & 0x3c)
1442 return 1;
1443
1444 vcpu->arch.apf.msr_val = data;
1445
1446 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1447 kvm_clear_async_pf_completion_queue(vcpu);
1448 kvm_async_pf_hash_reset(vcpu);
1449 return 0;
1450 }
1451
1452 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa))
1453 return 1;
1454
1455 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
1456 kvm_async_pf_wakeup_all(vcpu);
1457 return 0;
1458 }
1459
1460 static void kvmclock_reset(struct kvm_vcpu *vcpu)
1461 {
1462 if (vcpu->arch.time_page) {
1463 kvm_release_page_dirty(vcpu->arch.time_page);
1464 vcpu->arch.time_page = NULL;
1465 }
1466 }
1467
1468 int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1469 {
1470 switch (msr) {
1471 case MSR_EFER:
1472 return set_efer(vcpu, data);
1473 case MSR_K7_HWCR:
1474 data &= ~(u64)0x40; /* ignore flush filter disable */
1475 data &= ~(u64)0x100; /* ignore ignne emulation enable */
1476 if (data != 0) {
1477 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1478 data);
1479 return 1;
1480 }
1481 break;
1482 case MSR_FAM10H_MMIO_CONF_BASE:
1483 if (data != 0) {
1484 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1485 "0x%llx\n", data);
1486 return 1;
1487 }
1488 break;
1489 case MSR_AMD64_NB_CFG:
1490 break;
1491 case MSR_IA32_DEBUGCTLMSR:
1492 if (!data) {
1493 /* We support the non-activated case already */
1494 break;
1495 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1496 /* Values other than LBR and BTF are vendor-specific,
1497 thus reserved and should throw a #GP */
1498 return 1;
1499 }
1500 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1501 __func__, data);
1502 break;
1503 case MSR_IA32_UCODE_REV:
1504 case MSR_IA32_UCODE_WRITE:
1505 case MSR_VM_HSAVE_PA:
1506 case MSR_AMD64_PATCH_LOADER:
1507 break;
1508 case 0x200 ... 0x2ff:
1509 return set_msr_mtrr(vcpu, msr, data);
1510 case MSR_IA32_APICBASE:
1511 kvm_set_apic_base(vcpu, data);
1512 break;
1513 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1514 return kvm_x2apic_msr_write(vcpu, msr, data);
1515 case MSR_IA32_MISC_ENABLE:
1516 vcpu->arch.ia32_misc_enable_msr = data;
1517 break;
1518 case MSR_KVM_WALL_CLOCK_NEW:
1519 case MSR_KVM_WALL_CLOCK:
1520 vcpu->kvm->arch.wall_clock = data;
1521 kvm_write_wall_clock(vcpu->kvm, data);
1522 break;
1523 case MSR_KVM_SYSTEM_TIME_NEW:
1524 case MSR_KVM_SYSTEM_TIME: {
1525 kvmclock_reset(vcpu);
1526
1527 vcpu->arch.time = data;
1528 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1529
1530 /* we verify if the enable bit is set... */
1531 if (!(data & 1))
1532 break;
1533
1534 /* ...but clean it before doing the actual write */
1535 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1536
1537 vcpu->arch.time_page =
1538 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
1539
1540 if (is_error_page(vcpu->arch.time_page)) {
1541 kvm_release_page_clean(vcpu->arch.time_page);
1542 vcpu->arch.time_page = NULL;
1543 }
1544 break;
1545 }
1546 case MSR_KVM_ASYNC_PF_EN:
1547 if (kvm_pv_enable_async_pf(vcpu, data))
1548 return 1;
1549 break;
1550 case MSR_IA32_MCG_CTL:
1551 case MSR_IA32_MCG_STATUS:
1552 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1553 return set_msr_mce(vcpu, msr, data);
1554
1555 /* Performance counters are not protected by a CPUID bit,
1556 * so we should check all of them in the generic path for the sake of
1557 * cross vendor migration.
1558 * Writing a zero into the event select MSRs disables them,
1559 * which we perfectly emulate ;-). Any other value should be at least
1560 * reported, some guests depend on them.
1561 */
1562 case MSR_P6_EVNTSEL0:
1563 case MSR_P6_EVNTSEL1:
1564 case MSR_K7_EVNTSEL0:
1565 case MSR_K7_EVNTSEL1:
1566 case MSR_K7_EVNTSEL2:
1567 case MSR_K7_EVNTSEL3:
1568 if (data != 0)
1569 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1570 "0x%x data 0x%llx\n", msr, data);
1571 break;
1572 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1573 * so we ignore writes to make it happy.
1574 */
1575 case MSR_P6_PERFCTR0:
1576 case MSR_P6_PERFCTR1:
1577 case MSR_K7_PERFCTR0:
1578 case MSR_K7_PERFCTR1:
1579 case MSR_K7_PERFCTR2:
1580 case MSR_K7_PERFCTR3:
1581 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1582 "0x%x data 0x%llx\n", msr, data);
1583 break;
1584 case MSR_K7_CLK_CTL:
1585 /*
1586 * Ignore all writes to this no longer documented MSR.
1587 * Writes are only relevant for old K7 processors,
1588 * all pre-dating SVM, but a recommended workaround from
1589 * AMD for these chips. It is possible to speicify the
1590 * affected processor models on the command line, hence
1591 * the need to ignore the workaround.
1592 */
1593 break;
1594 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1595 if (kvm_hv_msr_partition_wide(msr)) {
1596 int r;
1597 mutex_lock(&vcpu->kvm->lock);
1598 r = set_msr_hyperv_pw(vcpu, msr, data);
1599 mutex_unlock(&vcpu->kvm->lock);
1600 return r;
1601 } else
1602 return set_msr_hyperv(vcpu, msr, data);
1603 break;
1604 case MSR_IA32_BBL_CR_CTL3:
1605 /* Drop writes to this legacy MSR -- see rdmsr
1606 * counterpart for further detail.
1607 */
1608 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
1609 break;
1610 default:
1611 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1612 return xen_hvm_config(vcpu, data);
1613 if (!ignore_msrs) {
1614 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1615 msr, data);
1616 return 1;
1617 } else {
1618 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1619 msr, data);
1620 break;
1621 }
1622 }
1623 return 0;
1624 }
1625 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1626
1627
1628 /*
1629 * Reads an msr value (of 'msr_index') into 'pdata'.
1630 * Returns 0 on success, non-0 otherwise.
1631 * Assumes vcpu_load() was already called.
1632 */
1633 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1634 {
1635 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1636 }
1637
1638 static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1639 {
1640 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1641
1642 if (!msr_mtrr_valid(msr))
1643 return 1;
1644
1645 if (msr == MSR_MTRRdefType)
1646 *pdata = vcpu->arch.mtrr_state.def_type +
1647 (vcpu->arch.mtrr_state.enabled << 10);
1648 else if (msr == MSR_MTRRfix64K_00000)
1649 *pdata = p[0];
1650 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1651 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1652 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1653 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1654 else if (msr == MSR_IA32_CR_PAT)
1655 *pdata = vcpu->arch.pat;
1656 else { /* Variable MTRRs */
1657 int idx, is_mtrr_mask;
1658 u64 *pt;
1659
1660 idx = (msr - 0x200) / 2;
1661 is_mtrr_mask = msr - 0x200 - 2 * idx;
1662 if (!is_mtrr_mask)
1663 pt =
1664 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1665 else
1666 pt =
1667 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1668 *pdata = *pt;
1669 }
1670
1671 return 0;
1672 }
1673
1674 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1675 {
1676 u64 data;
1677 u64 mcg_cap = vcpu->arch.mcg_cap;
1678 unsigned bank_num = mcg_cap & 0xff;
1679
1680 switch (msr) {
1681 case MSR_IA32_P5_MC_ADDR:
1682 case MSR_IA32_P5_MC_TYPE:
1683 data = 0;
1684 break;
1685 case MSR_IA32_MCG_CAP:
1686 data = vcpu->arch.mcg_cap;
1687 break;
1688 case MSR_IA32_MCG_CTL:
1689 if (!(mcg_cap & MCG_CTL_P))
1690 return 1;
1691 data = vcpu->arch.mcg_ctl;
1692 break;
1693 case MSR_IA32_MCG_STATUS:
1694 data = vcpu->arch.mcg_status;
1695 break;
1696 default:
1697 if (msr >= MSR_IA32_MC0_CTL &&
1698 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1699 u32 offset = msr - MSR_IA32_MC0_CTL;
1700 data = vcpu->arch.mce_banks[offset];
1701 break;
1702 }
1703 return 1;
1704 }
1705 *pdata = data;
1706 return 0;
1707 }
1708
1709 static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1710 {
1711 u64 data = 0;
1712 struct kvm *kvm = vcpu->kvm;
1713
1714 switch (msr) {
1715 case HV_X64_MSR_GUEST_OS_ID:
1716 data = kvm->arch.hv_guest_os_id;
1717 break;
1718 case HV_X64_MSR_HYPERCALL:
1719 data = kvm->arch.hv_hypercall;
1720 break;
1721 default:
1722 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1723 return 1;
1724 }
1725
1726 *pdata = data;
1727 return 0;
1728 }
1729
1730 static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1731 {
1732 u64 data = 0;
1733
1734 switch (msr) {
1735 case HV_X64_MSR_VP_INDEX: {
1736 int r;
1737 struct kvm_vcpu *v;
1738 kvm_for_each_vcpu(r, v, vcpu->kvm)
1739 if (v == vcpu)
1740 data = r;
1741 break;
1742 }
1743 case HV_X64_MSR_EOI:
1744 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1745 case HV_X64_MSR_ICR:
1746 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1747 case HV_X64_MSR_TPR:
1748 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
1749 default:
1750 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1751 return 1;
1752 }
1753 *pdata = data;
1754 return 0;
1755 }
1756
1757 int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1758 {
1759 u64 data;
1760
1761 switch (msr) {
1762 case MSR_IA32_PLATFORM_ID:
1763 case MSR_IA32_UCODE_REV:
1764 case MSR_IA32_EBL_CR_POWERON:
1765 case MSR_IA32_DEBUGCTLMSR:
1766 case MSR_IA32_LASTBRANCHFROMIP:
1767 case MSR_IA32_LASTBRANCHTOIP:
1768 case MSR_IA32_LASTINTFROMIP:
1769 case MSR_IA32_LASTINTTOIP:
1770 case MSR_K8_SYSCFG:
1771 case MSR_K7_HWCR:
1772 case MSR_VM_HSAVE_PA:
1773 case MSR_P6_PERFCTR0:
1774 case MSR_P6_PERFCTR1:
1775 case MSR_P6_EVNTSEL0:
1776 case MSR_P6_EVNTSEL1:
1777 case MSR_K7_EVNTSEL0:
1778 case MSR_K7_PERFCTR0:
1779 case MSR_K8_INT_PENDING_MSG:
1780 case MSR_AMD64_NB_CFG:
1781 case MSR_FAM10H_MMIO_CONF_BASE:
1782 data = 0;
1783 break;
1784 case MSR_MTRRcap:
1785 data = 0x500 | KVM_NR_VAR_MTRR;
1786 break;
1787 case 0x200 ... 0x2ff:
1788 return get_msr_mtrr(vcpu, msr, pdata);
1789 case 0xcd: /* fsb frequency */
1790 data = 3;
1791 break;
1792 /*
1793 * MSR_EBC_FREQUENCY_ID
1794 * Conservative value valid for even the basic CPU models.
1795 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
1796 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
1797 * and 266MHz for model 3, or 4. Set Core Clock
1798 * Frequency to System Bus Frequency Ratio to 1 (bits
1799 * 31:24) even though these are only valid for CPU
1800 * models > 2, however guests may end up dividing or
1801 * multiplying by zero otherwise.
1802 */
1803 case MSR_EBC_FREQUENCY_ID:
1804 data = 1 << 24;
1805 break;
1806 case MSR_IA32_APICBASE:
1807 data = kvm_get_apic_base(vcpu);
1808 break;
1809 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1810 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1811 break;
1812 case MSR_IA32_MISC_ENABLE:
1813 data = vcpu->arch.ia32_misc_enable_msr;
1814 break;
1815 case MSR_IA32_PERF_STATUS:
1816 /* TSC increment by tick */
1817 data = 1000ULL;
1818 /* CPU multiplier */
1819 data |= (((uint64_t)4ULL) << 40);
1820 break;
1821 case MSR_EFER:
1822 data = vcpu->arch.efer;
1823 break;
1824 case MSR_KVM_WALL_CLOCK:
1825 case MSR_KVM_WALL_CLOCK_NEW:
1826 data = vcpu->kvm->arch.wall_clock;
1827 break;
1828 case MSR_KVM_SYSTEM_TIME:
1829 case MSR_KVM_SYSTEM_TIME_NEW:
1830 data = vcpu->arch.time;
1831 break;
1832 case MSR_KVM_ASYNC_PF_EN:
1833 data = vcpu->arch.apf.msr_val;
1834 break;
1835 case MSR_IA32_P5_MC_ADDR:
1836 case MSR_IA32_P5_MC_TYPE:
1837 case MSR_IA32_MCG_CAP:
1838 case MSR_IA32_MCG_CTL:
1839 case MSR_IA32_MCG_STATUS:
1840 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1841 return get_msr_mce(vcpu, msr, pdata);
1842 case MSR_K7_CLK_CTL:
1843 /*
1844 * Provide expected ramp-up count for K7. All other
1845 * are set to zero, indicating minimum divisors for
1846 * every field.
1847 *
1848 * This prevents guest kernels on AMD host with CPU
1849 * type 6, model 8 and higher from exploding due to
1850 * the rdmsr failing.
1851 */
1852 data = 0x20000000;
1853 break;
1854 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1855 if (kvm_hv_msr_partition_wide(msr)) {
1856 int r;
1857 mutex_lock(&vcpu->kvm->lock);
1858 r = get_msr_hyperv_pw(vcpu, msr, pdata);
1859 mutex_unlock(&vcpu->kvm->lock);
1860 return r;
1861 } else
1862 return get_msr_hyperv(vcpu, msr, pdata);
1863 break;
1864 case MSR_IA32_BBL_CR_CTL3:
1865 /* This legacy MSR exists but isn't fully documented in current
1866 * silicon. It is however accessed by winxp in very narrow
1867 * scenarios where it sets bit #19, itself documented as
1868 * a "reserved" bit. Best effort attempt to source coherent
1869 * read data here should the balance of the register be
1870 * interpreted by the guest:
1871 *
1872 * L2 cache control register 3: 64GB range, 256KB size,
1873 * enabled, latency 0x1, configured
1874 */
1875 data = 0xbe702111;
1876 break;
1877 default:
1878 if (!ignore_msrs) {
1879 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1880 return 1;
1881 } else {
1882 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1883 data = 0;
1884 }
1885 break;
1886 }
1887 *pdata = data;
1888 return 0;
1889 }
1890 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1891
1892 /*
1893 * Read or write a bunch of msrs. All parameters are kernel addresses.
1894 *
1895 * @return number of msrs set successfully.
1896 */
1897 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1898 struct kvm_msr_entry *entries,
1899 int (*do_msr)(struct kvm_vcpu *vcpu,
1900 unsigned index, u64 *data))
1901 {
1902 int i, idx;
1903
1904 idx = srcu_read_lock(&vcpu->kvm->srcu);
1905 for (i = 0; i < msrs->nmsrs; ++i)
1906 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1907 break;
1908 srcu_read_unlock(&vcpu->kvm->srcu, idx);
1909
1910 return i;
1911 }
1912
1913 /*
1914 * Read or write a bunch of msrs. Parameters are user addresses.
1915 *
1916 * @return number of msrs set successfully.
1917 */
1918 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1919 int (*do_msr)(struct kvm_vcpu *vcpu,
1920 unsigned index, u64 *data),
1921 int writeback)
1922 {
1923 struct kvm_msrs msrs;
1924 struct kvm_msr_entry *entries;
1925 int r, n;
1926 unsigned size;
1927
1928 r = -EFAULT;
1929 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1930 goto out;
1931
1932 r = -E2BIG;
1933 if (msrs.nmsrs >= MAX_IO_MSRS)
1934 goto out;
1935
1936 r = -ENOMEM;
1937 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
1938 entries = kmalloc(size, GFP_KERNEL);
1939 if (!entries)
1940 goto out;
1941
1942 r = -EFAULT;
1943 if (copy_from_user(entries, user_msrs->entries, size))
1944 goto out_free;
1945
1946 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1947 if (r < 0)
1948 goto out_free;
1949
1950 r = -EFAULT;
1951 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1952 goto out_free;
1953
1954 r = n;
1955
1956 out_free:
1957 kfree(entries);
1958 out:
1959 return r;
1960 }
1961
1962 int kvm_dev_ioctl_check_extension(long ext)
1963 {
1964 int r;
1965
1966 switch (ext) {
1967 case KVM_CAP_IRQCHIP:
1968 case KVM_CAP_HLT:
1969 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
1970 case KVM_CAP_SET_TSS_ADDR:
1971 case KVM_CAP_EXT_CPUID:
1972 case KVM_CAP_CLOCKSOURCE:
1973 case KVM_CAP_PIT:
1974 case KVM_CAP_NOP_IO_DELAY:
1975 case KVM_CAP_MP_STATE:
1976 case KVM_CAP_SYNC_MMU:
1977 case KVM_CAP_USER_NMI:
1978 case KVM_CAP_REINJECT_CONTROL:
1979 case KVM_CAP_IRQ_INJECT_STATUS:
1980 case KVM_CAP_ASSIGN_DEV_IRQ:
1981 case KVM_CAP_IRQFD:
1982 case KVM_CAP_IOEVENTFD:
1983 case KVM_CAP_PIT2:
1984 case KVM_CAP_PIT_STATE2:
1985 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
1986 case KVM_CAP_XEN_HVM:
1987 case KVM_CAP_ADJUST_CLOCK:
1988 case KVM_CAP_VCPU_EVENTS:
1989 case KVM_CAP_HYPERV:
1990 case KVM_CAP_HYPERV_VAPIC:
1991 case KVM_CAP_HYPERV_SPIN:
1992 case KVM_CAP_PCI_SEGMENT:
1993 case KVM_CAP_DEBUGREGS:
1994 case KVM_CAP_X86_ROBUST_SINGLESTEP:
1995 case KVM_CAP_XSAVE:
1996 case KVM_CAP_ASYNC_PF:
1997 case KVM_CAP_GET_TSC_KHZ:
1998 r = 1;
1999 break;
2000 case KVM_CAP_COALESCED_MMIO:
2001 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2002 break;
2003 case KVM_CAP_VAPIC:
2004 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2005 break;
2006 case KVM_CAP_NR_VCPUS:
2007 r = KVM_MAX_VCPUS;
2008 break;
2009 case KVM_CAP_NR_MEMSLOTS:
2010 r = KVM_MEMORY_SLOTS;
2011 break;
2012 case KVM_CAP_PV_MMU: /* obsolete */
2013 r = 0;
2014 break;
2015 case KVM_CAP_IOMMU:
2016 r = iommu_found();
2017 break;
2018 case KVM_CAP_MCE:
2019 r = KVM_MAX_MCE_BANKS;
2020 break;
2021 case KVM_CAP_XCRS:
2022 r = cpu_has_xsave;
2023 break;
2024 case KVM_CAP_TSC_CONTROL:
2025 r = kvm_has_tsc_control;
2026 break;
2027 default:
2028 r = 0;
2029 break;
2030 }
2031 return r;
2032
2033 }
2034
2035 long kvm_arch_dev_ioctl(struct file *filp,
2036 unsigned int ioctl, unsigned long arg)
2037 {
2038 void __user *argp = (void __user *)arg;
2039 long r;
2040
2041 switch (ioctl) {
2042 case KVM_GET_MSR_INDEX_LIST: {
2043 struct kvm_msr_list __user *user_msr_list = argp;
2044 struct kvm_msr_list msr_list;
2045 unsigned n;
2046
2047 r = -EFAULT;
2048 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2049 goto out;
2050 n = msr_list.nmsrs;
2051 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2052 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2053 goto out;
2054 r = -E2BIG;
2055 if (n < msr_list.nmsrs)
2056 goto out;
2057 r = -EFAULT;
2058 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2059 num_msrs_to_save * sizeof(u32)))
2060 goto out;
2061 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2062 &emulated_msrs,
2063 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2064 goto out;
2065 r = 0;
2066 break;
2067 }
2068 case KVM_GET_SUPPORTED_CPUID: {
2069 struct kvm_cpuid2 __user *cpuid_arg = argp;
2070 struct kvm_cpuid2 cpuid;
2071
2072 r = -EFAULT;
2073 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2074 goto out;
2075 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
2076 cpuid_arg->entries);
2077 if (r)
2078 goto out;
2079
2080 r = -EFAULT;
2081 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2082 goto out;
2083 r = 0;
2084 break;
2085 }
2086 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2087 u64 mce_cap;
2088
2089 mce_cap = KVM_MCE_CAP_SUPPORTED;
2090 r = -EFAULT;
2091 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2092 goto out;
2093 r = 0;
2094 break;
2095 }
2096 default:
2097 r = -EINVAL;
2098 }
2099 out:
2100 return r;
2101 }
2102
2103 static void wbinvd_ipi(void *garbage)
2104 {
2105 wbinvd();
2106 }
2107
2108 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2109 {
2110 return vcpu->kvm->arch.iommu_domain &&
2111 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2112 }
2113
2114 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2115 {
2116 /* Address WBINVD may be executed by guest */
2117 if (need_emulate_wbinvd(vcpu)) {
2118 if (kvm_x86_ops->has_wbinvd_exit())
2119 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2120 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2121 smp_call_function_single(vcpu->cpu,
2122 wbinvd_ipi, NULL, 1);
2123 }
2124
2125 kvm_x86_ops->vcpu_load(vcpu, cpu);
2126 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2127 /* Make sure TSC doesn't go backwards */
2128 s64 tsc_delta;
2129 u64 tsc;
2130
2131 kvm_get_msr(vcpu, MSR_IA32_TSC, &tsc);
2132 tsc_delta = !vcpu->arch.last_guest_tsc ? 0 :
2133 tsc - vcpu->arch.last_guest_tsc;
2134
2135 if (tsc_delta < 0)
2136 mark_tsc_unstable("KVM discovered backwards TSC");
2137 if (check_tsc_unstable()) {
2138 kvm_x86_ops->adjust_tsc_offset(vcpu, -tsc_delta);
2139 vcpu->arch.tsc_catchup = 1;
2140 }
2141 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2142 if (vcpu->cpu != cpu)
2143 kvm_migrate_timers(vcpu);
2144 vcpu->cpu = cpu;
2145 }
2146 }
2147
2148 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2149 {
2150 kvm_x86_ops->vcpu_put(vcpu);
2151 kvm_put_guest_fpu(vcpu);
2152 kvm_get_msr(vcpu, MSR_IA32_TSC, &vcpu->arch.last_guest_tsc);
2153 }
2154
2155 static int is_efer_nx(void)
2156 {
2157 unsigned long long efer = 0;
2158
2159 rdmsrl_safe(MSR_EFER, &efer);
2160 return efer & EFER_NX;
2161 }
2162
2163 static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
2164 {
2165 int i;
2166 struct kvm_cpuid_entry2 *e, *entry;
2167
2168 entry = NULL;
2169 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
2170 e = &vcpu->arch.cpuid_entries[i];
2171 if (e->function == 0x80000001) {
2172 entry = e;
2173 break;
2174 }
2175 }
2176 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
2177 entry->edx &= ~(1 << 20);
2178 printk(KERN_INFO "kvm: guest NX capability removed\n");
2179 }
2180 }
2181
2182 /* when an old userspace process fills a new kernel module */
2183 static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
2184 struct kvm_cpuid *cpuid,
2185 struct kvm_cpuid_entry __user *entries)
2186 {
2187 int r, i;
2188 struct kvm_cpuid_entry *cpuid_entries;
2189
2190 r = -E2BIG;
2191 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2192 goto out;
2193 r = -ENOMEM;
2194 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
2195 if (!cpuid_entries)
2196 goto out;
2197 r = -EFAULT;
2198 if (copy_from_user(cpuid_entries, entries,
2199 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
2200 goto out_free;
2201 for (i = 0; i < cpuid->nent; i++) {
2202 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
2203 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
2204 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
2205 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
2206 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
2207 vcpu->arch.cpuid_entries[i].index = 0;
2208 vcpu->arch.cpuid_entries[i].flags = 0;
2209 vcpu->arch.cpuid_entries[i].padding[0] = 0;
2210 vcpu->arch.cpuid_entries[i].padding[1] = 0;
2211 vcpu->arch.cpuid_entries[i].padding[2] = 0;
2212 }
2213 vcpu->arch.cpuid_nent = cpuid->nent;
2214 cpuid_fix_nx_cap(vcpu);
2215 r = 0;
2216 kvm_apic_set_version(vcpu);
2217 kvm_x86_ops->cpuid_update(vcpu);
2218 update_cpuid(vcpu);
2219
2220 out_free:
2221 vfree(cpuid_entries);
2222 out:
2223 return r;
2224 }
2225
2226 static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
2227 struct kvm_cpuid2 *cpuid,
2228 struct kvm_cpuid_entry2 __user *entries)
2229 {
2230 int r;
2231
2232 r = -E2BIG;
2233 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2234 goto out;
2235 r = -EFAULT;
2236 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
2237 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
2238 goto out;
2239 vcpu->arch.cpuid_nent = cpuid->nent;
2240 kvm_apic_set_version(vcpu);
2241 kvm_x86_ops->cpuid_update(vcpu);
2242 update_cpuid(vcpu);
2243 return 0;
2244
2245 out:
2246 return r;
2247 }
2248
2249 static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
2250 struct kvm_cpuid2 *cpuid,
2251 struct kvm_cpuid_entry2 __user *entries)
2252 {
2253 int r;
2254
2255 r = -E2BIG;
2256 if (cpuid->nent < vcpu->arch.cpuid_nent)
2257 goto out;
2258 r = -EFAULT;
2259 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
2260 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
2261 goto out;
2262 return 0;
2263
2264 out:
2265 cpuid->nent = vcpu->arch.cpuid_nent;
2266 return r;
2267 }
2268
2269 static void cpuid_mask(u32 *word, int wordnum)
2270 {
2271 *word &= boot_cpu_data.x86_capability[wordnum];
2272 }
2273
2274 static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
2275 u32 index)
2276 {
2277 entry->function = function;
2278 entry->index = index;
2279 cpuid_count(entry->function, entry->index,
2280 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
2281 entry->flags = 0;
2282 }
2283
2284 #define F(x) bit(X86_FEATURE_##x)
2285
2286 static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
2287 u32 index, int *nent, int maxnent)
2288 {
2289 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
2290 #ifdef CONFIG_X86_64
2291 unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL)
2292 ? F(GBPAGES) : 0;
2293 unsigned f_lm = F(LM);
2294 #else
2295 unsigned f_gbpages = 0;
2296 unsigned f_lm = 0;
2297 #endif
2298 unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
2299
2300 /* cpuid 1.edx */
2301 const u32 kvm_supported_word0_x86_features =
2302 F(FPU) | F(VME) | F(DE) | F(PSE) |
2303 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2304 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
2305 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2306 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
2307 0 /* Reserved, DS, ACPI */ | F(MMX) |
2308 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
2309 0 /* HTT, TM, Reserved, PBE */;
2310 /* cpuid 0x80000001.edx */
2311 const u32 kvm_supported_word1_x86_features =
2312 F(FPU) | F(VME) | F(DE) | F(PSE) |
2313 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2314 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
2315 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2316 F(PAT) | F(PSE36) | 0 /* Reserved */ |
2317 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
2318 F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
2319 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
2320 /* cpuid 1.ecx */
2321 const u32 kvm_supported_word4_x86_features =
2322 F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ |
2323 0 /* DS-CPL, VMX, SMX, EST */ |
2324 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
2325 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
2326 0 /* Reserved, DCA */ | F(XMM4_1) |
2327 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
2328 0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) |
2329 F(F16C);
2330 /* cpuid 0x80000001.ecx */
2331 const u32 kvm_supported_word6_x86_features =
2332 F(LAHF_LM) | F(CMP_LEGACY) | 0 /*SVM*/ | 0 /* ExtApicSpace */ |
2333 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
2334 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(XOP) |
2335 0 /* SKINIT, WDT, LWP */ | F(FMA4) | F(TBM);
2336
2337 /* all calls to cpuid_count() should be made on the same cpu */
2338 get_cpu();
2339 do_cpuid_1_ent(entry, function, index);
2340 ++*nent;
2341
2342 switch (function) {
2343 case 0:
2344 entry->eax = min(entry->eax, (u32)0xd);
2345 break;
2346 case 1:
2347 entry->edx &= kvm_supported_word0_x86_features;
2348 cpuid_mask(&entry->edx, 0);
2349 entry->ecx &= kvm_supported_word4_x86_features;
2350 cpuid_mask(&entry->ecx, 4);
2351 /* we support x2apic emulation even if host does not support
2352 * it since we emulate x2apic in software */
2353 entry->ecx |= F(X2APIC);
2354 break;
2355 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
2356 * may return different values. This forces us to get_cpu() before
2357 * issuing the first command, and also to emulate this annoying behavior
2358 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
2359 case 2: {
2360 int t, times = entry->eax & 0xff;
2361
2362 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
2363 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
2364 for (t = 1; t < times && *nent < maxnent; ++t) {
2365 do_cpuid_1_ent(&entry[t], function, 0);
2366 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
2367 ++*nent;
2368 }
2369 break;
2370 }
2371 /* function 4 and 0xb have additional index. */
2372 case 4: {
2373 int i, cache_type;
2374
2375 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2376 /* read more entries until cache_type is zero */
2377 for (i = 1; *nent < maxnent; ++i) {
2378 cache_type = entry[i - 1].eax & 0x1f;
2379 if (!cache_type)
2380 break;
2381 do_cpuid_1_ent(&entry[i], function, i);
2382 entry[i].flags |=
2383 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2384 ++*nent;
2385 }
2386 break;
2387 }
2388 case 0xb: {
2389 int i, level_type;
2390
2391 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2392 /* read more entries until level_type is zero */
2393 for (i = 1; *nent < maxnent; ++i) {
2394 level_type = entry[i - 1].ecx & 0xff00;
2395 if (!level_type)
2396 break;
2397 do_cpuid_1_ent(&entry[i], function, i);
2398 entry[i].flags |=
2399 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2400 ++*nent;
2401 }
2402 break;
2403 }
2404 case 0xd: {
2405 int i;
2406
2407 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2408 for (i = 1; *nent < maxnent && i < 64; ++i) {
2409 if (entry[i].eax == 0)
2410 continue;
2411 do_cpuid_1_ent(&entry[i], function, i);
2412 entry[i].flags |=
2413 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2414 ++*nent;
2415 }
2416 break;
2417 }
2418 case KVM_CPUID_SIGNATURE: {
2419 char signature[12] = "KVMKVMKVM\0\0";
2420 u32 *sigptr = (u32 *)signature;
2421 entry->eax = 0;
2422 entry->ebx = sigptr[0];
2423 entry->ecx = sigptr[1];
2424 entry->edx = sigptr[2];
2425 break;
2426 }
2427 case KVM_CPUID_FEATURES:
2428 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) |
2429 (1 << KVM_FEATURE_NOP_IO_DELAY) |
2430 (1 << KVM_FEATURE_CLOCKSOURCE2) |
2431 (1 << KVM_FEATURE_ASYNC_PF) |
2432 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
2433 entry->ebx = 0;
2434 entry->ecx = 0;
2435 entry->edx = 0;
2436 break;
2437 case 0x80000000:
2438 entry->eax = min(entry->eax, 0x8000001a);
2439 break;
2440 case 0x80000001:
2441 entry->edx &= kvm_supported_word1_x86_features;
2442 cpuid_mask(&entry->edx, 1);
2443 entry->ecx &= kvm_supported_word6_x86_features;
2444 cpuid_mask(&entry->ecx, 6);
2445 break;
2446 }
2447
2448 kvm_x86_ops->set_supported_cpuid(function, entry);
2449
2450 put_cpu();
2451 }
2452
2453 #undef F
2454
2455 static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
2456 struct kvm_cpuid_entry2 __user *entries)
2457 {
2458 struct kvm_cpuid_entry2 *cpuid_entries;
2459 int limit, nent = 0, r = -E2BIG;
2460 u32 func;
2461
2462 if (cpuid->nent < 1)
2463 goto out;
2464 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2465 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
2466 r = -ENOMEM;
2467 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
2468 if (!cpuid_entries)
2469 goto out;
2470
2471 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
2472 limit = cpuid_entries[0].eax;
2473 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
2474 do_cpuid_ent(&cpuid_entries[nent], func, 0,
2475 &nent, cpuid->nent);
2476 r = -E2BIG;
2477 if (nent >= cpuid->nent)
2478 goto out_free;
2479
2480 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
2481 limit = cpuid_entries[nent - 1].eax;
2482 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
2483 do_cpuid_ent(&cpuid_entries[nent], func, 0,
2484 &nent, cpuid->nent);
2485
2486
2487
2488 r = -E2BIG;
2489 if (nent >= cpuid->nent)
2490 goto out_free;
2491
2492 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_SIGNATURE, 0, &nent,
2493 cpuid->nent);
2494
2495 r = -E2BIG;
2496 if (nent >= cpuid->nent)
2497 goto out_free;
2498
2499 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_FEATURES, 0, &nent,
2500 cpuid->nent);
2501
2502 r = -E2BIG;
2503 if (nent >= cpuid->nent)
2504 goto out_free;
2505
2506 r = -EFAULT;
2507 if (copy_to_user(entries, cpuid_entries,
2508 nent * sizeof(struct kvm_cpuid_entry2)))
2509 goto out_free;
2510 cpuid->nent = nent;
2511 r = 0;
2512
2513 out_free:
2514 vfree(cpuid_entries);
2515 out:
2516 return r;
2517 }
2518
2519 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2520 struct kvm_lapic_state *s)
2521 {
2522 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
2523
2524 return 0;
2525 }
2526
2527 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2528 struct kvm_lapic_state *s)
2529 {
2530 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
2531 kvm_apic_post_state_restore(vcpu);
2532 update_cr8_intercept(vcpu);
2533
2534 return 0;
2535 }
2536
2537 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2538 struct kvm_interrupt *irq)
2539 {
2540 if (irq->irq < 0 || irq->irq >= 256)
2541 return -EINVAL;
2542 if (irqchip_in_kernel(vcpu->kvm))
2543 return -ENXIO;
2544
2545 kvm_queue_interrupt(vcpu, irq->irq, false);
2546 kvm_make_request(KVM_REQ_EVENT, vcpu);
2547
2548 return 0;
2549 }
2550
2551 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2552 {
2553 kvm_inject_nmi(vcpu);
2554
2555 return 0;
2556 }
2557
2558 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2559 struct kvm_tpr_access_ctl *tac)
2560 {
2561 if (tac->flags)
2562 return -EINVAL;
2563 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2564 return 0;
2565 }
2566
2567 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2568 u64 mcg_cap)
2569 {
2570 int r;
2571 unsigned bank_num = mcg_cap & 0xff, bank;
2572
2573 r = -EINVAL;
2574 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
2575 goto out;
2576 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2577 goto out;
2578 r = 0;
2579 vcpu->arch.mcg_cap = mcg_cap;
2580 /* Init IA32_MCG_CTL to all 1s */
2581 if (mcg_cap & MCG_CTL_P)
2582 vcpu->arch.mcg_ctl = ~(u64)0;
2583 /* Init IA32_MCi_CTL to all 1s */
2584 for (bank = 0; bank < bank_num; bank++)
2585 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2586 out:
2587 return r;
2588 }
2589
2590 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2591 struct kvm_x86_mce *mce)
2592 {
2593 u64 mcg_cap = vcpu->arch.mcg_cap;
2594 unsigned bank_num = mcg_cap & 0xff;
2595 u64 *banks = vcpu->arch.mce_banks;
2596
2597 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2598 return -EINVAL;
2599 /*
2600 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2601 * reporting is disabled
2602 */
2603 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2604 vcpu->arch.mcg_ctl != ~(u64)0)
2605 return 0;
2606 banks += 4 * mce->bank;
2607 /*
2608 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2609 * reporting is disabled for the bank
2610 */
2611 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2612 return 0;
2613 if (mce->status & MCI_STATUS_UC) {
2614 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
2615 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
2616 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2617 return 0;
2618 }
2619 if (banks[1] & MCI_STATUS_VAL)
2620 mce->status |= MCI_STATUS_OVER;
2621 banks[2] = mce->addr;
2622 banks[3] = mce->misc;
2623 vcpu->arch.mcg_status = mce->mcg_status;
2624 banks[1] = mce->status;
2625 kvm_queue_exception(vcpu, MC_VECTOR);
2626 } else if (!(banks[1] & MCI_STATUS_VAL)
2627 || !(banks[1] & MCI_STATUS_UC)) {
2628 if (banks[1] & MCI_STATUS_VAL)
2629 mce->status |= MCI_STATUS_OVER;
2630 banks[2] = mce->addr;
2631 banks[3] = mce->misc;
2632 banks[1] = mce->status;
2633 } else
2634 banks[1] |= MCI_STATUS_OVER;
2635 return 0;
2636 }
2637
2638 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2639 struct kvm_vcpu_events *events)
2640 {
2641 events->exception.injected =
2642 vcpu->arch.exception.pending &&
2643 !kvm_exception_is_soft(vcpu->arch.exception.nr);
2644 events->exception.nr = vcpu->arch.exception.nr;
2645 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2646 events->exception.pad = 0;
2647 events->exception.error_code = vcpu->arch.exception.error_code;
2648
2649 events->interrupt.injected =
2650 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
2651 events->interrupt.nr = vcpu->arch.interrupt.nr;
2652 events->interrupt.soft = 0;
2653 events->interrupt.shadow =
2654 kvm_x86_ops->get_interrupt_shadow(vcpu,
2655 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
2656
2657 events->nmi.injected = vcpu->arch.nmi_injected;
2658 events->nmi.pending = vcpu->arch.nmi_pending;
2659 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2660 events->nmi.pad = 0;
2661
2662 events->sipi_vector = vcpu->arch.sipi_vector;
2663
2664 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
2665 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2666 | KVM_VCPUEVENT_VALID_SHADOW);
2667 memset(&events->reserved, 0, sizeof(events->reserved));
2668 }
2669
2670 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2671 struct kvm_vcpu_events *events)
2672 {
2673 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
2674 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2675 | KVM_VCPUEVENT_VALID_SHADOW))
2676 return -EINVAL;
2677
2678 vcpu->arch.exception.pending = events->exception.injected;
2679 vcpu->arch.exception.nr = events->exception.nr;
2680 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2681 vcpu->arch.exception.error_code = events->exception.error_code;
2682
2683 vcpu->arch.interrupt.pending = events->interrupt.injected;
2684 vcpu->arch.interrupt.nr = events->interrupt.nr;
2685 vcpu->arch.interrupt.soft = events->interrupt.soft;
2686 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2687 kvm_x86_ops->set_interrupt_shadow(vcpu,
2688 events->interrupt.shadow);
2689
2690 vcpu->arch.nmi_injected = events->nmi.injected;
2691 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2692 vcpu->arch.nmi_pending = events->nmi.pending;
2693 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2694
2695 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2696 vcpu->arch.sipi_vector = events->sipi_vector;
2697
2698 kvm_make_request(KVM_REQ_EVENT, vcpu);
2699
2700 return 0;
2701 }
2702
2703 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2704 struct kvm_debugregs *dbgregs)
2705 {
2706 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2707 dbgregs->dr6 = vcpu->arch.dr6;
2708 dbgregs->dr7 = vcpu->arch.dr7;
2709 dbgregs->flags = 0;
2710 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
2711 }
2712
2713 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2714 struct kvm_debugregs *dbgregs)
2715 {
2716 if (dbgregs->flags)
2717 return -EINVAL;
2718
2719 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2720 vcpu->arch.dr6 = dbgregs->dr6;
2721 vcpu->arch.dr7 = dbgregs->dr7;
2722
2723 return 0;
2724 }
2725
2726 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2727 struct kvm_xsave *guest_xsave)
2728 {
2729 if (cpu_has_xsave)
2730 memcpy(guest_xsave->region,
2731 &vcpu->arch.guest_fpu.state->xsave,
2732 xstate_size);
2733 else {
2734 memcpy(guest_xsave->region,
2735 &vcpu->arch.guest_fpu.state->fxsave,
2736 sizeof(struct i387_fxsave_struct));
2737 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2738 XSTATE_FPSSE;
2739 }
2740 }
2741
2742 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2743 struct kvm_xsave *guest_xsave)
2744 {
2745 u64 xstate_bv =
2746 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2747
2748 if (cpu_has_xsave)
2749 memcpy(&vcpu->arch.guest_fpu.state->xsave,
2750 guest_xsave->region, xstate_size);
2751 else {
2752 if (xstate_bv & ~XSTATE_FPSSE)
2753 return -EINVAL;
2754 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2755 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2756 }
2757 return 0;
2758 }
2759
2760 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2761 struct kvm_xcrs *guest_xcrs)
2762 {
2763 if (!cpu_has_xsave) {
2764 guest_xcrs->nr_xcrs = 0;
2765 return;
2766 }
2767
2768 guest_xcrs->nr_xcrs = 1;
2769 guest_xcrs->flags = 0;
2770 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2771 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2772 }
2773
2774 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2775 struct kvm_xcrs *guest_xcrs)
2776 {
2777 int i, r = 0;
2778
2779 if (!cpu_has_xsave)
2780 return -EINVAL;
2781
2782 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2783 return -EINVAL;
2784
2785 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2786 /* Only support XCR0 currently */
2787 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2788 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2789 guest_xcrs->xcrs[0].value);
2790 break;
2791 }
2792 if (r)
2793 r = -EINVAL;
2794 return r;
2795 }
2796
2797 long kvm_arch_vcpu_ioctl(struct file *filp,
2798 unsigned int ioctl, unsigned long arg)
2799 {
2800 struct kvm_vcpu *vcpu = filp->private_data;
2801 void __user *argp = (void __user *)arg;
2802 int r;
2803 union {
2804 struct kvm_lapic_state *lapic;
2805 struct kvm_xsave *xsave;
2806 struct kvm_xcrs *xcrs;
2807 void *buffer;
2808 } u;
2809
2810 u.buffer = NULL;
2811 switch (ioctl) {
2812 case KVM_GET_LAPIC: {
2813 r = -EINVAL;
2814 if (!vcpu->arch.apic)
2815 goto out;
2816 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
2817
2818 r = -ENOMEM;
2819 if (!u.lapic)
2820 goto out;
2821 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
2822 if (r)
2823 goto out;
2824 r = -EFAULT;
2825 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
2826 goto out;
2827 r = 0;
2828 break;
2829 }
2830 case KVM_SET_LAPIC: {
2831 r = -EINVAL;
2832 if (!vcpu->arch.apic)
2833 goto out;
2834 u.lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
2835 r = -ENOMEM;
2836 if (!u.lapic)
2837 goto out;
2838 r = -EFAULT;
2839 if (copy_from_user(u.lapic, argp, sizeof(struct kvm_lapic_state)))
2840 goto out;
2841 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
2842 if (r)
2843 goto out;
2844 r = 0;
2845 break;
2846 }
2847 case KVM_INTERRUPT: {
2848 struct kvm_interrupt irq;
2849
2850 r = -EFAULT;
2851 if (copy_from_user(&irq, argp, sizeof irq))
2852 goto out;
2853 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2854 if (r)
2855 goto out;
2856 r = 0;
2857 break;
2858 }
2859 case KVM_NMI: {
2860 r = kvm_vcpu_ioctl_nmi(vcpu);
2861 if (r)
2862 goto out;
2863 r = 0;
2864 break;
2865 }
2866 case KVM_SET_CPUID: {
2867 struct kvm_cpuid __user *cpuid_arg = argp;
2868 struct kvm_cpuid cpuid;
2869
2870 r = -EFAULT;
2871 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2872 goto out;
2873 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2874 if (r)
2875 goto out;
2876 break;
2877 }
2878 case KVM_SET_CPUID2: {
2879 struct kvm_cpuid2 __user *cpuid_arg = argp;
2880 struct kvm_cpuid2 cpuid;
2881
2882 r = -EFAULT;
2883 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2884 goto out;
2885 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
2886 cpuid_arg->entries);
2887 if (r)
2888 goto out;
2889 break;
2890 }
2891 case KVM_GET_CPUID2: {
2892 struct kvm_cpuid2 __user *cpuid_arg = argp;
2893 struct kvm_cpuid2 cpuid;
2894
2895 r = -EFAULT;
2896 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2897 goto out;
2898 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
2899 cpuid_arg->entries);
2900 if (r)
2901 goto out;
2902 r = -EFAULT;
2903 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2904 goto out;
2905 r = 0;
2906 break;
2907 }
2908 case KVM_GET_MSRS:
2909 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2910 break;
2911 case KVM_SET_MSRS:
2912 r = msr_io(vcpu, argp, do_set_msr, 0);
2913 break;
2914 case KVM_TPR_ACCESS_REPORTING: {
2915 struct kvm_tpr_access_ctl tac;
2916
2917 r = -EFAULT;
2918 if (copy_from_user(&tac, argp, sizeof tac))
2919 goto out;
2920 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2921 if (r)
2922 goto out;
2923 r = -EFAULT;
2924 if (copy_to_user(argp, &tac, sizeof tac))
2925 goto out;
2926 r = 0;
2927 break;
2928 };
2929 case KVM_SET_VAPIC_ADDR: {
2930 struct kvm_vapic_addr va;
2931
2932 r = -EINVAL;
2933 if (!irqchip_in_kernel(vcpu->kvm))
2934 goto out;
2935 r = -EFAULT;
2936 if (copy_from_user(&va, argp, sizeof va))
2937 goto out;
2938 r = 0;
2939 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2940 break;
2941 }
2942 case KVM_X86_SETUP_MCE: {
2943 u64 mcg_cap;
2944
2945 r = -EFAULT;
2946 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2947 goto out;
2948 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2949 break;
2950 }
2951 case KVM_X86_SET_MCE: {
2952 struct kvm_x86_mce mce;
2953
2954 r = -EFAULT;
2955 if (copy_from_user(&mce, argp, sizeof mce))
2956 goto out;
2957 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2958 break;
2959 }
2960 case KVM_GET_VCPU_EVENTS: {
2961 struct kvm_vcpu_events events;
2962
2963 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2964
2965 r = -EFAULT;
2966 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2967 break;
2968 r = 0;
2969 break;
2970 }
2971 case KVM_SET_VCPU_EVENTS: {
2972 struct kvm_vcpu_events events;
2973
2974 r = -EFAULT;
2975 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2976 break;
2977
2978 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2979 break;
2980 }
2981 case KVM_GET_DEBUGREGS: {
2982 struct kvm_debugregs dbgregs;
2983
2984 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2985
2986 r = -EFAULT;
2987 if (copy_to_user(argp, &dbgregs,
2988 sizeof(struct kvm_debugregs)))
2989 break;
2990 r = 0;
2991 break;
2992 }
2993 case KVM_SET_DEBUGREGS: {
2994 struct kvm_debugregs dbgregs;
2995
2996 r = -EFAULT;
2997 if (copy_from_user(&dbgregs, argp,
2998 sizeof(struct kvm_debugregs)))
2999 break;
3000
3001 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3002 break;
3003 }
3004 case KVM_GET_XSAVE: {
3005 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
3006 r = -ENOMEM;
3007 if (!u.xsave)
3008 break;
3009
3010 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
3011
3012 r = -EFAULT;
3013 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
3014 break;
3015 r = 0;
3016 break;
3017 }
3018 case KVM_SET_XSAVE: {
3019 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
3020 r = -ENOMEM;
3021 if (!u.xsave)
3022 break;
3023
3024 r = -EFAULT;
3025 if (copy_from_user(u.xsave, argp, sizeof(struct kvm_xsave)))
3026 break;
3027
3028 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
3029 break;
3030 }
3031 case KVM_GET_XCRS: {
3032 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
3033 r = -ENOMEM;
3034 if (!u.xcrs)
3035 break;
3036
3037 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
3038
3039 r = -EFAULT;
3040 if (copy_to_user(argp, u.xcrs,
3041 sizeof(struct kvm_xcrs)))
3042 break;
3043 r = 0;
3044 break;
3045 }
3046 case KVM_SET_XCRS: {
3047 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
3048 r = -ENOMEM;
3049 if (!u.xcrs)
3050 break;
3051
3052 r = -EFAULT;
3053 if (copy_from_user(u.xcrs, argp,
3054 sizeof(struct kvm_xcrs)))
3055 break;
3056
3057 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
3058 break;
3059 }
3060 case KVM_SET_TSC_KHZ: {
3061 u32 user_tsc_khz;
3062
3063 r = -EINVAL;
3064 if (!kvm_has_tsc_control)
3065 break;
3066
3067 user_tsc_khz = (u32)arg;
3068
3069 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3070 goto out;
3071
3072 kvm_x86_ops->set_tsc_khz(vcpu, user_tsc_khz);
3073
3074 r = 0;
3075 goto out;
3076 }
3077 case KVM_GET_TSC_KHZ: {
3078 r = -EIO;
3079 if (check_tsc_unstable())
3080 goto out;
3081
3082 r = vcpu_tsc_khz(vcpu);
3083
3084 goto out;
3085 }
3086 default:
3087 r = -EINVAL;
3088 }
3089 out:
3090 kfree(u.buffer);
3091 return r;
3092 }
3093
3094 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3095 {
3096 int ret;
3097
3098 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3099 return -1;
3100 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3101 return ret;
3102 }
3103
3104 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3105 u64 ident_addr)
3106 {
3107 kvm->arch.ept_identity_map_addr = ident_addr;
3108 return 0;
3109 }
3110
3111 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3112 u32 kvm_nr_mmu_pages)
3113 {
3114 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3115 return -EINVAL;
3116
3117 mutex_lock(&kvm->slots_lock);
3118 spin_lock(&kvm->mmu_lock);
3119
3120 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
3121 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
3122
3123 spin_unlock(&kvm->mmu_lock);
3124 mutex_unlock(&kvm->slots_lock);
3125 return 0;
3126 }
3127
3128 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3129 {
3130 return kvm->arch.n_max_mmu_pages;
3131 }
3132
3133 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3134 {
3135 int r;
3136
3137 r = 0;
3138 switch (chip->chip_id) {
3139 case KVM_IRQCHIP_PIC_MASTER:
3140 memcpy(&chip->chip.pic,
3141 &pic_irqchip(kvm)->pics[0],
3142 sizeof(struct kvm_pic_state));
3143 break;
3144 case KVM_IRQCHIP_PIC_SLAVE:
3145 memcpy(&chip->chip.pic,
3146 &pic_irqchip(kvm)->pics[1],
3147 sizeof(struct kvm_pic_state));
3148 break;
3149 case KVM_IRQCHIP_IOAPIC:
3150 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
3151 break;
3152 default:
3153 r = -EINVAL;
3154 break;
3155 }
3156 return r;
3157 }
3158
3159 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3160 {
3161 int r;
3162
3163 r = 0;
3164 switch (chip->chip_id) {
3165 case KVM_IRQCHIP_PIC_MASTER:
3166 spin_lock(&pic_irqchip(kvm)->lock);
3167 memcpy(&pic_irqchip(kvm)->pics[0],
3168 &chip->chip.pic,
3169 sizeof(struct kvm_pic_state));
3170 spin_unlock(&pic_irqchip(kvm)->lock);
3171 break;
3172 case KVM_IRQCHIP_PIC_SLAVE:
3173 spin_lock(&pic_irqchip(kvm)->lock);
3174 memcpy(&pic_irqchip(kvm)->pics[1],
3175 &chip->chip.pic,
3176 sizeof(struct kvm_pic_state));
3177 spin_unlock(&pic_irqchip(kvm)->lock);
3178 break;
3179 case KVM_IRQCHIP_IOAPIC:
3180 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
3181 break;
3182 default:
3183 r = -EINVAL;
3184 break;
3185 }
3186 kvm_pic_update_irq(pic_irqchip(kvm));
3187 return r;
3188 }
3189
3190 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3191 {
3192 int r = 0;
3193
3194 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3195 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
3196 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3197 return r;
3198 }
3199
3200 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3201 {
3202 int r = 0;
3203
3204 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3205 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
3206 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3207 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3208 return r;
3209 }
3210
3211 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3212 {
3213 int r = 0;
3214
3215 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3216 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3217 sizeof(ps->channels));
3218 ps->flags = kvm->arch.vpit->pit_state.flags;
3219 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3220 memset(&ps->reserved, 0, sizeof(ps->reserved));
3221 return r;
3222 }
3223
3224 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3225 {
3226 int r = 0, start = 0;
3227 u32 prev_legacy, cur_legacy;
3228 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3229 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3230 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3231 if (!prev_legacy && cur_legacy)
3232 start = 1;
3233 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3234 sizeof(kvm->arch.vpit->pit_state.channels));
3235 kvm->arch.vpit->pit_state.flags = ps->flags;
3236 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
3237 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3238 return r;
3239 }
3240
3241 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3242 struct kvm_reinject_control *control)
3243 {
3244 if (!kvm->arch.vpit)
3245 return -ENXIO;
3246 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3247 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
3248 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3249 return 0;
3250 }
3251
3252 /*
3253 * Get (and clear) the dirty memory log for a memory slot.
3254 */
3255 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
3256 struct kvm_dirty_log *log)
3257 {
3258 int r, i;
3259 struct kvm_memory_slot *memslot;
3260 unsigned long n;
3261 unsigned long is_dirty = 0;
3262
3263 mutex_lock(&kvm->slots_lock);
3264
3265 r = -EINVAL;
3266 if (log->slot >= KVM_MEMORY_SLOTS)
3267 goto out;
3268
3269 memslot = &kvm->memslots->memslots[log->slot];
3270 r = -ENOENT;
3271 if (!memslot->dirty_bitmap)
3272 goto out;
3273
3274 n = kvm_dirty_bitmap_bytes(memslot);
3275
3276 for (i = 0; !is_dirty && i < n/sizeof(long); i++)
3277 is_dirty = memslot->dirty_bitmap[i];
3278
3279 /* If nothing is dirty, don't bother messing with page tables. */
3280 if (is_dirty) {
3281 struct kvm_memslots *slots, *old_slots;
3282 unsigned long *dirty_bitmap;
3283
3284 dirty_bitmap = memslot->dirty_bitmap_head;
3285 if (memslot->dirty_bitmap == dirty_bitmap)
3286 dirty_bitmap += n / sizeof(long);
3287 memset(dirty_bitmap, 0, n);
3288
3289 r = -ENOMEM;
3290 slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL);
3291 if (!slots)
3292 goto out;
3293 memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots));
3294 slots->memslots[log->slot].dirty_bitmap = dirty_bitmap;
3295 slots->generation++;
3296
3297 old_slots = kvm->memslots;
3298 rcu_assign_pointer(kvm->memslots, slots);
3299 synchronize_srcu_expedited(&kvm->srcu);
3300 dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap;
3301 kfree(old_slots);
3302
3303 spin_lock(&kvm->mmu_lock);
3304 kvm_mmu_slot_remove_write_access(kvm, log->slot);
3305 spin_unlock(&kvm->mmu_lock);
3306
3307 r = -EFAULT;
3308 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n))
3309 goto out;
3310 } else {
3311 r = -EFAULT;
3312 if (clear_user(log->dirty_bitmap, n))
3313 goto out;
3314 }
3315
3316 r = 0;
3317 out:
3318 mutex_unlock(&kvm->slots_lock);
3319 return r;
3320 }
3321
3322 long kvm_arch_vm_ioctl(struct file *filp,
3323 unsigned int ioctl, unsigned long arg)
3324 {
3325 struct kvm *kvm = filp->private_data;
3326 void __user *argp = (void __user *)arg;
3327 int r = -ENOTTY;
3328 /*
3329 * This union makes it completely explicit to gcc-3.x
3330 * that these two variables' stack usage should be
3331 * combined, not added together.
3332 */
3333 union {
3334 struct kvm_pit_state ps;
3335 struct kvm_pit_state2 ps2;
3336 struct kvm_pit_config pit_config;
3337 } u;
3338
3339 switch (ioctl) {
3340 case KVM_SET_TSS_ADDR:
3341 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3342 if (r < 0)
3343 goto out;
3344 break;
3345 case KVM_SET_IDENTITY_MAP_ADDR: {
3346 u64 ident_addr;
3347
3348 r = -EFAULT;
3349 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3350 goto out;
3351 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3352 if (r < 0)
3353 goto out;
3354 break;
3355 }
3356 case KVM_SET_NR_MMU_PAGES:
3357 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3358 if (r)
3359 goto out;
3360 break;
3361 case KVM_GET_NR_MMU_PAGES:
3362 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3363 break;
3364 case KVM_CREATE_IRQCHIP: {
3365 struct kvm_pic *vpic;
3366
3367 mutex_lock(&kvm->lock);
3368 r = -EEXIST;
3369 if (kvm->arch.vpic)
3370 goto create_irqchip_unlock;
3371 r = -ENOMEM;
3372 vpic = kvm_create_pic(kvm);
3373 if (vpic) {
3374 r = kvm_ioapic_init(kvm);
3375 if (r) {
3376 mutex_lock(&kvm->slots_lock);
3377 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3378 &vpic->dev);
3379 mutex_unlock(&kvm->slots_lock);
3380 kfree(vpic);
3381 goto create_irqchip_unlock;
3382 }
3383 } else
3384 goto create_irqchip_unlock;
3385 smp_wmb();
3386 kvm->arch.vpic = vpic;
3387 smp_wmb();
3388 r = kvm_setup_default_irq_routing(kvm);
3389 if (r) {
3390 mutex_lock(&kvm->slots_lock);
3391 mutex_lock(&kvm->irq_lock);
3392 kvm_ioapic_destroy(kvm);
3393 kvm_destroy_pic(kvm);
3394 mutex_unlock(&kvm->irq_lock);
3395 mutex_unlock(&kvm->slots_lock);
3396 }
3397 create_irqchip_unlock:
3398 mutex_unlock(&kvm->lock);
3399 break;
3400 }
3401 case KVM_CREATE_PIT:
3402 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3403 goto create_pit;
3404 case KVM_CREATE_PIT2:
3405 r = -EFAULT;
3406 if (copy_from_user(&u.pit_config, argp,
3407 sizeof(struct kvm_pit_config)))
3408 goto out;
3409 create_pit:
3410 mutex_lock(&kvm->slots_lock);
3411 r = -EEXIST;
3412 if (kvm->arch.vpit)
3413 goto create_pit_unlock;
3414 r = -ENOMEM;
3415 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
3416 if (kvm->arch.vpit)
3417 r = 0;
3418 create_pit_unlock:
3419 mutex_unlock(&kvm->slots_lock);
3420 break;
3421 case KVM_IRQ_LINE_STATUS:
3422 case KVM_IRQ_LINE: {
3423 struct kvm_irq_level irq_event;
3424
3425 r = -EFAULT;
3426 if (copy_from_user(&irq_event, argp, sizeof irq_event))
3427 goto out;
3428 r = -ENXIO;
3429 if (irqchip_in_kernel(kvm)) {
3430 __s32 status;
3431 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3432 irq_event.irq, irq_event.level);
3433 if (ioctl == KVM_IRQ_LINE_STATUS) {
3434 r = -EFAULT;
3435 irq_event.status = status;
3436 if (copy_to_user(argp, &irq_event,
3437 sizeof irq_event))
3438 goto out;
3439 }
3440 r = 0;
3441 }
3442 break;
3443 }
3444 case KVM_GET_IRQCHIP: {
3445 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3446 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
3447
3448 r = -ENOMEM;
3449 if (!chip)
3450 goto out;
3451 r = -EFAULT;
3452 if (copy_from_user(chip, argp, sizeof *chip))
3453 goto get_irqchip_out;
3454 r = -ENXIO;
3455 if (!irqchip_in_kernel(kvm))
3456 goto get_irqchip_out;
3457 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
3458 if (r)
3459 goto get_irqchip_out;
3460 r = -EFAULT;
3461 if (copy_to_user(argp, chip, sizeof *chip))
3462 goto get_irqchip_out;
3463 r = 0;
3464 get_irqchip_out:
3465 kfree(chip);
3466 if (r)
3467 goto out;
3468 break;
3469 }
3470 case KVM_SET_IRQCHIP: {
3471 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3472 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
3473
3474 r = -ENOMEM;
3475 if (!chip)
3476 goto out;
3477 r = -EFAULT;
3478 if (copy_from_user(chip, argp, sizeof *chip))
3479 goto set_irqchip_out;
3480 r = -ENXIO;
3481 if (!irqchip_in_kernel(kvm))
3482 goto set_irqchip_out;
3483 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
3484 if (r)
3485 goto set_irqchip_out;
3486 r = 0;
3487 set_irqchip_out:
3488 kfree(chip);
3489 if (r)
3490 goto out;
3491 break;
3492 }
3493 case KVM_GET_PIT: {
3494 r = -EFAULT;
3495 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
3496 goto out;
3497 r = -ENXIO;
3498 if (!kvm->arch.vpit)
3499 goto out;
3500 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
3501 if (r)
3502 goto out;
3503 r = -EFAULT;
3504 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
3505 goto out;
3506 r = 0;
3507 break;
3508 }
3509 case KVM_SET_PIT: {
3510 r = -EFAULT;
3511 if (copy_from_user(&u.ps, argp, sizeof u.ps))
3512 goto out;
3513 r = -ENXIO;
3514 if (!kvm->arch.vpit)
3515 goto out;
3516 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
3517 if (r)
3518 goto out;
3519 r = 0;
3520 break;
3521 }
3522 case KVM_GET_PIT2: {
3523 r = -ENXIO;
3524 if (!kvm->arch.vpit)
3525 goto out;
3526 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3527 if (r)
3528 goto out;
3529 r = -EFAULT;
3530 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3531 goto out;
3532 r = 0;
3533 break;
3534 }
3535 case KVM_SET_PIT2: {
3536 r = -EFAULT;
3537 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3538 goto out;
3539 r = -ENXIO;
3540 if (!kvm->arch.vpit)
3541 goto out;
3542 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3543 if (r)
3544 goto out;
3545 r = 0;
3546 break;
3547 }
3548 case KVM_REINJECT_CONTROL: {
3549 struct kvm_reinject_control control;
3550 r = -EFAULT;
3551 if (copy_from_user(&control, argp, sizeof(control)))
3552 goto out;
3553 r = kvm_vm_ioctl_reinject(kvm, &control);
3554 if (r)
3555 goto out;
3556 r = 0;
3557 break;
3558 }
3559 case KVM_XEN_HVM_CONFIG: {
3560 r = -EFAULT;
3561 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3562 sizeof(struct kvm_xen_hvm_config)))
3563 goto out;
3564 r = -EINVAL;
3565 if (kvm->arch.xen_hvm_config.flags)
3566 goto out;
3567 r = 0;
3568 break;
3569 }
3570 case KVM_SET_CLOCK: {
3571 struct kvm_clock_data user_ns;
3572 u64 now_ns;
3573 s64 delta;
3574
3575 r = -EFAULT;
3576 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3577 goto out;
3578
3579 r = -EINVAL;
3580 if (user_ns.flags)
3581 goto out;
3582
3583 r = 0;
3584 local_irq_disable();
3585 now_ns = get_kernel_ns();
3586 delta = user_ns.clock - now_ns;
3587 local_irq_enable();
3588 kvm->arch.kvmclock_offset = delta;
3589 break;
3590 }
3591 case KVM_GET_CLOCK: {
3592 struct kvm_clock_data user_ns;
3593 u64 now_ns;
3594
3595 local_irq_disable();
3596 now_ns = get_kernel_ns();
3597 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3598 local_irq_enable();
3599 user_ns.flags = 0;
3600 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
3601
3602 r = -EFAULT;
3603 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3604 goto out;
3605 r = 0;
3606 break;
3607 }
3608
3609 default:
3610 ;
3611 }
3612 out:
3613 return r;
3614 }
3615
3616 static void kvm_init_msr_list(void)
3617 {
3618 u32 dummy[2];
3619 unsigned i, j;
3620
3621 /* skip the first msrs in the list. KVM-specific */
3622 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
3623 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3624 continue;
3625 if (j < i)
3626 msrs_to_save[j] = msrs_to_save[i];
3627 j++;
3628 }
3629 num_msrs_to_save = j;
3630 }
3631
3632 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3633 const void *v)
3634 {
3635 int handled = 0;
3636 int n;
3637
3638 do {
3639 n = min(len, 8);
3640 if (!(vcpu->arch.apic &&
3641 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3642 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3643 break;
3644 handled += n;
3645 addr += n;
3646 len -= n;
3647 v += n;
3648 } while (len);
3649
3650 return handled;
3651 }
3652
3653 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
3654 {
3655 int handled = 0;
3656 int n;
3657
3658 do {
3659 n = min(len, 8);
3660 if (!(vcpu->arch.apic &&
3661 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3662 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3663 break;
3664 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3665 handled += n;
3666 addr += n;
3667 len -= n;
3668 v += n;
3669 } while (len);
3670
3671 return handled;
3672 }
3673
3674 static void kvm_set_segment(struct kvm_vcpu *vcpu,
3675 struct kvm_segment *var, int seg)
3676 {
3677 kvm_x86_ops->set_segment(vcpu, var, seg);
3678 }
3679
3680 void kvm_get_segment(struct kvm_vcpu *vcpu,
3681 struct kvm_segment *var, int seg)
3682 {
3683 kvm_x86_ops->get_segment(vcpu, var, seg);
3684 }
3685
3686 static gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3687 {
3688 return gpa;
3689 }
3690
3691 static gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3692 {
3693 gpa_t t_gpa;
3694 struct x86_exception exception;
3695
3696 BUG_ON(!mmu_is_nested(vcpu));
3697
3698 /* NPT walks are always user-walks */
3699 access |= PFERR_USER_MASK;
3700 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
3701
3702 return t_gpa;
3703 }
3704
3705 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3706 struct x86_exception *exception)
3707 {
3708 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3709 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3710 }
3711
3712 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3713 struct x86_exception *exception)
3714 {
3715 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3716 access |= PFERR_FETCH_MASK;
3717 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3718 }
3719
3720 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3721 struct x86_exception *exception)
3722 {
3723 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3724 access |= PFERR_WRITE_MASK;
3725 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3726 }
3727
3728 /* uses this to access any guest's mapped memory without checking CPL */
3729 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3730 struct x86_exception *exception)
3731 {
3732 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
3733 }
3734
3735 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3736 struct kvm_vcpu *vcpu, u32 access,
3737 struct x86_exception *exception)
3738 {
3739 void *data = val;
3740 int r = X86EMUL_CONTINUE;
3741
3742 while (bytes) {
3743 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
3744 exception);
3745 unsigned offset = addr & (PAGE_SIZE-1);
3746 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
3747 int ret;
3748
3749 if (gpa == UNMAPPED_GVA)
3750 return X86EMUL_PROPAGATE_FAULT;
3751 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
3752 if (ret < 0) {
3753 r = X86EMUL_IO_NEEDED;
3754 goto out;
3755 }
3756
3757 bytes -= toread;
3758 data += toread;
3759 addr += toread;
3760 }
3761 out:
3762 return r;
3763 }
3764
3765 /* used for instruction fetching */
3766 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
3767 gva_t addr, void *val, unsigned int bytes,
3768 struct x86_exception *exception)
3769 {
3770 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3771 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3772
3773 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
3774 access | PFERR_FETCH_MASK,
3775 exception);
3776 }
3777
3778 static int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
3779 gva_t addr, void *val, unsigned int bytes,
3780 struct x86_exception *exception)
3781 {
3782 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3783 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3784
3785 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
3786 exception);
3787 }
3788
3789 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3790 gva_t addr, void *val, unsigned int bytes,
3791 struct x86_exception *exception)
3792 {
3793 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3794 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
3795 }
3796
3797 static int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3798 gva_t addr, void *val,
3799 unsigned int bytes,
3800 struct x86_exception *exception)
3801 {
3802 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3803 void *data = val;
3804 int r = X86EMUL_CONTINUE;
3805
3806 while (bytes) {
3807 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
3808 PFERR_WRITE_MASK,
3809 exception);
3810 unsigned offset = addr & (PAGE_SIZE-1);
3811 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3812 int ret;
3813
3814 if (gpa == UNMAPPED_GVA)
3815 return X86EMUL_PROPAGATE_FAULT;
3816 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3817 if (ret < 0) {
3818 r = X86EMUL_IO_NEEDED;
3819 goto out;
3820 }
3821
3822 bytes -= towrite;
3823 data += towrite;
3824 addr += towrite;
3825 }
3826 out:
3827 return r;
3828 }
3829
3830 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
3831 unsigned long addr,
3832 void *val,
3833 unsigned int bytes,
3834 struct x86_exception *exception)
3835 {
3836 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3837 gpa_t gpa;
3838 int handled;
3839
3840 if (vcpu->mmio_read_completed) {
3841 memcpy(val, vcpu->mmio_data, bytes);
3842 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3843 vcpu->mmio_phys_addr, *(u64 *)val);
3844 vcpu->mmio_read_completed = 0;
3845 return X86EMUL_CONTINUE;
3846 }
3847
3848 gpa = kvm_mmu_gva_to_gpa_read(vcpu, addr, exception);
3849
3850 if (gpa == UNMAPPED_GVA)
3851 return X86EMUL_PROPAGATE_FAULT;
3852
3853 /* For APIC access vmexit */
3854 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3855 goto mmio;
3856
3857 if (kvm_read_guest_virt(ctxt, addr, val, bytes, exception)
3858 == X86EMUL_CONTINUE)
3859 return X86EMUL_CONTINUE;
3860
3861 mmio:
3862 /*
3863 * Is this MMIO handled locally?
3864 */
3865 handled = vcpu_mmio_read(vcpu, gpa, bytes, val);
3866
3867 if (handled == bytes)
3868 return X86EMUL_CONTINUE;
3869
3870 gpa += handled;
3871 bytes -= handled;
3872 val += handled;
3873
3874 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
3875
3876 vcpu->mmio_needed = 1;
3877 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3878 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
3879 vcpu->mmio_size = bytes;
3880 vcpu->run->mmio.len = min(vcpu->mmio_size, 8);
3881 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 0;
3882 vcpu->mmio_index = 0;
3883
3884 return X86EMUL_IO_NEEDED;
3885 }
3886
3887 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
3888 const void *val, int bytes)
3889 {
3890 int ret;
3891
3892 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
3893 if (ret < 0)
3894 return 0;
3895 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
3896 return 1;
3897 }
3898
3899 static int emulator_write_emulated_onepage(unsigned long addr,
3900 const void *val,
3901 unsigned int bytes,
3902 struct x86_exception *exception,
3903 struct kvm_vcpu *vcpu)
3904 {
3905 gpa_t gpa;
3906 int handled;
3907
3908 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, exception);
3909
3910 if (gpa == UNMAPPED_GVA)
3911 return X86EMUL_PROPAGATE_FAULT;
3912
3913 /* For APIC access vmexit */
3914 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3915 goto mmio;
3916
3917 if (emulator_write_phys(vcpu, gpa, val, bytes))
3918 return X86EMUL_CONTINUE;
3919
3920 mmio:
3921 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
3922 /*
3923 * Is this MMIO handled locally?
3924 */
3925 handled = vcpu_mmio_write(vcpu, gpa, bytes, val);
3926 if (handled == bytes)
3927 return X86EMUL_CONTINUE;
3928
3929 gpa += handled;
3930 bytes -= handled;
3931 val += handled;
3932
3933 vcpu->mmio_needed = 1;
3934 memcpy(vcpu->mmio_data, val, bytes);
3935 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3936 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
3937 vcpu->mmio_size = bytes;
3938 vcpu->run->mmio.len = min(vcpu->mmio_size, 8);
3939 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 1;
3940 memcpy(vcpu->run->mmio.data, vcpu->mmio_data, 8);
3941 vcpu->mmio_index = 0;
3942
3943 return X86EMUL_CONTINUE;
3944 }
3945
3946 int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
3947 unsigned long addr,
3948 const void *val,
3949 unsigned int bytes,
3950 struct x86_exception *exception)
3951 {
3952 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3953
3954 /* Crossing a page boundary? */
3955 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3956 int rc, now;
3957
3958 now = -addr & ~PAGE_MASK;
3959 rc = emulator_write_emulated_onepage(addr, val, now, exception,
3960 vcpu);
3961 if (rc != X86EMUL_CONTINUE)
3962 return rc;
3963 addr += now;
3964 val += now;
3965 bytes -= now;
3966 }
3967 return emulator_write_emulated_onepage(addr, val, bytes, exception,
3968 vcpu);
3969 }
3970
3971 #define CMPXCHG_TYPE(t, ptr, old, new) \
3972 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
3973
3974 #ifdef CONFIG_X86_64
3975 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
3976 #else
3977 # define CMPXCHG64(ptr, old, new) \
3978 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
3979 #endif
3980
3981 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
3982 unsigned long addr,
3983 const void *old,
3984 const void *new,
3985 unsigned int bytes,
3986 struct x86_exception *exception)
3987 {
3988 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3989 gpa_t gpa;
3990 struct page *page;
3991 char *kaddr;
3992 bool exchanged;
3993
3994 /* guests cmpxchg8b have to be emulated atomically */
3995 if (bytes > 8 || (bytes & (bytes - 1)))
3996 goto emul_write;
3997
3998 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
3999
4000 if (gpa == UNMAPPED_GVA ||
4001 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4002 goto emul_write;
4003
4004 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4005 goto emul_write;
4006
4007 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4008 if (is_error_page(page)) {
4009 kvm_release_page_clean(page);
4010 goto emul_write;
4011 }
4012
4013 kaddr = kmap_atomic(page, KM_USER0);
4014 kaddr += offset_in_page(gpa);
4015 switch (bytes) {
4016 case 1:
4017 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4018 break;
4019 case 2:
4020 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4021 break;
4022 case 4:
4023 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4024 break;
4025 case 8:
4026 exchanged = CMPXCHG64(kaddr, old, new);
4027 break;
4028 default:
4029 BUG();
4030 }
4031 kunmap_atomic(kaddr, KM_USER0);
4032 kvm_release_page_dirty(page);
4033
4034 if (!exchanged)
4035 return X86EMUL_CMPXCHG_FAILED;
4036
4037 kvm_mmu_pte_write(vcpu, gpa, new, bytes, 1);
4038
4039 return X86EMUL_CONTINUE;
4040
4041 emul_write:
4042 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
4043
4044 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
4045 }
4046
4047 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4048 {
4049 /* TODO: String I/O for in kernel device */
4050 int r;
4051
4052 if (vcpu->arch.pio.in)
4053 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4054 vcpu->arch.pio.size, pd);
4055 else
4056 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4057 vcpu->arch.pio.port, vcpu->arch.pio.size,
4058 pd);
4059 return r;
4060 }
4061
4062
4063 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4064 int size, unsigned short port, void *val,
4065 unsigned int count)
4066 {
4067 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4068
4069 if (vcpu->arch.pio.count)
4070 goto data_avail;
4071
4072 trace_kvm_pio(0, port, size, count);
4073
4074 vcpu->arch.pio.port = port;
4075 vcpu->arch.pio.in = 1;
4076 vcpu->arch.pio.count = count;
4077 vcpu->arch.pio.size = size;
4078
4079 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4080 data_avail:
4081 memcpy(val, vcpu->arch.pio_data, size * count);
4082 vcpu->arch.pio.count = 0;
4083 return 1;
4084 }
4085
4086 vcpu->run->exit_reason = KVM_EXIT_IO;
4087 vcpu->run->io.direction = KVM_EXIT_IO_IN;
4088 vcpu->run->io.size = size;
4089 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4090 vcpu->run->io.count = count;
4091 vcpu->run->io.port = port;
4092
4093 return 0;
4094 }
4095
4096 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4097 int size, unsigned short port,
4098 const void *val, unsigned int count)
4099 {
4100 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4101
4102 trace_kvm_pio(1, port, size, count);
4103
4104 vcpu->arch.pio.port = port;
4105 vcpu->arch.pio.in = 0;
4106 vcpu->arch.pio.count = count;
4107 vcpu->arch.pio.size = size;
4108
4109 memcpy(vcpu->arch.pio_data, val, size * count);
4110
4111 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4112 vcpu->arch.pio.count = 0;
4113 return 1;
4114 }
4115
4116 vcpu->run->exit_reason = KVM_EXIT_IO;
4117 vcpu->run->io.direction = KVM_EXIT_IO_OUT;
4118 vcpu->run->io.size = size;
4119 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4120 vcpu->run->io.count = count;
4121 vcpu->run->io.port = port;
4122
4123 return 0;
4124 }
4125
4126 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4127 {
4128 return kvm_x86_ops->get_segment_base(vcpu, seg);
4129 }
4130
4131 int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
4132 {
4133 kvm_mmu_invlpg(vcpu, address);
4134 return X86EMUL_CONTINUE;
4135 }
4136
4137 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4138 {
4139 if (!need_emulate_wbinvd(vcpu))
4140 return X86EMUL_CONTINUE;
4141
4142 if (kvm_x86_ops->has_wbinvd_exit()) {
4143 int cpu = get_cpu();
4144
4145 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4146 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4147 wbinvd_ipi, NULL, 1);
4148 put_cpu();
4149 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
4150 } else
4151 wbinvd();
4152 return X86EMUL_CONTINUE;
4153 }
4154 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4155
4156 int emulate_clts(struct kvm_vcpu *vcpu)
4157 {
4158 kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4159 kvm_x86_ops->fpu_activate(vcpu);
4160 return X86EMUL_CONTINUE;
4161 }
4162
4163 int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
4164 {
4165 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
4166 }
4167
4168 int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
4169 {
4170
4171 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
4172 }
4173
4174 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
4175 {
4176 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
4177 }
4178
4179 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
4180 {
4181 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4182 unsigned long value;
4183
4184 switch (cr) {
4185 case 0:
4186 value = kvm_read_cr0(vcpu);
4187 break;
4188 case 2:
4189 value = vcpu->arch.cr2;
4190 break;
4191 case 3:
4192 value = kvm_read_cr3(vcpu);
4193 break;
4194 case 4:
4195 value = kvm_read_cr4(vcpu);
4196 break;
4197 case 8:
4198 value = kvm_get_cr8(vcpu);
4199 break;
4200 default:
4201 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
4202 return 0;
4203 }
4204
4205 return value;
4206 }
4207
4208 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
4209 {
4210 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4211 int res = 0;
4212
4213 switch (cr) {
4214 case 0:
4215 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
4216 break;
4217 case 2:
4218 vcpu->arch.cr2 = val;
4219 break;
4220 case 3:
4221 res = kvm_set_cr3(vcpu, val);
4222 break;
4223 case 4:
4224 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
4225 break;
4226 case 8:
4227 res = kvm_set_cr8(vcpu, val);
4228 break;
4229 default:
4230 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
4231 res = -1;
4232 }
4233
4234 return res;
4235 }
4236
4237 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
4238 {
4239 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
4240 }
4241
4242 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4243 {
4244 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
4245 }
4246
4247 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4248 {
4249 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
4250 }
4251
4252 static unsigned long emulator_get_cached_segment_base(
4253 struct x86_emulate_ctxt *ctxt, int seg)
4254 {
4255 return get_segment_base(emul_to_vcpu(ctxt), seg);
4256 }
4257
4258 static bool emulator_get_cached_descriptor(struct x86_emulate_ctxt *ctxt,
4259 struct desc_struct *desc, u32 *base3,
4260 int seg)
4261 {
4262 struct kvm_segment var;
4263
4264 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
4265
4266 if (var.unusable)
4267 return false;
4268
4269 if (var.g)
4270 var.limit >>= 12;
4271 set_desc_limit(desc, var.limit);
4272 set_desc_base(desc, (unsigned long)var.base);
4273 #ifdef CONFIG_X86_64
4274 if (base3)
4275 *base3 = var.base >> 32;
4276 #endif
4277 desc->type = var.type;
4278 desc->s = var.s;
4279 desc->dpl = var.dpl;
4280 desc->p = var.present;
4281 desc->avl = var.avl;
4282 desc->l = var.l;
4283 desc->d = var.db;
4284 desc->g = var.g;
4285
4286 return true;
4287 }
4288
4289 static void emulator_set_cached_descriptor(struct x86_emulate_ctxt *ctxt,
4290 struct desc_struct *desc, u32 base3,
4291 int seg)
4292 {
4293 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4294 struct kvm_segment var;
4295
4296 /* needed to preserve selector */
4297 kvm_get_segment(vcpu, &var, seg);
4298
4299 var.base = get_desc_base(desc);
4300 #ifdef CONFIG_X86_64
4301 var.base |= ((u64)base3) << 32;
4302 #endif
4303 var.limit = get_desc_limit(desc);
4304 if (desc->g)
4305 var.limit = (var.limit << 12) | 0xfff;
4306 var.type = desc->type;
4307 var.present = desc->p;
4308 var.dpl = desc->dpl;
4309 var.db = desc->d;
4310 var.s = desc->s;
4311 var.l = desc->l;
4312 var.g = desc->g;
4313 var.avl = desc->avl;
4314 var.present = desc->p;
4315 var.unusable = !var.present;
4316 var.padding = 0;
4317
4318 kvm_set_segment(vcpu, &var, seg);
4319 return;
4320 }
4321
4322 static u16 emulator_get_segment_selector(struct x86_emulate_ctxt *ctxt, int seg)
4323 {
4324 struct kvm_segment kvm_seg;
4325
4326 kvm_get_segment(emul_to_vcpu(ctxt), &kvm_seg, seg);
4327 return kvm_seg.selector;
4328 }
4329
4330 static void emulator_set_segment_selector(struct x86_emulate_ctxt *ctxt,
4331 u16 sel, int seg)
4332 {
4333 struct kvm_segment kvm_seg;
4334
4335 kvm_get_segment(emul_to_vcpu(ctxt), &kvm_seg, seg);
4336 kvm_seg.selector = sel;
4337 kvm_set_segment(emul_to_vcpu(ctxt), &kvm_seg, seg);
4338 }
4339
4340 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4341 u32 msr_index, u64 *pdata)
4342 {
4343 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4344 }
4345
4346 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4347 u32 msr_index, u64 data)
4348 {
4349 return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data);
4350 }
4351
4352 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4353 {
4354 preempt_disable();
4355 kvm_load_guest_fpu(ctxt->vcpu);
4356 /*
4357 * CR0.TS may reference the host fpu state, not the guest fpu state,
4358 * so it may be clear at this point.
4359 */
4360 clts();
4361 }
4362
4363 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4364 {
4365 preempt_enable();
4366 }
4367
4368 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
4369 struct x86_instruction_info *info,
4370 enum x86_intercept_stage stage)
4371 {
4372 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
4373 }
4374
4375 static struct x86_emulate_ops emulate_ops = {
4376 .read_std = kvm_read_guest_virt_system,
4377 .write_std = kvm_write_guest_virt_system,
4378 .fetch = kvm_fetch_guest_virt,
4379 .read_emulated = emulator_read_emulated,
4380 .write_emulated = emulator_write_emulated,
4381 .cmpxchg_emulated = emulator_cmpxchg_emulated,
4382 .pio_in_emulated = emulator_pio_in_emulated,
4383 .pio_out_emulated = emulator_pio_out_emulated,
4384 .get_cached_descriptor = emulator_get_cached_descriptor,
4385 .set_cached_descriptor = emulator_set_cached_descriptor,
4386 .get_segment_selector = emulator_get_segment_selector,
4387 .set_segment_selector = emulator_set_segment_selector,
4388 .get_cached_segment_base = emulator_get_cached_segment_base,
4389 .get_gdt = emulator_get_gdt,
4390 .get_idt = emulator_get_idt,
4391 .get_cr = emulator_get_cr,
4392 .set_cr = emulator_set_cr,
4393 .cpl = emulator_get_cpl,
4394 .get_dr = emulator_get_dr,
4395 .set_dr = emulator_set_dr,
4396 .set_msr = emulator_set_msr,
4397 .get_msr = emulator_get_msr,
4398 .get_fpu = emulator_get_fpu,
4399 .put_fpu = emulator_put_fpu,
4400 .intercept = emulator_intercept,
4401 };
4402
4403 static void cache_all_regs(struct kvm_vcpu *vcpu)
4404 {
4405 kvm_register_read(vcpu, VCPU_REGS_RAX);
4406 kvm_register_read(vcpu, VCPU_REGS_RSP);
4407 kvm_register_read(vcpu, VCPU_REGS_RIP);
4408 vcpu->arch.regs_dirty = ~0;
4409 }
4410
4411 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4412 {
4413 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4414 /*
4415 * an sti; sti; sequence only disable interrupts for the first
4416 * instruction. So, if the last instruction, be it emulated or
4417 * not, left the system with the INT_STI flag enabled, it
4418 * means that the last instruction is an sti. We should not
4419 * leave the flag on in this case. The same goes for mov ss
4420 */
4421 if (!(int_shadow & mask))
4422 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4423 }
4424
4425 static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4426 {
4427 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4428 if (ctxt->exception.vector == PF_VECTOR)
4429 kvm_propagate_fault(vcpu, &ctxt->exception);
4430 else if (ctxt->exception.error_code_valid)
4431 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4432 ctxt->exception.error_code);
4433 else
4434 kvm_queue_exception(vcpu, ctxt->exception.vector);
4435 }
4436
4437 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4438 {
4439 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
4440 int cs_db, cs_l;
4441
4442 cache_all_regs(vcpu);
4443
4444 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4445
4446 vcpu->arch.emulate_ctxt.vcpu = vcpu;
4447 vcpu->arch.emulate_ctxt.eflags = kvm_get_rflags(vcpu);
4448 vcpu->arch.emulate_ctxt.eip = kvm_rip_read(vcpu);
4449 vcpu->arch.emulate_ctxt.mode =
4450 (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4451 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
4452 ? X86EMUL_MODE_VM86 : cs_l
4453 ? X86EMUL_MODE_PROT64 : cs_db
4454 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
4455 vcpu->arch.emulate_ctxt.guest_mode = is_guest_mode(vcpu);
4456 memset(c, 0, sizeof(struct decode_cache));
4457 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
4458 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
4459 }
4460
4461 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
4462 {
4463 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
4464 int ret;
4465
4466 init_emulate_ctxt(vcpu);
4467
4468 vcpu->arch.emulate_ctxt.decode.op_bytes = 2;
4469 vcpu->arch.emulate_ctxt.decode.ad_bytes = 2;
4470 vcpu->arch.emulate_ctxt.decode.eip = vcpu->arch.emulate_ctxt.eip +
4471 inc_eip;
4472 ret = emulate_int_real(&vcpu->arch.emulate_ctxt, &emulate_ops, irq);
4473
4474 if (ret != X86EMUL_CONTINUE)
4475 return EMULATE_FAIL;
4476
4477 vcpu->arch.emulate_ctxt.eip = c->eip;
4478 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
4479 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
4480 kvm_set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
4481
4482 if (irq == NMI_VECTOR)
4483 vcpu->arch.nmi_pending = false;
4484 else
4485 vcpu->arch.interrupt.pending = false;
4486
4487 return EMULATE_DONE;
4488 }
4489 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4490
4491 static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4492 {
4493 int r = EMULATE_DONE;
4494
4495 ++vcpu->stat.insn_emulation_fail;
4496 trace_kvm_emulate_insn_failed(vcpu);
4497 if (!is_guest_mode(vcpu)) {
4498 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4499 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4500 vcpu->run->internal.ndata = 0;
4501 r = EMULATE_FAIL;
4502 }
4503 kvm_queue_exception(vcpu, UD_VECTOR);
4504
4505 return r;
4506 }
4507
4508 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
4509 {
4510 gpa_t gpa;
4511
4512 if (tdp_enabled)
4513 return false;
4514
4515 /*
4516 * if emulation was due to access to shadowed page table
4517 * and it failed try to unshadow page and re-entetr the
4518 * guest to let CPU execute the instruction.
4519 */
4520 if (kvm_mmu_unprotect_page_virt(vcpu, gva))
4521 return true;
4522
4523 gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL);
4524
4525 if (gpa == UNMAPPED_GVA)
4526 return true; /* let cpu generate fault */
4527
4528 if (!kvm_is_error_hva(gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT)))
4529 return true;
4530
4531 return false;
4532 }
4533
4534 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
4535 unsigned long cr2,
4536 int emulation_type,
4537 void *insn,
4538 int insn_len)
4539 {
4540 int r;
4541 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
4542 bool writeback = true;
4543
4544 kvm_clear_exception_queue(vcpu);
4545 vcpu->arch.mmio_fault_cr2 = cr2;
4546 /*
4547 * TODO: fix emulate.c to use guest_read/write_register
4548 * instead of direct ->regs accesses, can save hundred cycles
4549 * on Intel for instructions that don't read/change RSP, for
4550 * for example.
4551 */
4552 cache_all_regs(vcpu);
4553
4554 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
4555 init_emulate_ctxt(vcpu);
4556 vcpu->arch.emulate_ctxt.interruptibility = 0;
4557 vcpu->arch.emulate_ctxt.have_exception = false;
4558 vcpu->arch.emulate_ctxt.perm_ok = false;
4559
4560 vcpu->arch.emulate_ctxt.only_vendor_specific_insn
4561 = emulation_type & EMULTYPE_TRAP_UD;
4562
4563 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, insn, insn_len);
4564
4565 trace_kvm_emulate_insn_start(vcpu);
4566 ++vcpu->stat.insn_emulation;
4567 if (r) {
4568 if (emulation_type & EMULTYPE_TRAP_UD)
4569 return EMULATE_FAIL;
4570 if (reexecute_instruction(vcpu, cr2))
4571 return EMULATE_DONE;
4572 if (emulation_type & EMULTYPE_SKIP)
4573 return EMULATE_FAIL;
4574 return handle_emulation_failure(vcpu);
4575 }
4576 }
4577
4578 if (emulation_type & EMULTYPE_SKIP) {
4579 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
4580 return EMULATE_DONE;
4581 }
4582
4583 /* this is needed for vmware backdoor interface to work since it
4584 changes registers values during IO operation */
4585 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
4586 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
4587 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
4588 }
4589
4590 restart:
4591 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt);
4592
4593 if (r == EMULATION_INTERCEPTED)
4594 return EMULATE_DONE;
4595
4596 if (r == EMULATION_FAILED) {
4597 if (reexecute_instruction(vcpu, cr2))
4598 return EMULATE_DONE;
4599
4600 return handle_emulation_failure(vcpu);
4601 }
4602
4603 if (vcpu->arch.emulate_ctxt.have_exception) {
4604 inject_emulated_exception(vcpu);
4605 r = EMULATE_DONE;
4606 } else if (vcpu->arch.pio.count) {
4607 if (!vcpu->arch.pio.in)
4608 vcpu->arch.pio.count = 0;
4609 else
4610 writeback = false;
4611 r = EMULATE_DO_MMIO;
4612 } else if (vcpu->mmio_needed) {
4613 if (!vcpu->mmio_is_write)
4614 writeback = false;
4615 r = EMULATE_DO_MMIO;
4616 } else if (r == EMULATION_RESTART)
4617 goto restart;
4618 else
4619 r = EMULATE_DONE;
4620
4621 if (writeback) {
4622 toggle_interruptibility(vcpu,
4623 vcpu->arch.emulate_ctxt.interruptibility);
4624 kvm_set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
4625 kvm_make_request(KVM_REQ_EVENT, vcpu);
4626 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
4627 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
4628 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
4629 } else
4630 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
4631
4632 return r;
4633 }
4634 EXPORT_SYMBOL_GPL(x86_emulate_instruction);
4635
4636 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
4637 {
4638 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
4639 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
4640 size, port, &val, 1);
4641 /* do not return to emulator after return from userspace */
4642 vcpu->arch.pio.count = 0;
4643 return ret;
4644 }
4645 EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
4646
4647 static void tsc_bad(void *info)
4648 {
4649 __this_cpu_write(cpu_tsc_khz, 0);
4650 }
4651
4652 static void tsc_khz_changed(void *data)
4653 {
4654 struct cpufreq_freqs *freq = data;
4655 unsigned long khz = 0;
4656
4657 if (data)
4658 khz = freq->new;
4659 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4660 khz = cpufreq_quick_get(raw_smp_processor_id());
4661 if (!khz)
4662 khz = tsc_khz;
4663 __this_cpu_write(cpu_tsc_khz, khz);
4664 }
4665
4666 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
4667 void *data)
4668 {
4669 struct cpufreq_freqs *freq = data;
4670 struct kvm *kvm;
4671 struct kvm_vcpu *vcpu;
4672 int i, send_ipi = 0;
4673
4674 /*
4675 * We allow guests to temporarily run on slowing clocks,
4676 * provided we notify them after, or to run on accelerating
4677 * clocks, provided we notify them before. Thus time never
4678 * goes backwards.
4679 *
4680 * However, we have a problem. We can't atomically update
4681 * the frequency of a given CPU from this function; it is
4682 * merely a notifier, which can be called from any CPU.
4683 * Changing the TSC frequency at arbitrary points in time
4684 * requires a recomputation of local variables related to
4685 * the TSC for each VCPU. We must flag these local variables
4686 * to be updated and be sure the update takes place with the
4687 * new frequency before any guests proceed.
4688 *
4689 * Unfortunately, the combination of hotplug CPU and frequency
4690 * change creates an intractable locking scenario; the order
4691 * of when these callouts happen is undefined with respect to
4692 * CPU hotplug, and they can race with each other. As such,
4693 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
4694 * undefined; you can actually have a CPU frequency change take
4695 * place in between the computation of X and the setting of the
4696 * variable. To protect against this problem, all updates of
4697 * the per_cpu tsc_khz variable are done in an interrupt
4698 * protected IPI, and all callers wishing to update the value
4699 * must wait for a synchronous IPI to complete (which is trivial
4700 * if the caller is on the CPU already). This establishes the
4701 * necessary total order on variable updates.
4702 *
4703 * Note that because a guest time update may take place
4704 * anytime after the setting of the VCPU's request bit, the
4705 * correct TSC value must be set before the request. However,
4706 * to ensure the update actually makes it to any guest which
4707 * starts running in hardware virtualization between the set
4708 * and the acquisition of the spinlock, we must also ping the
4709 * CPU after setting the request bit.
4710 *
4711 */
4712
4713 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
4714 return 0;
4715 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
4716 return 0;
4717
4718 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
4719
4720 raw_spin_lock(&kvm_lock);
4721 list_for_each_entry(kvm, &vm_list, vm_list) {
4722 kvm_for_each_vcpu(i, vcpu, kvm) {
4723 if (vcpu->cpu != freq->cpu)
4724 continue;
4725 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
4726 if (vcpu->cpu != smp_processor_id())
4727 send_ipi = 1;
4728 }
4729 }
4730 raw_spin_unlock(&kvm_lock);
4731
4732 if (freq->old < freq->new && send_ipi) {
4733 /*
4734 * We upscale the frequency. Must make the guest
4735 * doesn't see old kvmclock values while running with
4736 * the new frequency, otherwise we risk the guest sees
4737 * time go backwards.
4738 *
4739 * In case we update the frequency for another cpu
4740 * (which might be in guest context) send an interrupt
4741 * to kick the cpu out of guest context. Next time
4742 * guest context is entered kvmclock will be updated,
4743 * so the guest will not see stale values.
4744 */
4745 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
4746 }
4747 return 0;
4748 }
4749
4750 static struct notifier_block kvmclock_cpufreq_notifier_block = {
4751 .notifier_call = kvmclock_cpufreq_notifier
4752 };
4753
4754 static int kvmclock_cpu_notifier(struct notifier_block *nfb,
4755 unsigned long action, void *hcpu)
4756 {
4757 unsigned int cpu = (unsigned long)hcpu;
4758
4759 switch (action) {
4760 case CPU_ONLINE:
4761 case CPU_DOWN_FAILED:
4762 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4763 break;
4764 case CPU_DOWN_PREPARE:
4765 smp_call_function_single(cpu, tsc_bad, NULL, 1);
4766 break;
4767 }
4768 return NOTIFY_OK;
4769 }
4770
4771 static struct notifier_block kvmclock_cpu_notifier_block = {
4772 .notifier_call = kvmclock_cpu_notifier,
4773 .priority = -INT_MAX
4774 };
4775
4776 static void kvm_timer_init(void)
4777 {
4778 int cpu;
4779
4780 max_tsc_khz = tsc_khz;
4781 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
4782 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
4783 #ifdef CONFIG_CPU_FREQ
4784 struct cpufreq_policy policy;
4785 memset(&policy, 0, sizeof(policy));
4786 cpu = get_cpu();
4787 cpufreq_get_policy(&policy, cpu);
4788 if (policy.cpuinfo.max_freq)
4789 max_tsc_khz = policy.cpuinfo.max_freq;
4790 put_cpu();
4791 #endif
4792 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
4793 CPUFREQ_TRANSITION_NOTIFIER);
4794 }
4795 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
4796 for_each_online_cpu(cpu)
4797 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4798 }
4799
4800 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
4801
4802 static int kvm_is_in_guest(void)
4803 {
4804 return percpu_read(current_vcpu) != NULL;
4805 }
4806
4807 static int kvm_is_user_mode(void)
4808 {
4809 int user_mode = 3;
4810
4811 if (percpu_read(current_vcpu))
4812 user_mode = kvm_x86_ops->get_cpl(percpu_read(current_vcpu));
4813
4814 return user_mode != 0;
4815 }
4816
4817 static unsigned long kvm_get_guest_ip(void)
4818 {
4819 unsigned long ip = 0;
4820
4821 if (percpu_read(current_vcpu))
4822 ip = kvm_rip_read(percpu_read(current_vcpu));
4823
4824 return ip;
4825 }
4826
4827 static struct perf_guest_info_callbacks kvm_guest_cbs = {
4828 .is_in_guest = kvm_is_in_guest,
4829 .is_user_mode = kvm_is_user_mode,
4830 .get_guest_ip = kvm_get_guest_ip,
4831 };
4832
4833 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
4834 {
4835 percpu_write(current_vcpu, vcpu);
4836 }
4837 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
4838
4839 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
4840 {
4841 percpu_write(current_vcpu, NULL);
4842 }
4843 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
4844
4845 int kvm_arch_init(void *opaque)
4846 {
4847 int r;
4848 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
4849
4850 if (kvm_x86_ops) {
4851 printk(KERN_ERR "kvm: already loaded the other module\n");
4852 r = -EEXIST;
4853 goto out;
4854 }
4855
4856 if (!ops->cpu_has_kvm_support()) {
4857 printk(KERN_ERR "kvm: no hardware support\n");
4858 r = -EOPNOTSUPP;
4859 goto out;
4860 }
4861 if (ops->disabled_by_bios()) {
4862 printk(KERN_ERR "kvm: disabled by bios\n");
4863 r = -EOPNOTSUPP;
4864 goto out;
4865 }
4866
4867 r = kvm_mmu_module_init();
4868 if (r)
4869 goto out;
4870
4871 kvm_init_msr_list();
4872
4873 kvm_x86_ops = ops;
4874 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
4875 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4876 PT_DIRTY_MASK, PT64_NX_MASK, 0);
4877
4878 kvm_timer_init();
4879
4880 perf_register_guest_info_callbacks(&kvm_guest_cbs);
4881
4882 if (cpu_has_xsave)
4883 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
4884
4885 return 0;
4886
4887 out:
4888 return r;
4889 }
4890
4891 void kvm_arch_exit(void)
4892 {
4893 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
4894
4895 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4896 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
4897 CPUFREQ_TRANSITION_NOTIFIER);
4898 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
4899 kvm_x86_ops = NULL;
4900 kvm_mmu_module_exit();
4901 }
4902
4903 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
4904 {
4905 ++vcpu->stat.halt_exits;
4906 if (irqchip_in_kernel(vcpu->kvm)) {
4907 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
4908 return 1;
4909 } else {
4910 vcpu->run->exit_reason = KVM_EXIT_HLT;
4911 return 0;
4912 }
4913 }
4914 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
4915
4916 static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
4917 unsigned long a1)
4918 {
4919 if (is_long_mode(vcpu))
4920 return a0;
4921 else
4922 return a0 | ((gpa_t)a1 << 32);
4923 }
4924
4925 int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
4926 {
4927 u64 param, ingpa, outgpa, ret;
4928 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
4929 bool fast, longmode;
4930 int cs_db, cs_l;
4931
4932 /*
4933 * hypercall generates UD from non zero cpl and real mode
4934 * per HYPER-V spec
4935 */
4936 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
4937 kvm_queue_exception(vcpu, UD_VECTOR);
4938 return 0;
4939 }
4940
4941 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4942 longmode = is_long_mode(vcpu) && cs_l == 1;
4943
4944 if (!longmode) {
4945 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
4946 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
4947 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
4948 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
4949 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
4950 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
4951 }
4952 #ifdef CONFIG_X86_64
4953 else {
4954 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
4955 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
4956 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
4957 }
4958 #endif
4959
4960 code = param & 0xffff;
4961 fast = (param >> 16) & 0x1;
4962 rep_cnt = (param >> 32) & 0xfff;
4963 rep_idx = (param >> 48) & 0xfff;
4964
4965 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
4966
4967 switch (code) {
4968 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
4969 kvm_vcpu_on_spin(vcpu);
4970 break;
4971 default:
4972 res = HV_STATUS_INVALID_HYPERCALL_CODE;
4973 break;
4974 }
4975
4976 ret = res | (((u64)rep_done & 0xfff) << 32);
4977 if (longmode) {
4978 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
4979 } else {
4980 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
4981 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
4982 }
4983
4984 return 1;
4985 }
4986
4987 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
4988 {
4989 unsigned long nr, a0, a1, a2, a3, ret;
4990 int r = 1;
4991
4992 if (kvm_hv_hypercall_enabled(vcpu->kvm))
4993 return kvm_hv_hypercall(vcpu);
4994
4995 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
4996 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
4997 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
4998 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
4999 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
5000
5001 trace_kvm_hypercall(nr, a0, a1, a2, a3);
5002
5003 if (!is_long_mode(vcpu)) {
5004 nr &= 0xFFFFFFFF;
5005 a0 &= 0xFFFFFFFF;
5006 a1 &= 0xFFFFFFFF;
5007 a2 &= 0xFFFFFFFF;
5008 a3 &= 0xFFFFFFFF;
5009 }
5010
5011 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5012 ret = -KVM_EPERM;
5013 goto out;
5014 }
5015
5016 switch (nr) {
5017 case KVM_HC_VAPIC_POLL_IRQ:
5018 ret = 0;
5019 break;
5020 case KVM_HC_MMU_OP:
5021 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
5022 break;
5023 default:
5024 ret = -KVM_ENOSYS;
5025 break;
5026 }
5027 out:
5028 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5029 ++vcpu->stat.hypercalls;
5030 return r;
5031 }
5032 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5033
5034 int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
5035 {
5036 char instruction[3];
5037 unsigned long rip = kvm_rip_read(vcpu);
5038
5039 /*
5040 * Blow out the MMU to ensure that no other VCPU has an active mapping
5041 * to ensure that the updated hypercall appears atomically across all
5042 * VCPUs.
5043 */
5044 kvm_mmu_zap_all(vcpu->kvm);
5045
5046 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5047
5048 return emulator_write_emulated(&vcpu->arch.emulate_ctxt,
5049 rip, instruction, 3, NULL);
5050 }
5051
5052 void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
5053 {
5054 struct desc_ptr dt = { limit, base };
5055
5056 kvm_x86_ops->set_gdt(vcpu, &dt);
5057 }
5058
5059 void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
5060 {
5061 struct desc_ptr dt = { limit, base };
5062
5063 kvm_x86_ops->set_idt(vcpu, &dt);
5064 }
5065
5066 static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
5067 {
5068 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
5069 int j, nent = vcpu->arch.cpuid_nent;
5070
5071 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
5072 /* when no next entry is found, the current entry[i] is reselected */
5073 for (j = i + 1; ; j = (j + 1) % nent) {
5074 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
5075 if (ej->function == e->function) {
5076 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
5077 return j;
5078 }
5079 }
5080 return 0; /* silence gcc, even though control never reaches here */
5081 }
5082
5083 /* find an entry with matching function, matching index (if needed), and that
5084 * should be read next (if it's stateful) */
5085 static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
5086 u32 function, u32 index)
5087 {
5088 if (e->function != function)
5089 return 0;
5090 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
5091 return 0;
5092 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
5093 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
5094 return 0;
5095 return 1;
5096 }
5097
5098 struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
5099 u32 function, u32 index)
5100 {
5101 int i;
5102 struct kvm_cpuid_entry2 *best = NULL;
5103
5104 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
5105 struct kvm_cpuid_entry2 *e;
5106
5107 e = &vcpu->arch.cpuid_entries[i];
5108 if (is_matching_cpuid_entry(e, function, index)) {
5109 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
5110 move_to_next_stateful_cpuid_entry(vcpu, i);
5111 best = e;
5112 break;
5113 }
5114 }
5115 return best;
5116 }
5117 EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
5118
5119 int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
5120 {
5121 struct kvm_cpuid_entry2 *best;
5122
5123 best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0);
5124 if (!best || best->eax < 0x80000008)
5125 goto not_found;
5126 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
5127 if (best)
5128 return best->eax & 0xff;
5129 not_found:
5130 return 36;
5131 }
5132
5133 /*
5134 * If no match is found, check whether we exceed the vCPU's limit
5135 * and return the content of the highest valid _standard_ leaf instead.
5136 * This is to satisfy the CPUID specification.
5137 */
5138 static struct kvm_cpuid_entry2* check_cpuid_limit(struct kvm_vcpu *vcpu,
5139 u32 function, u32 index)
5140 {
5141 struct kvm_cpuid_entry2 *maxlevel;
5142
5143 maxlevel = kvm_find_cpuid_entry(vcpu, function & 0x80000000, 0);
5144 if (!maxlevel || maxlevel->eax >= function)
5145 return NULL;
5146 if (function & 0x80000000) {
5147 maxlevel = kvm_find_cpuid_entry(vcpu, 0, 0);
5148 if (!maxlevel)
5149 return NULL;
5150 }
5151 return kvm_find_cpuid_entry(vcpu, maxlevel->eax, index);
5152 }
5153
5154 void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
5155 {
5156 u32 function, index;
5157 struct kvm_cpuid_entry2 *best;
5158
5159 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
5160 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5161 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
5162 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
5163 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
5164 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
5165 best = kvm_find_cpuid_entry(vcpu, function, index);
5166
5167 if (!best)
5168 best = check_cpuid_limit(vcpu, function, index);
5169
5170 if (best) {
5171 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
5172 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
5173 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
5174 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
5175 }
5176 kvm_x86_ops->skip_emulated_instruction(vcpu);
5177 trace_kvm_cpuid(function,
5178 kvm_register_read(vcpu, VCPU_REGS_RAX),
5179 kvm_register_read(vcpu, VCPU_REGS_RBX),
5180 kvm_register_read(vcpu, VCPU_REGS_RCX),
5181 kvm_register_read(vcpu, VCPU_REGS_RDX));
5182 }
5183 EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
5184
5185 /*
5186 * Check if userspace requested an interrupt window, and that the
5187 * interrupt window is open.
5188 *
5189 * No need to exit to userspace if we already have an interrupt queued.
5190 */
5191 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
5192 {
5193 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
5194 vcpu->run->request_interrupt_window &&
5195 kvm_arch_interrupt_allowed(vcpu));
5196 }
5197
5198 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
5199 {
5200 struct kvm_run *kvm_run = vcpu->run;
5201
5202 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
5203 kvm_run->cr8 = kvm_get_cr8(vcpu);
5204 kvm_run->apic_base = kvm_get_apic_base(vcpu);
5205 if (irqchip_in_kernel(vcpu->kvm))
5206 kvm_run->ready_for_interrupt_injection = 1;
5207 else
5208 kvm_run->ready_for_interrupt_injection =
5209 kvm_arch_interrupt_allowed(vcpu) &&
5210 !kvm_cpu_has_interrupt(vcpu) &&
5211 !kvm_event_needs_reinjection(vcpu);
5212 }
5213
5214 static void vapic_enter(struct kvm_vcpu *vcpu)
5215 {
5216 struct kvm_lapic *apic = vcpu->arch.apic;
5217 struct page *page;
5218
5219 if (!apic || !apic->vapic_addr)
5220 return;
5221
5222 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
5223
5224 vcpu->arch.apic->vapic_page = page;
5225 }
5226
5227 static void vapic_exit(struct kvm_vcpu *vcpu)
5228 {
5229 struct kvm_lapic *apic = vcpu->arch.apic;
5230 int idx;
5231
5232 if (!apic || !apic->vapic_addr)
5233 return;
5234
5235 idx = srcu_read_lock(&vcpu->kvm->srcu);
5236 kvm_release_page_dirty(apic->vapic_page);
5237 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
5238 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5239 }
5240
5241 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5242 {
5243 int max_irr, tpr;
5244
5245 if (!kvm_x86_ops->update_cr8_intercept)
5246 return;
5247
5248 if (!vcpu->arch.apic)
5249 return;
5250
5251 if (!vcpu->arch.apic->vapic_addr)
5252 max_irr = kvm_lapic_find_highest_irr(vcpu);
5253 else
5254 max_irr = -1;
5255
5256 if (max_irr != -1)
5257 max_irr >>= 4;
5258
5259 tpr = kvm_lapic_get_cr8(vcpu);
5260
5261 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5262 }
5263
5264 static void inject_pending_event(struct kvm_vcpu *vcpu)
5265 {
5266 /* try to reinject previous events if any */
5267 if (vcpu->arch.exception.pending) {
5268 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5269 vcpu->arch.exception.has_error_code,
5270 vcpu->arch.exception.error_code);
5271 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5272 vcpu->arch.exception.has_error_code,
5273 vcpu->arch.exception.error_code,
5274 vcpu->arch.exception.reinject);
5275 return;
5276 }
5277
5278 if (vcpu->arch.nmi_injected) {
5279 kvm_x86_ops->set_nmi(vcpu);
5280 return;
5281 }
5282
5283 if (vcpu->arch.interrupt.pending) {
5284 kvm_x86_ops->set_irq(vcpu);
5285 return;
5286 }
5287
5288 /* try to inject new event if pending */
5289 if (vcpu->arch.nmi_pending) {
5290 if (kvm_x86_ops->nmi_allowed(vcpu)) {
5291 vcpu->arch.nmi_pending = false;
5292 vcpu->arch.nmi_injected = true;
5293 kvm_x86_ops->set_nmi(vcpu);
5294 }
5295 } else if (kvm_cpu_has_interrupt(vcpu)) {
5296 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
5297 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5298 false);
5299 kvm_x86_ops->set_irq(vcpu);
5300 }
5301 }
5302 }
5303
5304 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
5305 {
5306 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
5307 !vcpu->guest_xcr0_loaded) {
5308 /* kvm_set_xcr() also depends on this */
5309 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
5310 vcpu->guest_xcr0_loaded = 1;
5311 }
5312 }
5313
5314 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
5315 {
5316 if (vcpu->guest_xcr0_loaded) {
5317 if (vcpu->arch.xcr0 != host_xcr0)
5318 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
5319 vcpu->guest_xcr0_loaded = 0;
5320 }
5321 }
5322
5323 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
5324 {
5325 int r;
5326 bool nmi_pending;
5327 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
5328 vcpu->run->request_interrupt_window;
5329
5330 if (vcpu->requests) {
5331 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
5332 kvm_mmu_unload(vcpu);
5333 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
5334 __kvm_migrate_timers(vcpu);
5335 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5336 r = kvm_guest_time_update(vcpu);
5337 if (unlikely(r))
5338 goto out;
5339 }
5340 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
5341 kvm_mmu_sync_roots(vcpu);
5342 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
5343 kvm_x86_ops->tlb_flush(vcpu);
5344 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
5345 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
5346 r = 0;
5347 goto out;
5348 }
5349 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
5350 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5351 r = 0;
5352 goto out;
5353 }
5354 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
5355 vcpu->fpu_active = 0;
5356 kvm_x86_ops->fpu_deactivate(vcpu);
5357 }
5358 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5359 /* Page is swapped out. Do synthetic halt */
5360 vcpu->arch.apf.halted = true;
5361 r = 1;
5362 goto out;
5363 }
5364 }
5365
5366 r = kvm_mmu_reload(vcpu);
5367 if (unlikely(r))
5368 goto out;
5369
5370 /*
5371 * An NMI can be injected between local nmi_pending read and
5372 * vcpu->arch.nmi_pending read inside inject_pending_event().
5373 * But in that case, KVM_REQ_EVENT will be set, which makes
5374 * the race described above benign.
5375 */
5376 nmi_pending = ACCESS_ONCE(vcpu->arch.nmi_pending);
5377
5378 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5379 inject_pending_event(vcpu);
5380
5381 /* enable NMI/IRQ window open exits if needed */
5382 if (nmi_pending)
5383 kvm_x86_ops->enable_nmi_window(vcpu);
5384 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
5385 kvm_x86_ops->enable_irq_window(vcpu);
5386
5387 if (kvm_lapic_enabled(vcpu)) {
5388 update_cr8_intercept(vcpu);
5389 kvm_lapic_sync_to_vapic(vcpu);
5390 }
5391 }
5392
5393 preempt_disable();
5394
5395 kvm_x86_ops->prepare_guest_switch(vcpu);
5396 if (vcpu->fpu_active)
5397 kvm_load_guest_fpu(vcpu);
5398 kvm_load_guest_xcr0(vcpu);
5399
5400 vcpu->mode = IN_GUEST_MODE;
5401
5402 /* We should set ->mode before check ->requests,
5403 * see the comment in make_all_cpus_request.
5404 */
5405 smp_mb();
5406
5407 local_irq_disable();
5408
5409 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
5410 || need_resched() || signal_pending(current)) {
5411 vcpu->mode = OUTSIDE_GUEST_MODE;
5412 smp_wmb();
5413 local_irq_enable();
5414 preempt_enable();
5415 kvm_x86_ops->cancel_injection(vcpu);
5416 r = 1;
5417 goto out;
5418 }
5419
5420 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5421
5422 kvm_guest_enter();
5423
5424 if (unlikely(vcpu->arch.switch_db_regs)) {
5425 set_debugreg(0, 7);
5426 set_debugreg(vcpu->arch.eff_db[0], 0);
5427 set_debugreg(vcpu->arch.eff_db[1], 1);
5428 set_debugreg(vcpu->arch.eff_db[2], 2);
5429 set_debugreg(vcpu->arch.eff_db[3], 3);
5430 }
5431
5432 trace_kvm_entry(vcpu->vcpu_id);
5433 kvm_x86_ops->run(vcpu);
5434
5435 /*
5436 * If the guest has used debug registers, at least dr7
5437 * will be disabled while returning to the host.
5438 * If we don't have active breakpoints in the host, we don't
5439 * care about the messed up debug address registers. But if
5440 * we have some of them active, restore the old state.
5441 */
5442 if (hw_breakpoint_active())
5443 hw_breakpoint_restore();
5444
5445 kvm_get_msr(vcpu, MSR_IA32_TSC, &vcpu->arch.last_guest_tsc);
5446
5447 vcpu->mode = OUTSIDE_GUEST_MODE;
5448 smp_wmb();
5449 local_irq_enable();
5450
5451 ++vcpu->stat.exits;
5452
5453 /*
5454 * We must have an instruction between local_irq_enable() and
5455 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5456 * the interrupt shadow. The stat.exits increment will do nicely.
5457 * But we need to prevent reordering, hence this barrier():
5458 */
5459 barrier();
5460
5461 kvm_guest_exit();
5462
5463 preempt_enable();
5464
5465 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5466
5467 /*
5468 * Profile KVM exit RIPs:
5469 */
5470 if (unlikely(prof_on == KVM_PROFILING)) {
5471 unsigned long rip = kvm_rip_read(vcpu);
5472 profile_hit(KVM_PROFILING, (void *)rip);
5473 }
5474
5475
5476 kvm_lapic_sync_from_vapic(vcpu);
5477
5478 r = kvm_x86_ops->handle_exit(vcpu);
5479 out:
5480 return r;
5481 }
5482
5483
5484 static int __vcpu_run(struct kvm_vcpu *vcpu)
5485 {
5486 int r;
5487 struct kvm *kvm = vcpu->kvm;
5488
5489 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
5490 pr_debug("vcpu %d received sipi with vector # %x\n",
5491 vcpu->vcpu_id, vcpu->arch.sipi_vector);
5492 kvm_lapic_reset(vcpu);
5493 r = kvm_arch_vcpu_reset(vcpu);
5494 if (r)
5495 return r;
5496 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5497 }
5498
5499 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5500 vapic_enter(vcpu);
5501
5502 r = 1;
5503 while (r > 0) {
5504 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
5505 !vcpu->arch.apf.halted)
5506 r = vcpu_enter_guest(vcpu);
5507 else {
5508 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5509 kvm_vcpu_block(vcpu);
5510 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5511 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
5512 {
5513 switch(vcpu->arch.mp_state) {
5514 case KVM_MP_STATE_HALTED:
5515 vcpu->arch.mp_state =
5516 KVM_MP_STATE_RUNNABLE;
5517 case KVM_MP_STATE_RUNNABLE:
5518 vcpu->arch.apf.halted = false;
5519 break;
5520 case KVM_MP_STATE_SIPI_RECEIVED:
5521 default:
5522 r = -EINTR;
5523 break;
5524 }
5525 }
5526 }
5527
5528 if (r <= 0)
5529 break;
5530
5531 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5532 if (kvm_cpu_has_pending_timer(vcpu))
5533 kvm_inject_pending_timer_irqs(vcpu);
5534
5535 if (dm_request_for_irq_injection(vcpu)) {
5536 r = -EINTR;
5537 vcpu->run->exit_reason = KVM_EXIT_INTR;
5538 ++vcpu->stat.request_irq_exits;
5539 }
5540
5541 kvm_check_async_pf_completion(vcpu);
5542
5543 if (signal_pending(current)) {
5544 r = -EINTR;
5545 vcpu->run->exit_reason = KVM_EXIT_INTR;
5546 ++vcpu->stat.signal_exits;
5547 }
5548 if (need_resched()) {
5549 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5550 kvm_resched(vcpu);
5551 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5552 }
5553 }
5554
5555 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5556
5557 vapic_exit(vcpu);
5558
5559 return r;
5560 }
5561
5562 static int complete_mmio(struct kvm_vcpu *vcpu)
5563 {
5564 struct kvm_run *run = vcpu->run;
5565 int r;
5566
5567 if (!(vcpu->arch.pio.count || vcpu->mmio_needed))
5568 return 1;
5569
5570 if (vcpu->mmio_needed) {
5571 vcpu->mmio_needed = 0;
5572 if (!vcpu->mmio_is_write)
5573 memcpy(vcpu->mmio_data, run->mmio.data, 8);
5574 vcpu->mmio_index += 8;
5575 if (vcpu->mmio_index < vcpu->mmio_size) {
5576 run->exit_reason = KVM_EXIT_MMIO;
5577 run->mmio.phys_addr = vcpu->mmio_phys_addr + vcpu->mmio_index;
5578 memcpy(run->mmio.data, vcpu->mmio_data + vcpu->mmio_index, 8);
5579 run->mmio.len = min(vcpu->mmio_size - vcpu->mmio_index, 8);
5580 run->mmio.is_write = vcpu->mmio_is_write;
5581 vcpu->mmio_needed = 1;
5582 return 0;
5583 }
5584 if (vcpu->mmio_is_write)
5585 return 1;
5586 vcpu->mmio_read_completed = 1;
5587 }
5588 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5589 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
5590 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5591 if (r != EMULATE_DONE)
5592 return 0;
5593 return 1;
5594 }
5595
5596 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
5597 {
5598 int r;
5599 sigset_t sigsaved;
5600
5601 if (!tsk_used_math(current) && init_fpu(current))
5602 return -ENOMEM;
5603
5604 if (vcpu->sigset_active)
5605 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
5606
5607 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
5608 kvm_vcpu_block(vcpu);
5609 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
5610 r = -EAGAIN;
5611 goto out;
5612 }
5613
5614 /* re-sync apic's tpr */
5615 if (!irqchip_in_kernel(vcpu->kvm)) {
5616 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
5617 r = -EINVAL;
5618 goto out;
5619 }
5620 }
5621
5622 r = complete_mmio(vcpu);
5623 if (r <= 0)
5624 goto out;
5625
5626 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
5627 kvm_register_write(vcpu, VCPU_REGS_RAX,
5628 kvm_run->hypercall.ret);
5629
5630 r = __vcpu_run(vcpu);
5631
5632 out:
5633 post_kvm_run_save(vcpu);
5634 if (vcpu->sigset_active)
5635 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
5636
5637 return r;
5638 }
5639
5640 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5641 {
5642 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
5643 /*
5644 * We are here if userspace calls get_regs() in the middle of
5645 * instruction emulation. Registers state needs to be copied
5646 * back from emulation context to vcpu. Usrapace shouldn't do
5647 * that usually, but some bad designed PV devices (vmware
5648 * backdoor interface) need this to work
5649 */
5650 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
5651 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
5652 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5653 }
5654 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
5655 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
5656 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
5657 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
5658 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
5659 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
5660 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
5661 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
5662 #ifdef CONFIG_X86_64
5663 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
5664 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
5665 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
5666 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
5667 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
5668 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
5669 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
5670 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
5671 #endif
5672
5673 regs->rip = kvm_rip_read(vcpu);
5674 regs->rflags = kvm_get_rflags(vcpu);
5675
5676 return 0;
5677 }
5678
5679 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5680 {
5681 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
5682 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5683
5684 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
5685 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
5686 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
5687 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
5688 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
5689 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
5690 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
5691 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
5692 #ifdef CONFIG_X86_64
5693 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
5694 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
5695 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
5696 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
5697 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
5698 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
5699 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
5700 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
5701 #endif
5702
5703 kvm_rip_write(vcpu, regs->rip);
5704 kvm_set_rflags(vcpu, regs->rflags);
5705
5706 vcpu->arch.exception.pending = false;
5707
5708 kvm_make_request(KVM_REQ_EVENT, vcpu);
5709
5710 return 0;
5711 }
5712
5713 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
5714 {
5715 struct kvm_segment cs;
5716
5717 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
5718 *db = cs.db;
5719 *l = cs.l;
5720 }
5721 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
5722
5723 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
5724 struct kvm_sregs *sregs)
5725 {
5726 struct desc_ptr dt;
5727
5728 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5729 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5730 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5731 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5732 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5733 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
5734
5735 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5736 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
5737
5738 kvm_x86_ops->get_idt(vcpu, &dt);
5739 sregs->idt.limit = dt.size;
5740 sregs->idt.base = dt.address;
5741 kvm_x86_ops->get_gdt(vcpu, &dt);
5742 sregs->gdt.limit = dt.size;
5743 sregs->gdt.base = dt.address;
5744
5745 sregs->cr0 = kvm_read_cr0(vcpu);
5746 sregs->cr2 = vcpu->arch.cr2;
5747 sregs->cr3 = kvm_read_cr3(vcpu);
5748 sregs->cr4 = kvm_read_cr4(vcpu);
5749 sregs->cr8 = kvm_get_cr8(vcpu);
5750 sregs->efer = vcpu->arch.efer;
5751 sregs->apic_base = kvm_get_apic_base(vcpu);
5752
5753 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
5754
5755 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
5756 set_bit(vcpu->arch.interrupt.nr,
5757 (unsigned long *)sregs->interrupt_bitmap);
5758
5759 return 0;
5760 }
5761
5762 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
5763 struct kvm_mp_state *mp_state)
5764 {
5765 mp_state->mp_state = vcpu->arch.mp_state;
5766 return 0;
5767 }
5768
5769 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
5770 struct kvm_mp_state *mp_state)
5771 {
5772 vcpu->arch.mp_state = mp_state->mp_state;
5773 kvm_make_request(KVM_REQ_EVENT, vcpu);
5774 return 0;
5775 }
5776
5777 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason,
5778 bool has_error_code, u32 error_code)
5779 {
5780 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
5781 int ret;
5782
5783 init_emulate_ctxt(vcpu);
5784
5785 ret = emulator_task_switch(&vcpu->arch.emulate_ctxt,
5786 tss_selector, reason, has_error_code,
5787 error_code);
5788
5789 if (ret)
5790 return EMULATE_FAIL;
5791
5792 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
5793 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
5794 kvm_set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
5795 kvm_make_request(KVM_REQ_EVENT, vcpu);
5796 return EMULATE_DONE;
5797 }
5798 EXPORT_SYMBOL_GPL(kvm_task_switch);
5799
5800 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5801 struct kvm_sregs *sregs)
5802 {
5803 int mmu_reset_needed = 0;
5804 int pending_vec, max_bits, idx;
5805 struct desc_ptr dt;
5806
5807 dt.size = sregs->idt.limit;
5808 dt.address = sregs->idt.base;
5809 kvm_x86_ops->set_idt(vcpu, &dt);
5810 dt.size = sregs->gdt.limit;
5811 dt.address = sregs->gdt.base;
5812 kvm_x86_ops->set_gdt(vcpu, &dt);
5813
5814 vcpu->arch.cr2 = sregs->cr2;
5815 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
5816 vcpu->arch.cr3 = sregs->cr3;
5817 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
5818
5819 kvm_set_cr8(vcpu, sregs->cr8);
5820
5821 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
5822 kvm_x86_ops->set_efer(vcpu, sregs->efer);
5823 kvm_set_apic_base(vcpu, sregs->apic_base);
5824
5825 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
5826 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
5827 vcpu->arch.cr0 = sregs->cr0;
5828
5829 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
5830 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
5831 if (sregs->cr4 & X86_CR4_OSXSAVE)
5832 update_cpuid(vcpu);
5833
5834 idx = srcu_read_lock(&vcpu->kvm->srcu);
5835 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
5836 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
5837 mmu_reset_needed = 1;
5838 }
5839 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5840
5841 if (mmu_reset_needed)
5842 kvm_mmu_reset_context(vcpu);
5843
5844 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
5845 pending_vec = find_first_bit(
5846 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5847 if (pending_vec < max_bits) {
5848 kvm_queue_interrupt(vcpu, pending_vec, false);
5849 pr_debug("Set back pending irq %d\n", pending_vec);
5850 }
5851
5852 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5853 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5854 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5855 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5856 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5857 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
5858
5859 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5860 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
5861
5862 update_cr8_intercept(vcpu);
5863
5864 /* Older userspace won't unhalt the vcpu on reset. */
5865 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
5866 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
5867 !is_protmode(vcpu))
5868 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5869
5870 kvm_make_request(KVM_REQ_EVENT, vcpu);
5871
5872 return 0;
5873 }
5874
5875 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5876 struct kvm_guest_debug *dbg)
5877 {
5878 unsigned long rflags;
5879 int i, r;
5880
5881 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5882 r = -EBUSY;
5883 if (vcpu->arch.exception.pending)
5884 goto out;
5885 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5886 kvm_queue_exception(vcpu, DB_VECTOR);
5887 else
5888 kvm_queue_exception(vcpu, BP_VECTOR);
5889 }
5890
5891 /*
5892 * Read rflags as long as potentially injected trace flags are still
5893 * filtered out.
5894 */
5895 rflags = kvm_get_rflags(vcpu);
5896
5897 vcpu->guest_debug = dbg->control;
5898 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5899 vcpu->guest_debug = 0;
5900
5901 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5902 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5903 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5904 vcpu->arch.switch_db_regs =
5905 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5906 } else {
5907 for (i = 0; i < KVM_NR_DB_REGS; i++)
5908 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5909 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5910 }
5911
5912 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5913 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
5914 get_segment_base(vcpu, VCPU_SREG_CS);
5915
5916 /*
5917 * Trigger an rflags update that will inject or remove the trace
5918 * flags.
5919 */
5920 kvm_set_rflags(vcpu, rflags);
5921
5922 kvm_x86_ops->set_guest_debug(vcpu, dbg);
5923
5924 r = 0;
5925
5926 out:
5927
5928 return r;
5929 }
5930
5931 /*
5932 * Translate a guest virtual address to a guest physical address.
5933 */
5934 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5935 struct kvm_translation *tr)
5936 {
5937 unsigned long vaddr = tr->linear_address;
5938 gpa_t gpa;
5939 int idx;
5940
5941 idx = srcu_read_lock(&vcpu->kvm->srcu);
5942 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
5943 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5944 tr->physical_address = gpa;
5945 tr->valid = gpa != UNMAPPED_GVA;
5946 tr->writeable = 1;
5947 tr->usermode = 0;
5948
5949 return 0;
5950 }
5951
5952 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5953 {
5954 struct i387_fxsave_struct *fxsave =
5955 &vcpu->arch.guest_fpu.state->fxsave;
5956
5957 memcpy(fpu->fpr, fxsave->st_space, 128);
5958 fpu->fcw = fxsave->cwd;
5959 fpu->fsw = fxsave->swd;
5960 fpu->ftwx = fxsave->twd;
5961 fpu->last_opcode = fxsave->fop;
5962 fpu->last_ip = fxsave->rip;
5963 fpu->last_dp = fxsave->rdp;
5964 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5965
5966 return 0;
5967 }
5968
5969 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5970 {
5971 struct i387_fxsave_struct *fxsave =
5972 &vcpu->arch.guest_fpu.state->fxsave;
5973
5974 memcpy(fxsave->st_space, fpu->fpr, 128);
5975 fxsave->cwd = fpu->fcw;
5976 fxsave->swd = fpu->fsw;
5977 fxsave->twd = fpu->ftwx;
5978 fxsave->fop = fpu->last_opcode;
5979 fxsave->rip = fpu->last_ip;
5980 fxsave->rdp = fpu->last_dp;
5981 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5982
5983 return 0;
5984 }
5985
5986 int fx_init(struct kvm_vcpu *vcpu)
5987 {
5988 int err;
5989
5990 err = fpu_alloc(&vcpu->arch.guest_fpu);
5991 if (err)
5992 return err;
5993
5994 fpu_finit(&vcpu->arch.guest_fpu);
5995
5996 /*
5997 * Ensure guest xcr0 is valid for loading
5998 */
5999 vcpu->arch.xcr0 = XSTATE_FP;
6000
6001 vcpu->arch.cr0 |= X86_CR0_ET;
6002
6003 return 0;
6004 }
6005 EXPORT_SYMBOL_GPL(fx_init);
6006
6007 static void fx_free(struct kvm_vcpu *vcpu)
6008 {
6009 fpu_free(&vcpu->arch.guest_fpu);
6010 }
6011
6012 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6013 {
6014 if (vcpu->guest_fpu_loaded)
6015 return;
6016
6017 /*
6018 * Restore all possible states in the guest,
6019 * and assume host would use all available bits.
6020 * Guest xcr0 would be loaded later.
6021 */
6022 kvm_put_guest_xcr0(vcpu);
6023 vcpu->guest_fpu_loaded = 1;
6024 unlazy_fpu(current);
6025 fpu_restore_checking(&vcpu->arch.guest_fpu);
6026 trace_kvm_fpu(1);
6027 }
6028
6029 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6030 {
6031 kvm_put_guest_xcr0(vcpu);
6032
6033 if (!vcpu->guest_fpu_loaded)
6034 return;
6035
6036 vcpu->guest_fpu_loaded = 0;
6037 fpu_save_init(&vcpu->arch.guest_fpu);
6038 ++vcpu->stat.fpu_reload;
6039 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
6040 trace_kvm_fpu(0);
6041 }
6042
6043 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6044 {
6045 kvmclock_reset(vcpu);
6046
6047 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
6048 fx_free(vcpu);
6049 kvm_x86_ops->vcpu_free(vcpu);
6050 }
6051
6052 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6053 unsigned int id)
6054 {
6055 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6056 printk_once(KERN_WARNING
6057 "kvm: SMP vm created on host with unstable TSC; "
6058 "guest TSC will not be reliable\n");
6059 return kvm_x86_ops->vcpu_create(kvm, id);
6060 }
6061
6062 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6063 {
6064 int r;
6065
6066 vcpu->arch.mtrr_state.have_fixed = 1;
6067 vcpu_load(vcpu);
6068 r = kvm_arch_vcpu_reset(vcpu);
6069 if (r == 0)
6070 r = kvm_mmu_setup(vcpu);
6071 vcpu_put(vcpu);
6072 if (r < 0)
6073 goto free_vcpu;
6074
6075 return 0;
6076 free_vcpu:
6077 kvm_x86_ops->vcpu_free(vcpu);
6078 return r;
6079 }
6080
6081 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
6082 {
6083 vcpu->arch.apf.msr_val = 0;
6084
6085 vcpu_load(vcpu);
6086 kvm_mmu_unload(vcpu);
6087 vcpu_put(vcpu);
6088
6089 fx_free(vcpu);
6090 kvm_x86_ops->vcpu_free(vcpu);
6091 }
6092
6093 int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
6094 {
6095 vcpu->arch.nmi_pending = false;
6096 vcpu->arch.nmi_injected = false;
6097
6098 vcpu->arch.switch_db_regs = 0;
6099 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6100 vcpu->arch.dr6 = DR6_FIXED_1;
6101 vcpu->arch.dr7 = DR7_FIXED_1;
6102
6103 kvm_make_request(KVM_REQ_EVENT, vcpu);
6104 vcpu->arch.apf.msr_val = 0;
6105
6106 kvmclock_reset(vcpu);
6107
6108 kvm_clear_async_pf_completion_queue(vcpu);
6109 kvm_async_pf_hash_reset(vcpu);
6110 vcpu->arch.apf.halted = false;
6111
6112 return kvm_x86_ops->vcpu_reset(vcpu);
6113 }
6114
6115 int kvm_arch_hardware_enable(void *garbage)
6116 {
6117 struct kvm *kvm;
6118 struct kvm_vcpu *vcpu;
6119 int i;
6120
6121 kvm_shared_msr_cpu_online();
6122 list_for_each_entry(kvm, &vm_list, vm_list)
6123 kvm_for_each_vcpu(i, vcpu, kvm)
6124 if (vcpu->cpu == smp_processor_id())
6125 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6126 return kvm_x86_ops->hardware_enable(garbage);
6127 }
6128
6129 void kvm_arch_hardware_disable(void *garbage)
6130 {
6131 kvm_x86_ops->hardware_disable(garbage);
6132 drop_user_return_notifiers(garbage);
6133 }
6134
6135 int kvm_arch_hardware_setup(void)
6136 {
6137 return kvm_x86_ops->hardware_setup();
6138 }
6139
6140 void kvm_arch_hardware_unsetup(void)
6141 {
6142 kvm_x86_ops->hardware_unsetup();
6143 }
6144
6145 void kvm_arch_check_processor_compat(void *rtn)
6146 {
6147 kvm_x86_ops->check_processor_compatibility(rtn);
6148 }
6149
6150 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6151 {
6152 struct page *page;
6153 struct kvm *kvm;
6154 int r;
6155
6156 BUG_ON(vcpu->kvm == NULL);
6157 kvm = vcpu->kvm;
6158
6159 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
6160 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
6161 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
6162 vcpu->arch.mmu.translate_gpa = translate_gpa;
6163 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
6164 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
6165 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6166 else
6167 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
6168
6169 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6170 if (!page) {
6171 r = -ENOMEM;
6172 goto fail;
6173 }
6174 vcpu->arch.pio_data = page_address(page);
6175
6176 kvm_init_tsc_catchup(vcpu, max_tsc_khz);
6177
6178 r = kvm_mmu_create(vcpu);
6179 if (r < 0)
6180 goto fail_free_pio_data;
6181
6182 if (irqchip_in_kernel(kvm)) {
6183 r = kvm_create_lapic(vcpu);
6184 if (r < 0)
6185 goto fail_mmu_destroy;
6186 }
6187
6188 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6189 GFP_KERNEL);
6190 if (!vcpu->arch.mce_banks) {
6191 r = -ENOMEM;
6192 goto fail_free_lapic;
6193 }
6194 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6195
6196 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
6197 goto fail_free_mce_banks;
6198
6199 kvm_async_pf_hash_reset(vcpu);
6200
6201 return 0;
6202 fail_free_mce_banks:
6203 kfree(vcpu->arch.mce_banks);
6204 fail_free_lapic:
6205 kvm_free_lapic(vcpu);
6206 fail_mmu_destroy:
6207 kvm_mmu_destroy(vcpu);
6208 fail_free_pio_data:
6209 free_page((unsigned long)vcpu->arch.pio_data);
6210 fail:
6211 return r;
6212 }
6213
6214 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6215 {
6216 int idx;
6217
6218 kfree(vcpu->arch.mce_banks);
6219 kvm_free_lapic(vcpu);
6220 idx = srcu_read_lock(&vcpu->kvm->srcu);
6221 kvm_mmu_destroy(vcpu);
6222 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6223 free_page((unsigned long)vcpu->arch.pio_data);
6224 }
6225
6226 int kvm_arch_init_vm(struct kvm *kvm)
6227 {
6228 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
6229 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
6230
6231 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
6232 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
6233
6234 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
6235
6236 return 0;
6237 }
6238
6239 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
6240 {
6241 vcpu_load(vcpu);
6242 kvm_mmu_unload(vcpu);
6243 vcpu_put(vcpu);
6244 }
6245
6246 static void kvm_free_vcpus(struct kvm *kvm)
6247 {
6248 unsigned int i;
6249 struct kvm_vcpu *vcpu;
6250
6251 /*
6252 * Unpin any mmu pages first.
6253 */
6254 kvm_for_each_vcpu(i, vcpu, kvm) {
6255 kvm_clear_async_pf_completion_queue(vcpu);
6256 kvm_unload_vcpu_mmu(vcpu);
6257 }
6258 kvm_for_each_vcpu(i, vcpu, kvm)
6259 kvm_arch_vcpu_free(vcpu);
6260
6261 mutex_lock(&kvm->lock);
6262 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
6263 kvm->vcpus[i] = NULL;
6264
6265 atomic_set(&kvm->online_vcpus, 0);
6266 mutex_unlock(&kvm->lock);
6267 }
6268
6269 void kvm_arch_sync_events(struct kvm *kvm)
6270 {
6271 kvm_free_all_assigned_devices(kvm);
6272 kvm_free_pit(kvm);
6273 }
6274
6275 void kvm_arch_destroy_vm(struct kvm *kvm)
6276 {
6277 kvm_iommu_unmap_guest(kvm);
6278 kfree(kvm->arch.vpic);
6279 kfree(kvm->arch.vioapic);
6280 kvm_free_vcpus(kvm);
6281 if (kvm->arch.apic_access_page)
6282 put_page(kvm->arch.apic_access_page);
6283 if (kvm->arch.ept_identity_pagetable)
6284 put_page(kvm->arch.ept_identity_pagetable);
6285 }
6286
6287 int kvm_arch_prepare_memory_region(struct kvm *kvm,
6288 struct kvm_memory_slot *memslot,
6289 struct kvm_memory_slot old,
6290 struct kvm_userspace_memory_region *mem,
6291 int user_alloc)
6292 {
6293 int npages = memslot->npages;
6294 int map_flags = MAP_PRIVATE | MAP_ANONYMOUS;
6295
6296 /* Prevent internal slot pages from being moved by fork()/COW. */
6297 if (memslot->id >= KVM_MEMORY_SLOTS)
6298 map_flags = MAP_SHARED | MAP_ANONYMOUS;
6299
6300 /*To keep backward compatibility with older userspace,
6301 *x86 needs to hanlde !user_alloc case.
6302 */
6303 if (!user_alloc) {
6304 if (npages && !old.rmap) {
6305 unsigned long userspace_addr;
6306
6307 down_write(&current->mm->mmap_sem);
6308 userspace_addr = do_mmap(NULL, 0,
6309 npages * PAGE_SIZE,
6310 PROT_READ | PROT_WRITE,
6311 map_flags,
6312 0);
6313 up_write(&current->mm->mmap_sem);
6314
6315 if (IS_ERR((void *)userspace_addr))
6316 return PTR_ERR((void *)userspace_addr);
6317
6318 memslot->userspace_addr = userspace_addr;
6319 }
6320 }
6321
6322
6323 return 0;
6324 }
6325
6326 void kvm_arch_commit_memory_region(struct kvm *kvm,
6327 struct kvm_userspace_memory_region *mem,
6328 struct kvm_memory_slot old,
6329 int user_alloc)
6330 {
6331
6332 int nr_mmu_pages = 0, npages = mem->memory_size >> PAGE_SHIFT;
6333
6334 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
6335 int ret;
6336
6337 down_write(&current->mm->mmap_sem);
6338 ret = do_munmap(current->mm, old.userspace_addr,
6339 old.npages * PAGE_SIZE);
6340 up_write(&current->mm->mmap_sem);
6341 if (ret < 0)
6342 printk(KERN_WARNING
6343 "kvm_vm_ioctl_set_memory_region: "
6344 "failed to munmap memory\n");
6345 }
6346
6347 if (!kvm->arch.n_requested_mmu_pages)
6348 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
6349
6350 spin_lock(&kvm->mmu_lock);
6351 if (nr_mmu_pages)
6352 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
6353 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
6354 spin_unlock(&kvm->mmu_lock);
6355 }
6356
6357 void kvm_arch_flush_shadow(struct kvm *kvm)
6358 {
6359 kvm_mmu_zap_all(kvm);
6360 kvm_reload_remote_mmus(kvm);
6361 }
6362
6363 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
6364 {
6365 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6366 !vcpu->arch.apf.halted)
6367 || !list_empty_careful(&vcpu->async_pf.done)
6368 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
6369 || vcpu->arch.nmi_pending ||
6370 (kvm_arch_interrupt_allowed(vcpu) &&
6371 kvm_cpu_has_interrupt(vcpu));
6372 }
6373
6374 void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
6375 {
6376 int me;
6377 int cpu = vcpu->cpu;
6378
6379 if (waitqueue_active(&vcpu->wq)) {
6380 wake_up_interruptible(&vcpu->wq);
6381 ++vcpu->stat.halt_wakeup;
6382 }
6383
6384 me = get_cpu();
6385 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
6386 if (kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE)
6387 smp_send_reschedule(cpu);
6388 put_cpu();
6389 }
6390
6391 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
6392 {
6393 return kvm_x86_ops->interrupt_allowed(vcpu);
6394 }
6395
6396 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
6397 {
6398 unsigned long current_rip = kvm_rip_read(vcpu) +
6399 get_segment_base(vcpu, VCPU_SREG_CS);
6400
6401 return current_rip == linear_rip;
6402 }
6403 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
6404
6405 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
6406 {
6407 unsigned long rflags;
6408
6409 rflags = kvm_x86_ops->get_rflags(vcpu);
6410 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6411 rflags &= ~X86_EFLAGS_TF;
6412 return rflags;
6413 }
6414 EXPORT_SYMBOL_GPL(kvm_get_rflags);
6415
6416 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
6417 {
6418 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
6419 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
6420 rflags |= X86_EFLAGS_TF;
6421 kvm_x86_ops->set_rflags(vcpu, rflags);
6422 kvm_make_request(KVM_REQ_EVENT, vcpu);
6423 }
6424 EXPORT_SYMBOL_GPL(kvm_set_rflags);
6425
6426 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
6427 {
6428 int r;
6429
6430 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
6431 is_error_page(work->page))
6432 return;
6433
6434 r = kvm_mmu_reload(vcpu);
6435 if (unlikely(r))
6436 return;
6437
6438 if (!vcpu->arch.mmu.direct_map &&
6439 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
6440 return;
6441
6442 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
6443 }
6444
6445 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
6446 {
6447 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
6448 }
6449
6450 static inline u32 kvm_async_pf_next_probe(u32 key)
6451 {
6452 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
6453 }
6454
6455 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6456 {
6457 u32 key = kvm_async_pf_hash_fn(gfn);
6458
6459 while (vcpu->arch.apf.gfns[key] != ~0)
6460 key = kvm_async_pf_next_probe(key);
6461
6462 vcpu->arch.apf.gfns[key] = gfn;
6463 }
6464
6465 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
6466 {
6467 int i;
6468 u32 key = kvm_async_pf_hash_fn(gfn);
6469
6470 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
6471 (vcpu->arch.apf.gfns[key] != gfn &&
6472 vcpu->arch.apf.gfns[key] != ~0); i++)
6473 key = kvm_async_pf_next_probe(key);
6474
6475 return key;
6476 }
6477
6478 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6479 {
6480 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
6481 }
6482
6483 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6484 {
6485 u32 i, j, k;
6486
6487 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
6488 while (true) {
6489 vcpu->arch.apf.gfns[i] = ~0;
6490 do {
6491 j = kvm_async_pf_next_probe(j);
6492 if (vcpu->arch.apf.gfns[j] == ~0)
6493 return;
6494 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
6495 /*
6496 * k lies cyclically in ]i,j]
6497 * | i.k.j |
6498 * |....j i.k.| or |.k..j i...|
6499 */
6500 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
6501 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
6502 i = j;
6503 }
6504 }
6505
6506 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
6507 {
6508
6509 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
6510 sizeof(val));
6511 }
6512
6513 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
6514 struct kvm_async_pf *work)
6515 {
6516 struct x86_exception fault;
6517
6518 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
6519 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
6520
6521 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
6522 (vcpu->arch.apf.send_user_only &&
6523 kvm_x86_ops->get_cpl(vcpu) == 0))
6524 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
6525 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6526 fault.vector = PF_VECTOR;
6527 fault.error_code_valid = true;
6528 fault.error_code = 0;
6529 fault.nested_page_fault = false;
6530 fault.address = work->arch.token;
6531 kvm_inject_page_fault(vcpu, &fault);
6532 }
6533 }
6534
6535 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
6536 struct kvm_async_pf *work)
6537 {
6538 struct x86_exception fault;
6539
6540 trace_kvm_async_pf_ready(work->arch.token, work->gva);
6541 if (is_error_page(work->page))
6542 work->arch.token = ~0; /* broadcast wakeup */
6543 else
6544 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
6545
6546 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
6547 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6548 fault.vector = PF_VECTOR;
6549 fault.error_code_valid = true;
6550 fault.error_code = 0;
6551 fault.nested_page_fault = false;
6552 fault.address = work->arch.token;
6553 kvm_inject_page_fault(vcpu, &fault);
6554 }
6555 vcpu->arch.apf.halted = false;
6556 }
6557
6558 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
6559 {
6560 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
6561 return true;
6562 else
6563 return !kvm_event_needs_reinjection(vcpu) &&
6564 kvm_x86_ops->interrupt_allowed(vcpu);
6565 }
6566
6567 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
6568 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
6569 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
6570 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
6571 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
6572 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
6573 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
6574 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
6575 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
6576 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
6577 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
6578 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree