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KVM: x86 emulator: drop vcpu argument from intercept callback
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / arch / x86 / kvm / emulate.c
blobacb9fcc283eea0459f73e410668f349a9256a463
1 /******************************************************************************
2 * emulate.c
3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
9 * privileged instructions:
10 *
11 * Copyright (C) 2006 Qumranet
12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
23 #include <linux/kvm_host.h>
24 #include "kvm_cache_regs.h"
25 #include <linux/module.h>
26 #include <asm/kvm_emulate.h>
27
28 #include "x86.h"
29 #include "tss.h"
30
31 /*
32 * Opcode effective-address decode tables.
33 * Note that we only emulate instructions that have at least one memory
34 * operand (excluding implicit stack references). We assume that stack
35 * references and instruction fetches will never occur in special memory
36 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
37 * not be handled.
38 */
39
40 /* Operand sizes: 8-bit operands or specified/overridden size. */
41 #define ByteOp (1<<0) /* 8-bit operands. */
42 /* Destination operand type. */
43 #define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
44 #define DstReg (2<<1) /* Register operand. */
45 #define DstMem (3<<1) /* Memory operand. */
46 #define DstAcc (4<<1) /* Destination Accumulator */
47 #define DstDI (5<<1) /* Destination is in ES:(E)DI */
48 #define DstMem64 (6<<1) /* 64bit memory operand */
49 #define DstImmUByte (7<<1) /* 8-bit unsigned immediate operand */
50 #define DstMask (7<<1)
51 /* Source operand type. */
52 #define SrcNone (0<<4) /* No source operand. */
53 #define SrcReg (1<<4) /* Register operand. */
54 #define SrcMem (2<<4) /* Memory operand. */
55 #define SrcMem16 (3<<4) /* Memory operand (16-bit). */
56 #define SrcMem32 (4<<4) /* Memory operand (32-bit). */
57 #define SrcImm (5<<4) /* Immediate operand. */
58 #define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */
59 #define SrcOne (7<<4) /* Implied '1' */
60 #define SrcImmUByte (8<<4) /* 8-bit unsigned immediate operand. */
61 #define SrcImmU (9<<4) /* Immediate operand, unsigned */
62 #define SrcSI (0xa<<4) /* Source is in the DS:RSI */
63 #define SrcImmFAddr (0xb<<4) /* Source is immediate far address */
64 #define SrcMemFAddr (0xc<<4) /* Source is far address in memory */
65 #define SrcAcc (0xd<<4) /* Source Accumulator */
66 #define SrcImmU16 (0xe<<4) /* Immediate operand, unsigned, 16 bits */
67 #define SrcMask (0xf<<4)
68 /* Generic ModRM decode. */
69 #define ModRM (1<<8)
70 /* Destination is only written; never read. */
71 #define Mov (1<<9)
72 #define BitOp (1<<10)
73 #define MemAbs (1<<11) /* Memory operand is absolute displacement */
74 #define String (1<<12) /* String instruction (rep capable) */
75 #define Stack (1<<13) /* Stack instruction (push/pop) */
76 #define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
77 #define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
78 #define Prefix (1<<16) /* Instruction varies with 66/f2/f3 prefix */
79 #define Sse (1<<17) /* SSE Vector instruction */
80 #define RMExt (1<<18) /* Opcode extension in ModRM r/m if mod == 3 */
81 /* Misc flags */
82 #define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
83 #define VendorSpecific (1<<22) /* Vendor specific instruction */
84 #define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
85 #define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
86 #define Undefined (1<<25) /* No Such Instruction */
87 #define Lock (1<<26) /* lock prefix is allowed for the instruction */
88 #define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
89 #define No64 (1<<28)
90 /* Source 2 operand type */
91 #define Src2None (0<<29)
92 #define Src2CL (1<<29)
93 #define Src2ImmByte (2<<29)
94 #define Src2One (3<<29)
95 #define Src2Imm (4<<29)
96 #define Src2Mask (7<<29)
97
98 #define X2(x...) x, x
99 #define X3(x...) X2(x), x
100 #define X4(x...) X2(x), X2(x)
101 #define X5(x...) X4(x), x
102 #define X6(x...) X4(x), X2(x)
103 #define X7(x...) X4(x), X3(x)
104 #define X8(x...) X4(x), X4(x)
105 #define X16(x...) X8(x), X8(x)
106
107 struct opcode {
108 u32 flags;
109 u8 intercept;
110 union {
111 int (*execute)(struct x86_emulate_ctxt *ctxt);
112 struct opcode *group;
113 struct group_dual *gdual;
114 struct gprefix *gprefix;
115 } u;
116 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
117 };
118
119 struct group_dual {
120 struct opcode mod012[8];
121 struct opcode mod3[8];
122 };
123
124 struct gprefix {
125 struct opcode pfx_no;
126 struct opcode pfx_66;
127 struct opcode pfx_f2;
128 struct opcode pfx_f3;
129 };
130
131 /* EFLAGS bit definitions. */
132 #define EFLG_ID (1<<21)
133 #define EFLG_VIP (1<<20)
134 #define EFLG_VIF (1<<19)
135 #define EFLG_AC (1<<18)
136 #define EFLG_VM (1<<17)
137 #define EFLG_RF (1<<16)
138 #define EFLG_IOPL (3<<12)
139 #define EFLG_NT (1<<14)
140 #define EFLG_OF (1<<11)
141 #define EFLG_DF (1<<10)
142 #define EFLG_IF (1<<9)
143 #define EFLG_TF (1<<8)
144 #define EFLG_SF (1<<7)
145 #define EFLG_ZF (1<<6)
146 #define EFLG_AF (1<<4)
147 #define EFLG_PF (1<<2)
148 #define EFLG_CF (1<<0)
149
150 #define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
151 #define EFLG_RESERVED_ONE_MASK 2
152
153 /*
154 * Instruction emulation:
155 * Most instructions are emulated directly via a fragment of inline assembly
156 * code. This allows us to save/restore EFLAGS and thus very easily pick up
157 * any modified flags.
158 */
159
160 #if defined(CONFIG_X86_64)
161 #define _LO32 "k" /* force 32-bit operand */
162 #define _STK "%%rsp" /* stack pointer */
163 #elif defined(__i386__)
164 #define _LO32 "" /* force 32-bit operand */
165 #define _STK "%%esp" /* stack pointer */
166 #endif
167
168 /*
169 * These EFLAGS bits are restored from saved value during emulation, and
170 * any changes are written back to the saved value after emulation.
171 */
172 #define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
173
174 /* Before executing instruction: restore necessary bits in EFLAGS. */
175 #define _PRE_EFLAGS(_sav, _msk, _tmp) \
176 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
177 "movl %"_sav",%"_LO32 _tmp"; " \
178 "push %"_tmp"; " \
179 "push %"_tmp"; " \
180 "movl %"_msk",%"_LO32 _tmp"; " \
181 "andl %"_LO32 _tmp",("_STK"); " \
182 "pushf; " \
183 "notl %"_LO32 _tmp"; " \
184 "andl %"_LO32 _tmp",("_STK"); " \
185 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
186 "pop %"_tmp"; " \
187 "orl %"_LO32 _tmp",("_STK"); " \
188 "popf; " \
189 "pop %"_sav"; "
190
191 /* After executing instruction: write-back necessary bits in EFLAGS. */
192 #define _POST_EFLAGS(_sav, _msk, _tmp) \
193 /* _sav |= EFLAGS & _msk; */ \
194 "pushf; " \
195 "pop %"_tmp"; " \
196 "andl %"_msk",%"_LO32 _tmp"; " \
197 "orl %"_LO32 _tmp",%"_sav"; "
198
199 #ifdef CONFIG_X86_64
200 #define ON64(x) x
201 #else
202 #define ON64(x)
203 #endif
204
205 #define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix, _dsttype) \
206 do { \
207 __asm__ __volatile__ ( \
208 _PRE_EFLAGS("0", "4", "2") \
209 _op _suffix " %"_x"3,%1; " \
210 _POST_EFLAGS("0", "4", "2") \
211 : "=m" (_eflags), "+q" (*(_dsttype*)&(_dst).val),\
212 "=&r" (_tmp) \
213 : _y ((_src).val), "i" (EFLAGS_MASK)); \
214 } while (0)
215
216
217 /* Raw emulation: instruction has two explicit operands. */
218 #define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
219 do { \
220 unsigned long _tmp; \
221 \
222 switch ((_dst).bytes) { \
223 case 2: \
224 ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w",u16);\
225 break; \
226 case 4: \
227 ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l",u32);\
228 break; \
229 case 8: \
230 ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q",u64)); \
231 break; \
232 } \
233 } while (0)
234
235 #define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
236 do { \
237 unsigned long _tmp; \
238 switch ((_dst).bytes) { \
239 case 1: \
240 ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b",u8); \
241 break; \
242 default: \
243 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
244 _wx, _wy, _lx, _ly, _qx, _qy); \
245 break; \
246 } \
247 } while (0)
248
249 /* Source operand is byte-sized and may be restricted to just %cl. */
250 #define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
251 __emulate_2op(_op, _src, _dst, _eflags, \
252 "b", "c", "b", "c", "b", "c", "b", "c")
253
254 /* Source operand is byte, word, long or quad sized. */
255 #define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
256 __emulate_2op(_op, _src, _dst, _eflags, \
257 "b", "q", "w", "r", _LO32, "r", "", "r")
258
259 /* Source operand is word, long or quad sized. */
260 #define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
261 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
262 "w", "r", _LO32, "r", "", "r")
263
264 /* Instruction has three operands and one operand is stored in ECX register */
265 #define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \
266 do { \
267 unsigned long _tmp; \
268 _type _clv = (_cl).val; \
269 _type _srcv = (_src).val; \
270 _type _dstv = (_dst).val; \
271 \
272 __asm__ __volatile__ ( \
273 _PRE_EFLAGS("0", "5", "2") \
274 _op _suffix " %4,%1 \n" \
275 _POST_EFLAGS("0", "5", "2") \
276 : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \
277 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
278 ); \
279 \
280 (_cl).val = (unsigned long) _clv; \
281 (_src).val = (unsigned long) _srcv; \
282 (_dst).val = (unsigned long) _dstv; \
283 } while (0)
284
285 #define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \
286 do { \
287 switch ((_dst).bytes) { \
288 case 2: \
289 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
290 "w", unsigned short); \
291 break; \
292 case 4: \
293 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
294 "l", unsigned int); \
295 break; \
296 case 8: \
297 ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
298 "q", unsigned long)); \
299 break; \
300 } \
301 } while (0)
302
303 #define __emulate_1op(_op, _dst, _eflags, _suffix) \
304 do { \
305 unsigned long _tmp; \
306 \
307 __asm__ __volatile__ ( \
308 _PRE_EFLAGS("0", "3", "2") \
309 _op _suffix " %1; " \
310 _POST_EFLAGS("0", "3", "2") \
311 : "=m" (_eflags), "+m" ((_dst).val), \
312 "=&r" (_tmp) \
313 : "i" (EFLAGS_MASK)); \
314 } while (0)
315
316 /* Instruction has only one explicit operand (no source operand). */
317 #define emulate_1op(_op, _dst, _eflags) \
318 do { \
319 switch ((_dst).bytes) { \
320 case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \
321 case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \
322 case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \
323 case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \
324 } \
325 } while (0)
326
327 #define __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, _suffix) \
328 do { \
329 unsigned long _tmp; \
330 \
331 __asm__ __volatile__ ( \
332 _PRE_EFLAGS("0", "4", "1") \
333 _op _suffix " %5; " \
334 _POST_EFLAGS("0", "4", "1") \
335 : "=m" (_eflags), "=&r" (_tmp), \
336 "+a" (_rax), "+d" (_rdx) \
337 : "i" (EFLAGS_MASK), "m" ((_src).val), \
338 "a" (_rax), "d" (_rdx)); \
339 } while (0)
340
341 #define __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, _eflags, _suffix, _ex) \
342 do { \
343 unsigned long _tmp; \
344 \
345 __asm__ __volatile__ ( \
346 _PRE_EFLAGS("0", "5", "1") \
347 "1: \n\t" \
348 _op _suffix " %6; " \
349 "2: \n\t" \
350 _POST_EFLAGS("0", "5", "1") \
351 ".pushsection .fixup,\"ax\" \n\t" \
352 "3: movb $1, %4 \n\t" \
353 "jmp 2b \n\t" \
354 ".popsection \n\t" \
355 _ASM_EXTABLE(1b, 3b) \
356 : "=m" (_eflags), "=&r" (_tmp), \
357 "+a" (_rax), "+d" (_rdx), "+qm"(_ex) \
358 : "i" (EFLAGS_MASK), "m" ((_src).val), \
359 "a" (_rax), "d" (_rdx)); \
360 } while (0)
361
362 /* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */
363 #define emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags) \
364 do { \
365 switch((_src).bytes) { \
366 case 1: \
367 __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, \
368 _eflags, "b"); \
369 break; \
370 case 2: \
371 __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, \
372 _eflags, "w"); \
373 break; \
374 case 4: \
375 __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, \
376 _eflags, "l"); \
377 break; \
378 case 8: \
379 ON64(__emulate_1op_rax_rdx(_op, _src, _rax, _rdx, \
380 _eflags, "q")); \
381 break; \
382 } \
383 } while (0)
384
385 #define emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, _eflags, _ex) \
386 do { \
387 switch((_src).bytes) { \
388 case 1: \
389 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
390 _eflags, "b", _ex); \
391 break; \
392 case 2: \
393 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
394 _eflags, "w", _ex); \
395 break; \
396 case 4: \
397 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
398 _eflags, "l", _ex); \
399 break; \
400 case 8: ON64( \
401 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
402 _eflags, "q", _ex)); \
403 break; \
404 } \
405 } while (0)
406
407 /* Fetch next part of the instruction being emulated. */
408 #define insn_fetch(_type, _size, _eip) \
409 ({ unsigned long _x; \
410 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
411 if (rc != X86EMUL_CONTINUE) \
412 goto done; \
413 (_eip) += (_size); \
414 (_type)_x; \
415 })
416
417 #define insn_fetch_arr(_arr, _size, _eip) \
418 ({ rc = do_insn_fetch(ctxt, ops, (_eip), _arr, (_size)); \
419 if (rc != X86EMUL_CONTINUE) \
420 goto done; \
421 (_eip) += (_size); \
422 })
423
424 static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
425 enum x86_intercept intercept,
426 enum x86_intercept_stage stage)
427 {
428 struct x86_instruction_info info = {
429 .intercept = intercept,
430 .rep_prefix = ctxt->decode.rep_prefix,
431 .modrm_mod = ctxt->decode.modrm_mod,
432 .modrm_reg = ctxt->decode.modrm_reg,
433 .modrm_rm = ctxt->decode.modrm_rm,
434 .src_val = ctxt->decode.src.val64,
435 .src_bytes = ctxt->decode.src.bytes,
436 .dst_bytes = ctxt->decode.dst.bytes,
437 .ad_bytes = ctxt->decode.ad_bytes,
438 .next_rip = ctxt->eip,
439 };
440
441 return ctxt->ops->intercept(ctxt, &info, stage);
442 }
443
444 static inline unsigned long ad_mask(struct decode_cache *c)
445 {
446 return (1UL << (c->ad_bytes << 3)) - 1;
447 }
448
449 /* Access/update address held in a register, based on addressing mode. */
450 static inline unsigned long
451 address_mask(struct decode_cache *c, unsigned long reg)
452 {
453 if (c->ad_bytes == sizeof(unsigned long))
454 return reg;
455 else
456 return reg & ad_mask(c);
457 }
458
459 static inline unsigned long
460 register_address(struct decode_cache *c, unsigned long reg)
461 {
462 return address_mask(c, reg);
463 }
464
465 static inline void
466 register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
467 {
468 if (c->ad_bytes == sizeof(unsigned long))
469 *reg += inc;
470 else
471 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
472 }
473
474 static inline void jmp_rel(struct decode_cache *c, int rel)
475 {
476 register_address_increment(c, &c->eip, rel);
477 }
478
479 static u32 desc_limit_scaled(struct desc_struct *desc)
480 {
481 u32 limit = get_desc_limit(desc);
482
483 return desc->g ? (limit << 12) | 0xfff : limit;
484 }
485
486 static void set_seg_override(struct decode_cache *c, int seg)
487 {
488 c->has_seg_override = true;
489 c->seg_override = seg;
490 }
491
492 static unsigned long seg_base(struct x86_emulate_ctxt *ctxt,
493 struct x86_emulate_ops *ops, int seg)
494 {
495 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
496 return 0;
497
498 return ops->get_cached_segment_base(ctxt, seg);
499 }
500
501 static unsigned seg_override(struct x86_emulate_ctxt *ctxt,
502 struct x86_emulate_ops *ops,
503 struct decode_cache *c)
504 {
505 if (!c->has_seg_override)
506 return 0;
507
508 return c->seg_override;
509 }
510
511 static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
512 u32 error, bool valid)
513 {
514 ctxt->exception.vector = vec;
515 ctxt->exception.error_code = error;
516 ctxt->exception.error_code_valid = valid;
517 return X86EMUL_PROPAGATE_FAULT;
518 }
519
520 static int emulate_db(struct x86_emulate_ctxt *ctxt)
521 {
522 return emulate_exception(ctxt, DB_VECTOR, 0, false);
523 }
524
525 static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
526 {
527 return emulate_exception(ctxt, GP_VECTOR, err, true);
528 }
529
530 static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
531 {
532 return emulate_exception(ctxt, SS_VECTOR, err, true);
533 }
534
535 static int emulate_ud(struct x86_emulate_ctxt *ctxt)
536 {
537 return emulate_exception(ctxt, UD_VECTOR, 0, false);
538 }
539
540 static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
541 {
542 return emulate_exception(ctxt, TS_VECTOR, err, true);
543 }
544
545 static int emulate_de(struct x86_emulate_ctxt *ctxt)
546 {
547 return emulate_exception(ctxt, DE_VECTOR, 0, false);
548 }
549
550 static int emulate_nm(struct x86_emulate_ctxt *ctxt)
551 {
552 return emulate_exception(ctxt, NM_VECTOR, 0, false);
553 }
554
555 static int __linearize(struct x86_emulate_ctxt *ctxt,
556 struct segmented_address addr,
557 unsigned size, bool write, bool fetch,
558 ulong *linear)
559 {
560 struct decode_cache *c = &ctxt->decode;
561 struct desc_struct desc;
562 bool usable;
563 ulong la;
564 u32 lim;
565 unsigned cpl, rpl;
566
567 la = seg_base(ctxt, ctxt->ops, addr.seg) + addr.ea;
568 switch (ctxt->mode) {
569 case X86EMUL_MODE_REAL:
570 break;
571 case X86EMUL_MODE_PROT64:
572 if (((signed long)la << 16) >> 16 != la)
573 return emulate_gp(ctxt, 0);
574 break;
575 default:
576 usable = ctxt->ops->get_cached_descriptor(ctxt, &desc, NULL,
577 addr.seg);
578 if (!usable)
579 goto bad;
580 /* code segment or read-only data segment */
581 if (((desc.type & 8) || !(desc.type & 2)) && write)
582 goto bad;
583 /* unreadable code segment */
584 if (!fetch && (desc.type & 8) && !(desc.type & 2))
585 goto bad;
586 lim = desc_limit_scaled(&desc);
587 if ((desc.type & 8) || !(desc.type & 4)) {
588 /* expand-up segment */
589 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
590 goto bad;
591 } else {
592 /* exapand-down segment */
593 if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim)
594 goto bad;
595 lim = desc.d ? 0xffffffff : 0xffff;
596 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
597 goto bad;
598 }
599 cpl = ctxt->ops->cpl(ctxt);
600 rpl = ctxt->ops->get_segment_selector(ctxt, addr.seg) & 3;
601 cpl = max(cpl, rpl);
602 if (!(desc.type & 8)) {
603 /* data segment */
604 if (cpl > desc.dpl)
605 goto bad;
606 } else if ((desc.type & 8) && !(desc.type & 4)) {
607 /* nonconforming code segment */
608 if (cpl != desc.dpl)
609 goto bad;
610 } else if ((desc.type & 8) && (desc.type & 4)) {
611 /* conforming code segment */
612 if (cpl < desc.dpl)
613 goto bad;
614 }
615 break;
616 }
617 if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : c->ad_bytes != 8)
618 la &= (u32)-1;
619 *linear = la;
620 return X86EMUL_CONTINUE;
621 bad:
622 if (addr.seg == VCPU_SREG_SS)
623 return emulate_ss(ctxt, addr.seg);
624 else
625 return emulate_gp(ctxt, addr.seg);
626 }
627
628 static int linearize(struct x86_emulate_ctxt *ctxt,
629 struct segmented_address addr,
630 unsigned size, bool write,
631 ulong *linear)
632 {
633 return __linearize(ctxt, addr, size, write, false, linear);
634 }
635
636
637 static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
638 struct segmented_address addr,
639 void *data,
640 unsigned size)
641 {
642 int rc;
643 ulong linear;
644
645 rc = linearize(ctxt, addr, size, false, &linear);
646 if (rc != X86EMUL_CONTINUE)
647 return rc;
648 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
649 }
650
651 static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
652 struct x86_emulate_ops *ops,
653 unsigned long eip, u8 *dest)
654 {
655 struct fetch_cache *fc = &ctxt->decode.fetch;
656 int rc;
657 int size, cur_size;
658
659 if (eip == fc->end) {
660 unsigned long linear;
661 struct segmented_address addr = { .seg=VCPU_SREG_CS, .ea=eip};
662 cur_size = fc->end - fc->start;
663 size = min(15UL - cur_size, PAGE_SIZE - offset_in_page(eip));
664 rc = __linearize(ctxt, addr, size, false, true, &linear);
665 if (rc != X86EMUL_CONTINUE)
666 return rc;
667 rc = ops->fetch(ctxt, linear, fc->data + cur_size,
668 size, &ctxt->exception);
669 if (rc != X86EMUL_CONTINUE)
670 return rc;
671 fc->end += size;
672 }
673 *dest = fc->data[eip - fc->start];
674 return X86EMUL_CONTINUE;
675 }
676
677 static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
678 struct x86_emulate_ops *ops,
679 unsigned long eip, void *dest, unsigned size)
680 {
681 int rc;
682
683 /* x86 instructions are limited to 15 bytes. */
684 if (eip + size - ctxt->eip > 15)
685 return X86EMUL_UNHANDLEABLE;
686 while (size--) {
687 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
688 if (rc != X86EMUL_CONTINUE)
689 return rc;
690 }
691 return X86EMUL_CONTINUE;
692 }
693
694 /*
695 * Given the 'reg' portion of a ModRM byte, and a register block, return a
696 * pointer into the block that addresses the relevant register.
697 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
698 */
699 static void *decode_register(u8 modrm_reg, unsigned long *regs,
700 int highbyte_regs)
701 {
702 void *p;
703
704 p = &regs[modrm_reg];
705 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
706 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
707 return p;
708 }
709
710 static int read_descriptor(struct x86_emulate_ctxt *ctxt,
711 struct x86_emulate_ops *ops,
712 struct segmented_address addr,
713 u16 *size, unsigned long *address, int op_bytes)
714 {
715 int rc;
716
717 if (op_bytes == 2)
718 op_bytes = 3;
719 *address = 0;
720 rc = segmented_read_std(ctxt, addr, size, 2);
721 if (rc != X86EMUL_CONTINUE)
722 return rc;
723 addr.ea += 2;
724 rc = segmented_read_std(ctxt, addr, address, op_bytes);
725 return rc;
726 }
727
728 static int test_cc(unsigned int condition, unsigned int flags)
729 {
730 int rc = 0;
731
732 switch ((condition & 15) >> 1) {
733 case 0: /* o */
734 rc |= (flags & EFLG_OF);
735 break;
736 case 1: /* b/c/nae */
737 rc |= (flags & EFLG_CF);
738 break;
739 case 2: /* z/e */
740 rc |= (flags & EFLG_ZF);
741 break;
742 case 3: /* be/na */
743 rc |= (flags & (EFLG_CF|EFLG_ZF));
744 break;
745 case 4: /* s */
746 rc |= (flags & EFLG_SF);
747 break;
748 case 5: /* p/pe */
749 rc |= (flags & EFLG_PF);
750 break;
751 case 7: /* le/ng */
752 rc |= (flags & EFLG_ZF);
753 /* fall through */
754 case 6: /* l/nge */
755 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
756 break;
757 }
758
759 /* Odd condition identifiers (lsb == 1) have inverted sense. */
760 return (!!rc ^ (condition & 1));
761 }
762
763 static void fetch_register_operand(struct operand *op)
764 {
765 switch (op->bytes) {
766 case 1:
767 op->val = *(u8 *)op->addr.reg;
768 break;
769 case 2:
770 op->val = *(u16 *)op->addr.reg;
771 break;
772 case 4:
773 op->val = *(u32 *)op->addr.reg;
774 break;
775 case 8:
776 op->val = *(u64 *)op->addr.reg;
777 break;
778 }
779 }
780
781 static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
782 {
783 ctxt->ops->get_fpu(ctxt);
784 switch (reg) {
785 case 0: asm("movdqu %%xmm0, %0" : "=m"(*data)); break;
786 case 1: asm("movdqu %%xmm1, %0" : "=m"(*data)); break;
787 case 2: asm("movdqu %%xmm2, %0" : "=m"(*data)); break;
788 case 3: asm("movdqu %%xmm3, %0" : "=m"(*data)); break;
789 case 4: asm("movdqu %%xmm4, %0" : "=m"(*data)); break;
790 case 5: asm("movdqu %%xmm5, %0" : "=m"(*data)); break;
791 case 6: asm("movdqu %%xmm6, %0" : "=m"(*data)); break;
792 case 7: asm("movdqu %%xmm7, %0" : "=m"(*data)); break;
793 #ifdef CONFIG_X86_64
794 case 8: asm("movdqu %%xmm8, %0" : "=m"(*data)); break;
795 case 9: asm("movdqu %%xmm9, %0" : "=m"(*data)); break;
796 case 10: asm("movdqu %%xmm10, %0" : "=m"(*data)); break;
797 case 11: asm("movdqu %%xmm11, %0" : "=m"(*data)); break;
798 case 12: asm("movdqu %%xmm12, %0" : "=m"(*data)); break;
799 case 13: asm("movdqu %%xmm13, %0" : "=m"(*data)); break;
800 case 14: asm("movdqu %%xmm14, %0" : "=m"(*data)); break;
801 case 15: asm("movdqu %%xmm15, %0" : "=m"(*data)); break;
802 #endif
803 default: BUG();
804 }
805 ctxt->ops->put_fpu(ctxt);
806 }
807
808 static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
809 int reg)
810 {
811 ctxt->ops->get_fpu(ctxt);
812 switch (reg) {
813 case 0: asm("movdqu %0, %%xmm0" : : "m"(*data)); break;
814 case 1: asm("movdqu %0, %%xmm1" : : "m"(*data)); break;
815 case 2: asm("movdqu %0, %%xmm2" : : "m"(*data)); break;
816 case 3: asm("movdqu %0, %%xmm3" : : "m"(*data)); break;
817 case 4: asm("movdqu %0, %%xmm4" : : "m"(*data)); break;
818 case 5: asm("movdqu %0, %%xmm5" : : "m"(*data)); break;
819 case 6: asm("movdqu %0, %%xmm6" : : "m"(*data)); break;
820 case 7: asm("movdqu %0, %%xmm7" : : "m"(*data)); break;
821 #ifdef CONFIG_X86_64
822 case 8: asm("movdqu %0, %%xmm8" : : "m"(*data)); break;
823 case 9: asm("movdqu %0, %%xmm9" : : "m"(*data)); break;
824 case 10: asm("movdqu %0, %%xmm10" : : "m"(*data)); break;
825 case 11: asm("movdqu %0, %%xmm11" : : "m"(*data)); break;
826 case 12: asm("movdqu %0, %%xmm12" : : "m"(*data)); break;
827 case 13: asm("movdqu %0, %%xmm13" : : "m"(*data)); break;
828 case 14: asm("movdqu %0, %%xmm14" : : "m"(*data)); break;
829 case 15: asm("movdqu %0, %%xmm15" : : "m"(*data)); break;
830 #endif
831 default: BUG();
832 }
833 ctxt->ops->put_fpu(ctxt);
834 }
835
836 static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
837 struct operand *op,
838 struct decode_cache *c,
839 int inhibit_bytereg)
840 {
841 unsigned reg = c->modrm_reg;
842 int highbyte_regs = c->rex_prefix == 0;
843
844 if (!(c->d & ModRM))
845 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
846
847 if (c->d & Sse) {
848 op->type = OP_XMM;
849 op->bytes = 16;
850 op->addr.xmm = reg;
851 read_sse_reg(ctxt, &op->vec_val, reg);
852 return;
853 }
854
855 op->type = OP_REG;
856 if ((c->d & ByteOp) && !inhibit_bytereg) {
857 op->addr.reg = decode_register(reg, c->regs, highbyte_regs);
858 op->bytes = 1;
859 } else {
860 op->addr.reg = decode_register(reg, c->regs, 0);
861 op->bytes = c->op_bytes;
862 }
863 fetch_register_operand(op);
864 op->orig_val = op->val;
865 }
866
867 static int decode_modrm(struct x86_emulate_ctxt *ctxt,
868 struct x86_emulate_ops *ops,
869 struct operand *op)
870 {
871 struct decode_cache *c = &ctxt->decode;
872 u8 sib;
873 int index_reg = 0, base_reg = 0, scale;
874 int rc = X86EMUL_CONTINUE;
875 ulong modrm_ea = 0;
876
877 if (c->rex_prefix) {
878 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
879 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
880 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
881 }
882
883 c->modrm = insn_fetch(u8, 1, c->eip);
884 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
885 c->modrm_reg |= (c->modrm & 0x38) >> 3;
886 c->modrm_rm |= (c->modrm & 0x07);
887 c->modrm_seg = VCPU_SREG_DS;
888
889 if (c->modrm_mod == 3) {
890 op->type = OP_REG;
891 op->bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
892 op->addr.reg = decode_register(c->modrm_rm,
893 c->regs, c->d & ByteOp);
894 if (c->d & Sse) {
895 op->type = OP_XMM;
896 op->bytes = 16;
897 op->addr.xmm = c->modrm_rm;
898 read_sse_reg(ctxt, &op->vec_val, c->modrm_rm);
899 return rc;
900 }
901 fetch_register_operand(op);
902 return rc;
903 }
904
905 op->type = OP_MEM;
906
907 if (c->ad_bytes == 2) {
908 unsigned bx = c->regs[VCPU_REGS_RBX];
909 unsigned bp = c->regs[VCPU_REGS_RBP];
910 unsigned si = c->regs[VCPU_REGS_RSI];
911 unsigned di = c->regs[VCPU_REGS_RDI];
912
913 /* 16-bit ModR/M decode. */
914 switch (c->modrm_mod) {
915 case 0:
916 if (c->modrm_rm == 6)
917 modrm_ea += insn_fetch(u16, 2, c->eip);
918 break;
919 case 1:
920 modrm_ea += insn_fetch(s8, 1, c->eip);
921 break;
922 case 2:
923 modrm_ea += insn_fetch(u16, 2, c->eip);
924 break;
925 }
926 switch (c->modrm_rm) {
927 case 0:
928 modrm_ea += bx + si;
929 break;
930 case 1:
931 modrm_ea += bx + di;
932 break;
933 case 2:
934 modrm_ea += bp + si;
935 break;
936 case 3:
937 modrm_ea += bp + di;
938 break;
939 case 4:
940 modrm_ea += si;
941 break;
942 case 5:
943 modrm_ea += di;
944 break;
945 case 6:
946 if (c->modrm_mod != 0)
947 modrm_ea += bp;
948 break;
949 case 7:
950 modrm_ea += bx;
951 break;
952 }
953 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
954 (c->modrm_rm == 6 && c->modrm_mod != 0))
955 c->modrm_seg = VCPU_SREG_SS;
956 modrm_ea = (u16)modrm_ea;
957 } else {
958 /* 32/64-bit ModR/M decode. */
959 if ((c->modrm_rm & 7) == 4) {
960 sib = insn_fetch(u8, 1, c->eip);
961 index_reg |= (sib >> 3) & 7;
962 base_reg |= sib & 7;
963 scale = sib >> 6;
964
965 if ((base_reg & 7) == 5 && c->modrm_mod == 0)
966 modrm_ea += insn_fetch(s32, 4, c->eip);
967 else
968 modrm_ea += c->regs[base_reg];
969 if (index_reg != 4)
970 modrm_ea += c->regs[index_reg] << scale;
971 } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
972 if (ctxt->mode == X86EMUL_MODE_PROT64)
973 c->rip_relative = 1;
974 } else
975 modrm_ea += c->regs[c->modrm_rm];
976 switch (c->modrm_mod) {
977 case 0:
978 if (c->modrm_rm == 5)
979 modrm_ea += insn_fetch(s32, 4, c->eip);
980 break;
981 case 1:
982 modrm_ea += insn_fetch(s8, 1, c->eip);
983 break;
984 case 2:
985 modrm_ea += insn_fetch(s32, 4, c->eip);
986 break;
987 }
988 }
989 op->addr.mem.ea = modrm_ea;
990 done:
991 return rc;
992 }
993
994 static int decode_abs(struct x86_emulate_ctxt *ctxt,
995 struct x86_emulate_ops *ops,
996 struct operand *op)
997 {
998 struct decode_cache *c = &ctxt->decode;
999 int rc = X86EMUL_CONTINUE;
1000
1001 op->type = OP_MEM;
1002 switch (c->ad_bytes) {
1003 case 2:
1004 op->addr.mem.ea = insn_fetch(u16, 2, c->eip);
1005 break;
1006 case 4:
1007 op->addr.mem.ea = insn_fetch(u32, 4, c->eip);
1008 break;
1009 case 8:
1010 op->addr.mem.ea = insn_fetch(u64, 8, c->eip);
1011 break;
1012 }
1013 done:
1014 return rc;
1015 }
1016
1017 static void fetch_bit_operand(struct decode_cache *c)
1018 {
1019 long sv = 0, mask;
1020
1021 if (c->dst.type == OP_MEM && c->src.type == OP_REG) {
1022 mask = ~(c->dst.bytes * 8 - 1);
1023
1024 if (c->src.bytes == 2)
1025 sv = (s16)c->src.val & (s16)mask;
1026 else if (c->src.bytes == 4)
1027 sv = (s32)c->src.val & (s32)mask;
1028
1029 c->dst.addr.mem.ea += (sv >> 3);
1030 }
1031
1032 /* only subword offset */
1033 c->src.val &= (c->dst.bytes << 3) - 1;
1034 }
1035
1036 static int read_emulated(struct x86_emulate_ctxt *ctxt,
1037 struct x86_emulate_ops *ops,
1038 unsigned long addr, void *dest, unsigned size)
1039 {
1040 int rc;
1041 struct read_cache *mc = &ctxt->decode.mem_read;
1042
1043 while (size) {
1044 int n = min(size, 8u);
1045 size -= n;
1046 if (mc->pos < mc->end)
1047 goto read_cached;
1048
1049 rc = ops->read_emulated(ctxt, addr, mc->data + mc->end, n,
1050 &ctxt->exception);
1051 if (rc != X86EMUL_CONTINUE)
1052 return rc;
1053 mc->end += n;
1054
1055 read_cached:
1056 memcpy(dest, mc->data + mc->pos, n);
1057 mc->pos += n;
1058 dest += n;
1059 addr += n;
1060 }
1061 return X86EMUL_CONTINUE;
1062 }
1063
1064 static int segmented_read(struct x86_emulate_ctxt *ctxt,
1065 struct segmented_address addr,
1066 void *data,
1067 unsigned size)
1068 {
1069 int rc;
1070 ulong linear;
1071
1072 rc = linearize(ctxt, addr, size, false, &linear);
1073 if (rc != X86EMUL_CONTINUE)
1074 return rc;
1075 return read_emulated(ctxt, ctxt->ops, linear, data, size);
1076 }
1077
1078 static int segmented_write(struct x86_emulate_ctxt *ctxt,
1079 struct segmented_address addr,
1080 const void *data,
1081 unsigned size)
1082 {
1083 int rc;
1084 ulong linear;
1085
1086 rc = linearize(ctxt, addr, size, true, &linear);
1087 if (rc != X86EMUL_CONTINUE)
1088 return rc;
1089 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1090 &ctxt->exception);
1091 }
1092
1093 static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1094 struct segmented_address addr,
1095 const void *orig_data, const void *data,
1096 unsigned size)
1097 {
1098 int rc;
1099 ulong linear;
1100
1101 rc = linearize(ctxt, addr, size, true, &linear);
1102 if (rc != X86EMUL_CONTINUE)
1103 return rc;
1104 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1105 size, &ctxt->exception);
1106 }
1107
1108 static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
1109 struct x86_emulate_ops *ops,
1110 unsigned int size, unsigned short port,
1111 void *dest)
1112 {
1113 struct read_cache *rc = &ctxt->decode.io_read;
1114
1115 if (rc->pos == rc->end) { /* refill pio read ahead */
1116 struct decode_cache *c = &ctxt->decode;
1117 unsigned int in_page, n;
1118 unsigned int count = c->rep_prefix ?
1119 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1;
1120 in_page = (ctxt->eflags & EFLG_DF) ?
1121 offset_in_page(c->regs[VCPU_REGS_RDI]) :
1122 PAGE_SIZE - offset_in_page(c->regs[VCPU_REGS_RDI]);
1123 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1124 count);
1125 if (n == 0)
1126 n = 1;
1127 rc->pos = rc->end = 0;
1128 if (!ops->pio_in_emulated(ctxt, size, port, rc->data, n))
1129 return 0;
1130 rc->end = n * size;
1131 }
1132
1133 memcpy(dest, rc->data + rc->pos, size);
1134 rc->pos += size;
1135 return 1;
1136 }
1137
1138 static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
1139 struct x86_emulate_ops *ops,
1140 u16 selector, struct desc_ptr *dt)
1141 {
1142 if (selector & 1 << 2) {
1143 struct desc_struct desc;
1144 memset (dt, 0, sizeof *dt);
1145 if (!ops->get_cached_descriptor(ctxt, &desc, NULL,
1146 VCPU_SREG_LDTR))
1147 return;
1148
1149 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1150 dt->address = get_desc_base(&desc);
1151 } else
1152 ops->get_gdt(ctxt, dt);
1153 }
1154
1155 /* allowed just for 8 bytes segments */
1156 static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1157 struct x86_emulate_ops *ops,
1158 u16 selector, struct desc_struct *desc)
1159 {
1160 struct desc_ptr dt;
1161 u16 index = selector >> 3;
1162 int ret;
1163 ulong addr;
1164
1165 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
1166
1167 if (dt.size < index * 8 + 7)
1168 return emulate_gp(ctxt, selector & 0xfffc);
1169 addr = dt.address + index * 8;
1170 ret = ops->read_std(ctxt, addr, desc, sizeof *desc, &ctxt->exception);
1171
1172 return ret;
1173 }
1174
1175 /* allowed just for 8 bytes segments */
1176 static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1177 struct x86_emulate_ops *ops,
1178 u16 selector, struct desc_struct *desc)
1179 {
1180 struct desc_ptr dt;
1181 u16 index = selector >> 3;
1182 ulong addr;
1183 int ret;
1184
1185 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
1186
1187 if (dt.size < index * 8 + 7)
1188 return emulate_gp(ctxt, selector & 0xfffc);
1189
1190 addr = dt.address + index * 8;
1191 ret = ops->write_std(ctxt, addr, desc, sizeof *desc, &ctxt->exception);
1192
1193 return ret;
1194 }
1195
1196 /* Does not support long mode */
1197 static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1198 struct x86_emulate_ops *ops,
1199 u16 selector, int seg)
1200 {
1201 struct desc_struct seg_desc;
1202 u8 dpl, rpl, cpl;
1203 unsigned err_vec = GP_VECTOR;
1204 u32 err_code = 0;
1205 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
1206 int ret;
1207
1208 memset(&seg_desc, 0, sizeof seg_desc);
1209
1210 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
1211 || ctxt->mode == X86EMUL_MODE_REAL) {
1212 /* set real mode segment descriptor */
1213 set_desc_base(&seg_desc, selector << 4);
1214 set_desc_limit(&seg_desc, 0xffff);
1215 seg_desc.type = 3;
1216 seg_desc.p = 1;
1217 seg_desc.s = 1;
1218 goto load;
1219 }
1220
1221 /* NULL selector is not valid for TR, CS and SS */
1222 if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR)
1223 && null_selector)
1224 goto exception;
1225
1226 /* TR should be in GDT only */
1227 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1228 goto exception;
1229
1230 if (null_selector) /* for NULL selector skip all following checks */
1231 goto load;
1232
1233 ret = read_segment_descriptor(ctxt, ops, selector, &seg_desc);
1234 if (ret != X86EMUL_CONTINUE)
1235 return ret;
1236
1237 err_code = selector & 0xfffc;
1238 err_vec = GP_VECTOR;
1239
1240 /* can't load system descriptor into segment selecor */
1241 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1242 goto exception;
1243
1244 if (!seg_desc.p) {
1245 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1246 goto exception;
1247 }
1248
1249 rpl = selector & 3;
1250 dpl = seg_desc.dpl;
1251 cpl = ops->cpl(ctxt);
1252
1253 switch (seg) {
1254 case VCPU_SREG_SS:
1255 /*
1256 * segment is not a writable data segment or segment
1257 * selector's RPL != CPL or segment selector's RPL != CPL
1258 */
1259 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1260 goto exception;
1261 break;
1262 case VCPU_SREG_CS:
1263 if (!(seg_desc.type & 8))
1264 goto exception;
1265
1266 if (seg_desc.type & 4) {
1267 /* conforming */
1268 if (dpl > cpl)
1269 goto exception;
1270 } else {
1271 /* nonconforming */
1272 if (rpl > cpl || dpl != cpl)
1273 goto exception;
1274 }
1275 /* CS(RPL) <- CPL */
1276 selector = (selector & 0xfffc) | cpl;
1277 break;
1278 case VCPU_SREG_TR:
1279 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1280 goto exception;
1281 break;
1282 case VCPU_SREG_LDTR:
1283 if (seg_desc.s || seg_desc.type != 2)
1284 goto exception;
1285 break;
1286 default: /* DS, ES, FS, or GS */
1287 /*
1288 * segment is not a data or readable code segment or
1289 * ((segment is a data or nonconforming code segment)
1290 * and (both RPL and CPL > DPL))
1291 */
1292 if ((seg_desc.type & 0xa) == 0x8 ||
1293 (((seg_desc.type & 0xc) != 0xc) &&
1294 (rpl > dpl && cpl > dpl)))
1295 goto exception;
1296 break;
1297 }
1298
1299 if (seg_desc.s) {
1300 /* mark segment as accessed */
1301 seg_desc.type |= 1;
1302 ret = write_segment_descriptor(ctxt, ops, selector, &seg_desc);
1303 if (ret != X86EMUL_CONTINUE)
1304 return ret;
1305 }
1306 load:
1307 ops->set_segment_selector(ctxt, selector, seg);
1308 ops->set_cached_descriptor(ctxt, &seg_desc, 0, seg);
1309 return X86EMUL_CONTINUE;
1310 exception:
1311 emulate_exception(ctxt, err_vec, err_code, true);
1312 return X86EMUL_PROPAGATE_FAULT;
1313 }
1314
1315 static void write_register_operand(struct operand *op)
1316 {
1317 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1318 switch (op->bytes) {
1319 case 1:
1320 *(u8 *)op->addr.reg = (u8)op->val;
1321 break;
1322 case 2:
1323 *(u16 *)op->addr.reg = (u16)op->val;
1324 break;
1325 case 4:
1326 *op->addr.reg = (u32)op->val;
1327 break; /* 64b: zero-extend */
1328 case 8:
1329 *op->addr.reg = op->val;
1330 break;
1331 }
1332 }
1333
1334 static inline int writeback(struct x86_emulate_ctxt *ctxt,
1335 struct x86_emulate_ops *ops)
1336 {
1337 int rc;
1338 struct decode_cache *c = &ctxt->decode;
1339
1340 switch (c->dst.type) {
1341 case OP_REG:
1342 write_register_operand(&c->dst);
1343 break;
1344 case OP_MEM:
1345 if (c->lock_prefix)
1346 rc = segmented_cmpxchg(ctxt,
1347 c->dst.addr.mem,
1348 &c->dst.orig_val,
1349 &c->dst.val,
1350 c->dst.bytes);
1351 else
1352 rc = segmented_write(ctxt,
1353 c->dst.addr.mem,
1354 &c->dst.val,
1355 c->dst.bytes);
1356 if (rc != X86EMUL_CONTINUE)
1357 return rc;
1358 break;
1359 case OP_XMM:
1360 write_sse_reg(ctxt, &c->dst.vec_val, c->dst.addr.xmm);
1361 break;
1362 case OP_NONE:
1363 /* no writeback */
1364 break;
1365 default:
1366 break;
1367 }
1368 return X86EMUL_CONTINUE;
1369 }
1370
1371 static int em_push(struct x86_emulate_ctxt *ctxt)
1372 {
1373 struct decode_cache *c = &ctxt->decode;
1374 struct segmented_address addr;
1375
1376 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
1377 addr.ea = register_address(c, c->regs[VCPU_REGS_RSP]);
1378 addr.seg = VCPU_SREG_SS;
1379
1380 /* Disable writeback. */
1381 c->dst.type = OP_NONE;
1382 return segmented_write(ctxt, addr, &c->src.val, c->op_bytes);
1383 }
1384
1385 static int emulate_pop(struct x86_emulate_ctxt *ctxt,
1386 struct x86_emulate_ops *ops,
1387 void *dest, int len)
1388 {
1389 struct decode_cache *c = &ctxt->decode;
1390 int rc;
1391 struct segmented_address addr;
1392
1393 addr.ea = register_address(c, c->regs[VCPU_REGS_RSP]);
1394 addr.seg = VCPU_SREG_SS;
1395 rc = segmented_read(ctxt, addr, dest, len);
1396 if (rc != X86EMUL_CONTINUE)
1397 return rc;
1398
1399 register_address_increment(c, &c->regs[VCPU_REGS_RSP], len);
1400 return rc;
1401 }
1402
1403 static int emulate_popf(struct x86_emulate_ctxt *ctxt,
1404 struct x86_emulate_ops *ops,
1405 void *dest, int len)
1406 {
1407 int rc;
1408 unsigned long val, change_mask;
1409 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1410 int cpl = ops->cpl(ctxt);
1411
1412 rc = emulate_pop(ctxt, ops, &val, len);
1413 if (rc != X86EMUL_CONTINUE)
1414 return rc;
1415
1416 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1417 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
1418
1419 switch(ctxt->mode) {
1420 case X86EMUL_MODE_PROT64:
1421 case X86EMUL_MODE_PROT32:
1422 case X86EMUL_MODE_PROT16:
1423 if (cpl == 0)
1424 change_mask |= EFLG_IOPL;
1425 if (cpl <= iopl)
1426 change_mask |= EFLG_IF;
1427 break;
1428 case X86EMUL_MODE_VM86:
1429 if (iopl < 3)
1430 return emulate_gp(ctxt, 0);
1431 change_mask |= EFLG_IF;
1432 break;
1433 default: /* real mode */
1434 change_mask |= (EFLG_IOPL | EFLG_IF);
1435 break;
1436 }
1437
1438 *(unsigned long *)dest =
1439 (ctxt->eflags & ~change_mask) | (val & change_mask);
1440
1441 return rc;
1442 }
1443
1444 static int emulate_push_sreg(struct x86_emulate_ctxt *ctxt,
1445 struct x86_emulate_ops *ops, int seg)
1446 {
1447 struct decode_cache *c = &ctxt->decode;
1448
1449 c->src.val = ops->get_segment_selector(ctxt, seg);
1450
1451 return em_push(ctxt);
1452 }
1453
1454 static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt,
1455 struct x86_emulate_ops *ops, int seg)
1456 {
1457 struct decode_cache *c = &ctxt->decode;
1458 unsigned long selector;
1459 int rc;
1460
1461 rc = emulate_pop(ctxt, ops, &selector, c->op_bytes);
1462 if (rc != X86EMUL_CONTINUE)
1463 return rc;
1464
1465 rc = load_segment_descriptor(ctxt, ops, (u16)selector, seg);
1466 return rc;
1467 }
1468
1469 static int emulate_pusha(struct x86_emulate_ctxt *ctxt)
1470 {
1471 struct decode_cache *c = &ctxt->decode;
1472 unsigned long old_esp = c->regs[VCPU_REGS_RSP];
1473 int rc = X86EMUL_CONTINUE;
1474 int reg = VCPU_REGS_RAX;
1475
1476 while (reg <= VCPU_REGS_RDI) {
1477 (reg == VCPU_REGS_RSP) ?
1478 (c->src.val = old_esp) : (c->src.val = c->regs[reg]);
1479
1480 rc = em_push(ctxt);
1481 if (rc != X86EMUL_CONTINUE)
1482 return rc;
1483
1484 ++reg;
1485 }
1486
1487 return rc;
1488 }
1489
1490 static int emulate_popa(struct x86_emulate_ctxt *ctxt,
1491 struct x86_emulate_ops *ops)
1492 {
1493 struct decode_cache *c = &ctxt->decode;
1494 int rc = X86EMUL_CONTINUE;
1495 int reg = VCPU_REGS_RDI;
1496
1497 while (reg >= VCPU_REGS_RAX) {
1498 if (reg == VCPU_REGS_RSP) {
1499 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
1500 c->op_bytes);
1501 --reg;
1502 }
1503
1504 rc = emulate_pop(ctxt, ops, &c->regs[reg], c->op_bytes);
1505 if (rc != X86EMUL_CONTINUE)
1506 break;
1507 --reg;
1508 }
1509 return rc;
1510 }
1511
1512 int emulate_int_real(struct x86_emulate_ctxt *ctxt,
1513 struct x86_emulate_ops *ops, int irq)
1514 {
1515 struct decode_cache *c = &ctxt->decode;
1516 int rc;
1517 struct desc_ptr dt;
1518 gva_t cs_addr;
1519 gva_t eip_addr;
1520 u16 cs, eip;
1521
1522 /* TODO: Add limit checks */
1523 c->src.val = ctxt->eflags;
1524 rc = em_push(ctxt);
1525 if (rc != X86EMUL_CONTINUE)
1526 return rc;
1527
1528 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1529
1530 c->src.val = ops->get_segment_selector(ctxt, VCPU_SREG_CS);
1531 rc = em_push(ctxt);
1532 if (rc != X86EMUL_CONTINUE)
1533 return rc;
1534
1535 c->src.val = c->eip;
1536 rc = em_push(ctxt);
1537 if (rc != X86EMUL_CONTINUE)
1538 return rc;
1539
1540 ops->get_idt(ctxt, &dt);
1541
1542 eip_addr = dt.address + (irq << 2);
1543 cs_addr = dt.address + (irq << 2) + 2;
1544
1545 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
1546 if (rc != X86EMUL_CONTINUE)
1547 return rc;
1548
1549 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
1550 if (rc != X86EMUL_CONTINUE)
1551 return rc;
1552
1553 rc = load_segment_descriptor(ctxt, ops, cs, VCPU_SREG_CS);
1554 if (rc != X86EMUL_CONTINUE)
1555 return rc;
1556
1557 c->eip = eip;
1558
1559 return rc;
1560 }
1561
1562 static int emulate_int(struct x86_emulate_ctxt *ctxt,
1563 struct x86_emulate_ops *ops, int irq)
1564 {
1565 switch(ctxt->mode) {
1566 case X86EMUL_MODE_REAL:
1567 return emulate_int_real(ctxt, ops, irq);
1568 case X86EMUL_MODE_VM86:
1569 case X86EMUL_MODE_PROT16:
1570 case X86EMUL_MODE_PROT32:
1571 case X86EMUL_MODE_PROT64:
1572 default:
1573 /* Protected mode interrupts unimplemented yet */
1574 return X86EMUL_UNHANDLEABLE;
1575 }
1576 }
1577
1578 static int emulate_iret_real(struct x86_emulate_ctxt *ctxt,
1579 struct x86_emulate_ops *ops)
1580 {
1581 struct decode_cache *c = &ctxt->decode;
1582 int rc = X86EMUL_CONTINUE;
1583 unsigned long temp_eip = 0;
1584 unsigned long temp_eflags = 0;
1585 unsigned long cs = 0;
1586 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1587 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1588 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1589 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
1590
1591 /* TODO: Add stack limit check */
1592
1593 rc = emulate_pop(ctxt, ops, &temp_eip, c->op_bytes);
1594
1595 if (rc != X86EMUL_CONTINUE)
1596 return rc;
1597
1598 if (temp_eip & ~0xffff)
1599 return emulate_gp(ctxt, 0);
1600
1601 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1602
1603 if (rc != X86EMUL_CONTINUE)
1604 return rc;
1605
1606 rc = emulate_pop(ctxt, ops, &temp_eflags, c->op_bytes);
1607
1608 if (rc != X86EMUL_CONTINUE)
1609 return rc;
1610
1611 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
1612
1613 if (rc != X86EMUL_CONTINUE)
1614 return rc;
1615
1616 c->eip = temp_eip;
1617
1618
1619 if (c->op_bytes == 4)
1620 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
1621 else if (c->op_bytes == 2) {
1622 ctxt->eflags &= ~0xffff;
1623 ctxt->eflags |= temp_eflags;
1624 }
1625
1626 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1627 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1628
1629 return rc;
1630 }
1631
1632 static inline int emulate_iret(struct x86_emulate_ctxt *ctxt,
1633 struct x86_emulate_ops* ops)
1634 {
1635 switch(ctxt->mode) {
1636 case X86EMUL_MODE_REAL:
1637 return emulate_iret_real(ctxt, ops);
1638 case X86EMUL_MODE_VM86:
1639 case X86EMUL_MODE_PROT16:
1640 case X86EMUL_MODE_PROT32:
1641 case X86EMUL_MODE_PROT64:
1642 default:
1643 /* iret from protected mode unimplemented yet */
1644 return X86EMUL_UNHANDLEABLE;
1645 }
1646 }
1647
1648 static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
1649 struct x86_emulate_ops *ops)
1650 {
1651 struct decode_cache *c = &ctxt->decode;
1652
1653 return emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes);
1654 }
1655
1656 static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
1657 {
1658 struct decode_cache *c = &ctxt->decode;
1659 switch (c->modrm_reg) {
1660 case 0: /* rol */
1661 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
1662 break;
1663 case 1: /* ror */
1664 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
1665 break;
1666 case 2: /* rcl */
1667 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
1668 break;
1669 case 3: /* rcr */
1670 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
1671 break;
1672 case 4: /* sal/shl */
1673 case 6: /* sal/shl */
1674 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
1675 break;
1676 case 5: /* shr */
1677 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
1678 break;
1679 case 7: /* sar */
1680 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
1681 break;
1682 }
1683 }
1684
1685 static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
1686 struct x86_emulate_ops *ops)
1687 {
1688 struct decode_cache *c = &ctxt->decode;
1689 unsigned long *rax = &c->regs[VCPU_REGS_RAX];
1690 unsigned long *rdx = &c->regs[VCPU_REGS_RDX];
1691 u8 de = 0;
1692
1693 switch (c->modrm_reg) {
1694 case 0 ... 1: /* test */
1695 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
1696 break;
1697 case 2: /* not */
1698 c->dst.val = ~c->dst.val;
1699 break;
1700 case 3: /* neg */
1701 emulate_1op("neg", c->dst, ctxt->eflags);
1702 break;
1703 case 4: /* mul */
1704 emulate_1op_rax_rdx("mul", c->src, *rax, *rdx, ctxt->eflags);
1705 break;
1706 case 5: /* imul */
1707 emulate_1op_rax_rdx("imul", c->src, *rax, *rdx, ctxt->eflags);
1708 break;
1709 case 6: /* div */
1710 emulate_1op_rax_rdx_ex("div", c->src, *rax, *rdx,
1711 ctxt->eflags, de);
1712 break;
1713 case 7: /* idiv */
1714 emulate_1op_rax_rdx_ex("idiv", c->src, *rax, *rdx,
1715 ctxt->eflags, de);
1716 break;
1717 default:
1718 return X86EMUL_UNHANDLEABLE;
1719 }
1720 if (de)
1721 return emulate_de(ctxt);
1722 return X86EMUL_CONTINUE;
1723 }
1724
1725 static int emulate_grp45(struct x86_emulate_ctxt *ctxt)
1726 {
1727 struct decode_cache *c = &ctxt->decode;
1728 int rc = X86EMUL_CONTINUE;
1729
1730 switch (c->modrm_reg) {
1731 case 0: /* inc */
1732 emulate_1op("inc", c->dst, ctxt->eflags);
1733 break;
1734 case 1: /* dec */
1735 emulate_1op("dec", c->dst, ctxt->eflags);
1736 break;
1737 case 2: /* call near abs */ {
1738 long int old_eip;
1739 old_eip = c->eip;
1740 c->eip = c->src.val;
1741 c->src.val = old_eip;
1742 rc = em_push(ctxt);
1743 break;
1744 }
1745 case 4: /* jmp abs */
1746 c->eip = c->src.val;
1747 break;
1748 case 6: /* push */
1749 rc = em_push(ctxt);
1750 break;
1751 }
1752 return rc;
1753 }
1754
1755 static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
1756 struct x86_emulate_ops *ops)
1757 {
1758 struct decode_cache *c = &ctxt->decode;
1759 u64 old = c->dst.orig_val64;
1760
1761 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1762 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
1763 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1764 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
1765 ctxt->eflags &= ~EFLG_ZF;
1766 } else {
1767 c->dst.val64 = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1768 (u32) c->regs[VCPU_REGS_RBX];
1769
1770 ctxt->eflags |= EFLG_ZF;
1771 }
1772 return X86EMUL_CONTINUE;
1773 }
1774
1775 static int emulate_ret_far(struct x86_emulate_ctxt *ctxt,
1776 struct x86_emulate_ops *ops)
1777 {
1778 struct decode_cache *c = &ctxt->decode;
1779 int rc;
1780 unsigned long cs;
1781
1782 rc = emulate_pop(ctxt, ops, &c->eip, c->op_bytes);
1783 if (rc != X86EMUL_CONTINUE)
1784 return rc;
1785 if (c->op_bytes == 4)
1786 c->eip = (u32)c->eip;
1787 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1788 if (rc != X86EMUL_CONTINUE)
1789 return rc;
1790 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
1791 return rc;
1792 }
1793
1794 static int emulate_load_segment(struct x86_emulate_ctxt *ctxt,
1795 struct x86_emulate_ops *ops, int seg)
1796 {
1797 struct decode_cache *c = &ctxt->decode;
1798 unsigned short sel;
1799 int rc;
1800
1801 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
1802
1803 rc = load_segment_descriptor(ctxt, ops, sel, seg);
1804 if (rc != X86EMUL_CONTINUE)
1805 return rc;
1806
1807 c->dst.val = c->src.val;
1808 return rc;
1809 }
1810
1811 static inline void
1812 setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
1813 struct x86_emulate_ops *ops, struct desc_struct *cs,
1814 struct desc_struct *ss)
1815 {
1816 memset(cs, 0, sizeof(struct desc_struct));
1817 ops->get_cached_descriptor(ctxt, cs, NULL, VCPU_SREG_CS);
1818 memset(ss, 0, sizeof(struct desc_struct));
1819
1820 cs->l = 0; /* will be adjusted later */
1821 set_desc_base(cs, 0); /* flat segment */
1822 cs->g = 1; /* 4kb granularity */
1823 set_desc_limit(cs, 0xfffff); /* 4GB limit */
1824 cs->type = 0x0b; /* Read, Execute, Accessed */
1825 cs->s = 1;
1826 cs->dpl = 0; /* will be adjusted later */
1827 cs->p = 1;
1828 cs->d = 1;
1829
1830 set_desc_base(ss, 0); /* flat segment */
1831 set_desc_limit(ss, 0xfffff); /* 4GB limit */
1832 ss->g = 1; /* 4kb granularity */
1833 ss->s = 1;
1834 ss->type = 0x03; /* Read/Write, Accessed */
1835 ss->d = 1; /* 32bit stack segment */
1836 ss->dpl = 0;
1837 ss->p = 1;
1838 }
1839
1840 static int
1841 emulate_syscall(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
1842 {
1843 struct decode_cache *c = &ctxt->decode;
1844 struct desc_struct cs, ss;
1845 u64 msr_data;
1846 u16 cs_sel, ss_sel;
1847
1848 /* syscall is not available in real mode */
1849 if (ctxt->mode == X86EMUL_MODE_REAL ||
1850 ctxt->mode == X86EMUL_MODE_VM86)
1851 return emulate_ud(ctxt);
1852
1853 setup_syscalls_segments(ctxt, ops, &cs, &ss);
1854
1855 ops->get_msr(ctxt, MSR_STAR, &msr_data);
1856 msr_data >>= 32;
1857 cs_sel = (u16)(msr_data & 0xfffc);
1858 ss_sel = (u16)(msr_data + 8);
1859
1860 if (is_long_mode(ctxt->vcpu)) {
1861 cs.d = 0;
1862 cs.l = 1;
1863 }
1864 ops->set_cached_descriptor(ctxt, &cs, 0, VCPU_SREG_CS);
1865 ops->set_segment_selector(ctxt, cs_sel, VCPU_SREG_CS);
1866 ops->set_cached_descriptor(ctxt, &ss, 0, VCPU_SREG_SS);
1867 ops->set_segment_selector(ctxt, ss_sel, VCPU_SREG_SS);
1868
1869 c->regs[VCPU_REGS_RCX] = c->eip;
1870 if (is_long_mode(ctxt->vcpu)) {
1871 #ifdef CONFIG_X86_64
1872 c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
1873
1874 ops->get_msr(ctxt,
1875 ctxt->mode == X86EMUL_MODE_PROT64 ?
1876 MSR_LSTAR : MSR_CSTAR, &msr_data);
1877 c->eip = msr_data;
1878
1879 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
1880 ctxt->eflags &= ~(msr_data | EFLG_RF);
1881 #endif
1882 } else {
1883 /* legacy mode */
1884 ops->get_msr(ctxt, MSR_STAR, &msr_data);
1885 c->eip = (u32)msr_data;
1886
1887 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1888 }
1889
1890 return X86EMUL_CONTINUE;
1891 }
1892
1893 static int
1894 emulate_sysenter(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
1895 {
1896 struct decode_cache *c = &ctxt->decode;
1897 struct desc_struct cs, ss;
1898 u64 msr_data;
1899 u16 cs_sel, ss_sel;
1900
1901 /* inject #GP if in real mode */
1902 if (ctxt->mode == X86EMUL_MODE_REAL)
1903 return emulate_gp(ctxt, 0);
1904
1905 /* XXX sysenter/sysexit have not been tested in 64bit mode.
1906 * Therefore, we inject an #UD.
1907 */
1908 if (ctxt->mode == X86EMUL_MODE_PROT64)
1909 return emulate_ud(ctxt);
1910
1911 setup_syscalls_segments(ctxt, ops, &cs, &ss);
1912
1913 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
1914 switch (ctxt->mode) {
1915 case X86EMUL_MODE_PROT32:
1916 if ((msr_data & 0xfffc) == 0x0)
1917 return emulate_gp(ctxt, 0);
1918 break;
1919 case X86EMUL_MODE_PROT64:
1920 if (msr_data == 0x0)
1921 return emulate_gp(ctxt, 0);
1922 break;
1923 }
1924
1925 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1926 cs_sel = (u16)msr_data;
1927 cs_sel &= ~SELECTOR_RPL_MASK;
1928 ss_sel = cs_sel + 8;
1929 ss_sel &= ~SELECTOR_RPL_MASK;
1930 if (ctxt->mode == X86EMUL_MODE_PROT64
1931 || is_long_mode(ctxt->vcpu)) {
1932 cs.d = 0;
1933 cs.l = 1;
1934 }
1935
1936 ops->set_cached_descriptor(ctxt, &cs, 0, VCPU_SREG_CS);
1937 ops->set_segment_selector(ctxt, cs_sel, VCPU_SREG_CS);
1938 ops->set_cached_descriptor(ctxt, &ss, 0, VCPU_SREG_SS);
1939 ops->set_segment_selector(ctxt, ss_sel, VCPU_SREG_SS);
1940
1941 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
1942 c->eip = msr_data;
1943
1944 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
1945 c->regs[VCPU_REGS_RSP] = msr_data;
1946
1947 return X86EMUL_CONTINUE;
1948 }
1949
1950 static int
1951 emulate_sysexit(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
1952 {
1953 struct decode_cache *c = &ctxt->decode;
1954 struct desc_struct cs, ss;
1955 u64 msr_data;
1956 int usermode;
1957 u16 cs_sel, ss_sel;
1958
1959 /* inject #GP if in real mode or Virtual 8086 mode */
1960 if (ctxt->mode == X86EMUL_MODE_REAL ||
1961 ctxt->mode == X86EMUL_MODE_VM86)
1962 return emulate_gp(ctxt, 0);
1963
1964 setup_syscalls_segments(ctxt, ops, &cs, &ss);
1965
1966 if ((c->rex_prefix & 0x8) != 0x0)
1967 usermode = X86EMUL_MODE_PROT64;
1968 else
1969 usermode = X86EMUL_MODE_PROT32;
1970
1971 cs.dpl = 3;
1972 ss.dpl = 3;
1973 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
1974 switch (usermode) {
1975 case X86EMUL_MODE_PROT32:
1976 cs_sel = (u16)(msr_data + 16);
1977 if ((msr_data & 0xfffc) == 0x0)
1978 return emulate_gp(ctxt, 0);
1979 ss_sel = (u16)(msr_data + 24);
1980 break;
1981 case X86EMUL_MODE_PROT64:
1982 cs_sel = (u16)(msr_data + 32);
1983 if (msr_data == 0x0)
1984 return emulate_gp(ctxt, 0);
1985 ss_sel = cs_sel + 8;
1986 cs.d = 0;
1987 cs.l = 1;
1988 break;
1989 }
1990 cs_sel |= SELECTOR_RPL_MASK;
1991 ss_sel |= SELECTOR_RPL_MASK;
1992
1993 ops->set_cached_descriptor(ctxt, &cs, 0, VCPU_SREG_CS);
1994 ops->set_segment_selector(ctxt, cs_sel, VCPU_SREG_CS);
1995 ops->set_cached_descriptor(ctxt, &ss, 0, VCPU_SREG_SS);
1996 ops->set_segment_selector(ctxt, ss_sel, VCPU_SREG_SS);
1997
1998 c->eip = c->regs[VCPU_REGS_RDX];
1999 c->regs[VCPU_REGS_RSP] = c->regs[VCPU_REGS_RCX];
2000
2001 return X86EMUL_CONTINUE;
2002 }
2003
2004 static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt,
2005 struct x86_emulate_ops *ops)
2006 {
2007 int iopl;
2008 if (ctxt->mode == X86EMUL_MODE_REAL)
2009 return false;
2010 if (ctxt->mode == X86EMUL_MODE_VM86)
2011 return true;
2012 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
2013 return ops->cpl(ctxt) > iopl;
2014 }
2015
2016 static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
2017 struct x86_emulate_ops *ops,
2018 u16 port, u16 len)
2019 {
2020 struct desc_struct tr_seg;
2021 u32 base3;
2022 int r;
2023 u16 io_bitmap_ptr, perm, bit_idx = port & 0x7;
2024 unsigned mask = (1 << len) - 1;
2025 unsigned long base;
2026
2027 ops->get_cached_descriptor(ctxt, &tr_seg, &base3, VCPU_SREG_TR);
2028 if (!tr_seg.p)
2029 return false;
2030 if (desc_limit_scaled(&tr_seg) < 103)
2031 return false;
2032 base = get_desc_base(&tr_seg);
2033 #ifdef CONFIG_X86_64
2034 base |= ((u64)base3) << 32;
2035 #endif
2036 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
2037 if (r != X86EMUL_CONTINUE)
2038 return false;
2039 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
2040 return false;
2041 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
2042 if (r != X86EMUL_CONTINUE)
2043 return false;
2044 if ((perm >> bit_idx) & mask)
2045 return false;
2046 return true;
2047 }
2048
2049 static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
2050 struct x86_emulate_ops *ops,
2051 u16 port, u16 len)
2052 {
2053 if (ctxt->perm_ok)
2054 return true;
2055
2056 if (emulator_bad_iopl(ctxt, ops))
2057 if (!emulator_io_port_access_allowed(ctxt, ops, port, len))
2058 return false;
2059
2060 ctxt->perm_ok = true;
2061
2062 return true;
2063 }
2064
2065 static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
2066 struct x86_emulate_ops *ops,
2067 struct tss_segment_16 *tss)
2068 {
2069 struct decode_cache *c = &ctxt->decode;
2070
2071 tss->ip = c->eip;
2072 tss->flag = ctxt->eflags;
2073 tss->ax = c->regs[VCPU_REGS_RAX];
2074 tss->cx = c->regs[VCPU_REGS_RCX];
2075 tss->dx = c->regs[VCPU_REGS_RDX];
2076 tss->bx = c->regs[VCPU_REGS_RBX];
2077 tss->sp = c->regs[VCPU_REGS_RSP];
2078 tss->bp = c->regs[VCPU_REGS_RBP];
2079 tss->si = c->regs[VCPU_REGS_RSI];
2080 tss->di = c->regs[VCPU_REGS_RDI];
2081
2082 tss->es = ops->get_segment_selector(ctxt, VCPU_SREG_ES);
2083 tss->cs = ops->get_segment_selector(ctxt, VCPU_SREG_CS);
2084 tss->ss = ops->get_segment_selector(ctxt, VCPU_SREG_SS);
2085 tss->ds = ops->get_segment_selector(ctxt, VCPU_SREG_DS);
2086 tss->ldt = ops->get_segment_selector(ctxt, VCPU_SREG_LDTR);
2087 }
2088
2089 static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
2090 struct x86_emulate_ops *ops,
2091 struct tss_segment_16 *tss)
2092 {
2093 struct decode_cache *c = &ctxt->decode;
2094 int ret;
2095
2096 c->eip = tss->ip;
2097 ctxt->eflags = tss->flag | 2;
2098 c->regs[VCPU_REGS_RAX] = tss->ax;
2099 c->regs[VCPU_REGS_RCX] = tss->cx;
2100 c->regs[VCPU_REGS_RDX] = tss->dx;
2101 c->regs[VCPU_REGS_RBX] = tss->bx;
2102 c->regs[VCPU_REGS_RSP] = tss->sp;
2103 c->regs[VCPU_REGS_RBP] = tss->bp;
2104 c->regs[VCPU_REGS_RSI] = tss->si;
2105 c->regs[VCPU_REGS_RDI] = tss->di;
2106
2107 /*
2108 * SDM says that segment selectors are loaded before segment
2109 * descriptors
2110 */
2111 ops->set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2112 ops->set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2113 ops->set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2114 ops->set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2115 ops->set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2116
2117 /*
2118 * Now load segment descriptors. If fault happenes at this stage
2119 * it is handled in a context of new task
2120 */
2121 ret = load_segment_descriptor(ctxt, ops, tss->ldt, VCPU_SREG_LDTR);
2122 if (ret != X86EMUL_CONTINUE)
2123 return ret;
2124 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
2125 if (ret != X86EMUL_CONTINUE)
2126 return ret;
2127 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
2128 if (ret != X86EMUL_CONTINUE)
2129 return ret;
2130 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
2131 if (ret != X86EMUL_CONTINUE)
2132 return ret;
2133 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
2134 if (ret != X86EMUL_CONTINUE)
2135 return ret;
2136
2137 return X86EMUL_CONTINUE;
2138 }
2139
2140 static int task_switch_16(struct x86_emulate_ctxt *ctxt,
2141 struct x86_emulate_ops *ops,
2142 u16 tss_selector, u16 old_tss_sel,
2143 ulong old_tss_base, struct desc_struct *new_desc)
2144 {
2145 struct tss_segment_16 tss_seg;
2146 int ret;
2147 u32 new_tss_base = get_desc_base(new_desc);
2148
2149 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
2150 &ctxt->exception);
2151 if (ret != X86EMUL_CONTINUE)
2152 /* FIXME: need to provide precise fault address */
2153 return ret;
2154
2155 save_state_to_tss16(ctxt, ops, &tss_seg);
2156
2157 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
2158 &ctxt->exception);
2159 if (ret != X86EMUL_CONTINUE)
2160 /* FIXME: need to provide precise fault address */
2161 return ret;
2162
2163 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
2164 &ctxt->exception);
2165 if (ret != X86EMUL_CONTINUE)
2166 /* FIXME: need to provide precise fault address */
2167 return ret;
2168
2169 if (old_tss_sel != 0xffff) {
2170 tss_seg.prev_task_link = old_tss_sel;
2171
2172 ret = ops->write_std(ctxt, new_tss_base,
2173 &tss_seg.prev_task_link,
2174 sizeof tss_seg.prev_task_link,
2175 &ctxt->exception);
2176 if (ret != X86EMUL_CONTINUE)
2177 /* FIXME: need to provide precise fault address */
2178 return ret;
2179 }
2180
2181 return load_state_from_tss16(ctxt, ops, &tss_seg);
2182 }
2183
2184 static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
2185 struct x86_emulate_ops *ops,
2186 struct tss_segment_32 *tss)
2187 {
2188 struct decode_cache *c = &ctxt->decode;
2189
2190 tss->cr3 = ops->get_cr(ctxt, 3);
2191 tss->eip = c->eip;
2192 tss->eflags = ctxt->eflags;
2193 tss->eax = c->regs[VCPU_REGS_RAX];
2194 tss->ecx = c->regs[VCPU_REGS_RCX];
2195 tss->edx = c->regs[VCPU_REGS_RDX];
2196 tss->ebx = c->regs[VCPU_REGS_RBX];
2197 tss->esp = c->regs[VCPU_REGS_RSP];
2198 tss->ebp = c->regs[VCPU_REGS_RBP];
2199 tss->esi = c->regs[VCPU_REGS_RSI];
2200 tss->edi = c->regs[VCPU_REGS_RDI];
2201
2202 tss->es = ops->get_segment_selector(ctxt, VCPU_SREG_ES);
2203 tss->cs = ops->get_segment_selector(ctxt, VCPU_SREG_CS);
2204 tss->ss = ops->get_segment_selector(ctxt, VCPU_SREG_SS);
2205 tss->ds = ops->get_segment_selector(ctxt, VCPU_SREG_DS);
2206 tss->fs = ops->get_segment_selector(ctxt, VCPU_SREG_FS);
2207 tss->gs = ops->get_segment_selector(ctxt, VCPU_SREG_GS);
2208 tss->ldt_selector = ops->get_segment_selector(ctxt, VCPU_SREG_LDTR);
2209 }
2210
2211 static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
2212 struct x86_emulate_ops *ops,
2213 struct tss_segment_32 *tss)
2214 {
2215 struct decode_cache *c = &ctxt->decode;
2216 int ret;
2217
2218 if (ops->set_cr(ctxt, 3, tss->cr3))
2219 return emulate_gp(ctxt, 0);
2220 c->eip = tss->eip;
2221 ctxt->eflags = tss->eflags | 2;
2222 c->regs[VCPU_REGS_RAX] = tss->eax;
2223 c->regs[VCPU_REGS_RCX] = tss->ecx;
2224 c->regs[VCPU_REGS_RDX] = tss->edx;
2225 c->regs[VCPU_REGS_RBX] = tss->ebx;
2226 c->regs[VCPU_REGS_RSP] = tss->esp;
2227 c->regs[VCPU_REGS_RBP] = tss->ebp;
2228 c->regs[VCPU_REGS_RSI] = tss->esi;
2229 c->regs[VCPU_REGS_RDI] = tss->edi;
2230
2231 /*
2232 * SDM says that segment selectors are loaded before segment
2233 * descriptors
2234 */
2235 ops->set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2236 ops->set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2237 ops->set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2238 ops->set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2239 ops->set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2240 ops->set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2241 ops->set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
2242
2243 /*
2244 * Now load segment descriptors. If fault happenes at this stage
2245 * it is handled in a context of new task
2246 */
2247 ret = load_segment_descriptor(ctxt, ops, tss->ldt_selector, VCPU_SREG_LDTR);
2248 if (ret != X86EMUL_CONTINUE)
2249 return ret;
2250 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
2251 if (ret != X86EMUL_CONTINUE)
2252 return ret;
2253 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
2254 if (ret != X86EMUL_CONTINUE)
2255 return ret;
2256 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
2257 if (ret != X86EMUL_CONTINUE)
2258 return ret;
2259 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
2260 if (ret != X86EMUL_CONTINUE)
2261 return ret;
2262 ret = load_segment_descriptor(ctxt, ops, tss->fs, VCPU_SREG_FS);
2263 if (ret != X86EMUL_CONTINUE)
2264 return ret;
2265 ret = load_segment_descriptor(ctxt, ops, tss->gs, VCPU_SREG_GS);
2266 if (ret != X86EMUL_CONTINUE)
2267 return ret;
2268
2269 return X86EMUL_CONTINUE;
2270 }
2271
2272 static int task_switch_32(struct x86_emulate_ctxt *ctxt,
2273 struct x86_emulate_ops *ops,
2274 u16 tss_selector, u16 old_tss_sel,
2275 ulong old_tss_base, struct desc_struct *new_desc)
2276 {
2277 struct tss_segment_32 tss_seg;
2278 int ret;
2279 u32 new_tss_base = get_desc_base(new_desc);
2280
2281 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
2282 &ctxt->exception);
2283 if (ret != X86EMUL_CONTINUE)
2284 /* FIXME: need to provide precise fault address */
2285 return ret;
2286
2287 save_state_to_tss32(ctxt, ops, &tss_seg);
2288
2289 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
2290 &ctxt->exception);
2291 if (ret != X86EMUL_CONTINUE)
2292 /* FIXME: need to provide precise fault address */
2293 return ret;
2294
2295 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
2296 &ctxt->exception);
2297 if (ret != X86EMUL_CONTINUE)
2298 /* FIXME: need to provide precise fault address */
2299 return ret;
2300
2301 if (old_tss_sel != 0xffff) {
2302 tss_seg.prev_task_link = old_tss_sel;
2303
2304 ret = ops->write_std(ctxt, new_tss_base,
2305 &tss_seg.prev_task_link,
2306 sizeof tss_seg.prev_task_link,
2307 &ctxt->exception);
2308 if (ret != X86EMUL_CONTINUE)
2309 /* FIXME: need to provide precise fault address */
2310 return ret;
2311 }
2312
2313 return load_state_from_tss32(ctxt, ops, &tss_seg);
2314 }
2315
2316 static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
2317 struct x86_emulate_ops *ops,
2318 u16 tss_selector, int reason,
2319 bool has_error_code, u32 error_code)
2320 {
2321 struct desc_struct curr_tss_desc, next_tss_desc;
2322 int ret;
2323 u16 old_tss_sel = ops->get_segment_selector(ctxt, VCPU_SREG_TR);
2324 ulong old_tss_base =
2325 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
2326 u32 desc_limit;
2327
2328 /* FIXME: old_tss_base == ~0 ? */
2329
2330 ret = read_segment_descriptor(ctxt, ops, tss_selector, &next_tss_desc);
2331 if (ret != X86EMUL_CONTINUE)
2332 return ret;
2333 ret = read_segment_descriptor(ctxt, ops, old_tss_sel, &curr_tss_desc);
2334 if (ret != X86EMUL_CONTINUE)
2335 return ret;
2336
2337 /* FIXME: check that next_tss_desc is tss */
2338
2339 if (reason != TASK_SWITCH_IRET) {
2340 if ((tss_selector & 3) > next_tss_desc.dpl ||
2341 ops->cpl(ctxt) > next_tss_desc.dpl)
2342 return emulate_gp(ctxt, 0);
2343 }
2344
2345 desc_limit = desc_limit_scaled(&next_tss_desc);
2346 if (!next_tss_desc.p ||
2347 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2348 desc_limit < 0x2b)) {
2349 emulate_ts(ctxt, tss_selector & 0xfffc);
2350 return X86EMUL_PROPAGATE_FAULT;
2351 }
2352
2353 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2354 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
2355 write_segment_descriptor(ctxt, ops, old_tss_sel,
2356 &curr_tss_desc);
2357 }
2358
2359 if (reason == TASK_SWITCH_IRET)
2360 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2361
2362 /* set back link to prev task only if NT bit is set in eflags
2363 note that old_tss_sel is not used afetr this point */
2364 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2365 old_tss_sel = 0xffff;
2366
2367 if (next_tss_desc.type & 8)
2368 ret = task_switch_32(ctxt, ops, tss_selector, old_tss_sel,
2369 old_tss_base, &next_tss_desc);
2370 else
2371 ret = task_switch_16(ctxt, ops, tss_selector, old_tss_sel,
2372 old_tss_base, &next_tss_desc);
2373 if (ret != X86EMUL_CONTINUE)
2374 return ret;
2375
2376 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2377 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2378
2379 if (reason != TASK_SWITCH_IRET) {
2380 next_tss_desc.type |= (1 << 1); /* set busy flag */
2381 write_segment_descriptor(ctxt, ops, tss_selector,
2382 &next_tss_desc);
2383 }
2384
2385 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
2386 ops->set_cached_descriptor(ctxt, &next_tss_desc, 0, VCPU_SREG_TR);
2387 ops->set_segment_selector(ctxt, tss_selector, VCPU_SREG_TR);
2388
2389 if (has_error_code) {
2390 struct decode_cache *c = &ctxt->decode;
2391
2392 c->op_bytes = c->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2393 c->lock_prefix = 0;
2394 c->src.val = (unsigned long) error_code;
2395 ret = em_push(ctxt);
2396 }
2397
2398 return ret;
2399 }
2400
2401 int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
2402 u16 tss_selector, int reason,
2403 bool has_error_code, u32 error_code)
2404 {
2405 struct x86_emulate_ops *ops = ctxt->ops;
2406 struct decode_cache *c = &ctxt->decode;
2407 int rc;
2408
2409 c->eip = ctxt->eip;
2410 c->dst.type = OP_NONE;
2411
2412 rc = emulator_do_task_switch(ctxt, ops, tss_selector, reason,
2413 has_error_code, error_code);
2414
2415 if (rc == X86EMUL_CONTINUE)
2416 ctxt->eip = c->eip;
2417
2418 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
2419 }
2420
2421 static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned seg,
2422 int reg, struct operand *op)
2423 {
2424 struct decode_cache *c = &ctxt->decode;
2425 int df = (ctxt->eflags & EFLG_DF) ? -1 : 1;
2426
2427 register_address_increment(c, &c->regs[reg], df * op->bytes);
2428 op->addr.mem.ea = register_address(c, c->regs[reg]);
2429 op->addr.mem.seg = seg;
2430 }
2431
2432 static int em_das(struct x86_emulate_ctxt *ctxt)
2433 {
2434 struct decode_cache *c = &ctxt->decode;
2435 u8 al, old_al;
2436 bool af, cf, old_cf;
2437
2438 cf = ctxt->eflags & X86_EFLAGS_CF;
2439 al = c->dst.val;
2440
2441 old_al = al;
2442 old_cf = cf;
2443 cf = false;
2444 af = ctxt->eflags & X86_EFLAGS_AF;
2445 if ((al & 0x0f) > 9 || af) {
2446 al -= 6;
2447 cf = old_cf | (al >= 250);
2448 af = true;
2449 } else {
2450 af = false;
2451 }
2452 if (old_al > 0x99 || old_cf) {
2453 al -= 0x60;
2454 cf = true;
2455 }
2456
2457 c->dst.val = al;
2458 /* Set PF, ZF, SF */
2459 c->src.type = OP_IMM;
2460 c->src.val = 0;
2461 c->src.bytes = 1;
2462 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
2463 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2464 if (cf)
2465 ctxt->eflags |= X86_EFLAGS_CF;
2466 if (af)
2467 ctxt->eflags |= X86_EFLAGS_AF;
2468 return X86EMUL_CONTINUE;
2469 }
2470
2471 static int em_call_far(struct x86_emulate_ctxt *ctxt)
2472 {
2473 struct decode_cache *c = &ctxt->decode;
2474 u16 sel, old_cs;
2475 ulong old_eip;
2476 int rc;
2477
2478 old_cs = ctxt->ops->get_segment_selector(ctxt, VCPU_SREG_CS);
2479 old_eip = c->eip;
2480
2481 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
2482 if (load_segment_descriptor(ctxt, ctxt->ops, sel, VCPU_SREG_CS))
2483 return X86EMUL_CONTINUE;
2484
2485 c->eip = 0;
2486 memcpy(&c->eip, c->src.valptr, c->op_bytes);
2487
2488 c->src.val = old_cs;
2489 rc = em_push(ctxt);
2490 if (rc != X86EMUL_CONTINUE)
2491 return rc;
2492
2493 c->src.val = old_eip;
2494 return em_push(ctxt);
2495 }
2496
2497 static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
2498 {
2499 struct decode_cache *c = &ctxt->decode;
2500 int rc;
2501
2502 c->dst.type = OP_REG;
2503 c->dst.addr.reg = &c->eip;
2504 c->dst.bytes = c->op_bytes;
2505 rc = emulate_pop(ctxt, ctxt->ops, &c->dst.val, c->op_bytes);
2506 if (rc != X86EMUL_CONTINUE)
2507 return rc;
2508 register_address_increment(c, &c->regs[VCPU_REGS_RSP], c->src.val);
2509 return X86EMUL_CONTINUE;
2510 }
2511
2512 static int em_imul(struct x86_emulate_ctxt *ctxt)
2513 {
2514 struct decode_cache *c = &ctxt->decode;
2515
2516 emulate_2op_SrcV_nobyte("imul", c->src, c->dst, ctxt->eflags);
2517 return X86EMUL_CONTINUE;
2518 }
2519
2520 static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
2521 {
2522 struct decode_cache *c = &ctxt->decode;
2523
2524 c->dst.val = c->src2.val;
2525 return em_imul(ctxt);
2526 }
2527
2528 static int em_cwd(struct x86_emulate_ctxt *ctxt)
2529 {
2530 struct decode_cache *c = &ctxt->decode;
2531
2532 c->dst.type = OP_REG;
2533 c->dst.bytes = c->src.bytes;
2534 c->dst.addr.reg = &c->regs[VCPU_REGS_RDX];
2535 c->dst.val = ~((c->src.val >> (c->src.bytes * 8 - 1)) - 1);
2536
2537 return X86EMUL_CONTINUE;
2538 }
2539
2540 static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
2541 {
2542 struct decode_cache *c = &ctxt->decode;
2543 u64 tsc = 0;
2544
2545 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
2546 c->regs[VCPU_REGS_RAX] = (u32)tsc;
2547 c->regs[VCPU_REGS_RDX] = tsc >> 32;
2548 return X86EMUL_CONTINUE;
2549 }
2550
2551 static int em_mov(struct x86_emulate_ctxt *ctxt)
2552 {
2553 struct decode_cache *c = &ctxt->decode;
2554 c->dst.val = c->src.val;
2555 return X86EMUL_CONTINUE;
2556 }
2557
2558 static int em_movdqu(struct x86_emulate_ctxt *ctxt)
2559 {
2560 struct decode_cache *c = &ctxt->decode;
2561 memcpy(&c->dst.vec_val, &c->src.vec_val, c->op_bytes);
2562 return X86EMUL_CONTINUE;
2563 }
2564
2565 static int em_invlpg(struct x86_emulate_ctxt *ctxt)
2566 {
2567 struct decode_cache *c = &ctxt->decode;
2568 int rc;
2569 ulong linear;
2570
2571 rc = linearize(ctxt, c->src.addr.mem, 1, false, &linear);
2572 if (rc == X86EMUL_CONTINUE)
2573 emulate_invlpg(ctxt->vcpu, linear);
2574 /* Disable writeback. */
2575 c->dst.type = OP_NONE;
2576 return X86EMUL_CONTINUE;
2577 }
2578
2579 static bool valid_cr(int nr)
2580 {
2581 switch (nr) {
2582 case 0:
2583 case 2 ... 4:
2584 case 8:
2585 return true;
2586 default:
2587 return false;
2588 }
2589 }
2590
2591 static int check_cr_read(struct x86_emulate_ctxt *ctxt)
2592 {
2593 struct decode_cache *c = &ctxt->decode;
2594
2595 if (!valid_cr(c->modrm_reg))
2596 return emulate_ud(ctxt);
2597
2598 return X86EMUL_CONTINUE;
2599 }
2600
2601 static int check_cr_write(struct x86_emulate_ctxt *ctxt)
2602 {
2603 struct decode_cache *c = &ctxt->decode;
2604 u64 new_val = c->src.val64;
2605 int cr = c->modrm_reg;
2606
2607 static u64 cr_reserved_bits[] = {
2608 0xffffffff00000000ULL,
2609 0, 0, 0, /* CR3 checked later */
2610 CR4_RESERVED_BITS,
2611 0, 0, 0,
2612 CR8_RESERVED_BITS,
2613 };
2614
2615 if (!valid_cr(cr))
2616 return emulate_ud(ctxt);
2617
2618 if (new_val & cr_reserved_bits[cr])
2619 return emulate_gp(ctxt, 0);
2620
2621 switch (cr) {
2622 case 0: {
2623 u64 cr4, efer;
2624 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
2625 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
2626 return emulate_gp(ctxt, 0);
2627
2628 cr4 = ctxt->ops->get_cr(ctxt, 4);
2629 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
2630
2631 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
2632 !(cr4 & X86_CR4_PAE))
2633 return emulate_gp(ctxt, 0);
2634
2635 break;
2636 }
2637 case 3: {
2638 u64 rsvd = 0;
2639
2640 if (is_long_mode(ctxt->vcpu))
2641 rsvd = CR3_L_MODE_RESERVED_BITS;
2642 else if (is_pae(ctxt->vcpu))
2643 rsvd = CR3_PAE_RESERVED_BITS;
2644 else if (is_paging(ctxt->vcpu))
2645 rsvd = CR3_NONPAE_RESERVED_BITS;
2646
2647 if (new_val & rsvd)
2648 return emulate_gp(ctxt, 0);
2649
2650 break;
2651 }
2652 case 4: {
2653 u64 cr4, efer;
2654
2655 cr4 = ctxt->ops->get_cr(ctxt, 4);
2656 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
2657
2658 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
2659 return emulate_gp(ctxt, 0);
2660
2661 break;
2662 }
2663 }
2664
2665 return X86EMUL_CONTINUE;
2666 }
2667
2668 static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
2669 {
2670 unsigned long dr7;
2671
2672 ctxt->ops->get_dr(ctxt, 7, &dr7);
2673
2674 /* Check if DR7.Global_Enable is set */
2675 return dr7 & (1 << 13);
2676 }
2677
2678 static int check_dr_read(struct x86_emulate_ctxt *ctxt)
2679 {
2680 struct decode_cache *c = &ctxt->decode;
2681 int dr = c->modrm_reg;
2682 u64 cr4;
2683
2684 if (dr > 7)
2685 return emulate_ud(ctxt);
2686
2687 cr4 = ctxt->ops->get_cr(ctxt, 4);
2688 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
2689 return emulate_ud(ctxt);
2690
2691 if (check_dr7_gd(ctxt))
2692 return emulate_db(ctxt);
2693
2694 return X86EMUL_CONTINUE;
2695 }
2696
2697 static int check_dr_write(struct x86_emulate_ctxt *ctxt)
2698 {
2699 struct decode_cache *c = &ctxt->decode;
2700 u64 new_val = c->src.val64;
2701 int dr = c->modrm_reg;
2702
2703 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
2704 return emulate_gp(ctxt, 0);
2705
2706 return check_dr_read(ctxt);
2707 }
2708
2709 static int check_svme(struct x86_emulate_ctxt *ctxt)
2710 {
2711 u64 efer;
2712
2713 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
2714
2715 if (!(efer & EFER_SVME))
2716 return emulate_ud(ctxt);
2717
2718 return X86EMUL_CONTINUE;
2719 }
2720
2721 static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
2722 {
2723 u64 rax = kvm_register_read(ctxt->vcpu, VCPU_REGS_RAX);
2724
2725 /* Valid physical address? */
2726 if (rax & 0xffff000000000000)
2727 return emulate_gp(ctxt, 0);
2728
2729 return check_svme(ctxt);
2730 }
2731
2732 static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
2733 {
2734 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
2735
2736 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
2737 return emulate_ud(ctxt);
2738
2739 return X86EMUL_CONTINUE;
2740 }
2741
2742 static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
2743 {
2744 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
2745 u64 rcx = kvm_register_read(ctxt->vcpu, VCPU_REGS_RCX);
2746
2747 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
2748 (rcx > 3))
2749 return emulate_gp(ctxt, 0);
2750
2751 return X86EMUL_CONTINUE;
2752 }
2753
2754 static int check_perm_in(struct x86_emulate_ctxt *ctxt)
2755 {
2756 struct decode_cache *c = &ctxt->decode;
2757
2758 c->dst.bytes = min(c->dst.bytes, 4u);
2759 if (!emulator_io_permited(ctxt, ctxt->ops, c->src.val, c->dst.bytes))
2760 return emulate_gp(ctxt, 0);
2761
2762 return X86EMUL_CONTINUE;
2763 }
2764
2765 static int check_perm_out(struct x86_emulate_ctxt *ctxt)
2766 {
2767 struct decode_cache *c = &ctxt->decode;
2768
2769 c->src.bytes = min(c->src.bytes, 4u);
2770 if (!emulator_io_permited(ctxt, ctxt->ops, c->dst.val, c->src.bytes))
2771 return emulate_gp(ctxt, 0);
2772
2773 return X86EMUL_CONTINUE;
2774 }
2775
2776 #define D(_y) { .flags = (_y) }
2777 #define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i }
2778 #define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \
2779 .check_perm = (_p) }
2780 #define N D(0)
2781 #define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
2782 #define G(_f, _g) { .flags = ((_f) | Group), .u.group = (_g) }
2783 #define GD(_f, _g) { .flags = ((_f) | Group | GroupDual), .u.gdual = (_g) }
2784 #define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
2785 #define II(_f, _e, _i) \
2786 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i }
2787 #define IIP(_f, _e, _i, _p) \
2788 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i, \
2789 .check_perm = (_p) }
2790 #define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
2791
2792 #define D2bv(_f) D((_f) | ByteOp), D(_f)
2793 #define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
2794 #define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
2795
2796 #define D6ALU(_f) D2bv((_f) | DstMem | SrcReg | ModRM), \
2797 D2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock), \
2798 D2bv(((_f) & ~Lock) | DstAcc | SrcImm)
2799
2800 static struct opcode group7_rm1[] = {
2801 DI(SrcNone | ModRM | Priv, monitor),
2802 DI(SrcNone | ModRM | Priv, mwait),
2803 N, N, N, N, N, N,
2804 };
2805
2806 static struct opcode group7_rm3[] = {
2807 DIP(SrcNone | ModRM | Prot | Priv, vmrun, check_svme_pa),
2808 DI(SrcNone | ModRM | Prot | VendorSpecific, vmmcall),
2809 DIP(SrcNone | ModRM | Prot | Priv, vmload, check_svme_pa),
2810 DIP(SrcNone | ModRM | Prot | Priv, vmsave, check_svme_pa),
2811 DIP(SrcNone | ModRM | Prot | Priv, stgi, check_svme),
2812 DIP(SrcNone | ModRM | Prot | Priv, clgi, check_svme),
2813 DIP(SrcNone | ModRM | Prot | Priv, skinit, check_svme),
2814 DIP(SrcNone | ModRM | Prot | Priv, invlpga, check_svme),
2815 };
2816
2817 static struct opcode group7_rm7[] = {
2818 N,
2819 DIP(SrcNone | ModRM, rdtscp, check_rdtsc),
2820 N, N, N, N, N, N,
2821 };
2822 static struct opcode group1[] = {
2823 X7(D(Lock)), N
2824 };
2825
2826 static struct opcode group1A[] = {
2827 D(DstMem | SrcNone | ModRM | Mov | Stack), N, N, N, N, N, N, N,
2828 };
2829
2830 static struct opcode group3[] = {
2831 D(DstMem | SrcImm | ModRM), D(DstMem | SrcImm | ModRM),
2832 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
2833 X4(D(SrcMem | ModRM)),
2834 };
2835
2836 static struct opcode group4[] = {
2837 D(ByteOp | DstMem | SrcNone | ModRM | Lock), D(ByteOp | DstMem | SrcNone | ModRM | Lock),
2838 N, N, N, N, N, N,
2839 };
2840
2841 static struct opcode group5[] = {
2842 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
2843 D(SrcMem | ModRM | Stack),
2844 I(SrcMemFAddr | ModRM | ImplicitOps | Stack, em_call_far),
2845 D(SrcMem | ModRM | Stack), D(SrcMemFAddr | ModRM | ImplicitOps),
2846 D(SrcMem | ModRM | Stack), N,
2847 };
2848
2849 static struct opcode group6[] = {
2850 DI(ModRM | Prot, sldt),
2851 DI(ModRM | Prot, str),
2852 DI(ModRM | Prot | Priv, lldt),
2853 DI(ModRM | Prot | Priv, ltr),
2854 N, N, N, N,
2855 };
2856
2857 static struct group_dual group7 = { {
2858 DI(ModRM | Mov | DstMem | Priv, sgdt),
2859 DI(ModRM | Mov | DstMem | Priv, sidt),
2860 DI(ModRM | SrcMem | Priv, lgdt), DI(ModRM | SrcMem | Priv, lidt),
2861 DI(SrcNone | ModRM | DstMem | Mov, smsw), N,
2862 DI(SrcMem16 | ModRM | Mov | Priv, lmsw),
2863 DI(SrcMem | ModRM | ByteOp | Priv | NoAccess, invlpg),
2864 }, {
2865 D(SrcNone | ModRM | Priv | VendorSpecific), EXT(0, group7_rm1),
2866 N, EXT(0, group7_rm3),
2867 DI(SrcNone | ModRM | DstMem | Mov, smsw), N,
2868 DI(SrcMem16 | ModRM | Mov | Priv, lmsw), EXT(0, group7_rm7),
2869 } };
2870
2871 static struct opcode group8[] = {
2872 N, N, N, N,
2873 D(DstMem | SrcImmByte | ModRM), D(DstMem | SrcImmByte | ModRM | Lock),
2874 D(DstMem | SrcImmByte | ModRM | Lock), D(DstMem | SrcImmByte | ModRM | Lock),
2875 };
2876
2877 static struct group_dual group9 = { {
2878 N, D(DstMem64 | ModRM | Lock), N, N, N, N, N, N,
2879 }, {
2880 N, N, N, N, N, N, N, N,
2881 } };
2882
2883 static struct opcode group11[] = {
2884 I(DstMem | SrcImm | ModRM | Mov, em_mov), X7(D(Undefined)),
2885 };
2886
2887 static struct gprefix pfx_0f_6f_0f_7f = {
2888 N, N, N, I(Sse, em_movdqu),
2889 };
2890
2891 static struct opcode opcode_table[256] = {
2892 /* 0x00 - 0x07 */
2893 D6ALU(Lock),
2894 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2895 /* 0x08 - 0x0F */
2896 D6ALU(Lock),
2897 D(ImplicitOps | Stack | No64), N,
2898 /* 0x10 - 0x17 */
2899 D6ALU(Lock),
2900 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2901 /* 0x18 - 0x1F */
2902 D6ALU(Lock),
2903 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2904 /* 0x20 - 0x27 */
2905 D6ALU(Lock), N, N,
2906 /* 0x28 - 0x2F */
2907 D6ALU(Lock), N, I(ByteOp | DstAcc | No64, em_das),
2908 /* 0x30 - 0x37 */
2909 D6ALU(Lock), N, N,
2910 /* 0x38 - 0x3F */
2911 D6ALU(0), N, N,
2912 /* 0x40 - 0x4F */
2913 X16(D(DstReg)),
2914 /* 0x50 - 0x57 */
2915 X8(I(SrcReg | Stack, em_push)),
2916 /* 0x58 - 0x5F */
2917 X8(D(DstReg | Stack)),
2918 /* 0x60 - 0x67 */
2919 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2920 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
2921 N, N, N, N,
2922 /* 0x68 - 0x6F */
2923 I(SrcImm | Mov | Stack, em_push),
2924 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
2925 I(SrcImmByte | Mov | Stack, em_push),
2926 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
2927 D2bvIP(DstDI | Mov | String, ins, check_perm_in), /* insb, insw/insd */
2928 D2bvIP(SrcSI | ImplicitOps | String, outs, check_perm_out), /* outsb, outsw/outsd */
2929 /* 0x70 - 0x7F */
2930 X16(D(SrcImmByte)),
2931 /* 0x80 - 0x87 */
2932 G(ByteOp | DstMem | SrcImm | ModRM | Group, group1),
2933 G(DstMem | SrcImm | ModRM | Group, group1),
2934 G(ByteOp | DstMem | SrcImm | ModRM | No64 | Group, group1),
2935 G(DstMem | SrcImmByte | ModRM | Group, group1),
2936 D2bv(DstMem | SrcReg | ModRM), D2bv(DstMem | SrcReg | ModRM | Lock),
2937 /* 0x88 - 0x8F */
2938 I2bv(DstMem | SrcReg | ModRM | Mov, em_mov),
2939 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
2940 D(DstMem | SrcNone | ModRM | Mov), D(ModRM | SrcMem | NoAccess | DstReg),
2941 D(ImplicitOps | SrcMem16 | ModRM), G(0, group1A),
2942 /* 0x90 - 0x97 */
2943 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
2944 /* 0x98 - 0x9F */
2945 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
2946 I(SrcImmFAddr | No64, em_call_far), N,
2947 DI(ImplicitOps | Stack, pushf), DI(ImplicitOps | Stack, popf), N, N,
2948 /* 0xA0 - 0xA7 */
2949 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
2950 I2bv(DstMem | SrcAcc | Mov | MemAbs, em_mov),
2951 I2bv(SrcSI | DstDI | Mov | String, em_mov),
2952 D2bv(SrcSI | DstDI | String),
2953 /* 0xA8 - 0xAF */
2954 D2bv(DstAcc | SrcImm),
2955 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
2956 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
2957 D2bv(SrcAcc | DstDI | String),
2958 /* 0xB0 - 0xB7 */
2959 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
2960 /* 0xB8 - 0xBF */
2961 X8(I(DstReg | SrcImm | Mov, em_mov)),
2962 /* 0xC0 - 0xC7 */
2963 D2bv(DstMem | SrcImmByte | ModRM),
2964 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
2965 D(ImplicitOps | Stack),
2966 D(DstReg | SrcMemFAddr | ModRM | No64), D(DstReg | SrcMemFAddr | ModRM | No64),
2967 G(ByteOp, group11), G(0, group11),
2968 /* 0xC8 - 0xCF */
2969 N, N, N, D(ImplicitOps | Stack),
2970 D(ImplicitOps), DI(SrcImmByte, intn),
2971 D(ImplicitOps | No64), DI(ImplicitOps, iret),
2972 /* 0xD0 - 0xD7 */
2973 D2bv(DstMem | SrcOne | ModRM), D2bv(DstMem | ModRM),
2974 N, N, N, N,
2975 /* 0xD8 - 0xDF */
2976 N, N, N, N, N, N, N, N,
2977 /* 0xE0 - 0xE7 */
2978 X4(D(SrcImmByte)),
2979 D2bvIP(SrcImmUByte | DstAcc, in, check_perm_in),
2980 D2bvIP(SrcAcc | DstImmUByte, out, check_perm_out),
2981 /* 0xE8 - 0xEF */
2982 D(SrcImm | Stack), D(SrcImm | ImplicitOps),
2983 D(SrcImmFAddr | No64), D(SrcImmByte | ImplicitOps),
2984 D2bvIP(SrcNone | DstAcc, in, check_perm_in),
2985 D2bvIP(SrcAcc | ImplicitOps, out, check_perm_out),
2986 /* 0xF0 - 0xF7 */
2987 N, DI(ImplicitOps, icebp), N, N,
2988 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
2989 G(ByteOp, group3), G(0, group3),
2990 /* 0xF8 - 0xFF */
2991 D(ImplicitOps), D(ImplicitOps), D(ImplicitOps), D(ImplicitOps),
2992 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
2993 };
2994
2995 static struct opcode twobyte_table[256] = {
2996 /* 0x00 - 0x0F */
2997 G(0, group6), GD(0, &group7), N, N,
2998 N, D(ImplicitOps | VendorSpecific), DI(ImplicitOps | Priv, clts), N,
2999 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
3000 N, D(ImplicitOps | ModRM), N, N,
3001 /* 0x10 - 0x1F */
3002 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
3003 /* 0x20 - 0x2F */
3004 DIP(ModRM | DstMem | Priv | Op3264, cr_read, check_cr_read),
3005 DIP(ModRM | DstMem | Priv | Op3264, dr_read, check_dr_read),
3006 DIP(ModRM | SrcMem | Priv | Op3264, cr_write, check_cr_write),
3007 DIP(ModRM | SrcMem | Priv | Op3264, dr_write, check_dr_write),
3008 N, N, N, N,
3009 N, N, N, N, N, N, N, N,
3010 /* 0x30 - 0x3F */
3011 DI(ImplicitOps | Priv, wrmsr),
3012 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
3013 DI(ImplicitOps | Priv, rdmsr),
3014 DIP(ImplicitOps | Priv, rdpmc, check_rdpmc),
3015 D(ImplicitOps | VendorSpecific), D(ImplicitOps | Priv | VendorSpecific),
3016 N, N,
3017 N, N, N, N, N, N, N, N,
3018 /* 0x40 - 0x4F */
3019 X16(D(DstReg | SrcMem | ModRM | Mov)),
3020 /* 0x50 - 0x5F */
3021 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3022 /* 0x60 - 0x6F */
3023 N, N, N, N,
3024 N, N, N, N,
3025 N, N, N, N,
3026 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
3027 /* 0x70 - 0x7F */
3028 N, N, N, N,
3029 N, N, N, N,
3030 N, N, N, N,
3031 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
3032 /* 0x80 - 0x8F */
3033 X16(D(SrcImm)),
3034 /* 0x90 - 0x9F */
3035 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
3036 /* 0xA0 - 0xA7 */
3037 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
3038 DI(ImplicitOps, cpuid), D(DstMem | SrcReg | ModRM | BitOp),
3039 D(DstMem | SrcReg | Src2ImmByte | ModRM),
3040 D(DstMem | SrcReg | Src2CL | ModRM), N, N,
3041 /* 0xA8 - 0xAF */
3042 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
3043 DI(ImplicitOps, rsm), D(DstMem | SrcReg | ModRM | BitOp | Lock),
3044 D(DstMem | SrcReg | Src2ImmByte | ModRM),
3045 D(DstMem | SrcReg | Src2CL | ModRM),
3046 D(ModRM), I(DstReg | SrcMem | ModRM, em_imul),
3047 /* 0xB0 - 0xB7 */
3048 D2bv(DstMem | SrcReg | ModRM | Lock),
3049 D(DstReg | SrcMemFAddr | ModRM), D(DstMem | SrcReg | ModRM | BitOp | Lock),
3050 D(DstReg | SrcMemFAddr | ModRM), D(DstReg | SrcMemFAddr | ModRM),
3051 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
3052 /* 0xB8 - 0xBF */
3053 N, N,
3054 G(BitOp, group8), D(DstMem | SrcReg | ModRM | BitOp | Lock),
3055 D(DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
3056 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
3057 /* 0xC0 - 0xCF */
3058 D2bv(DstMem | SrcReg | ModRM | Lock),
3059 N, D(DstMem | SrcReg | ModRM | Mov),
3060 N, N, N, GD(0, &group9),
3061 N, N, N, N, N, N, N, N,
3062 /* 0xD0 - 0xDF */
3063 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3064 /* 0xE0 - 0xEF */
3065 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3066 /* 0xF0 - 0xFF */
3067 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
3068 };
3069
3070 #undef D
3071 #undef N
3072 #undef G
3073 #undef GD
3074 #undef I
3075 #undef GP
3076 #undef EXT
3077
3078 #undef D2bv
3079 #undef D2bvIP
3080 #undef I2bv
3081 #undef D6ALU
3082
3083 static unsigned imm_size(struct decode_cache *c)
3084 {
3085 unsigned size;
3086
3087 size = (c->d & ByteOp) ? 1 : c->op_bytes;
3088 if (size == 8)
3089 size = 4;
3090 return size;
3091 }
3092
3093 static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
3094 unsigned size, bool sign_extension)
3095 {
3096 struct decode_cache *c = &ctxt->decode;
3097 struct x86_emulate_ops *ops = ctxt->ops;
3098 int rc = X86EMUL_CONTINUE;
3099
3100 op->type = OP_IMM;
3101 op->bytes = size;
3102 op->addr.mem.ea = c->eip;
3103 /* NB. Immediates are sign-extended as necessary. */
3104 switch (op->bytes) {
3105 case 1:
3106 op->val = insn_fetch(s8, 1, c->eip);
3107 break;
3108 case 2:
3109 op->val = insn_fetch(s16, 2, c->eip);
3110 break;
3111 case 4:
3112 op->val = insn_fetch(s32, 4, c->eip);
3113 break;
3114 }
3115 if (!sign_extension) {
3116 switch (op->bytes) {
3117 case 1:
3118 op->val &= 0xff;
3119 break;
3120 case 2:
3121 op->val &= 0xffff;
3122 break;
3123 case 4:
3124 op->val &= 0xffffffff;
3125 break;
3126 }
3127 }
3128 done:
3129 return rc;
3130 }
3131
3132 int
3133 x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
3134 {
3135 struct x86_emulate_ops *ops = ctxt->ops;
3136 struct decode_cache *c = &ctxt->decode;
3137 int rc = X86EMUL_CONTINUE;
3138 int mode = ctxt->mode;
3139 int def_op_bytes, def_ad_bytes, dual, goffset, simd_prefix;
3140 bool op_prefix = false;
3141 struct opcode opcode, *g_mod012, *g_mod3;
3142 struct operand memop = { .type = OP_NONE };
3143
3144 c->eip = ctxt->eip;
3145 c->fetch.start = c->eip;
3146 c->fetch.end = c->fetch.start + insn_len;
3147 if (insn_len > 0)
3148 memcpy(c->fetch.data, insn, insn_len);
3149
3150 switch (mode) {
3151 case X86EMUL_MODE_REAL:
3152 case X86EMUL_MODE_VM86:
3153 case X86EMUL_MODE_PROT16:
3154 def_op_bytes = def_ad_bytes = 2;
3155 break;
3156 case X86EMUL_MODE_PROT32:
3157 def_op_bytes = def_ad_bytes = 4;
3158 break;
3159 #ifdef CONFIG_X86_64
3160 case X86EMUL_MODE_PROT64:
3161 def_op_bytes = 4;
3162 def_ad_bytes = 8;
3163 break;
3164 #endif
3165 default:
3166 return -1;
3167 }
3168
3169 c->op_bytes = def_op_bytes;
3170 c->ad_bytes = def_ad_bytes;
3171
3172 /* Legacy prefixes. */
3173 for (;;) {
3174 switch (c->b = insn_fetch(u8, 1, c->eip)) {
3175 case 0x66: /* operand-size override */
3176 op_prefix = true;
3177 /* switch between 2/4 bytes */
3178 c->op_bytes = def_op_bytes ^ 6;
3179 break;
3180 case 0x67: /* address-size override */
3181 if (mode == X86EMUL_MODE_PROT64)
3182 /* switch between 4/8 bytes */
3183 c->ad_bytes = def_ad_bytes ^ 12;
3184 else
3185 /* switch between 2/4 bytes */
3186 c->ad_bytes = def_ad_bytes ^ 6;
3187 break;
3188 case 0x26: /* ES override */
3189 case 0x2e: /* CS override */
3190 case 0x36: /* SS override */
3191 case 0x3e: /* DS override */
3192 set_seg_override(c, (c->b >> 3) & 3);
3193 break;
3194 case 0x64: /* FS override */
3195 case 0x65: /* GS override */
3196 set_seg_override(c, c->b & 7);
3197 break;
3198 case 0x40 ... 0x4f: /* REX */
3199 if (mode != X86EMUL_MODE_PROT64)
3200 goto done_prefixes;
3201 c->rex_prefix = c->b;
3202 continue;
3203 case 0xf0: /* LOCK */
3204 c->lock_prefix = 1;
3205 break;
3206 case 0xf2: /* REPNE/REPNZ */
3207 case 0xf3: /* REP/REPE/REPZ */
3208 c->rep_prefix = c->b;
3209 break;
3210 default:
3211 goto done_prefixes;
3212 }
3213
3214 /* Any legacy prefix after a REX prefix nullifies its effect. */
3215
3216 c->rex_prefix = 0;
3217 }
3218
3219 done_prefixes:
3220
3221 /* REX prefix. */
3222 if (c->rex_prefix & 8)
3223 c->op_bytes = 8; /* REX.W */
3224
3225 /* Opcode byte(s). */
3226 opcode = opcode_table[c->b];
3227 /* Two-byte opcode? */
3228 if (c->b == 0x0f) {
3229 c->twobyte = 1;
3230 c->b = insn_fetch(u8, 1, c->eip);
3231 opcode = twobyte_table[c->b];
3232 }
3233 c->d = opcode.flags;
3234
3235 if (c->d & Group) {
3236 dual = c->d & GroupDual;
3237 c->modrm = insn_fetch(u8, 1, c->eip);
3238 --c->eip;
3239
3240 if (c->d & GroupDual) {
3241 g_mod012 = opcode.u.gdual->mod012;
3242 g_mod3 = opcode.u.gdual->mod3;
3243 } else
3244 g_mod012 = g_mod3 = opcode.u.group;
3245
3246 c->d &= ~(Group | GroupDual);
3247
3248 goffset = (c->modrm >> 3) & 7;
3249
3250 if ((c->modrm >> 6) == 3)
3251 opcode = g_mod3[goffset];
3252 else
3253 opcode = g_mod012[goffset];
3254
3255 if (opcode.flags & RMExt) {
3256 goffset = c->modrm & 7;
3257 opcode = opcode.u.group[goffset];
3258 }
3259
3260 c->d |= opcode.flags;
3261 }
3262
3263 if (c->d & Prefix) {
3264 if (c->rep_prefix && op_prefix)
3265 return X86EMUL_UNHANDLEABLE;
3266 simd_prefix = op_prefix ? 0x66 : c->rep_prefix;
3267 switch (simd_prefix) {
3268 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
3269 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
3270 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
3271 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
3272 }
3273 c->d |= opcode.flags;
3274 }
3275
3276 c->execute = opcode.u.execute;
3277 c->check_perm = opcode.check_perm;
3278 c->intercept = opcode.intercept;
3279
3280 /* Unrecognised? */
3281 if (c->d == 0 || (c->d & Undefined))
3282 return -1;
3283
3284 if (!(c->d & VendorSpecific) && ctxt->only_vendor_specific_insn)
3285 return -1;
3286
3287 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
3288 c->op_bytes = 8;
3289
3290 if (c->d & Op3264) {
3291 if (mode == X86EMUL_MODE_PROT64)
3292 c->op_bytes = 8;
3293 else
3294 c->op_bytes = 4;
3295 }
3296
3297 if (c->d & Sse)
3298 c->op_bytes = 16;
3299
3300 /* ModRM and SIB bytes. */
3301 if (c->d & ModRM) {
3302 rc = decode_modrm(ctxt, ops, &memop);
3303 if (!c->has_seg_override)
3304 set_seg_override(c, c->modrm_seg);
3305 } else if (c->d & MemAbs)
3306 rc = decode_abs(ctxt, ops, &memop);
3307 if (rc != X86EMUL_CONTINUE)
3308 goto done;
3309
3310 if (!c->has_seg_override)
3311 set_seg_override(c, VCPU_SREG_DS);
3312
3313 memop.addr.mem.seg = seg_override(ctxt, ops, c);
3314
3315 if (memop.type == OP_MEM && c->ad_bytes != 8)
3316 memop.addr.mem.ea = (u32)memop.addr.mem.ea;
3317
3318 if (memop.type == OP_MEM && c->rip_relative)
3319 memop.addr.mem.ea += c->eip;
3320
3321 /*
3322 * Decode and fetch the source operand: register, memory
3323 * or immediate.
3324 */
3325 switch (c->d & SrcMask) {
3326 case SrcNone:
3327 break;
3328 case SrcReg:
3329 decode_register_operand(ctxt, &c->src, c, 0);
3330 break;
3331 case SrcMem16:
3332 memop.bytes = 2;
3333 goto srcmem_common;
3334 case SrcMem32:
3335 memop.bytes = 4;
3336 goto srcmem_common;
3337 case SrcMem:
3338 memop.bytes = (c->d & ByteOp) ? 1 :
3339 c->op_bytes;
3340 srcmem_common:
3341 c->src = memop;
3342 break;
3343 case SrcImmU16:
3344 rc = decode_imm(ctxt, &c->src, 2, false);
3345 break;
3346 case SrcImm:
3347 rc = decode_imm(ctxt, &c->src, imm_size(c), true);
3348 break;
3349 case SrcImmU:
3350 rc = decode_imm(ctxt, &c->src, imm_size(c), false);
3351 break;
3352 case SrcImmByte:
3353 rc = decode_imm(ctxt, &c->src, 1, true);
3354 break;
3355 case SrcImmUByte:
3356 rc = decode_imm(ctxt, &c->src, 1, false);
3357 break;
3358 case SrcAcc:
3359 c->src.type = OP_REG;
3360 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
3361 c->src.addr.reg = &c->regs[VCPU_REGS_RAX];
3362 fetch_register_operand(&c->src);
3363 break;
3364 case SrcOne:
3365 c->src.bytes = 1;
3366 c->src.val = 1;
3367 break;
3368 case SrcSI:
3369 c->src.type = OP_MEM;
3370 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
3371 c->src.addr.mem.ea =
3372 register_address(c, c->regs[VCPU_REGS_RSI]);
3373 c->src.addr.mem.seg = seg_override(ctxt, ops, c),
3374 c->src.val = 0;
3375 break;
3376 case SrcImmFAddr:
3377 c->src.type = OP_IMM;
3378 c->src.addr.mem.ea = c->eip;
3379 c->src.bytes = c->op_bytes + 2;
3380 insn_fetch_arr(c->src.valptr, c->src.bytes, c->eip);
3381 break;
3382 case SrcMemFAddr:
3383 memop.bytes = c->op_bytes + 2;
3384 goto srcmem_common;
3385 break;
3386 }
3387
3388 if (rc != X86EMUL_CONTINUE)
3389 goto done;
3390
3391 /*
3392 * Decode and fetch the second source operand: register, memory
3393 * or immediate.
3394 */
3395 switch (c->d & Src2Mask) {
3396 case Src2None:
3397 break;
3398 case Src2CL:
3399 c->src2.bytes = 1;
3400 c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8;
3401 break;
3402 case Src2ImmByte:
3403 rc = decode_imm(ctxt, &c->src2, 1, true);
3404 break;
3405 case Src2One:
3406 c->src2.bytes = 1;
3407 c->src2.val = 1;
3408 break;
3409 case Src2Imm:
3410 rc = decode_imm(ctxt, &c->src2, imm_size(c), true);
3411 break;
3412 }
3413
3414 if (rc != X86EMUL_CONTINUE)
3415 goto done;
3416
3417 /* Decode and fetch the destination operand: register or memory. */
3418 switch (c->d & DstMask) {
3419 case DstReg:
3420 decode_register_operand(ctxt, &c->dst, c,
3421 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
3422 break;
3423 case DstImmUByte:
3424 c->dst.type = OP_IMM;
3425 c->dst.addr.mem.ea = c->eip;
3426 c->dst.bytes = 1;
3427 c->dst.val = insn_fetch(u8, 1, c->eip);
3428 break;
3429 case DstMem:
3430 case DstMem64:
3431 c->dst = memop;
3432 if ((c->d & DstMask) == DstMem64)
3433 c->dst.bytes = 8;
3434 else
3435 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
3436 if (c->d & BitOp)
3437 fetch_bit_operand(c);
3438 c->dst.orig_val = c->dst.val;
3439 break;
3440 case DstAcc:
3441 c->dst.type = OP_REG;
3442 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
3443 c->dst.addr.reg = &c->regs[VCPU_REGS_RAX];
3444 fetch_register_operand(&c->dst);
3445 c->dst.orig_val = c->dst.val;
3446 break;
3447 case DstDI:
3448 c->dst.type = OP_MEM;
3449 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
3450 c->dst.addr.mem.ea =
3451 register_address(c, c->regs[VCPU_REGS_RDI]);
3452 c->dst.addr.mem.seg = VCPU_SREG_ES;
3453 c->dst.val = 0;
3454 break;
3455 case ImplicitOps:
3456 /* Special instructions do their own operand decoding. */
3457 default:
3458 c->dst.type = OP_NONE; /* Disable writeback. */
3459 return 0;
3460 }
3461
3462 done:
3463 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
3464 }
3465
3466 static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
3467 {
3468 struct decode_cache *c = &ctxt->decode;
3469
3470 /* The second termination condition only applies for REPE
3471 * and REPNE. Test if the repeat string operation prefix is
3472 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
3473 * corresponding termination condition according to:
3474 * - if REPE/REPZ and ZF = 0 then done
3475 * - if REPNE/REPNZ and ZF = 1 then done
3476 */
3477 if (((c->b == 0xa6) || (c->b == 0xa7) ||
3478 (c->b == 0xae) || (c->b == 0xaf))
3479 && (((c->rep_prefix == REPE_PREFIX) &&
3480 ((ctxt->eflags & EFLG_ZF) == 0))
3481 || ((c->rep_prefix == REPNE_PREFIX) &&
3482 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
3483 return true;
3484
3485 return false;
3486 }
3487
3488 int
3489 x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
3490 {
3491 struct x86_emulate_ops *ops = ctxt->ops;
3492 u64 msr_data;
3493 struct decode_cache *c = &ctxt->decode;
3494 int rc = X86EMUL_CONTINUE;
3495 int saved_dst_type = c->dst.type;
3496 int irq; /* Used for int 3, int, and into */
3497
3498 ctxt->decode.mem_read.pos = 0;
3499
3500 if (ctxt->mode == X86EMUL_MODE_PROT64 && (c->d & No64)) {
3501 rc = emulate_ud(ctxt);
3502 goto done;
3503 }
3504
3505 /* LOCK prefix is allowed only with some instructions */
3506 if (c->lock_prefix && (!(c->d & Lock) || c->dst.type != OP_MEM)) {
3507 rc = emulate_ud(ctxt);
3508 goto done;
3509 }
3510
3511 if ((c->d & SrcMask) == SrcMemFAddr && c->src.type != OP_MEM) {
3512 rc = emulate_ud(ctxt);
3513 goto done;
3514 }
3515
3516 if ((c->d & Sse)
3517 && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)
3518 || !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
3519 rc = emulate_ud(ctxt);
3520 goto done;
3521 }
3522
3523 if ((c->d & Sse) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
3524 rc = emulate_nm(ctxt);
3525 goto done;
3526 }
3527
3528 if (unlikely(ctxt->guest_mode) && c->intercept) {
3529 rc = emulator_check_intercept(ctxt, c->intercept,
3530 X86_ICPT_PRE_EXCEPT);
3531 if (rc != X86EMUL_CONTINUE)
3532 goto done;
3533 }
3534
3535 /* Privileged instruction can be executed only in CPL=0 */
3536 if ((c->d & Priv) && ops->cpl(ctxt)) {
3537 rc = emulate_gp(ctxt, 0);
3538 goto done;
3539 }
3540
3541 /* Instruction can only be executed in protected mode */
3542 if ((c->d & Prot) && !(ctxt->mode & X86EMUL_MODE_PROT)) {
3543 rc = emulate_ud(ctxt);
3544 goto done;
3545 }
3546
3547 /* Do instruction specific permission checks */
3548 if (c->check_perm) {
3549 rc = c->check_perm(ctxt);
3550 if (rc != X86EMUL_CONTINUE)
3551 goto done;
3552 }
3553
3554 if (unlikely(ctxt->guest_mode) && c->intercept) {
3555 rc = emulator_check_intercept(ctxt, c->intercept,
3556 X86_ICPT_POST_EXCEPT);
3557 if (rc != X86EMUL_CONTINUE)
3558 goto done;
3559 }
3560
3561 if (c->rep_prefix && (c->d & String)) {
3562 /* All REP prefixes have the same first termination condition */
3563 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0) {
3564 ctxt->eip = c->eip;
3565 goto done;
3566 }
3567 }
3568
3569 if ((c->src.type == OP_MEM) && !(c->d & NoAccess)) {
3570 rc = segmented_read(ctxt, c->src.addr.mem,
3571 c->src.valptr, c->src.bytes);
3572 if (rc != X86EMUL_CONTINUE)
3573 goto done;
3574 c->src.orig_val64 = c->src.val64;
3575 }
3576
3577 if (c->src2.type == OP_MEM) {
3578 rc = segmented_read(ctxt, c->src2.addr.mem,
3579 &c->src2.val, c->src2.bytes);
3580 if (rc != X86EMUL_CONTINUE)
3581 goto done;
3582 }
3583
3584 if ((c->d & DstMask) == ImplicitOps)
3585 goto special_insn;
3586
3587
3588 if ((c->dst.type == OP_MEM) && !(c->d & Mov)) {
3589 /* optimisation - avoid slow emulated read if Mov */
3590 rc = segmented_read(ctxt, c->dst.addr.mem,
3591 &c->dst.val, c->dst.bytes);
3592 if (rc != X86EMUL_CONTINUE)
3593 goto done;
3594 }
3595 c->dst.orig_val = c->dst.val;
3596
3597 special_insn:
3598
3599 if (unlikely(ctxt->guest_mode) && c->intercept) {
3600 rc = emulator_check_intercept(ctxt, c->intercept,
3601 X86_ICPT_POST_MEMACCESS);
3602 if (rc != X86EMUL_CONTINUE)
3603 goto done;
3604 }
3605
3606 if (c->execute) {
3607 rc = c->execute(ctxt);
3608 if (rc != X86EMUL_CONTINUE)
3609 goto done;
3610 goto writeback;
3611 }
3612
3613 if (c->twobyte)
3614 goto twobyte_insn;
3615
3616 switch (c->b) {
3617 case 0x00 ... 0x05:
3618 add: /* add */
3619 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
3620 break;
3621 case 0x06: /* push es */
3622 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_ES);
3623 break;
3624 case 0x07: /* pop es */
3625 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_ES);
3626 break;
3627 case 0x08 ... 0x0d:
3628 or: /* or */
3629 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
3630 break;
3631 case 0x0e: /* push cs */
3632 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_CS);
3633 break;
3634 case 0x10 ... 0x15:
3635 adc: /* adc */
3636 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
3637 break;
3638 case 0x16: /* push ss */
3639 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_SS);
3640 break;
3641 case 0x17: /* pop ss */
3642 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_SS);
3643 break;
3644 case 0x18 ... 0x1d:
3645 sbb: /* sbb */
3646 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
3647 break;
3648 case 0x1e: /* push ds */
3649 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_DS);
3650 break;
3651 case 0x1f: /* pop ds */
3652 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_DS);
3653 break;
3654 case 0x20 ... 0x25:
3655 and: /* and */
3656 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
3657 break;
3658 case 0x28 ... 0x2d:
3659 sub: /* sub */
3660 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
3661 break;
3662 case 0x30 ... 0x35:
3663 xor: /* xor */
3664 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
3665 break;
3666 case 0x38 ... 0x3d:
3667 cmp: /* cmp */
3668 c->dst.type = OP_NONE; /* Disable writeback. */
3669 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
3670 break;
3671 case 0x40 ... 0x47: /* inc r16/r32 */
3672 emulate_1op("inc", c->dst, ctxt->eflags);
3673 break;
3674 case 0x48 ... 0x4f: /* dec r16/r32 */
3675 emulate_1op("dec", c->dst, ctxt->eflags);
3676 break;
3677 case 0x58 ... 0x5f: /* pop reg */
3678 pop_instruction:
3679 rc = emulate_pop(ctxt, ops, &c->dst.val, c->op_bytes);
3680 break;
3681 case 0x60: /* pusha */
3682 rc = emulate_pusha(ctxt);
3683 break;
3684 case 0x61: /* popa */
3685 rc = emulate_popa(ctxt, ops);
3686 break;
3687 case 0x63: /* movsxd */
3688 if (ctxt->mode != X86EMUL_MODE_PROT64)
3689 goto cannot_emulate;
3690 c->dst.val = (s32) c->src.val;
3691 break;
3692 case 0x6c: /* insb */
3693 case 0x6d: /* insw/insd */
3694 c->src.val = c->regs[VCPU_REGS_RDX];
3695 goto do_io_in;
3696 case 0x6e: /* outsb */
3697 case 0x6f: /* outsw/outsd */
3698 c->dst.val = c->regs[VCPU_REGS_RDX];
3699 goto do_io_out;
3700 break;
3701 case 0x70 ... 0x7f: /* jcc (short) */
3702 if (test_cc(c->b, ctxt->eflags))
3703 jmp_rel(c, c->src.val);
3704 break;
3705 case 0x80 ... 0x83: /* Grp1 */
3706 switch (c->modrm_reg) {
3707 case 0:
3708 goto add;
3709 case 1:
3710 goto or;
3711 case 2:
3712 goto adc;
3713 case 3:
3714 goto sbb;
3715 case 4:
3716 goto and;
3717 case 5:
3718 goto sub;
3719 case 6:
3720 goto xor;
3721 case 7:
3722 goto cmp;
3723 }
3724 break;
3725 case 0x84 ... 0x85:
3726 test:
3727 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
3728 break;
3729 case 0x86 ... 0x87: /* xchg */
3730 xchg:
3731 /* Write back the register source. */
3732 c->src.val = c->dst.val;
3733 write_register_operand(&c->src);
3734 /*
3735 * Write back the memory destination with implicit LOCK
3736 * prefix.
3737 */
3738 c->dst.val = c->src.orig_val;
3739 c->lock_prefix = 1;
3740 break;
3741 case 0x8c: /* mov r/m, sreg */
3742 if (c->modrm_reg > VCPU_SREG_GS) {
3743 rc = emulate_ud(ctxt);
3744 goto done;
3745 }
3746 c->dst.val = ops->get_segment_selector(ctxt, c->modrm_reg);
3747 break;
3748 case 0x8d: /* lea r16/r32, m */
3749 c->dst.val = c->src.addr.mem.ea;
3750 break;
3751 case 0x8e: { /* mov seg, r/m16 */
3752 uint16_t sel;
3753
3754 sel = c->src.val;
3755
3756 if (c->modrm_reg == VCPU_SREG_CS ||
3757 c->modrm_reg > VCPU_SREG_GS) {
3758 rc = emulate_ud(ctxt);
3759 goto done;
3760 }
3761
3762 if (c->modrm_reg == VCPU_SREG_SS)
3763 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3764
3765 rc = load_segment_descriptor(ctxt, ops, sel, c->modrm_reg);
3766
3767 c->dst.type = OP_NONE; /* Disable writeback. */
3768 break;
3769 }
3770 case 0x8f: /* pop (sole member of Grp1a) */
3771 rc = emulate_grp1a(ctxt, ops);
3772 break;
3773 case 0x90 ... 0x97: /* nop / xchg reg, rax */
3774 if (c->dst.addr.reg == &c->regs[VCPU_REGS_RAX])
3775 break;
3776 goto xchg;
3777 case 0x98: /* cbw/cwde/cdqe */
3778 switch (c->op_bytes) {
3779 case 2: c->dst.val = (s8)c->dst.val; break;
3780 case 4: c->dst.val = (s16)c->dst.val; break;
3781 case 8: c->dst.val = (s32)c->dst.val; break;
3782 }
3783 break;
3784 case 0x9c: /* pushf */
3785 c->src.val = (unsigned long) ctxt->eflags;
3786 rc = em_push(ctxt);
3787 break;
3788 case 0x9d: /* popf */
3789 c->dst.type = OP_REG;
3790 c->dst.addr.reg = &ctxt->eflags;
3791 c->dst.bytes = c->op_bytes;
3792 rc = emulate_popf(ctxt, ops, &c->dst.val, c->op_bytes);
3793 break;
3794 case 0xa6 ... 0xa7: /* cmps */
3795 goto cmp;
3796 case 0xa8 ... 0xa9: /* test ax, imm */
3797 goto test;
3798 case 0xae ... 0xaf: /* scas */
3799 goto cmp;
3800 case 0xc0 ... 0xc1:
3801 emulate_grp2(ctxt);
3802 break;
3803 case 0xc3: /* ret */
3804 c->dst.type = OP_REG;
3805 c->dst.addr.reg = &c->eip;
3806 c->dst.bytes = c->op_bytes;
3807 goto pop_instruction;
3808 case 0xc4: /* les */
3809 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_ES);
3810 break;
3811 case 0xc5: /* lds */
3812 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_DS);
3813 break;
3814 case 0xcb: /* ret far */
3815 rc = emulate_ret_far(ctxt, ops);
3816 break;
3817 case 0xcc: /* int3 */
3818 irq = 3;
3819 goto do_interrupt;
3820 case 0xcd: /* int n */
3821 irq = c->src.val;
3822 do_interrupt:
3823 rc = emulate_int(ctxt, ops, irq);
3824 break;
3825 case 0xce: /* into */
3826 if (ctxt->eflags & EFLG_OF) {
3827 irq = 4;
3828 goto do_interrupt;
3829 }
3830 break;
3831 case 0xcf: /* iret */
3832 rc = emulate_iret(ctxt, ops);
3833 break;
3834 case 0xd0 ... 0xd1: /* Grp2 */
3835 emulate_grp2(ctxt);
3836 break;
3837 case 0xd2 ... 0xd3: /* Grp2 */
3838 c->src.val = c->regs[VCPU_REGS_RCX];
3839 emulate_grp2(ctxt);
3840 break;
3841 case 0xe0 ... 0xe2: /* loop/loopz/loopnz */
3842 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
3843 if (address_mask(c, c->regs[VCPU_REGS_RCX]) != 0 &&
3844 (c->b == 0xe2 || test_cc(c->b ^ 0x5, ctxt->eflags)))
3845 jmp_rel(c, c->src.val);
3846 break;
3847 case 0xe3: /* jcxz/jecxz/jrcxz */
3848 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0)
3849 jmp_rel(c, c->src.val);
3850 break;
3851 case 0xe4: /* inb */
3852 case 0xe5: /* in */
3853 goto do_io_in;
3854 case 0xe6: /* outb */
3855 case 0xe7: /* out */
3856 goto do_io_out;
3857 case 0xe8: /* call (near) */ {
3858 long int rel = c->src.val;
3859 c->src.val = (unsigned long) c->eip;
3860 jmp_rel(c, rel);
3861 rc = em_push(ctxt);
3862 break;
3863 }
3864 case 0xe9: /* jmp rel */
3865 goto jmp;
3866 case 0xea: { /* jmp far */
3867 unsigned short sel;
3868 jump_far:
3869 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
3870
3871 if (load_segment_descriptor(ctxt, ops, sel, VCPU_SREG_CS))
3872 goto done;
3873
3874 c->eip = 0;
3875 memcpy(&c->eip, c->src.valptr, c->op_bytes);
3876 break;
3877 }
3878 case 0xeb:
3879 jmp: /* jmp rel short */
3880 jmp_rel(c, c->src.val);
3881 c->dst.type = OP_NONE; /* Disable writeback. */
3882 break;
3883 case 0xec: /* in al,dx */
3884 case 0xed: /* in (e/r)ax,dx */
3885 c->src.val = c->regs[VCPU_REGS_RDX];
3886 do_io_in:
3887 if (!pio_in_emulated(ctxt, ops, c->dst.bytes, c->src.val,
3888 &c->dst.val))
3889 goto done; /* IO is needed */
3890 break;
3891 case 0xee: /* out dx,al */
3892 case 0xef: /* out dx,(e/r)ax */
3893 c->dst.val = c->regs[VCPU_REGS_RDX];
3894 do_io_out:
3895 ops->pio_out_emulated(ctxt, c->src.bytes, c->dst.val,
3896 &c->src.val, 1);
3897 c->dst.type = OP_NONE; /* Disable writeback. */
3898 break;
3899 case 0xf4: /* hlt */
3900 ctxt->vcpu->arch.halt_request = 1;
3901 break;
3902 case 0xf5: /* cmc */
3903 /* complement carry flag from eflags reg */
3904 ctxt->eflags ^= EFLG_CF;
3905 break;
3906 case 0xf6 ... 0xf7: /* Grp3 */
3907 rc = emulate_grp3(ctxt, ops);
3908 break;
3909 case 0xf8: /* clc */
3910 ctxt->eflags &= ~EFLG_CF;
3911 break;
3912 case 0xf9: /* stc */
3913 ctxt->eflags |= EFLG_CF;
3914 break;
3915 case 0xfa: /* cli */
3916 if (emulator_bad_iopl(ctxt, ops)) {
3917 rc = emulate_gp(ctxt, 0);
3918 goto done;
3919 } else
3920 ctxt->eflags &= ~X86_EFLAGS_IF;
3921 break;
3922 case 0xfb: /* sti */
3923 if (emulator_bad_iopl(ctxt, ops)) {
3924 rc = emulate_gp(ctxt, 0);
3925 goto done;
3926 } else {
3927 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3928 ctxt->eflags |= X86_EFLAGS_IF;
3929 }
3930 break;
3931 case 0xfc: /* cld */
3932 ctxt->eflags &= ~EFLG_DF;
3933 break;
3934 case 0xfd: /* std */
3935 ctxt->eflags |= EFLG_DF;
3936 break;
3937 case 0xfe: /* Grp4 */
3938 grp45:
3939 rc = emulate_grp45(ctxt);
3940 break;
3941 case 0xff: /* Grp5 */
3942 if (c->modrm_reg == 5)
3943 goto jump_far;
3944 goto grp45;
3945 default:
3946 goto cannot_emulate;
3947 }
3948
3949 if (rc != X86EMUL_CONTINUE)
3950 goto done;
3951
3952 writeback:
3953 rc = writeback(ctxt, ops);
3954 if (rc != X86EMUL_CONTINUE)
3955 goto done;
3956
3957 /*
3958 * restore dst type in case the decoding will be reused
3959 * (happens for string instruction )
3960 */
3961 c->dst.type = saved_dst_type;
3962
3963 if ((c->d & SrcMask) == SrcSI)
3964 string_addr_inc(ctxt, seg_override(ctxt, ops, c),
3965 VCPU_REGS_RSI, &c->src);
3966
3967 if ((c->d & DstMask) == DstDI)
3968 string_addr_inc(ctxt, VCPU_SREG_ES, VCPU_REGS_RDI,
3969 &c->dst);
3970
3971 if (c->rep_prefix && (c->d & String)) {
3972 struct read_cache *r = &ctxt->decode.io_read;
3973 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
3974
3975 if (!string_insn_completed(ctxt)) {
3976 /*
3977 * Re-enter guest when pio read ahead buffer is empty
3978 * or, if it is not used, after each 1024 iteration.
3979 */
3980 if ((r->end != 0 || c->regs[VCPU_REGS_RCX] & 0x3ff) &&
3981 (r->end == 0 || r->end != r->pos)) {
3982 /*
3983 * Reset read cache. Usually happens before
3984 * decode, but since instruction is restarted
3985 * we have to do it here.
3986 */
3987 ctxt->decode.mem_read.end = 0;
3988 return EMULATION_RESTART;
3989 }
3990 goto done; /* skip rip writeback */
3991 }
3992 }
3993
3994 ctxt->eip = c->eip;
3995
3996 done:
3997 if (rc == X86EMUL_PROPAGATE_FAULT)
3998 ctxt->have_exception = true;
3999 if (rc == X86EMUL_INTERCEPTED)
4000 return EMULATION_INTERCEPTED;
4001
4002 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
4003
4004 twobyte_insn:
4005 switch (c->b) {
4006 case 0x01: /* lgdt, lidt, lmsw */
4007 switch (c->modrm_reg) {
4008 u16 size;
4009 unsigned long address;
4010
4011 case 0: /* vmcall */
4012 if (c->modrm_mod != 3 || c->modrm_rm != 1)
4013 goto cannot_emulate;
4014
4015 rc = kvm_fix_hypercall(ctxt->vcpu);
4016 if (rc != X86EMUL_CONTINUE)
4017 goto done;
4018
4019 /* Let the processor re-execute the fixed hypercall */
4020 c->eip = ctxt->eip;
4021 /* Disable writeback. */
4022 c->dst.type = OP_NONE;
4023 break;
4024 case 2: /* lgdt */
4025 rc = read_descriptor(ctxt, ops, c->src.addr.mem,
4026 &size, &address, c->op_bytes);
4027 if (rc != X86EMUL_CONTINUE)
4028 goto done;
4029 realmode_lgdt(ctxt->vcpu, size, address);
4030 /* Disable writeback. */
4031 c->dst.type = OP_NONE;
4032 break;
4033 case 3: /* lidt/vmmcall */
4034 if (c->modrm_mod == 3) {
4035 switch (c->modrm_rm) {
4036 case 1:
4037 rc = kvm_fix_hypercall(ctxt->vcpu);
4038 break;
4039 default:
4040 goto cannot_emulate;
4041 }
4042 } else {
4043 rc = read_descriptor(ctxt, ops, c->src.addr.mem,
4044 &size, &address,
4045 c->op_bytes);
4046 if (rc != X86EMUL_CONTINUE)
4047 goto done;
4048 realmode_lidt(ctxt->vcpu, size, address);
4049 }
4050 /* Disable writeback. */
4051 c->dst.type = OP_NONE;
4052 break;
4053 case 4: /* smsw */
4054 c->dst.bytes = 2;
4055 c->dst.val = ops->get_cr(ctxt, 0);
4056 break;
4057 case 6: /* lmsw */
4058 ops->set_cr(ctxt, 0, (ops->get_cr(ctxt, 0) & ~0x0eul) |
4059 (c->src.val & 0x0f));
4060 c->dst.type = OP_NONE;
4061 break;
4062 case 5: /* not defined */
4063 emulate_ud(ctxt);
4064 rc = X86EMUL_PROPAGATE_FAULT;
4065 goto done;
4066 case 7: /* invlpg*/
4067 rc = em_invlpg(ctxt);
4068 break;
4069 default:
4070 goto cannot_emulate;
4071 }
4072 break;
4073 case 0x05: /* syscall */
4074 rc = emulate_syscall(ctxt, ops);
4075 break;
4076 case 0x06:
4077 emulate_clts(ctxt->vcpu);
4078 break;
4079 case 0x09: /* wbinvd */
4080 kvm_emulate_wbinvd(ctxt->vcpu);
4081 break;
4082 case 0x08: /* invd */
4083 case 0x0d: /* GrpP (prefetch) */
4084 case 0x18: /* Grp16 (prefetch/nop) */
4085 break;
4086 case 0x20: /* mov cr, reg */
4087 c->dst.val = ops->get_cr(ctxt, c->modrm_reg);
4088 break;
4089 case 0x21: /* mov from dr to reg */
4090 ops->get_dr(ctxt, c->modrm_reg, &c->dst.val);
4091 break;
4092 case 0x22: /* mov reg, cr */
4093 if (ops->set_cr(ctxt, c->modrm_reg, c->src.val)) {
4094 emulate_gp(ctxt, 0);
4095 rc = X86EMUL_PROPAGATE_FAULT;
4096 goto done;
4097 }
4098 c->dst.type = OP_NONE;
4099 break;
4100 case 0x23: /* mov from reg to dr */
4101 if (ops->set_dr(ctxt, c->modrm_reg, c->src.val &
4102 ((ctxt->mode == X86EMUL_MODE_PROT64) ?
4103 ~0ULL : ~0U)) < 0) {
4104 /* #UD condition is already handled by the code above */
4105 emulate_gp(ctxt, 0);
4106 rc = X86EMUL_PROPAGATE_FAULT;
4107 goto done;
4108 }
4109
4110 c->dst.type = OP_NONE; /* no writeback */
4111 break;
4112 case 0x30:
4113 /* wrmsr */
4114 msr_data = (u32)c->regs[VCPU_REGS_RAX]
4115 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
4116 if (ops->set_msr(ctxt, c->regs[VCPU_REGS_RCX], msr_data)) {
4117 emulate_gp(ctxt, 0);
4118 rc = X86EMUL_PROPAGATE_FAULT;
4119 goto done;
4120 }
4121 rc = X86EMUL_CONTINUE;
4122 break;
4123 case 0x32:
4124 /* rdmsr */
4125 if (ops->get_msr(ctxt, c->regs[VCPU_REGS_RCX], &msr_data)) {
4126 emulate_gp(ctxt, 0);
4127 rc = X86EMUL_PROPAGATE_FAULT;
4128 goto done;
4129 } else {
4130 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
4131 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
4132 }
4133 rc = X86EMUL_CONTINUE;
4134 break;
4135 case 0x34: /* sysenter */
4136 rc = emulate_sysenter(ctxt, ops);
4137 break;
4138 case 0x35: /* sysexit */
4139 rc = emulate_sysexit(ctxt, ops);
4140 break;
4141 case 0x40 ... 0x4f: /* cmov */
4142 c->dst.val = c->dst.orig_val = c->src.val;
4143 if (!test_cc(c->b, ctxt->eflags))
4144 c->dst.type = OP_NONE; /* no writeback */
4145 break;
4146 case 0x80 ... 0x8f: /* jnz rel, etc*/
4147 if (test_cc(c->b, ctxt->eflags))
4148 jmp_rel(c, c->src.val);
4149 break;
4150 case 0x90 ... 0x9f: /* setcc r/m8 */
4151 c->dst.val = test_cc(c->b, ctxt->eflags);
4152 break;
4153 case 0xa0: /* push fs */
4154 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_FS);
4155 break;
4156 case 0xa1: /* pop fs */
4157 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_FS);
4158 break;
4159 case 0xa3:
4160 bt: /* bt */
4161 c->dst.type = OP_NONE;
4162 /* only subword offset */
4163 c->src.val &= (c->dst.bytes << 3) - 1;
4164 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
4165 break;
4166 case 0xa4: /* shld imm8, r, r/m */
4167 case 0xa5: /* shld cl, r, r/m */
4168 emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags);
4169 break;
4170 case 0xa8: /* push gs */
4171 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_GS);
4172 break;
4173 case 0xa9: /* pop gs */
4174 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_GS);
4175 break;
4176 case 0xab:
4177 bts: /* bts */
4178 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
4179 break;
4180 case 0xac: /* shrd imm8, r, r/m */
4181 case 0xad: /* shrd cl, r, r/m */
4182 emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags);
4183 break;
4184 case 0xae: /* clflush */
4185 break;
4186 case 0xb0 ... 0xb1: /* cmpxchg */
4187 /*
4188 * Save real source value, then compare EAX against
4189 * destination.
4190 */
4191 c->src.orig_val = c->src.val;
4192 c->src.val = c->regs[VCPU_REGS_RAX];
4193 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
4194 if (ctxt->eflags & EFLG_ZF) {
4195 /* Success: write back to memory. */
4196 c->dst.val = c->src.orig_val;
4197 } else {
4198 /* Failure: write the value we saw to EAX. */
4199 c->dst.type = OP_REG;
4200 c->dst.addr.reg = (unsigned long *)&c->regs[VCPU_REGS_RAX];
4201 }
4202 break;
4203 case 0xb2: /* lss */
4204 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_SS);
4205 break;
4206 case 0xb3:
4207 btr: /* btr */
4208 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
4209 break;
4210 case 0xb4: /* lfs */
4211 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_FS);
4212 break;
4213 case 0xb5: /* lgs */
4214 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_GS);
4215 break;
4216 case 0xb6 ... 0xb7: /* movzx */
4217 c->dst.bytes = c->op_bytes;
4218 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
4219 : (u16) c->src.val;
4220 break;
4221 case 0xba: /* Grp8 */
4222 switch (c->modrm_reg & 3) {
4223 case 0:
4224 goto bt;
4225 case 1:
4226 goto bts;
4227 case 2:
4228 goto btr;
4229 case 3:
4230 goto btc;
4231 }
4232 break;
4233 case 0xbb:
4234 btc: /* btc */
4235 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
4236 break;
4237 case 0xbc: { /* bsf */
4238 u8 zf;
4239 __asm__ ("bsf %2, %0; setz %1"
4240 : "=r"(c->dst.val), "=q"(zf)
4241 : "r"(c->src.val));
4242 ctxt->eflags &= ~X86_EFLAGS_ZF;
4243 if (zf) {
4244 ctxt->eflags |= X86_EFLAGS_ZF;
4245 c->dst.type = OP_NONE; /* Disable writeback. */
4246 }
4247 break;
4248 }
4249 case 0xbd: { /* bsr */
4250 u8 zf;
4251 __asm__ ("bsr %2, %0; setz %1"
4252 : "=r"(c->dst.val), "=q"(zf)
4253 : "r"(c->src.val));
4254 ctxt->eflags &= ~X86_EFLAGS_ZF;
4255 if (zf) {
4256 ctxt->eflags |= X86_EFLAGS_ZF;
4257 c->dst.type = OP_NONE; /* Disable writeback. */
4258 }
4259 break;
4260 }
4261 case 0xbe ... 0xbf: /* movsx */
4262 c->dst.bytes = c->op_bytes;
4263 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
4264 (s16) c->src.val;
4265 break;
4266 case 0xc0 ... 0xc1: /* xadd */
4267 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
4268 /* Write back the register source. */
4269 c->src.val = c->dst.orig_val;
4270 write_register_operand(&c->src);
4271 break;
4272 case 0xc3: /* movnti */
4273 c->dst.bytes = c->op_bytes;
4274 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
4275 (u64) c->src.val;
4276 break;
4277 case 0xc7: /* Grp9 (cmpxchg8b) */
4278 rc = emulate_grp9(ctxt, ops);
4279 break;
4280 default:
4281 goto cannot_emulate;
4282 }
4283
4284 if (rc != X86EMUL_CONTINUE)
4285 goto done;
4286
4287 goto writeback;
4288
4289 cannot_emulate:
4290 return EMULATION_FAILED;
4291 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree