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usb: musb: fix compile error
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / usb / musb / tusb6010.c
blobb410357cf0165b0f4e835caaa50add9724065d95
1 /*
2 * TUSB6010 USB 2.0 OTG Dual Role controller
3 *
4 * Copyright (C) 2006 Nokia Corporation
5 * Tony Lindgren <tony@atomide.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * Notes:
12 * - Driver assumes that interface to external host (main CPU) is
13 * configured for NOR FLASH interface instead of VLYNQ serial
14 * interface.
15 */
16
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/errno.h>
20 #include <linux/init.h>
21 #include <linux/usb.h>
22 #include <linux/irq.h>
23 #include <linux/platform_device.h>
24 #include <linux/dma-mapping.h>
25
26 #include "musb_core.h"
27
28 struct tusb6010_glue {
29 struct device *dev;
30 struct platform_device *musb;
31 };
32
33 static void tusb_musb_set_vbus(struct musb *musb, int is_on);
34
35 #define TUSB_REV_MAJOR(reg_val) ((reg_val >> 4) & 0xf)
36 #define TUSB_REV_MINOR(reg_val) (reg_val & 0xf)
37
38 /*
39 * Checks the revision. We need to use the DMA register as 3.0 does not
40 * have correct versions for TUSB_PRCM_REV or TUSB_INT_CTRL_REV.
41 */
42 u8 tusb_get_revision(struct musb *musb)
43 {
44 void __iomem *tbase = musb->ctrl_base;
45 u32 die_id;
46 u8 rev;
47
48 rev = musb_readl(tbase, TUSB_DMA_CTRL_REV) & 0xff;
49 if (TUSB_REV_MAJOR(rev) == 3) {
50 die_id = TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase,
51 TUSB_DIDR1_HI));
52 if (die_id >= TUSB_DIDR1_HI_REV_31)
53 rev |= 1;
54 }
55
56 return rev;
57 }
58
59 static int tusb_print_revision(struct musb *musb)
60 {
61 void __iomem *tbase = musb->ctrl_base;
62 u8 rev;
63
64 rev = tusb_get_revision(musb);
65
66 pr_info("tusb: %s%i.%i %s%i.%i %s%i.%i %s%i.%i %s%i %s%i.%i\n",
67 "prcm",
68 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_PRCM_REV)),
69 TUSB_REV_MINOR(musb_readl(tbase, TUSB_PRCM_REV)),
70 "int",
71 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_INT_CTRL_REV)),
72 TUSB_REV_MINOR(musb_readl(tbase, TUSB_INT_CTRL_REV)),
73 "gpio",
74 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_GPIO_REV)),
75 TUSB_REV_MINOR(musb_readl(tbase, TUSB_GPIO_REV)),
76 "dma",
77 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)),
78 TUSB_REV_MINOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)),
79 "dieid",
80 TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase, TUSB_DIDR1_HI)),
81 "rev",
82 TUSB_REV_MAJOR(rev), TUSB_REV_MINOR(rev));
83
84 return tusb_get_revision(musb);
85 }
86
87 #define WBUS_QUIRK_MASK (TUSB_PHY_OTG_CTRL_TESTM2 | TUSB_PHY_OTG_CTRL_TESTM1 \
88 | TUSB_PHY_OTG_CTRL_TESTM0)
89
90 /*
91 * Workaround for spontaneous WBUS wake-up issue #2 for tusb3.0.
92 * Disables power detection in PHY for the duration of idle.
93 */
94 static void tusb_wbus_quirk(struct musb *musb, int enabled)
95 {
96 void __iomem *tbase = musb->ctrl_base;
97 static u32 phy_otg_ctrl, phy_otg_ena;
98 u32 tmp;
99
100 if (enabled) {
101 phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
102 phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
103 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT
104 | phy_otg_ena | WBUS_QUIRK_MASK;
105 musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp);
106 tmp = phy_otg_ena & ~WBUS_QUIRK_MASK;
107 tmp |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_TESTM2;
108 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
109 dev_dbg(musb->controller, "Enabled tusb wbus quirk ctrl %08x ena %08x\n",
110 musb_readl(tbase, TUSB_PHY_OTG_CTRL),
111 musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
112 } else if (musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE)
113 & TUSB_PHY_OTG_CTRL_TESTM2) {
114 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl;
115 musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp);
116 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena;
117 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
118 dev_dbg(musb->controller, "Disabled tusb wbus quirk ctrl %08x ena %08x\n",
119 musb_readl(tbase, TUSB_PHY_OTG_CTRL),
120 musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
121 phy_otg_ctrl = 0;
122 phy_otg_ena = 0;
123 }
124 }
125
126 /*
127 * TUSB 6010 may use a parallel bus that doesn't support byte ops;
128 * so both loading and unloading FIFOs need explicit byte counts.
129 */
130
131 static inline void
132 tusb_fifo_write_unaligned(void __iomem *fifo, const u8 *buf, u16 len)
133 {
134 u32 val;
135 int i;
136
137 if (len > 4) {
138 for (i = 0; i < (len >> 2); i++) {
139 memcpy(&val, buf, 4);
140 musb_writel(fifo, 0, val);
141 buf += 4;
142 }
143 len %= 4;
144 }
145 if (len > 0) {
146 /* Write the rest 1 - 3 bytes to FIFO */
147 memcpy(&val, buf, len);
148 musb_writel(fifo, 0, val);
149 }
150 }
151
152 static inline void tusb_fifo_read_unaligned(void __iomem *fifo,
153 void __iomem *buf, u16 len)
154 {
155 u32 val;
156 int i;
157
158 if (len > 4) {
159 for (i = 0; i < (len >> 2); i++) {
160 val = musb_readl(fifo, 0);
161 memcpy(buf, &val, 4);
162 buf += 4;
163 }
164 len %= 4;
165 }
166 if (len > 0) {
167 /* Read the rest 1 - 3 bytes from FIFO */
168 val = musb_readl(fifo, 0);
169 memcpy(buf, &val, len);
170 }
171 }
172
173 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *buf)
174 {
175 struct musb *musb = hw_ep->musb;
176 void __iomem *ep_conf = hw_ep->conf;
177 void __iomem *fifo = hw_ep->fifo;
178 u8 epnum = hw_ep->epnum;
179
180 prefetch(buf);
181
182 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
183 'T', epnum, fifo, len, buf);
184
185 if (epnum)
186 musb_writel(ep_conf, TUSB_EP_TX_OFFSET,
187 TUSB_EP_CONFIG_XFR_SIZE(len));
188 else
189 musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_DIR_TX |
190 TUSB_EP0_CONFIG_XFR_SIZE(len));
191
192 if (likely((0x01 & (unsigned long) buf) == 0)) {
193
194 /* Best case is 32bit-aligned destination address */
195 if ((0x02 & (unsigned long) buf) == 0) {
196 if (len >= 4) {
197 writesl(fifo, buf, len >> 2);
198 buf += (len & ~0x03);
199 len &= 0x03;
200 }
201 } else {
202 if (len >= 2) {
203 u32 val;
204 int i;
205
206 /* Cannot use writesw, fifo is 32-bit */
207 for (i = 0; i < (len >> 2); i++) {
208 val = (u32)(*(u16 *)buf);
209 buf += 2;
210 val |= (*(u16 *)buf) << 16;
211 buf += 2;
212 musb_writel(fifo, 0, val);
213 }
214 len &= 0x03;
215 }
216 }
217 }
218
219 if (len > 0)
220 tusb_fifo_write_unaligned(fifo, buf, len);
221 }
222
223 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *buf)
224 {
225 struct musb *musb = hw_ep->musb;
226 void __iomem *ep_conf = hw_ep->conf;
227 void __iomem *fifo = hw_ep->fifo;
228 u8 epnum = hw_ep->epnum;
229
230 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
231 'R', epnum, fifo, len, buf);
232
233 if (epnum)
234 musb_writel(ep_conf, TUSB_EP_RX_OFFSET,
235 TUSB_EP_CONFIG_XFR_SIZE(len));
236 else
237 musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_XFR_SIZE(len));
238
239 if (likely((0x01 & (unsigned long) buf) == 0)) {
240
241 /* Best case is 32bit-aligned destination address */
242 if ((0x02 & (unsigned long) buf) == 0) {
243 if (len >= 4) {
244 readsl(fifo, buf, len >> 2);
245 buf += (len & ~0x03);
246 len &= 0x03;
247 }
248 } else {
249 if (len >= 2) {
250 u32 val;
251 int i;
252
253 /* Cannot use readsw, fifo is 32-bit */
254 for (i = 0; i < (len >> 2); i++) {
255 val = musb_readl(fifo, 0);
256 *(u16 *)buf = (u16)(val & 0xffff);
257 buf += 2;
258 *(u16 *)buf = (u16)(val >> 16);
259 buf += 2;
260 }
261 len &= 0x03;
262 }
263 }
264 }
265
266 if (len > 0)
267 tusb_fifo_read_unaligned(fifo, buf, len);
268 }
269
270 static struct musb *the_musb;
271
272 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
273
274 /* This is used by gadget drivers, and OTG transceiver logic, allowing
275 * at most mA current to be drawn from VBUS during a Default-B session
276 * (that is, while VBUS exceeds 4.4V). In Default-A (including pure host
277 * mode), or low power Default-B sessions, something else supplies power.
278 * Caller must take care of locking.
279 */
280 static int tusb_draw_power(struct otg_transceiver *x, unsigned mA)
281 {
282 struct musb *musb = the_musb;
283 void __iomem *tbase = musb->ctrl_base;
284 u32 reg;
285
286 /* tps65030 seems to consume max 100mA, with maybe 60mA available
287 * (measured on one board) for things other than tps and tusb.
288 *
289 * Boards sharing the CPU clock with CLKIN will need to prevent
290 * certain idle sleep states while the USB link is active.
291 *
292 * REVISIT we could use VBUS to supply only _one_ of { 1.5V, 3.3V }.
293 * The actual current usage would be very board-specific. For now,
294 * it's simpler to just use an aggregate (also board-specific).
295 */
296 if (x->default_a || mA < (musb->min_power << 1))
297 mA = 0;
298
299 reg = musb_readl(tbase, TUSB_PRCM_MNGMT);
300 if (mA) {
301 musb->is_bus_powered = 1;
302 reg |= TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN;
303 } else {
304 musb->is_bus_powered = 0;
305 reg &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN);
306 }
307 musb_writel(tbase, TUSB_PRCM_MNGMT, reg);
308
309 dev_dbg(musb->controller, "draw max %d mA VBUS\n", mA);
310 return 0;
311 }
312
313 #else
314 #define tusb_draw_power NULL
315 #endif
316
317 /* workaround for issue 13: change clock during chip idle
318 * (to be fixed in rev3 silicon) ... symptoms include disconnect
319 * or looping suspend/resume cycles
320 */
321 static void tusb_set_clock_source(struct musb *musb, unsigned mode)
322 {
323 void __iomem *tbase = musb->ctrl_base;
324 u32 reg;
325
326 reg = musb_readl(tbase, TUSB_PRCM_CONF);
327 reg &= ~TUSB_PRCM_CONF_SYS_CLKSEL(0x3);
328
329 /* 0 = refclk (clkin, XI)
330 * 1 = PHY 60 MHz (internal PLL)
331 * 2 = not supported
332 * 3 = what?
333 */
334 if (mode > 0)
335 reg |= TUSB_PRCM_CONF_SYS_CLKSEL(mode & 0x3);
336
337 musb_writel(tbase, TUSB_PRCM_CONF, reg);
338
339 /* FIXME tusb6010_platform_retime(mode == 0); */
340 }
341
342 /*
343 * Idle TUSB6010 until next wake-up event; NOR access always wakes.
344 * Other code ensures that we idle unless we're connected _and_ the
345 * USB link is not suspended ... and tells us the relevant wakeup
346 * events. SW_EN for voltage is handled separately.
347 */
348 static void tusb_allow_idle(struct musb *musb, u32 wakeup_enables)
349 {
350 void __iomem *tbase = musb->ctrl_base;
351 u32 reg;
352
353 if ((wakeup_enables & TUSB_PRCM_WBUS)
354 && (tusb_get_revision(musb) == TUSB_REV_30))
355 tusb_wbus_quirk(musb, 1);
356
357 tusb_set_clock_source(musb, 0);
358
359 wakeup_enables |= TUSB_PRCM_WNORCS;
360 musb_writel(tbase, TUSB_PRCM_WAKEUP_MASK, ~wakeup_enables);
361
362 /* REVISIT writeup of WID implies that if WID set and ID is grounded,
363 * TUSB_PHY_OTG_CTRL.TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP must be cleared.
364 * Presumably that's mostly to save power, hence WID is immaterial ...
365 */
366
367 reg = musb_readl(tbase, TUSB_PRCM_MNGMT);
368 /* issue 4: when driving vbus, use hipower (vbus_det) comparator */
369 if (is_host_active(musb)) {
370 reg |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
371 reg &= ~TUSB_PRCM_MNGMT_OTG_SESS_END_EN;
372 } else {
373 reg |= TUSB_PRCM_MNGMT_OTG_SESS_END_EN;
374 reg &= ~TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
375 }
376 reg |= TUSB_PRCM_MNGMT_PM_IDLE | TUSB_PRCM_MNGMT_DEV_IDLE;
377 musb_writel(tbase, TUSB_PRCM_MNGMT, reg);
378
379 dev_dbg(musb->controller, "idle, wake on %02x\n", wakeup_enables);
380 }
381
382 /*
383 * Updates cable VBUS status. Caller must take care of locking.
384 */
385 static int tusb_musb_vbus_status(struct musb *musb)
386 {
387 void __iomem *tbase = musb->ctrl_base;
388 u32 otg_stat, prcm_mngmt;
389 int ret = 0;
390
391 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
392 prcm_mngmt = musb_readl(tbase, TUSB_PRCM_MNGMT);
393
394 /* Temporarily enable VBUS detection if it was disabled for
395 * suspend mode. Unless it's enabled otg_stat and devctl will
396 * not show correct VBUS state.
397 */
398 if (!(prcm_mngmt & TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN)) {
399 u32 tmp = prcm_mngmt;
400 tmp |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
401 musb_writel(tbase, TUSB_PRCM_MNGMT, tmp);
402 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
403 musb_writel(tbase, TUSB_PRCM_MNGMT, prcm_mngmt);
404 }
405
406 if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID)
407 ret = 1;
408
409 return ret;
410 }
411
412 static struct timer_list musb_idle_timer;
413
414 static void musb_do_idle(unsigned long _musb)
415 {
416 struct musb *musb = (void *)_musb;
417 unsigned long flags;
418
419 spin_lock_irqsave(&musb->lock, flags);
420
421 switch (musb->xceiv->state) {
422 case OTG_STATE_A_WAIT_BCON:
423 if ((musb->a_wait_bcon != 0)
424 && (musb->idle_timeout == 0
425 || time_after(jiffies, musb->idle_timeout))) {
426 dev_dbg(musb->controller, "Nothing connected %s, turning off VBUS\n",
427 otg_state_string(musb->xceiv->state));
428 }
429 /* FALLTHROUGH */
430 case OTG_STATE_A_IDLE:
431 tusb_musb_set_vbus(musb, 0);
432 default:
433 break;
434 }
435
436 if (!musb->is_active) {
437 u32 wakeups;
438
439 /* wait until khubd handles port change status */
440 if (is_host_active(musb) && (musb->port1_status >> 16))
441 goto done;
442
443 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
444 if (is_peripheral_enabled(musb) && !musb->gadget_driver)
445 wakeups = 0;
446 else {
447 wakeups = TUSB_PRCM_WHOSTDISCON
448 | TUSB_PRCM_WBUS
449 | TUSB_PRCM_WVBUS;
450 if (is_otg_enabled(musb))
451 wakeups |= TUSB_PRCM_WID;
452 }
453 #else
454 wakeups = TUSB_PRCM_WHOSTDISCON | TUSB_PRCM_WBUS;
455 #endif
456 tusb_allow_idle(musb, wakeups);
457 }
458 done:
459 spin_unlock_irqrestore(&musb->lock, flags);
460 }
461
462 /*
463 * Maybe put TUSB6010 into idle mode mode depending on USB link status,
464 * like "disconnected" or "suspended". We'll be woken out of it by
465 * connect, resume, or disconnect.
466 *
467 * Needs to be called as the last function everywhere where there is
468 * register access to TUSB6010 because of NOR flash wake-up.
469 * Caller should own controller spinlock.
470 *
471 * Delay because peripheral enables D+ pullup 3msec after SE0, and
472 * we don't want to treat that full speed J as a wakeup event.
473 * ... peripherals must draw only suspend current after 10 msec.
474 */
475 static void tusb_musb_try_idle(struct musb *musb, unsigned long timeout)
476 {
477 unsigned long default_timeout = jiffies + msecs_to_jiffies(3);
478 static unsigned long last_timer;
479
480 if (timeout == 0)
481 timeout = default_timeout;
482
483 /* Never idle if active, or when VBUS timeout is not set as host */
484 if (musb->is_active || ((musb->a_wait_bcon == 0)
485 && (musb->xceiv->state == OTG_STATE_A_WAIT_BCON))) {
486 dev_dbg(musb->controller, "%s active, deleting timer\n",
487 otg_state_string(musb->xceiv->state));
488 del_timer(&musb_idle_timer);
489 last_timer = jiffies;
490 return;
491 }
492
493 if (time_after(last_timer, timeout)) {
494 if (!timer_pending(&musb_idle_timer))
495 last_timer = timeout;
496 else {
497 dev_dbg(musb->controller, "Longer idle timer already pending, ignoring\n");
498 return;
499 }
500 }
501 last_timer = timeout;
502
503 dev_dbg(musb->controller, "%s inactive, for idle timer for %lu ms\n",
504 otg_state_string(musb->xceiv->state),
505 (unsigned long)jiffies_to_msecs(timeout - jiffies));
506 mod_timer(&musb_idle_timer, timeout);
507 }
508
509 /* ticks of 60 MHz clock */
510 #define DEVCLOCK 60000000
511 #define OTG_TIMER_MS(msecs) ((msecs) \
512 ? (TUSB_DEV_OTG_TIMER_VAL((DEVCLOCK/1000)*(msecs)) \
513 | TUSB_DEV_OTG_TIMER_ENABLE) \
514 : 0)
515
516 static void tusb_musb_set_vbus(struct musb *musb, int is_on)
517 {
518 void __iomem *tbase = musb->ctrl_base;
519 u32 conf, prcm, timer;
520 u8 devctl;
521
522 /* HDRC controls CPEN, but beware current surges during device
523 * connect. They can trigger transient overcurrent conditions
524 * that must be ignored.
525 */
526
527 prcm = musb_readl(tbase, TUSB_PRCM_MNGMT);
528 conf = musb_readl(tbase, TUSB_DEV_CONF);
529 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
530
531 if (is_on) {
532 timer = OTG_TIMER_MS(OTG_TIME_A_WAIT_VRISE);
533 musb->xceiv->default_a = 1;
534 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
535 devctl |= MUSB_DEVCTL_SESSION;
536
537 conf |= TUSB_DEV_CONF_USB_HOST_MODE;
538 MUSB_HST_MODE(musb);
539 } else {
540 u32 otg_stat;
541
542 timer = 0;
543
544 /* If ID pin is grounded, we want to be a_idle */
545 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
546 if (!(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS)) {
547 switch (musb->xceiv->state) {
548 case OTG_STATE_A_WAIT_VRISE:
549 case OTG_STATE_A_WAIT_BCON:
550 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
551 break;
552 case OTG_STATE_A_WAIT_VFALL:
553 musb->xceiv->state = OTG_STATE_A_IDLE;
554 break;
555 default:
556 musb->xceiv->state = OTG_STATE_A_IDLE;
557 }
558 musb->is_active = 0;
559 musb->xceiv->default_a = 1;
560 MUSB_HST_MODE(musb);
561 } else {
562 musb->is_active = 0;
563 musb->xceiv->default_a = 0;
564 musb->xceiv->state = OTG_STATE_B_IDLE;
565 MUSB_DEV_MODE(musb);
566 }
567
568 devctl &= ~MUSB_DEVCTL_SESSION;
569 conf &= ~TUSB_DEV_CONF_USB_HOST_MODE;
570 }
571 prcm &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN);
572
573 musb_writel(tbase, TUSB_PRCM_MNGMT, prcm);
574 musb_writel(tbase, TUSB_DEV_OTG_TIMER, timer);
575 musb_writel(tbase, TUSB_DEV_CONF, conf);
576 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
577
578 dev_dbg(musb->controller, "VBUS %s, devctl %02x otg %3x conf %08x prcm %08x\n",
579 otg_state_string(musb->xceiv->state),
580 musb_readb(musb->mregs, MUSB_DEVCTL),
581 musb_readl(tbase, TUSB_DEV_OTG_STAT),
582 conf, prcm);
583 }
584
585 /*
586 * Sets the mode to OTG, peripheral or host by changing the ID detection.
587 * Caller must take care of locking.
588 *
589 * Note that if a mini-A cable is plugged in the ID line will stay down as
590 * the weak ID pull-up is not able to pull the ID up.
591 *
592 * REVISIT: It would be possible to add support for changing between host
593 * and peripheral modes in non-OTG configurations by reconfiguring hardware
594 * and then setting musb->board_mode. For now, only support OTG mode.
595 */
596 static int tusb_musb_set_mode(struct musb *musb, u8 musb_mode)
597 {
598 void __iomem *tbase = musb->ctrl_base;
599 u32 otg_stat, phy_otg_ctrl, phy_otg_ena, dev_conf;
600
601 if (musb->board_mode != MUSB_OTG) {
602 ERR("Changing mode currently only supported in OTG mode\n");
603 return -EINVAL;
604 }
605
606 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
607 phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
608 phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
609 dev_conf = musb_readl(tbase, TUSB_DEV_CONF);
610
611 switch (musb_mode) {
612
613 #ifdef CONFIG_USB_MUSB_HDRC_HCD
614 case MUSB_HOST: /* Disable PHY ID detect, ground ID */
615 phy_otg_ctrl &= ~TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
616 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
617 dev_conf |= TUSB_DEV_CONF_ID_SEL;
618 dev_conf &= ~TUSB_DEV_CONF_SOFT_ID;
619 break;
620 #endif
621
622 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
623 case MUSB_PERIPHERAL: /* Disable PHY ID detect, keep ID pull-up on */
624 phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
625 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
626 dev_conf |= (TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID);
627 break;
628 #endif
629
630 #ifdef CONFIG_USB_MUSB_OTG
631 case MUSB_OTG: /* Use PHY ID detection */
632 phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
633 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
634 dev_conf &= ~(TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID);
635 break;
636 #endif
637
638 default:
639 dev_dbg(musb->controller, "Trying to set mode %i\n", musb_mode);
640 return -EINVAL;
641 }
642
643 musb_writel(tbase, TUSB_PHY_OTG_CTRL,
644 TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl);
645 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE,
646 TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena);
647 musb_writel(tbase, TUSB_DEV_CONF, dev_conf);
648
649 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
650 if ((musb_mode == MUSB_PERIPHERAL) &&
651 !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS))
652 INFO("Cannot be peripheral with mini-A cable "
653 "otg_stat: %08x\n", otg_stat);
654
655 return 0;
656 }
657
658 static inline unsigned long
659 tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase)
660 {
661 u32 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
662 unsigned long idle_timeout = 0;
663
664 /* ID pin */
665 if ((int_src & TUSB_INT_SRC_ID_STATUS_CHNG)) {
666 int default_a;
667
668 if (is_otg_enabled(musb))
669 default_a = !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS);
670 else
671 default_a = is_host_enabled(musb);
672 dev_dbg(musb->controller, "Default-%c\n", default_a ? 'A' : 'B');
673 musb->xceiv->default_a = default_a;
674 tusb_musb_set_vbus(musb, default_a);
675
676 /* Don't allow idling immediately */
677 if (default_a)
678 idle_timeout = jiffies + (HZ * 3);
679 }
680
681 /* VBUS state change */
682 if (int_src & TUSB_INT_SRC_VBUS_SENSE_CHNG) {
683
684 /* B-dev state machine: no vbus ~= disconnect */
685 if ((is_otg_enabled(musb) && !musb->xceiv->default_a)
686 || !is_host_enabled(musb)) {
687 #ifdef CONFIG_USB_MUSB_HDRC_HCD
688 /* ? musb_root_disconnect(musb); */
689 musb->port1_status &=
690 ~(USB_PORT_STAT_CONNECTION
691 | USB_PORT_STAT_ENABLE
692 | USB_PORT_STAT_LOW_SPEED
693 | USB_PORT_STAT_HIGH_SPEED
694 | USB_PORT_STAT_TEST
695 );
696 #endif
697
698 if (otg_stat & TUSB_DEV_OTG_STAT_SESS_END) {
699 dev_dbg(musb->controller, "Forcing disconnect (no interrupt)\n");
700 if (musb->xceiv->state != OTG_STATE_B_IDLE) {
701 /* INTR_DISCONNECT can hide... */
702 musb->xceiv->state = OTG_STATE_B_IDLE;
703 musb->int_usb |= MUSB_INTR_DISCONNECT;
704 }
705 musb->is_active = 0;
706 }
707 dev_dbg(musb->controller, "vbus change, %s, otg %03x\n",
708 otg_state_string(musb->xceiv->state), otg_stat);
709 idle_timeout = jiffies + (1 * HZ);
710 schedule_work(&musb->irq_work);
711
712 } else /* A-dev state machine */ {
713 dev_dbg(musb->controller, "vbus change, %s, otg %03x\n",
714 otg_state_string(musb->xceiv->state), otg_stat);
715
716 switch (musb->xceiv->state) {
717 case OTG_STATE_A_IDLE:
718 dev_dbg(musb->controller, "Got SRP, turning on VBUS\n");
719 musb_platform_set_vbus(musb, 1);
720
721 /* CONNECT can wake if a_wait_bcon is set */
722 if (musb->a_wait_bcon != 0)
723 musb->is_active = 0;
724 else
725 musb->is_active = 1;
726
727 /*
728 * OPT FS A TD.4.6 needs few seconds for
729 * A_WAIT_VRISE
730 */
731 idle_timeout = jiffies + (2 * HZ);
732
733 break;
734 case OTG_STATE_A_WAIT_VRISE:
735 /* ignore; A-session-valid < VBUS_VALID/2,
736 * we monitor this with the timer
737 */
738 break;
739 case OTG_STATE_A_WAIT_VFALL:
740 /* REVISIT this irq triggers during short
741 * spikes caused by enumeration ...
742 */
743 if (musb->vbuserr_retry) {
744 musb->vbuserr_retry--;
745 tusb_musb_set_vbus(musb, 1);
746 } else {
747 musb->vbuserr_retry
748 = VBUSERR_RETRY_COUNT;
749 tusb_musb_set_vbus(musb, 0);
750 }
751 break;
752 default:
753 break;
754 }
755 }
756 }
757
758 /* OTG timer expiration */
759 if (int_src & TUSB_INT_SRC_OTG_TIMEOUT) {
760 u8 devctl;
761
762 dev_dbg(musb->controller, "%s timer, %03x\n",
763 otg_state_string(musb->xceiv->state), otg_stat);
764
765 switch (musb->xceiv->state) {
766 case OTG_STATE_A_WAIT_VRISE:
767 /* VBUS has probably been valid for a while now,
768 * but may well have bounced out of range a bit
769 */
770 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
771 if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID) {
772 if ((devctl & MUSB_DEVCTL_VBUS)
773 != MUSB_DEVCTL_VBUS) {
774 dev_dbg(musb->controller, "devctl %02x\n", devctl);
775 break;
776 }
777 musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
778 musb->is_active = 0;
779 idle_timeout = jiffies
780 + msecs_to_jiffies(musb->a_wait_bcon);
781 } else {
782 /* REVISIT report overcurrent to hub? */
783 ERR("vbus too slow, devctl %02x\n", devctl);
784 tusb_musb_set_vbus(musb, 0);
785 }
786 break;
787 case OTG_STATE_A_WAIT_BCON:
788 if (musb->a_wait_bcon != 0)
789 idle_timeout = jiffies
790 + msecs_to_jiffies(musb->a_wait_bcon);
791 break;
792 case OTG_STATE_A_SUSPEND:
793 break;
794 case OTG_STATE_B_WAIT_ACON:
795 break;
796 default:
797 break;
798 }
799 }
800 schedule_work(&musb->irq_work);
801
802 return idle_timeout;
803 }
804
805 static irqreturn_t tusb_musb_interrupt(int irq, void *__hci)
806 {
807 struct musb *musb = __hci;
808 void __iomem *tbase = musb->ctrl_base;
809 unsigned long flags, idle_timeout = 0;
810 u32 int_mask, int_src;
811
812 spin_lock_irqsave(&musb->lock, flags);
813
814 /* Mask all interrupts to allow using both edge and level GPIO irq */
815 int_mask = musb_readl(tbase, TUSB_INT_MASK);
816 musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS);
817
818 int_src = musb_readl(tbase, TUSB_INT_SRC) & ~TUSB_INT_SRC_RESERVED_BITS;
819 dev_dbg(musb->controller, "TUSB IRQ %08x\n", int_src);
820
821 musb->int_usb = (u8) int_src;
822
823 /* Acknowledge wake-up source interrupts */
824 if (int_src & TUSB_INT_SRC_DEV_WAKEUP) {
825 u32 reg;
826 u32 i;
827
828 if (tusb_get_revision(musb) == TUSB_REV_30)
829 tusb_wbus_quirk(musb, 0);
830
831 /* there are issues re-locking the PLL on wakeup ... */
832
833 /* work around issue 8 */
834 for (i = 0xf7f7f7; i > 0xf7f7f7 - 1000; i--) {
835 musb_writel(tbase, TUSB_SCRATCH_PAD, 0);
836 musb_writel(tbase, TUSB_SCRATCH_PAD, i);
837 reg = musb_readl(tbase, TUSB_SCRATCH_PAD);
838 if (reg == i)
839 break;
840 dev_dbg(musb->controller, "TUSB NOR not ready\n");
841 }
842
843 /* work around issue 13 (2nd half) */
844 tusb_set_clock_source(musb, 1);
845
846 reg = musb_readl(tbase, TUSB_PRCM_WAKEUP_SOURCE);
847 musb_writel(tbase, TUSB_PRCM_WAKEUP_CLEAR, reg);
848 if (reg & ~TUSB_PRCM_WNORCS) {
849 musb->is_active = 1;
850 schedule_work(&musb->irq_work);
851 }
852 dev_dbg(musb->controller, "wake %sactive %02x\n",
853 musb->is_active ? "" : "in", reg);
854
855 /* REVISIT host side TUSB_PRCM_WHOSTDISCON, TUSB_PRCM_WBUS */
856 }
857
858 if (int_src & TUSB_INT_SRC_USB_IP_CONN)
859 del_timer(&musb_idle_timer);
860
861 /* OTG state change reports (annoyingly) not issued by Mentor core */
862 if (int_src & (TUSB_INT_SRC_VBUS_SENSE_CHNG
863 | TUSB_INT_SRC_OTG_TIMEOUT
864 | TUSB_INT_SRC_ID_STATUS_CHNG))
865 idle_timeout = tusb_otg_ints(musb, int_src, tbase);
866
867 /* TX dma callback must be handled here, RX dma callback is
868 * handled in tusb_omap_dma_cb.
869 */
870 if ((int_src & TUSB_INT_SRC_TXRX_DMA_DONE)) {
871 u32 dma_src = musb_readl(tbase, TUSB_DMA_INT_SRC);
872 u32 real_dma_src = musb_readl(tbase, TUSB_DMA_INT_MASK);
873
874 dev_dbg(musb->controller, "DMA IRQ %08x\n", dma_src);
875 real_dma_src = ~real_dma_src & dma_src;
876 if (tusb_dma_omap() && real_dma_src) {
877 int tx_source = (real_dma_src & 0xffff);
878 int i;
879
880 for (i = 1; i <= 15; i++) {
881 if (tx_source & (1 << i)) {
882 dev_dbg(musb->controller, "completing ep%i %s\n", i, "tx");
883 musb_dma_completion(musb, i, 1);
884 }
885 }
886 }
887 musb_writel(tbase, TUSB_DMA_INT_CLEAR, dma_src);
888 }
889
890 /* EP interrupts. In OCP mode tusb6010 mirrors the MUSB interrupts */
891 if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX)) {
892 u32 musb_src = musb_readl(tbase, TUSB_USBIP_INT_SRC);
893
894 musb_writel(tbase, TUSB_USBIP_INT_CLEAR, musb_src);
895 musb->int_rx = (((musb_src >> 16) & 0xffff) << 1);
896 musb->int_tx = (musb_src & 0xffff);
897 } else {
898 musb->int_rx = 0;
899 musb->int_tx = 0;
900 }
901
902 if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX | 0xff))
903 musb_interrupt(musb);
904
905 /* Acknowledge TUSB interrupts. Clear only non-reserved bits */
906 musb_writel(tbase, TUSB_INT_SRC_CLEAR,
907 int_src & ~TUSB_INT_MASK_RESERVED_BITS);
908
909 tusb_musb_try_idle(musb, idle_timeout);
910
911 musb_writel(tbase, TUSB_INT_MASK, int_mask);
912 spin_unlock_irqrestore(&musb->lock, flags);
913
914 return IRQ_HANDLED;
915 }
916
917 static int dma_off;
918
919 /*
920 * Enables TUSB6010. Caller must take care of locking.
921 * REVISIT:
922 * - Check what is unnecessary in MGC_HdrcStart()
923 */
924 static void tusb_musb_enable(struct musb *musb)
925 {
926 void __iomem *tbase = musb->ctrl_base;
927
928 /* Setup TUSB6010 main interrupt mask. Enable all interrupts except SOF.
929 * REVISIT: Enable and deal with TUSB_INT_SRC_USB_IP_SOF */
930 musb_writel(tbase, TUSB_INT_MASK, TUSB_INT_SRC_USB_IP_SOF);
931
932 /* Setup TUSB interrupt, disable DMA and GPIO interrupts */
933 musb_writel(tbase, TUSB_USBIP_INT_MASK, 0);
934 musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff);
935 musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff);
936
937 /* Clear all subsystem interrups */
938 musb_writel(tbase, TUSB_USBIP_INT_CLEAR, 0x7fffffff);
939 musb_writel(tbase, TUSB_DMA_INT_CLEAR, 0x7fffffff);
940 musb_writel(tbase, TUSB_GPIO_INT_CLEAR, 0x1ff);
941
942 /* Acknowledge pending interrupt(s) */
943 musb_writel(tbase, TUSB_INT_SRC_CLEAR, ~TUSB_INT_MASK_RESERVED_BITS);
944
945 /* Only 0 clock cycles for minimum interrupt de-assertion time and
946 * interrupt polarity active low seems to work reliably here */
947 musb_writel(tbase, TUSB_INT_CTRL_CONF,
948 TUSB_INT_CTRL_CONF_INT_RELCYC(0));
949
950 irq_set_irq_type(musb->nIrq, IRQ_TYPE_LEVEL_LOW);
951
952 /* maybe force into the Default-A OTG state machine */
953 if (!(musb_readl(tbase, TUSB_DEV_OTG_STAT)
954 & TUSB_DEV_OTG_STAT_ID_STATUS))
955 musb_writel(tbase, TUSB_INT_SRC_SET,
956 TUSB_INT_SRC_ID_STATUS_CHNG);
957
958 if (is_dma_capable() && dma_off)
959 printk(KERN_WARNING "%s %s: dma not reactivated\n",
960 __FILE__, __func__);
961 else
962 dma_off = 1;
963 }
964
965 /*
966 * Disables TUSB6010. Caller must take care of locking.
967 */
968 static void tusb_musb_disable(struct musb *musb)
969 {
970 void __iomem *tbase = musb->ctrl_base;
971
972 /* FIXME stop DMA, IRQs, timers, ... */
973
974 /* disable all IRQs */
975 musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS);
976 musb_writel(tbase, TUSB_USBIP_INT_MASK, 0x7fffffff);
977 musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff);
978 musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff);
979
980 del_timer(&musb_idle_timer);
981
982 if (is_dma_capable() && !dma_off) {
983 printk(KERN_WARNING "%s %s: dma still active\n",
984 __FILE__, __func__);
985 dma_off = 1;
986 }
987 }
988
989 /*
990 * Sets up TUSB6010 CPU interface specific signals and registers
991 * Note: Settings optimized for OMAP24xx
992 */
993 static void tusb_setup_cpu_interface(struct musb *musb)
994 {
995 void __iomem *tbase = musb->ctrl_base;
996
997 /*
998 * Disable GPIO[5:0] pullups (used as output DMA requests)
999 * Don't disable GPIO[7:6] as they are needed for wake-up.
1000 */
1001 musb_writel(tbase, TUSB_PULLUP_1_CTRL, 0x0000003F);
1002
1003 /* Disable all pullups on NOR IF, DMAREQ0 and DMAREQ1 */
1004 musb_writel(tbase, TUSB_PULLUP_2_CTRL, 0x01FFFFFF);
1005
1006 /* Turn GPIO[5:0] to DMAREQ[5:0] signals */
1007 musb_writel(tbase, TUSB_GPIO_CONF, TUSB_GPIO_CONF_DMAREQ(0x3f));
1008
1009 /* Burst size 16x16 bits, all six DMA requests enabled, DMA request
1010 * de-assertion time 2 system clocks p 62 */
1011 musb_writel(tbase, TUSB_DMA_REQ_CONF,
1012 TUSB_DMA_REQ_CONF_BURST_SIZE(2) |
1013 TUSB_DMA_REQ_CONF_DMA_REQ_EN(0x3f) |
1014 TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(2));
1015
1016 /* Set 0 wait count for synchronous burst access */
1017 musb_writel(tbase, TUSB_WAIT_COUNT, 1);
1018 }
1019
1020 static int tusb_musb_start(struct musb *musb)
1021 {
1022 void __iomem *tbase = musb->ctrl_base;
1023 int ret = 0;
1024 unsigned long flags;
1025 u32 reg;
1026
1027 if (musb->board_set_power)
1028 ret = musb->board_set_power(1);
1029 if (ret != 0) {
1030 printk(KERN_ERR "tusb: Cannot enable TUSB6010\n");
1031 return ret;
1032 }
1033
1034 spin_lock_irqsave(&musb->lock, flags);
1035
1036 if (musb_readl(tbase, TUSB_PROD_TEST_RESET) !=
1037 TUSB_PROD_TEST_RESET_VAL) {
1038 printk(KERN_ERR "tusb: Unable to detect TUSB6010\n");
1039 goto err;
1040 }
1041
1042 ret = tusb_print_revision(musb);
1043 if (ret < 2) {
1044 printk(KERN_ERR "tusb: Unsupported TUSB6010 revision %i\n",
1045 ret);
1046 goto err;
1047 }
1048
1049 /* The uint bit for "USB non-PDR interrupt enable" has to be 1 when
1050 * NOR FLASH interface is used */
1051 musb_writel(tbase, TUSB_VLYNQ_CTRL, 8);
1052
1053 /* Select PHY free running 60MHz as a system clock */
1054 tusb_set_clock_source(musb, 1);
1055
1056 /* VBus valid timer 1us, disable DFT/Debug and VLYNQ clocks for
1057 * power saving, enable VBus detect and session end comparators,
1058 * enable IDpullup, enable VBus charging */
1059 musb_writel(tbase, TUSB_PRCM_MNGMT,
1060 TUSB_PRCM_MNGMT_VBUS_VALID_TIMER(0xa) |
1061 TUSB_PRCM_MNGMT_VBUS_VALID_FLT_EN |
1062 TUSB_PRCM_MNGMT_OTG_SESS_END_EN |
1063 TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN |
1064 TUSB_PRCM_MNGMT_OTG_ID_PULLUP);
1065 tusb_setup_cpu_interface(musb);
1066
1067 /* simplify: always sense/pullup ID pins, as if in OTG mode */
1068 reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
1069 reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
1070 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, reg);
1071
1072 reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
1073 reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
1074 musb_writel(tbase, TUSB_PHY_OTG_CTRL, reg);
1075
1076 spin_unlock_irqrestore(&musb->lock, flags);
1077
1078 return 0;
1079
1080 err:
1081 spin_unlock_irqrestore(&musb->lock, flags);
1082
1083 if (musb->board_set_power)
1084 musb->board_set_power(0);
1085
1086 return -ENODEV;
1087 }
1088
1089 static int tusb_musb_init(struct musb *musb)
1090 {
1091 struct platform_device *pdev;
1092 struct resource *mem;
1093 void __iomem *sync = NULL;
1094 int ret;
1095
1096 usb_nop_xceiv_register();
1097 musb->xceiv = otg_get_transceiver();
1098 if (!musb->xceiv)
1099 return -ENODEV;
1100
1101 pdev = to_platform_device(musb->controller);
1102
1103 /* dma address for async dma */
1104 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1105 musb->async = mem->start;
1106
1107 /* dma address for sync dma */
1108 mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1109 if (!mem) {
1110 pr_debug("no sync dma resource?\n");
1111 ret = -ENODEV;
1112 goto done;
1113 }
1114 musb->sync = mem->start;
1115
1116 sync = ioremap(mem->start, resource_size(mem));
1117 if (!sync) {
1118 pr_debug("ioremap for sync failed\n");
1119 ret = -ENOMEM;
1120 goto done;
1121 }
1122 musb->sync_va = sync;
1123
1124 /* Offsets from base: VLYNQ at 0x000, MUSB regs at 0x400,
1125 * FIFOs at 0x600, TUSB at 0x800
1126 */
1127 musb->mregs += TUSB_BASE_OFFSET;
1128
1129 ret = tusb_musb_start(musb);
1130 if (ret) {
1131 printk(KERN_ERR "Could not start tusb6010 (%d)\n",
1132 ret);
1133 goto done;
1134 }
1135 musb->isr = tusb_musb_interrupt;
1136
1137 if (is_peripheral_enabled(musb)) {
1138 musb->xceiv->set_power = tusb_draw_power;
1139 the_musb = musb;
1140 }
1141
1142 setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb);
1143
1144 done:
1145 if (ret < 0) {
1146 if (sync)
1147 iounmap(sync);
1148
1149 otg_put_transceiver(musb->xceiv);
1150 usb_nop_xceiv_unregister();
1151 }
1152 return ret;
1153 }
1154
1155 static int tusb_musb_exit(struct musb *musb)
1156 {
1157 del_timer_sync(&musb_idle_timer);
1158 the_musb = NULL;
1159
1160 if (musb->board_set_power)
1161 musb->board_set_power(0);
1162
1163 iounmap(musb->sync_va);
1164
1165 otg_put_transceiver(musb->xceiv);
1166 usb_nop_xceiv_unregister();
1167 return 0;
1168 }
1169
1170 static const struct musb_platform_ops tusb_ops = {
1171 .init = tusb_musb_init,
1172 .exit = tusb_musb_exit,
1173
1174 .enable = tusb_musb_enable,
1175 .disable = tusb_musb_disable,
1176
1177 .set_mode = tusb_musb_set_mode,
1178 .try_idle = tusb_musb_try_idle,
1179
1180 .vbus_status = tusb_musb_vbus_status,
1181 .set_vbus = tusb_musb_set_vbus,
1182 };
1183
1184 static u64 tusb_dmamask = DMA_BIT_MASK(32);
1185
1186 static int __init tusb_probe(struct platform_device *pdev)
1187 {
1188 struct musb_hdrc_platform_data *pdata = pdev->dev.platform_data;
1189 struct platform_device *musb;
1190 struct tusb6010_glue *glue;
1191
1192 int ret = -ENOMEM;
1193
1194 glue = kzalloc(sizeof(*glue), GFP_KERNEL);
1195 if (!glue) {
1196 dev_err(&pdev->dev, "failed to allocate glue context\n");
1197 goto err0;
1198 }
1199
1200 musb = platform_device_alloc("musb-hdrc", -1);
1201 if (!musb) {
1202 dev_err(&pdev->dev, "failed to allocate musb device\n");
1203 goto err1;
1204 }
1205
1206 musb->dev.parent = &pdev->dev;
1207 musb->dev.dma_mask = &tusb_dmamask;
1208 musb->dev.coherent_dma_mask = tusb_dmamask;
1209
1210 glue->dev = &pdev->dev;
1211 glue->musb = musb;
1212
1213 pdata->platform_ops = &tusb_ops;
1214
1215 platform_set_drvdata(pdev, glue);
1216
1217 ret = platform_device_add_resources(musb, pdev->resource,
1218 pdev->num_resources);
1219 if (ret) {
1220 dev_err(&pdev->dev, "failed to add resources\n");
1221 goto err2;
1222 }
1223
1224 ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
1225 if (ret) {
1226 dev_err(&pdev->dev, "failed to add platform_data\n");
1227 goto err2;
1228 }
1229
1230 ret = platform_device_add(musb);
1231 if (ret) {
1232 dev_err(&pdev->dev, "failed to register musb device\n");
1233 goto err1;
1234 }
1235
1236 return 0;
1237
1238 err2:
1239 platform_device_put(musb);
1240
1241 err1:
1242 kfree(glue);
1243
1244 err0:
1245 return ret;
1246 }
1247
1248 static int __exit tusb_remove(struct platform_device *pdev)
1249 {
1250 struct tusb6010_glue *glue = platform_get_drvdata(pdev);
1251
1252 platform_device_del(glue->musb);
1253 platform_device_put(glue->musb);
1254 kfree(glue);
1255
1256 return 0;
1257 }
1258
1259 static struct platform_driver tusb_driver = {
1260 .remove = __exit_p(tusb_remove),
1261 .driver = {
1262 .name = "musb-tusb",
1263 },
1264 };
1265
1266 MODULE_DESCRIPTION("TUSB6010 MUSB Glue Layer");
1267 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1268 MODULE_LICENSE("GPL v2");
1269
1270 static int __init tusb_init(void)
1271 {
1272 return platform_driver_probe(&tusb_driver, tusb_probe);
1273 }
1274 subsys_initcall(tusb_init);
1275
1276 static void __exit tusb_exit(void)
1277 {
1278 platform_driver_unregister(&tusb_driver);
1279 }
1280 module_exit(tusb_exit);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree