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ASoC: Ensure we delay long enough for WM8994 FLL to lock when starting
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / sound / soc / codecs / wm8994.c
blobfece9d9696b8acb39c29ea72a5718071a6d4df0e
1 /*
2 * wm8994.c -- WM8994 ALSA SoC Audio driver
3 *
4 * Copyright 2009 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
18 #include <linux/pm.h>
19 #include <linux/i2c.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/slab.h>
24 #include <sound/core.h>
25 #include <sound/jack.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/soc.h>
29 #include <sound/initval.h>
30 #include <sound/tlv.h>
31 #include <trace/events/asoc.h>
32
33 #include <linux/mfd/wm8994/core.h>
34 #include <linux/mfd/wm8994/registers.h>
35 #include <linux/mfd/wm8994/pdata.h>
36 #include <linux/mfd/wm8994/gpio.h>
37
38 #include "wm8994.h"
39 #include "wm_hubs.h"
40
41 struct fll_config {
42 int src;
43 int in;
44 int out;
45 };
46
47 #define WM8994_NUM_DRC 3
48 #define WM8994_NUM_EQ 3
49
50 static int wm8994_drc_base[] = {
51 WM8994_AIF1_DRC1_1,
52 WM8994_AIF1_DRC2_1,
53 WM8994_AIF2_DRC_1,
54 };
55
56 static int wm8994_retune_mobile_base[] = {
57 WM8994_AIF1_DAC1_EQ_GAINS_1,
58 WM8994_AIF1_DAC2_EQ_GAINS_1,
59 WM8994_AIF2_EQ_GAINS_1,
60 };
61
62 struct wm8994_micdet {
63 struct snd_soc_jack *jack;
64 int det;
65 int shrt;
66 };
67
68 /* codec private data */
69 struct wm8994_priv {
70 struct wm_hubs_data hubs;
71 enum snd_soc_control_type control_type;
72 void *control_data;
73 struct snd_soc_codec *codec;
74 int sysclk[2];
75 int sysclk_rate[2];
76 int mclk[2];
77 int aifclk[2];
78 struct fll_config fll[2], fll_suspend[2];
79
80 int dac_rates[2];
81 int lrclk_shared[2];
82
83 int mbc_ena[3];
84
85 /* Platform dependent DRC configuration */
86 const char **drc_texts;
87 int drc_cfg[WM8994_NUM_DRC];
88 struct soc_enum drc_enum;
89
90 /* Platform dependent ReTune mobile configuration */
91 int num_retune_mobile_texts;
92 const char **retune_mobile_texts;
93 int retune_mobile_cfg[WM8994_NUM_EQ];
94 struct soc_enum retune_mobile_enum;
95
96 /* Platform dependent MBC configuration */
97 int mbc_cfg;
98 const char **mbc_texts;
99 struct soc_enum mbc_enum;
100
101 struct wm8994_micdet micdet[2];
102
103 wm8958_micdet_cb jack_cb;
104 void *jack_cb_data;
105 int micdet_irq;
106
107 int revision;
108 struct wm8994_pdata *pdata;
109
110 unsigned int aif1clk_enable:1;
111 unsigned int aif2clk_enable:1;
112
113 unsigned int aif1clk_disable:1;
114 unsigned int aif2clk_disable:1;
115 };
116
117 static int wm8994_readable(struct snd_soc_codec *codec, unsigned int reg)
118 {
119 switch (reg) {
120 case WM8994_GPIO_1:
121 case WM8994_GPIO_2:
122 case WM8994_GPIO_3:
123 case WM8994_GPIO_4:
124 case WM8994_GPIO_5:
125 case WM8994_GPIO_6:
126 case WM8994_GPIO_7:
127 case WM8994_GPIO_8:
128 case WM8994_GPIO_9:
129 case WM8994_GPIO_10:
130 case WM8994_GPIO_11:
131 case WM8994_INTERRUPT_STATUS_1:
132 case WM8994_INTERRUPT_STATUS_2:
133 case WM8994_INTERRUPT_RAW_STATUS_2:
134 return 1;
135 default:
136 break;
137 }
138
139 if (reg >= WM8994_CACHE_SIZE)
140 return 0;
141 return wm8994_access_masks[reg].readable != 0;
142 }
143
144 static int wm8994_volatile(struct snd_soc_codec *codec, unsigned int reg)
145 {
146 if (reg >= WM8994_CACHE_SIZE)
147 return 1;
148
149 switch (reg) {
150 case WM8994_SOFTWARE_RESET:
151 case WM8994_CHIP_REVISION:
152 case WM8994_DC_SERVO_1:
153 case WM8994_DC_SERVO_READBACK:
154 case WM8994_RATE_STATUS:
155 case WM8994_LDO_1:
156 case WM8994_LDO_2:
157 case WM8958_DSP2_EXECCONTROL:
158 case WM8958_MIC_DETECT_3:
159 return 1;
160 default:
161 return 0;
162 }
163 }
164
165 static int wm8994_write(struct snd_soc_codec *codec, unsigned int reg,
166 unsigned int value)
167 {
168 int ret;
169
170 BUG_ON(reg > WM8994_MAX_REGISTER);
171
172 if (!wm8994_volatile(codec, reg)) {
173 ret = snd_soc_cache_write(codec, reg, value);
174 if (ret != 0)
175 dev_err(codec->dev, "Cache write to %x failed: %d\n",
176 reg, ret);
177 }
178
179 return wm8994_reg_write(codec->control_data, reg, value);
180 }
181
182 static unsigned int wm8994_read(struct snd_soc_codec *codec,
183 unsigned int reg)
184 {
185 unsigned int val;
186 int ret;
187
188 BUG_ON(reg > WM8994_MAX_REGISTER);
189
190 if (!wm8994_volatile(codec, reg) && wm8994_readable(codec, reg) &&
191 reg < codec->driver->reg_cache_size) {
192 ret = snd_soc_cache_read(codec, reg, &val);
193 if (ret >= 0)
194 return val;
195 else
196 dev_err(codec->dev, "Cache read from %x failed: %d\n",
197 reg, ret);
198 }
199
200 return wm8994_reg_read(codec->control_data, reg);
201 }
202
203 static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
204 {
205 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
206 int rate;
207 int reg1 = 0;
208 int offset;
209
210 if (aif)
211 offset = 4;
212 else
213 offset = 0;
214
215 switch (wm8994->sysclk[aif]) {
216 case WM8994_SYSCLK_MCLK1:
217 rate = wm8994->mclk[0];
218 break;
219
220 case WM8994_SYSCLK_MCLK2:
221 reg1 |= 0x8;
222 rate = wm8994->mclk[1];
223 break;
224
225 case WM8994_SYSCLK_FLL1:
226 reg1 |= 0x10;
227 rate = wm8994->fll[0].out;
228 break;
229
230 case WM8994_SYSCLK_FLL2:
231 reg1 |= 0x18;
232 rate = wm8994->fll[1].out;
233 break;
234
235 default:
236 return -EINVAL;
237 }
238
239 if (rate >= 13500000) {
240 rate /= 2;
241 reg1 |= WM8994_AIF1CLK_DIV;
242
243 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
244 aif + 1, rate);
245 }
246
247 if (rate && rate < 3000000)
248 dev_warn(codec->dev, "AIF%dCLK is %dHz, should be >=3MHz for optimal performance\n",
249 aif + 1, rate);
250
251 wm8994->aifclk[aif] = rate;
252
253 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
254 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
255 reg1);
256
257 return 0;
258 }
259
260 static int configure_clock(struct snd_soc_codec *codec)
261 {
262 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
263 int old, new;
264
265 /* Bring up the AIF clocks first */
266 configure_aif_clock(codec, 0);
267 configure_aif_clock(codec, 1);
268
269 /* Then switch CLK_SYS over to the higher of them; a change
270 * can only happen as a result of a clocking change which can
271 * only be made outside of DAPM so we can safely redo the
272 * clocking.
273 */
274
275 /* If they're equal it doesn't matter which is used */
276 if (wm8994->aifclk[0] == wm8994->aifclk[1])
277 return 0;
278
279 if (wm8994->aifclk[0] < wm8994->aifclk[1])
280 new = WM8994_SYSCLK_SRC;
281 else
282 new = 0;
283
284 old = snd_soc_read(codec, WM8994_CLOCKING_1) & WM8994_SYSCLK_SRC;
285
286 /* If there's no change then we're done. */
287 if (old == new)
288 return 0;
289
290 snd_soc_update_bits(codec, WM8994_CLOCKING_1, WM8994_SYSCLK_SRC, new);
291
292 snd_soc_dapm_sync(&codec->dapm);
293
294 return 0;
295 }
296
297 static int check_clk_sys(struct snd_soc_dapm_widget *source,
298 struct snd_soc_dapm_widget *sink)
299 {
300 int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
301 const char *clk;
302
303 /* Check what we're currently using for CLK_SYS */
304 if (reg & WM8994_SYSCLK_SRC)
305 clk = "AIF2CLK";
306 else
307 clk = "AIF1CLK";
308
309 return strcmp(source->name, clk) == 0;
310 }
311
312 static const char *sidetone_hpf_text[] = {
313 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
314 };
315
316 static const struct soc_enum sidetone_hpf =
317 SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
318
319 static const char *adc_hpf_text[] = {
320 "HiFi", "Voice 1", "Voice 2", "Voice 3"
321 };
322
323 static const struct soc_enum aif1adc1_hpf =
324 SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text);
325
326 static const struct soc_enum aif1adc2_hpf =
327 SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text);
328
329 static const struct soc_enum aif2adc_hpf =
330 SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text);
331
332 static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
333 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
334 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
335 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
336 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
337
338 #define WM8994_DRC_SWITCH(xname, reg, shift) \
339 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
340 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
341 .put = wm8994_put_drc_sw, \
342 .private_value = SOC_SINGLE_VALUE(reg, shift, 1, 0) }
343
344 static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
345 struct snd_ctl_elem_value *ucontrol)
346 {
347 struct soc_mixer_control *mc =
348 (struct soc_mixer_control *)kcontrol->private_value;
349 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
350 int mask, ret;
351
352 /* Can't enable both ADC and DAC paths simultaneously */
353 if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
354 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
355 WM8994_AIF1ADC1R_DRC_ENA_MASK;
356 else
357 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
358
359 ret = snd_soc_read(codec, mc->reg);
360 if (ret < 0)
361 return ret;
362 if (ret & mask)
363 return -EINVAL;
364
365 return snd_soc_put_volsw(kcontrol, ucontrol);
366 }
367
368 static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
369 {
370 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
371 struct wm8994_pdata *pdata = wm8994->pdata;
372 int base = wm8994_drc_base[drc];
373 int cfg = wm8994->drc_cfg[drc];
374 int save, i;
375
376 /* Save any enables; the configuration should clear them. */
377 save = snd_soc_read(codec, base);
378 save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
379 WM8994_AIF1ADC1R_DRC_ENA;
380
381 for (i = 0; i < WM8994_DRC_REGS; i++)
382 snd_soc_update_bits(codec, base + i, 0xffff,
383 pdata->drc_cfgs[cfg].regs[i]);
384
385 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
386 WM8994_AIF1ADC1L_DRC_ENA |
387 WM8994_AIF1ADC1R_DRC_ENA, save);
388 }
389
390 /* Icky as hell but saves code duplication */
391 static int wm8994_get_drc(const char *name)
392 {
393 if (strcmp(name, "AIF1DRC1 Mode") == 0)
394 return 0;
395 if (strcmp(name, "AIF1DRC2 Mode") == 0)
396 return 1;
397 if (strcmp(name, "AIF2DRC Mode") == 0)
398 return 2;
399 return -EINVAL;
400 }
401
402 static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
403 struct snd_ctl_elem_value *ucontrol)
404 {
405 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
406 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
407 struct wm8994_pdata *pdata = wm8994->pdata;
408 int drc = wm8994_get_drc(kcontrol->id.name);
409 int value = ucontrol->value.integer.value[0];
410
411 if (drc < 0)
412 return drc;
413
414 if (value >= pdata->num_drc_cfgs)
415 return -EINVAL;
416
417 wm8994->drc_cfg[drc] = value;
418
419 wm8994_set_drc(codec, drc);
420
421 return 0;
422 }
423
424 static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
425 struct snd_ctl_elem_value *ucontrol)
426 {
427 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
428 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
429 int drc = wm8994_get_drc(kcontrol->id.name);
430
431 ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
432
433 return 0;
434 }
435
436 static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
437 {
438 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
439 struct wm8994_pdata *pdata = wm8994->pdata;
440 int base = wm8994_retune_mobile_base[block];
441 int iface, best, best_val, save, i, cfg;
442
443 if (!pdata || !wm8994->num_retune_mobile_texts)
444 return;
445
446 switch (block) {
447 case 0:
448 case 1:
449 iface = 0;
450 break;
451 case 2:
452 iface = 1;
453 break;
454 default:
455 return;
456 }
457
458 /* Find the version of the currently selected configuration
459 * with the nearest sample rate. */
460 cfg = wm8994->retune_mobile_cfg[block];
461 best = 0;
462 best_val = INT_MAX;
463 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
464 if (strcmp(pdata->retune_mobile_cfgs[i].name,
465 wm8994->retune_mobile_texts[cfg]) == 0 &&
466 abs(pdata->retune_mobile_cfgs[i].rate
467 - wm8994->dac_rates[iface]) < best_val) {
468 best = i;
469 best_val = abs(pdata->retune_mobile_cfgs[i].rate
470 - wm8994->dac_rates[iface]);
471 }
472 }
473
474 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
475 block,
476 pdata->retune_mobile_cfgs[best].name,
477 pdata->retune_mobile_cfgs[best].rate,
478 wm8994->dac_rates[iface]);
479
480 /* The EQ will be disabled while reconfiguring it, remember the
481 * current configuration.
482 */
483 save = snd_soc_read(codec, base);
484 save &= WM8994_AIF1DAC1_EQ_ENA;
485
486 for (i = 0; i < WM8994_EQ_REGS; i++)
487 snd_soc_update_bits(codec, base + i, 0xffff,
488 pdata->retune_mobile_cfgs[best].regs[i]);
489
490 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
491 }
492
493 /* Icky as hell but saves code duplication */
494 static int wm8994_get_retune_mobile_block(const char *name)
495 {
496 if (strcmp(name, "AIF1.1 EQ Mode") == 0)
497 return 0;
498 if (strcmp(name, "AIF1.2 EQ Mode") == 0)
499 return 1;
500 if (strcmp(name, "AIF2 EQ Mode") == 0)
501 return 2;
502 return -EINVAL;
503 }
504
505 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
506 struct snd_ctl_elem_value *ucontrol)
507 {
508 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
509 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
510 struct wm8994_pdata *pdata = wm8994->pdata;
511 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
512 int value = ucontrol->value.integer.value[0];
513
514 if (block < 0)
515 return block;
516
517 if (value >= pdata->num_retune_mobile_cfgs)
518 return -EINVAL;
519
520 wm8994->retune_mobile_cfg[block] = value;
521
522 wm8994_set_retune_mobile(codec, block);
523
524 return 0;
525 }
526
527 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
528 struct snd_ctl_elem_value *ucontrol)
529 {
530 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
531 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
532 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
533
534 ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
535
536 return 0;
537 }
538
539 static const char *aif_chan_src_text[] = {
540 "Left", "Right"
541 };
542
543 static const struct soc_enum aif1adcl_src =
544 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
545
546 static const struct soc_enum aif1adcr_src =
547 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
548
549 static const struct soc_enum aif2adcl_src =
550 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
551
552 static const struct soc_enum aif2adcr_src =
553 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
554
555 static const struct soc_enum aif1dacl_src =
556 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
557
558 static const struct soc_enum aif1dacr_src =
559 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
560
561 static const struct soc_enum aif2dacl_src =
562 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
563
564 static const struct soc_enum aif2dacr_src =
565 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
566
567 static const char *osr_text[] = {
568 "Low Power", "High Performance",
569 };
570
571 static const struct soc_enum dac_osr =
572 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text);
573
574 static const struct soc_enum adc_osr =
575 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text);
576
577 static void wm8958_mbc_apply(struct snd_soc_codec *codec, int mbc, int start)
578 {
579 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
580 struct wm8994_pdata *pdata = wm8994->pdata;
581 int pwr_reg = snd_soc_read(codec, WM8994_POWER_MANAGEMENT_5);
582 int ena, reg, aif, i;
583
584 switch (mbc) {
585 case 0:
586 pwr_reg &= (WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA);
587 aif = 0;
588 break;
589 case 1:
590 pwr_reg &= (WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA);
591 aif = 0;
592 break;
593 case 2:
594 pwr_reg &= (WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA);
595 aif = 1;
596 break;
597 default:
598 BUG();
599 return;
600 }
601
602 /* We can only enable the MBC if the AIF is enabled and we
603 * want it to be enabled. */
604 ena = pwr_reg && wm8994->mbc_ena[mbc];
605
606 reg = snd_soc_read(codec, WM8958_DSP2_PROGRAM);
607
608 dev_dbg(codec->dev, "MBC %d startup: %d, power: %x, DSP: %x\n",
609 mbc, start, pwr_reg, reg);
610
611 if (start && ena) {
612 /* If the DSP is already running then noop */
613 if (reg & WM8958_DSP2_ENA)
614 return;
615
616 /* Switch the clock over to the appropriate AIF */
617 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
618 WM8958_DSP2CLK_SRC | WM8958_DSP2CLK_ENA,
619 aif << WM8958_DSP2CLK_SRC_SHIFT |
620 WM8958_DSP2CLK_ENA);
621
622 snd_soc_update_bits(codec, WM8958_DSP2_PROGRAM,
623 WM8958_DSP2_ENA, WM8958_DSP2_ENA);
624
625 /* If we've got user supplied MBC settings use them */
626 if (pdata && pdata->num_mbc_cfgs) {
627 struct wm8958_mbc_cfg *cfg
628 = &pdata->mbc_cfgs[wm8994->mbc_cfg];
629
630 for (i = 0; i < ARRAY_SIZE(cfg->coeff_regs); i++)
631 snd_soc_write(codec, i + WM8958_MBC_BAND_1_K_1,
632 cfg->coeff_regs[i]);
633
634 for (i = 0; i < ARRAY_SIZE(cfg->cutoff_regs); i++)
635 snd_soc_write(codec,
636 i + WM8958_MBC_BAND_2_LOWER_CUTOFF_C1_1,
637 cfg->cutoff_regs[i]);
638 }
639
640 /* Run the DSP */
641 snd_soc_write(codec, WM8958_DSP2_EXECCONTROL,
642 WM8958_DSP2_RUNR);
643
644 /* And we're off! */
645 snd_soc_update_bits(codec, WM8958_DSP2_CONFIG,
646 WM8958_MBC_ENA | WM8958_MBC_SEL_MASK,
647 mbc << WM8958_MBC_SEL_SHIFT |
648 WM8958_MBC_ENA);
649 } else {
650 /* If the DSP is already stopped then noop */
651 if (!(reg & WM8958_DSP2_ENA))
652 return;
653
654 snd_soc_update_bits(codec, WM8958_DSP2_CONFIG,
655 WM8958_MBC_ENA, 0);
656 snd_soc_update_bits(codec, WM8958_DSP2_PROGRAM,
657 WM8958_DSP2_ENA, 0);
658 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
659 WM8958_DSP2CLK_ENA, 0);
660 }
661 }
662
663 static int wm8958_aif_ev(struct snd_soc_dapm_widget *w,
664 struct snd_kcontrol *kcontrol, int event)
665 {
666 struct snd_soc_codec *codec = w->codec;
667 int mbc;
668
669 switch (w->shift) {
670 case 13:
671 case 12:
672 mbc = 2;
673 break;
674 case 11:
675 case 10:
676 mbc = 1;
677 break;
678 case 9:
679 case 8:
680 mbc = 0;
681 break;
682 default:
683 BUG();
684 return -EINVAL;
685 }
686
687 switch (event) {
688 case SND_SOC_DAPM_POST_PMU:
689 wm8958_mbc_apply(codec, mbc, 1);
690 break;
691 case SND_SOC_DAPM_POST_PMD:
692 wm8958_mbc_apply(codec, mbc, 0);
693 break;
694 }
695
696 return 0;
697 }
698
699 static int wm8958_put_mbc_enum(struct snd_kcontrol *kcontrol,
700 struct snd_ctl_elem_value *ucontrol)
701 {
702 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
703 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
704 struct wm8994_pdata *pdata = wm8994->pdata;
705 int value = ucontrol->value.integer.value[0];
706 int reg;
707
708 /* Don't allow on the fly reconfiguration */
709 reg = snd_soc_read(codec, WM8994_CLOCKING_1);
710 if (reg < 0 || reg & WM8958_DSP2CLK_ENA)
711 return -EBUSY;
712
713 if (value >= pdata->num_mbc_cfgs)
714 return -EINVAL;
715
716 wm8994->mbc_cfg = value;
717
718 return 0;
719 }
720
721 static int wm8958_get_mbc_enum(struct snd_kcontrol *kcontrol,
722 struct snd_ctl_elem_value *ucontrol)
723 {
724 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
725 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
726
727 ucontrol->value.enumerated.item[0] = wm8994->mbc_cfg;
728
729 return 0;
730 }
731
732 static int wm8958_mbc_info(struct snd_kcontrol *kcontrol,
733 struct snd_ctl_elem_info *uinfo)
734 {
735 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
736 uinfo->count = 1;
737 uinfo->value.integer.min = 0;
738 uinfo->value.integer.max = 1;
739 return 0;
740 }
741
742 static int wm8958_mbc_get(struct snd_kcontrol *kcontrol,
743 struct snd_ctl_elem_value *ucontrol)
744 {
745 int mbc = kcontrol->private_value;
746 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
747 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
748
749 ucontrol->value.integer.value[0] = wm8994->mbc_ena[mbc];
750
751 return 0;
752 }
753
754 static int wm8958_mbc_put(struct snd_kcontrol *kcontrol,
755 struct snd_ctl_elem_value *ucontrol)
756 {
757 int mbc = kcontrol->private_value;
758 int i;
759 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
760 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
761
762 if (ucontrol->value.integer.value[0] > 1)
763 return -EINVAL;
764
765 for (i = 0; i < ARRAY_SIZE(wm8994->mbc_ena); i++) {
766 if (mbc != i && wm8994->mbc_ena[i]) {
767 dev_dbg(codec->dev, "MBC %d active already\n", mbc);
768 return -EBUSY;
769 }
770 }
771
772 wm8994->mbc_ena[mbc] = ucontrol->value.integer.value[0];
773
774 wm8958_mbc_apply(codec, mbc, wm8994->mbc_ena[mbc]);
775
776 return 0;
777 }
778
779 #define WM8958_MBC_SWITCH(xname, xval) {\
780 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
781 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,\
782 .info = wm8958_mbc_info, \
783 .get = wm8958_mbc_get, .put = wm8958_mbc_put, \
784 .private_value = xval }
785
786 static const struct snd_kcontrol_new wm8994_snd_controls[] = {
787 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
788 WM8994_AIF1_ADC1_RIGHT_VOLUME,
789 1, 119, 0, digital_tlv),
790 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
791 WM8994_AIF1_ADC2_RIGHT_VOLUME,
792 1, 119, 0, digital_tlv),
793 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
794 WM8994_AIF2_ADC_RIGHT_VOLUME,
795 1, 119, 0, digital_tlv),
796
797 SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
798 SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
799 SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
800 SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
801
802 SOC_ENUM("AIF1DACL Source", aif1dacl_src),
803 SOC_ENUM("AIF1DACR Source", aif1dacr_src),
804 SOC_ENUM("AIF2DACL Source", aif2dacl_src),
805 SOC_ENUM("AIF2DACR Source", aif2dacr_src),
806
807 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
808 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
809 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
810 WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
811 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
812 WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
813
814 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
815 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
816
817 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
818 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
819 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
820
821 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
822 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
823 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
824
825 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
826 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
827 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
828
829 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
830 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
831 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
832
833 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
834 5, 12, 0, st_tlv),
835 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
836 0, 12, 0, st_tlv),
837 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
838 5, 12, 0, st_tlv),
839 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
840 0, 12, 0, st_tlv),
841 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
842 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
843
844 SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
845 SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
846
847 SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
848 SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
849
850 SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
851 SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
852
853 SOC_ENUM("ADC OSR", adc_osr),
854 SOC_ENUM("DAC OSR", dac_osr),
855
856 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
857 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
858 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
859 WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
860
861 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
862 WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
863 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
864 WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
865
866 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
867 6, 1, 1, wm_hubs_spkmix_tlv),
868 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
869 2, 1, 1, wm_hubs_spkmix_tlv),
870
871 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
872 6, 1, 1, wm_hubs_spkmix_tlv),
873 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
874 2, 1, 1, wm_hubs_spkmix_tlv),
875
876 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
877 10, 15, 0, wm8994_3d_tlv),
878 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
879 8, 1, 0),
880 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
881 10, 15, 0, wm8994_3d_tlv),
882 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
883 8, 1, 0),
884 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
885 10, 15, 0, wm8994_3d_tlv),
886 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
887 8, 1, 0),
888 };
889
890 static const struct snd_kcontrol_new wm8994_eq_controls[] = {
891 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
892 eq_tlv),
893 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
894 eq_tlv),
895 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
896 eq_tlv),
897 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
898 eq_tlv),
899 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
900 eq_tlv),
901
902 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
903 eq_tlv),
904 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
905 eq_tlv),
906 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
907 eq_tlv),
908 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
909 eq_tlv),
910 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
911 eq_tlv),
912
913 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
914 eq_tlv),
915 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
916 eq_tlv),
917 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
918 eq_tlv),
919 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
920 eq_tlv),
921 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
922 eq_tlv),
923 };
924
925 static const struct snd_kcontrol_new wm8958_snd_controls[] = {
926 SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
927 WM8958_MBC_SWITCH("AIF1DAC1 MBC Switch", 0),
928 WM8958_MBC_SWITCH("AIF1DAC2 MBC Switch", 1),
929 WM8958_MBC_SWITCH("AIF2DAC MBC Switch", 2),
930 };
931
932 static int clk_sys_event(struct snd_soc_dapm_widget *w,
933 struct snd_kcontrol *kcontrol, int event)
934 {
935 struct snd_soc_codec *codec = w->codec;
936
937 switch (event) {
938 case SND_SOC_DAPM_PRE_PMU:
939 return configure_clock(codec);
940
941 case SND_SOC_DAPM_POST_PMD:
942 configure_clock(codec);
943 break;
944 }
945
946 return 0;
947 }
948
949 static void wm8994_update_class_w(struct snd_soc_codec *codec)
950 {
951 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
952 int enable = 1;
953 int source = 0; /* GCC flow analysis can't track enable */
954 int reg, reg_r;
955
956 /* Only support direct DAC->headphone paths */
957 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_1);
958 if (!(reg & WM8994_DAC1L_TO_HPOUT1L)) {
959 dev_vdbg(codec->dev, "HPL connected to output mixer\n");
960 enable = 0;
961 }
962
963 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_2);
964 if (!(reg & WM8994_DAC1R_TO_HPOUT1R)) {
965 dev_vdbg(codec->dev, "HPR connected to output mixer\n");
966 enable = 0;
967 }
968
969 /* We also need the same setting for L/R and only one path */
970 reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
971 switch (reg) {
972 case WM8994_AIF2DACL_TO_DAC1L:
973 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
974 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
975 break;
976 case WM8994_AIF1DAC2L_TO_DAC1L:
977 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
978 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
979 break;
980 case WM8994_AIF1DAC1L_TO_DAC1L:
981 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
982 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
983 break;
984 default:
985 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
986 enable = 0;
987 break;
988 }
989
990 reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
991 if (reg_r != reg) {
992 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
993 enable = 0;
994 }
995
996 if (enable) {
997 dev_dbg(codec->dev, "Class W enabled\n");
998 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
999 WM8994_CP_DYN_PWR |
1000 WM8994_CP_DYN_SRC_SEL_MASK,
1001 source | WM8994_CP_DYN_PWR);
1002 wm8994->hubs.class_w = true;
1003
1004 } else {
1005 dev_dbg(codec->dev, "Class W disabled\n");
1006 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
1007 WM8994_CP_DYN_PWR, 0);
1008 wm8994->hubs.class_w = false;
1009 }
1010 }
1011
1012 static int late_enable_ev(struct snd_soc_dapm_widget *w,
1013 struct snd_kcontrol *kcontrol, int event)
1014 {
1015 struct snd_soc_codec *codec = w->codec;
1016 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1017
1018 switch (event) {
1019 case SND_SOC_DAPM_PRE_PMU:
1020 if (wm8994->aif1clk_enable) {
1021 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1022 WM8994_AIF1CLK_ENA_MASK,
1023 WM8994_AIF1CLK_ENA);
1024 wm8994->aif1clk_enable = 0;
1025 }
1026 if (wm8994->aif2clk_enable) {
1027 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1028 WM8994_AIF2CLK_ENA_MASK,
1029 WM8994_AIF2CLK_ENA);
1030 wm8994->aif2clk_enable = 0;
1031 }
1032 break;
1033 }
1034
1035 return 0;
1036 }
1037
1038 static int late_disable_ev(struct snd_soc_dapm_widget *w,
1039 struct snd_kcontrol *kcontrol, int event)
1040 {
1041 struct snd_soc_codec *codec = w->codec;
1042 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1043
1044 switch (event) {
1045 case SND_SOC_DAPM_POST_PMD:
1046 if (wm8994->aif1clk_disable) {
1047 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1048 WM8994_AIF1CLK_ENA_MASK, 0);
1049 wm8994->aif1clk_disable = 0;
1050 }
1051 if (wm8994->aif2clk_disable) {
1052 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1053 WM8994_AIF2CLK_ENA_MASK, 0);
1054 wm8994->aif2clk_disable = 0;
1055 }
1056 break;
1057 }
1058
1059 return 0;
1060 }
1061
1062 static int aif1clk_ev(struct snd_soc_dapm_widget *w,
1063 struct snd_kcontrol *kcontrol, int event)
1064 {
1065 struct snd_soc_codec *codec = w->codec;
1066 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1067
1068 switch (event) {
1069 case SND_SOC_DAPM_PRE_PMU:
1070 wm8994->aif1clk_enable = 1;
1071 break;
1072 case SND_SOC_DAPM_POST_PMD:
1073 wm8994->aif1clk_disable = 1;
1074 break;
1075 }
1076
1077 return 0;
1078 }
1079
1080 static int aif2clk_ev(struct snd_soc_dapm_widget *w,
1081 struct snd_kcontrol *kcontrol, int event)
1082 {
1083 struct snd_soc_codec *codec = w->codec;
1084 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1085
1086 switch (event) {
1087 case SND_SOC_DAPM_PRE_PMU:
1088 wm8994->aif2clk_enable = 1;
1089 break;
1090 case SND_SOC_DAPM_POST_PMD:
1091 wm8994->aif2clk_disable = 1;
1092 break;
1093 }
1094
1095 return 0;
1096 }
1097
1098 static int adc_mux_ev(struct snd_soc_dapm_widget *w,
1099 struct snd_kcontrol *kcontrol, int event)
1100 {
1101 late_enable_ev(w, kcontrol, event);
1102 return 0;
1103 }
1104
1105 static int micbias_ev(struct snd_soc_dapm_widget *w,
1106 struct snd_kcontrol *kcontrol, int event)
1107 {
1108 late_enable_ev(w, kcontrol, event);
1109 return 0;
1110 }
1111
1112 static int dac_ev(struct snd_soc_dapm_widget *w,
1113 struct snd_kcontrol *kcontrol, int event)
1114 {
1115 struct snd_soc_codec *codec = w->codec;
1116 unsigned int mask = 1 << w->shift;
1117
1118 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1119 mask, mask);
1120 return 0;
1121 }
1122
1123 static const char *hp_mux_text[] = {
1124 "Mixer",
1125 "DAC",
1126 };
1127
1128 #define WM8994_HP_ENUM(xname, xenum) \
1129 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1130 .info = snd_soc_info_enum_double, \
1131 .get = snd_soc_dapm_get_enum_double, \
1132 .put = wm8994_put_hp_enum, \
1133 .private_value = (unsigned long)&xenum }
1134
1135 static int wm8994_put_hp_enum(struct snd_kcontrol *kcontrol,
1136 struct snd_ctl_elem_value *ucontrol)
1137 {
1138 struct snd_soc_dapm_widget *w = snd_kcontrol_chip(kcontrol);
1139 struct snd_soc_codec *codec = w->codec;
1140 int ret;
1141
1142 ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
1143
1144 wm8994_update_class_w(codec);
1145
1146 return ret;
1147 }
1148
1149 static const struct soc_enum hpl_enum =
1150 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_1, 8, 2, hp_mux_text);
1151
1152 static const struct snd_kcontrol_new hpl_mux =
1153 WM8994_HP_ENUM("Left Headphone Mux", hpl_enum);
1154
1155 static const struct soc_enum hpr_enum =
1156 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_2, 8, 2, hp_mux_text);
1157
1158 static const struct snd_kcontrol_new hpr_mux =
1159 WM8994_HP_ENUM("Right Headphone Mux", hpr_enum);
1160
1161 static const char *adc_mux_text[] = {
1162 "ADC",
1163 "DMIC",
1164 };
1165
1166 static const struct soc_enum adc_enum =
1167 SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
1168
1169 static const struct snd_kcontrol_new adcl_mux =
1170 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
1171
1172 static const struct snd_kcontrol_new adcr_mux =
1173 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
1174
1175 static const struct snd_kcontrol_new left_speaker_mixer[] = {
1176 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
1177 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
1178 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
1179 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
1180 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
1181 };
1182
1183 static const struct snd_kcontrol_new right_speaker_mixer[] = {
1184 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
1185 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
1186 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
1187 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
1188 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
1189 };
1190
1191 /* Debugging; dump chip status after DAPM transitions */
1192 static int post_ev(struct snd_soc_dapm_widget *w,
1193 struct snd_kcontrol *kcontrol, int event)
1194 {
1195 struct snd_soc_codec *codec = w->codec;
1196 dev_dbg(codec->dev, "SRC status: %x\n",
1197 snd_soc_read(codec,
1198 WM8994_RATE_STATUS));
1199 return 0;
1200 }
1201
1202 static const struct snd_kcontrol_new aif1adc1l_mix[] = {
1203 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1204 1, 1, 0),
1205 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1206 0, 1, 0),
1207 };
1208
1209 static const struct snd_kcontrol_new aif1adc1r_mix[] = {
1210 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1211 1, 1, 0),
1212 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1213 0, 1, 0),
1214 };
1215
1216 static const struct snd_kcontrol_new aif1adc2l_mix[] = {
1217 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1218 1, 1, 0),
1219 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1220 0, 1, 0),
1221 };
1222
1223 static const struct snd_kcontrol_new aif1adc2r_mix[] = {
1224 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1225 1, 1, 0),
1226 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1227 0, 1, 0),
1228 };
1229
1230 static const struct snd_kcontrol_new aif2dac2l_mix[] = {
1231 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1232 5, 1, 0),
1233 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1234 4, 1, 0),
1235 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1236 2, 1, 0),
1237 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1238 1, 1, 0),
1239 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1240 0, 1, 0),
1241 };
1242
1243 static const struct snd_kcontrol_new aif2dac2r_mix[] = {
1244 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1245 5, 1, 0),
1246 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1247 4, 1, 0),
1248 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1249 2, 1, 0),
1250 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1251 1, 1, 0),
1252 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1253 0, 1, 0),
1254 };
1255
1256 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1257 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1258 .info = snd_soc_info_volsw, \
1259 .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
1260 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
1261
1262 static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1263 struct snd_ctl_elem_value *ucontrol)
1264 {
1265 struct snd_soc_dapm_widget *w = snd_kcontrol_chip(kcontrol);
1266 struct snd_soc_codec *codec = w->codec;
1267 int ret;
1268
1269 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1270
1271 wm8994_update_class_w(codec);
1272
1273 return ret;
1274 }
1275
1276 static const struct snd_kcontrol_new dac1l_mix[] = {
1277 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1278 5, 1, 0),
1279 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1280 4, 1, 0),
1281 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1282 2, 1, 0),
1283 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1284 1, 1, 0),
1285 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1286 0, 1, 0),
1287 };
1288
1289 static const struct snd_kcontrol_new dac1r_mix[] = {
1290 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1291 5, 1, 0),
1292 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1293 4, 1, 0),
1294 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1295 2, 1, 0),
1296 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1297 1, 1, 0),
1298 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1299 0, 1, 0),
1300 };
1301
1302 static const char *sidetone_text[] = {
1303 "ADC/DMIC1", "DMIC2",
1304 };
1305
1306 static const struct soc_enum sidetone1_enum =
1307 SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
1308
1309 static const struct snd_kcontrol_new sidetone1_mux =
1310 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1311
1312 static const struct soc_enum sidetone2_enum =
1313 SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
1314
1315 static const struct snd_kcontrol_new sidetone2_mux =
1316 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1317
1318 static const char *aif1dac_text[] = {
1319 "AIF1DACDAT", "AIF3DACDAT",
1320 };
1321
1322 static const struct soc_enum aif1dac_enum =
1323 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
1324
1325 static const struct snd_kcontrol_new aif1dac_mux =
1326 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1327
1328 static const char *aif2dac_text[] = {
1329 "AIF2DACDAT", "AIF3DACDAT",
1330 };
1331
1332 static const struct soc_enum aif2dac_enum =
1333 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
1334
1335 static const struct snd_kcontrol_new aif2dac_mux =
1336 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1337
1338 static const char *aif2adc_text[] = {
1339 "AIF2ADCDAT", "AIF3DACDAT",
1340 };
1341
1342 static const struct soc_enum aif2adc_enum =
1343 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
1344
1345 static const struct snd_kcontrol_new aif2adc_mux =
1346 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1347
1348 static const char *aif3adc_text[] = {
1349 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
1350 };
1351
1352 static const struct soc_enum wm8994_aif3adc_enum =
1353 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
1354
1355 static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1356 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1357
1358 static const struct soc_enum wm8958_aif3adc_enum =
1359 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
1360
1361 static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1362 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1363
1364 static const char *mono_pcm_out_text[] = {
1365 "None", "AIF2ADCL", "AIF2ADCR",
1366 };
1367
1368 static const struct soc_enum mono_pcm_out_enum =
1369 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
1370
1371 static const struct snd_kcontrol_new mono_pcm_out_mux =
1372 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1373
1374 static const char *aif2dac_src_text[] = {
1375 "AIF2", "AIF3",
1376 };
1377
1378 /* Note that these two control shouldn't be simultaneously switched to AIF3 */
1379 static const struct soc_enum aif2dacl_src_enum =
1380 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
1381
1382 static const struct snd_kcontrol_new aif2dacl_src_mux =
1383 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1384
1385 static const struct soc_enum aif2dacr_src_enum =
1386 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
1387
1388 static const struct snd_kcontrol_new aif2dacr_src_mux =
1389 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
1390
1391 static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1392 SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_ev,
1393 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1394 SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_ev,
1395 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1396
1397 SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1398 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1399 SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1400 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1401 SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1402 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1403 SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1404 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1405
1406 SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1407 };
1408
1409 static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1410 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, NULL, 0),
1411 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, NULL, 0)
1412 };
1413
1414 static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1415 SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1416 dac_ev, SND_SOC_DAPM_PRE_PMU),
1417 SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1418 dac_ev, SND_SOC_DAPM_PRE_PMU),
1419 SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1420 dac_ev, SND_SOC_DAPM_PRE_PMU),
1421 SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1422 dac_ev, SND_SOC_DAPM_PRE_PMU),
1423 };
1424
1425 static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1426 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
1427 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
1428 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1429 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1430 };
1431
1432 static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
1433 SND_SOC_DAPM_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
1434 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1435 SND_SOC_DAPM_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
1436 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1437 };
1438
1439 static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
1440 SND_SOC_DAPM_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1441 SND_SOC_DAPM_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
1442 };
1443
1444 static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1445 SND_SOC_DAPM_INPUT("DMIC1DAT"),
1446 SND_SOC_DAPM_INPUT("DMIC2DAT"),
1447 SND_SOC_DAPM_INPUT("Clock"),
1448
1449 SND_SOC_DAPM_MICBIAS("MICBIAS", WM8994_MICBIAS, 2, 0),
1450 SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
1451 SND_SOC_DAPM_PRE_PMU),
1452
1453 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
1454 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1455
1456 SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8994_CLOCKING_1, 3, 0, NULL, 0),
1457 SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8994_CLOCKING_1, 2, 0, NULL, 0),
1458 SND_SOC_DAPM_SUPPLY("DSPINTCLK", WM8994_CLOCKING_1, 1, 0, NULL, 0),
1459
1460 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
1461 0, WM8994_POWER_MANAGEMENT_4, 9, 0),
1462 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
1463 0, WM8994_POWER_MANAGEMENT_4, 8, 0),
1464 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1465 WM8994_POWER_MANAGEMENT_5, 9, 0, wm8958_aif_ev,
1466 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1467 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1468 WM8994_POWER_MANAGEMENT_5, 8, 0, wm8958_aif_ev,
1469 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1470
1471 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
1472 0, WM8994_POWER_MANAGEMENT_4, 11, 0),
1473 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
1474 0, WM8994_POWER_MANAGEMENT_4, 10, 0),
1475 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1476 WM8994_POWER_MANAGEMENT_5, 11, 0, wm8958_aif_ev,
1477 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1478 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1479 WM8994_POWER_MANAGEMENT_5, 10, 0, wm8958_aif_ev,
1480 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1481
1482 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1483 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1484 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1485 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1486
1487 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1488 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1489 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1490 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1491
1492 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1493 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1494 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1495 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1496
1497 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1498 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1499
1500 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1501 dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1502 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1503 dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1504
1505 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1506 WM8994_POWER_MANAGEMENT_4, 13, 0),
1507 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1508 WM8994_POWER_MANAGEMENT_4, 12, 0),
1509 SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1510 WM8994_POWER_MANAGEMENT_5, 13, 0, wm8958_aif_ev,
1511 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1512 SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1513 WM8994_POWER_MANAGEMENT_5, 12, 0, wm8958_aif_ev,
1514 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1515
1516 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1517 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
1518 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
1519 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
1520
1521 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1522 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1523 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
1524
1525 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
1526 SND_SOC_DAPM_AIF_IN("AIF3ADCDAT", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
1527
1528 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1529
1530 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1531 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1532 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1533 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1534
1535 /* Power is done with the muxes since the ADC power also controls the
1536 * downsampling chain, the chip will automatically manage the analogue
1537 * specific portions.
1538 */
1539 SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1540 SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1541
1542 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
1543 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
1544
1545 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1546 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1547 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1548 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1549
1550 SND_SOC_DAPM_POST("Debug log", post_ev),
1551 };
1552
1553 static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1554 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1555 };
1556
1557 static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1558 SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1559 SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1560 SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1561 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1562 };
1563
1564 static const struct snd_soc_dapm_route intercon[] = {
1565 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1566 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1567
1568 { "DSP1CLK", NULL, "CLK_SYS" },
1569 { "DSP2CLK", NULL, "CLK_SYS" },
1570 { "DSPINTCLK", NULL, "CLK_SYS" },
1571
1572 { "AIF1ADC1L", NULL, "AIF1CLK" },
1573 { "AIF1ADC1L", NULL, "DSP1CLK" },
1574 { "AIF1ADC1R", NULL, "AIF1CLK" },
1575 { "AIF1ADC1R", NULL, "DSP1CLK" },
1576 { "AIF1ADC1R", NULL, "DSPINTCLK" },
1577
1578 { "AIF1DAC1L", NULL, "AIF1CLK" },
1579 { "AIF1DAC1L", NULL, "DSP1CLK" },
1580 { "AIF1DAC1R", NULL, "AIF1CLK" },
1581 { "AIF1DAC1R", NULL, "DSP1CLK" },
1582 { "AIF1DAC1R", NULL, "DSPINTCLK" },
1583
1584 { "AIF1ADC2L", NULL, "AIF1CLK" },
1585 { "AIF1ADC2L", NULL, "DSP1CLK" },
1586 { "AIF1ADC2R", NULL, "AIF1CLK" },
1587 { "AIF1ADC2R", NULL, "DSP1CLK" },
1588 { "AIF1ADC2R", NULL, "DSPINTCLK" },
1589
1590 { "AIF1DAC2L", NULL, "AIF1CLK" },
1591 { "AIF1DAC2L", NULL, "DSP1CLK" },
1592 { "AIF1DAC2R", NULL, "AIF1CLK" },
1593 { "AIF1DAC2R", NULL, "DSP1CLK" },
1594 { "AIF1DAC2R", NULL, "DSPINTCLK" },
1595
1596 { "AIF2ADCL", NULL, "AIF2CLK" },
1597 { "AIF2ADCL", NULL, "DSP2CLK" },
1598 { "AIF2ADCR", NULL, "AIF2CLK" },
1599 { "AIF2ADCR", NULL, "DSP2CLK" },
1600 { "AIF2ADCR", NULL, "DSPINTCLK" },
1601
1602 { "AIF2DACL", NULL, "AIF2CLK" },
1603 { "AIF2DACL", NULL, "DSP2CLK" },
1604 { "AIF2DACR", NULL, "AIF2CLK" },
1605 { "AIF2DACR", NULL, "DSP2CLK" },
1606 { "AIF2DACR", NULL, "DSPINTCLK" },
1607
1608 { "DMIC1L", NULL, "DMIC1DAT" },
1609 { "DMIC1L", NULL, "CLK_SYS" },
1610 { "DMIC1R", NULL, "DMIC1DAT" },
1611 { "DMIC1R", NULL, "CLK_SYS" },
1612 { "DMIC2L", NULL, "DMIC2DAT" },
1613 { "DMIC2L", NULL, "CLK_SYS" },
1614 { "DMIC2R", NULL, "DMIC2DAT" },
1615 { "DMIC2R", NULL, "CLK_SYS" },
1616
1617 { "ADCL", NULL, "AIF1CLK" },
1618 { "ADCL", NULL, "DSP1CLK" },
1619 { "ADCL", NULL, "DSPINTCLK" },
1620
1621 { "ADCR", NULL, "AIF1CLK" },
1622 { "ADCR", NULL, "DSP1CLK" },
1623 { "ADCR", NULL, "DSPINTCLK" },
1624
1625 { "ADCL Mux", "ADC", "ADCL" },
1626 { "ADCL Mux", "DMIC", "DMIC1L" },
1627 { "ADCR Mux", "ADC", "ADCR" },
1628 { "ADCR Mux", "DMIC", "DMIC1R" },
1629
1630 { "DAC1L", NULL, "AIF1CLK" },
1631 { "DAC1L", NULL, "DSP1CLK" },
1632 { "DAC1L", NULL, "DSPINTCLK" },
1633
1634 { "DAC1R", NULL, "AIF1CLK" },
1635 { "DAC1R", NULL, "DSP1CLK" },
1636 { "DAC1R", NULL, "DSPINTCLK" },
1637
1638 { "DAC2L", NULL, "AIF2CLK" },
1639 { "DAC2L", NULL, "DSP2CLK" },
1640 { "DAC2L", NULL, "DSPINTCLK" },
1641
1642 { "DAC2R", NULL, "AIF2DACR" },
1643 { "DAC2R", NULL, "AIF2CLK" },
1644 { "DAC2R", NULL, "DSP2CLK" },
1645 { "DAC2R", NULL, "DSPINTCLK" },
1646
1647 { "TOCLK", NULL, "CLK_SYS" },
1648
1649 /* AIF1 outputs */
1650 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1651 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1652 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1653
1654 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1655 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1656 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1657
1658 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1659 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1660 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1661
1662 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1663 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1664 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1665
1666 /* Pin level routing for AIF3 */
1667 { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1668 { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1669 { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1670 { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1671
1672 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1673 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1674 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1675 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1676 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1677 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1678 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1679
1680 /* DAC1 inputs */
1681 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1682 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1683 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1684 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1685 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1686
1687 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1688 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1689 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1690 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1691 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1692
1693 /* DAC2/AIF2 outputs */
1694 { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
1695 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1696 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1697 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1698 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1699 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1700
1701 { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
1702 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1703 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1704 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1705 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1706 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1707
1708 { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1709 { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1710 { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1711 { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1712
1713 { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1714
1715 /* AIF3 output */
1716 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1717 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1718 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1719 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1720 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1721 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1722 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1723 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1724
1725 /* Sidetone */
1726 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1727 { "Left Sidetone", "DMIC2", "DMIC2L" },
1728 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1729 { "Right Sidetone", "DMIC2", "DMIC2R" },
1730
1731 /* Output stages */
1732 { "Left Output Mixer", "DAC Switch", "DAC1L" },
1733 { "Right Output Mixer", "DAC Switch", "DAC1R" },
1734
1735 { "SPKL", "DAC1 Switch", "DAC1L" },
1736 { "SPKL", "DAC2 Switch", "DAC2L" },
1737
1738 { "SPKR", "DAC1 Switch", "DAC1R" },
1739 { "SPKR", "DAC2 Switch", "DAC2R" },
1740
1741 { "Left Headphone Mux", "DAC", "DAC1L" },
1742 { "Right Headphone Mux", "DAC", "DAC1R" },
1743 };
1744
1745 static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1746 { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1747 { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1748 { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1749 { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1750 { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1751 { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1752 { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1753 { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1754 };
1755
1756 static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
1757 { "DAC1L", NULL, "DAC1L Mixer" },
1758 { "DAC1R", NULL, "DAC1R Mixer" },
1759 { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1760 { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1761 };
1762
1763 static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
1764 { "AIF1DACDAT", NULL, "AIF2DACDAT" },
1765 { "AIF2DACDAT", NULL, "AIF1DACDAT" },
1766 { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
1767 { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
1768 { "MICBIAS", NULL, "CLK_SYS" },
1769 { "MICBIAS", NULL, "MICBIAS Supply" },
1770 };
1771
1772 static const struct snd_soc_dapm_route wm8994_intercon[] = {
1773 { "AIF2DACL", NULL, "AIF2DAC Mux" },
1774 { "AIF2DACR", NULL, "AIF2DAC Mux" },
1775 };
1776
1777 static const struct snd_soc_dapm_route wm8958_intercon[] = {
1778 { "AIF2DACL", NULL, "AIF2DACL Mux" },
1779 { "AIF2DACR", NULL, "AIF2DACR Mux" },
1780
1781 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1782 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1783 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1784 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1785
1786 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1787 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1788
1789 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1790 };
1791
1792 /* The size in bits of the FLL divide multiplied by 10
1793 * to allow rounding later */
1794 #define FIXED_FLL_SIZE ((1 << 16) * 10)
1795
1796 struct fll_div {
1797 u16 outdiv;
1798 u16 n;
1799 u16 k;
1800 u16 clk_ref_div;
1801 u16 fll_fratio;
1802 };
1803
1804 static int wm8994_get_fll_config(struct fll_div *fll,
1805 int freq_in, int freq_out)
1806 {
1807 u64 Kpart;
1808 unsigned int K, Ndiv, Nmod;
1809
1810 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
1811
1812 /* Scale the input frequency down to <= 13.5MHz */
1813 fll->clk_ref_div = 0;
1814 while (freq_in > 13500000) {
1815 fll->clk_ref_div++;
1816 freq_in /= 2;
1817
1818 if (fll->clk_ref_div > 3)
1819 return -EINVAL;
1820 }
1821 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
1822
1823 /* Scale the output to give 90MHz<=Fvco<=100MHz */
1824 fll->outdiv = 3;
1825 while (freq_out * (fll->outdiv + 1) < 90000000) {
1826 fll->outdiv++;
1827 if (fll->outdiv > 63)
1828 return -EINVAL;
1829 }
1830 freq_out *= fll->outdiv + 1;
1831 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
1832
1833 if (freq_in > 1000000) {
1834 fll->fll_fratio = 0;
1835 } else if (freq_in > 256000) {
1836 fll->fll_fratio = 1;
1837 freq_in *= 2;
1838 } else if (freq_in > 128000) {
1839 fll->fll_fratio = 2;
1840 freq_in *= 4;
1841 } else if (freq_in > 64000) {
1842 fll->fll_fratio = 3;
1843 freq_in *= 8;
1844 } else {
1845 fll->fll_fratio = 4;
1846 freq_in *= 16;
1847 }
1848 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
1849
1850 /* Now, calculate N.K */
1851 Ndiv = freq_out / freq_in;
1852
1853 fll->n = Ndiv;
1854 Nmod = freq_out % freq_in;
1855 pr_debug("Nmod=%d\n", Nmod);
1856
1857 /* Calculate fractional part - scale up so we can round. */
1858 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1859
1860 do_div(Kpart, freq_in);
1861
1862 K = Kpart & 0xFFFFFFFF;
1863
1864 if ((K % 10) >= 5)
1865 K += 5;
1866
1867 /* Move down to proper range now rounding is done */
1868 fll->k = K / 10;
1869
1870 pr_debug("N=%x K=%x\n", fll->n, fll->k);
1871
1872 return 0;
1873 }
1874
1875 static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
1876 unsigned int freq_in, unsigned int freq_out)
1877 {
1878 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1879 int reg_offset, ret;
1880 struct fll_div fll;
1881 u16 reg, aif1, aif2;
1882
1883 aif1 = snd_soc_read(codec, WM8994_AIF1_CLOCKING_1)
1884 & WM8994_AIF1CLK_ENA;
1885
1886 aif2 = snd_soc_read(codec, WM8994_AIF2_CLOCKING_1)
1887 & WM8994_AIF2CLK_ENA;
1888
1889 switch (id) {
1890 case WM8994_FLL1:
1891 reg_offset = 0;
1892 id = 0;
1893 break;
1894 case WM8994_FLL2:
1895 reg_offset = 0x20;
1896 id = 1;
1897 break;
1898 default:
1899 return -EINVAL;
1900 }
1901
1902 switch (src) {
1903 case 0:
1904 /* Allow no source specification when stopping */
1905 if (freq_out)
1906 return -EINVAL;
1907 src = wm8994->fll[id].src;
1908 break;
1909 case WM8994_FLL_SRC_MCLK1:
1910 case WM8994_FLL_SRC_MCLK2:
1911 case WM8994_FLL_SRC_LRCLK:
1912 case WM8994_FLL_SRC_BCLK:
1913 break;
1914 default:
1915 return -EINVAL;
1916 }
1917
1918 /* Are we changing anything? */
1919 if (wm8994->fll[id].src == src &&
1920 wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
1921 return 0;
1922
1923 /* If we're stopping the FLL redo the old config - no
1924 * registers will actually be written but we avoid GCC flow
1925 * analysis bugs spewing warnings.
1926 */
1927 if (freq_out)
1928 ret = wm8994_get_fll_config(&fll, freq_in, freq_out);
1929 else
1930 ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in,
1931 wm8994->fll[id].out);
1932 if (ret < 0)
1933 return ret;
1934
1935 /* Gate the AIF clocks while we reclock */
1936 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1937 WM8994_AIF1CLK_ENA, 0);
1938 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1939 WM8994_AIF2CLK_ENA, 0);
1940
1941 /* We always need to disable the FLL while reconfiguring */
1942 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1943 WM8994_FLL1_ENA, 0);
1944
1945 reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
1946 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
1947 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
1948 WM8994_FLL1_OUTDIV_MASK |
1949 WM8994_FLL1_FRATIO_MASK, reg);
1950
1951 snd_soc_write(codec, WM8994_FLL1_CONTROL_3 + reg_offset, fll.k);
1952
1953 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
1954 WM8994_FLL1_N_MASK,
1955 fll.n << WM8994_FLL1_N_SHIFT);
1956
1957 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
1958 WM8994_FLL1_REFCLK_DIV_MASK |
1959 WM8994_FLL1_REFCLK_SRC_MASK,
1960 (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
1961 (src - 1));
1962
1963 /* Enable (with fractional mode if required) */
1964 if (freq_out) {
1965 if (fll.k)
1966 reg = WM8994_FLL1_ENA | WM8994_FLL1_FRAC;
1967 else
1968 reg = WM8994_FLL1_ENA;
1969 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1970 WM8994_FLL1_ENA | WM8994_FLL1_FRAC,
1971 reg);
1972
1973 msleep(5);
1974 }
1975
1976 wm8994->fll[id].in = freq_in;
1977 wm8994->fll[id].out = freq_out;
1978 wm8994->fll[id].src = src;
1979
1980 /* Enable any gated AIF clocks */
1981 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1982 WM8994_AIF1CLK_ENA, aif1);
1983 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1984 WM8994_AIF2CLK_ENA, aif2);
1985
1986 configure_clock(codec);
1987
1988 return 0;
1989 }
1990
1991
1992 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
1993
1994 static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
1995 unsigned int freq_in, unsigned int freq_out)
1996 {
1997 return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
1998 }
1999
2000 static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
2001 int clk_id, unsigned int freq, int dir)
2002 {
2003 struct snd_soc_codec *codec = dai->codec;
2004 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2005 int i;
2006
2007 switch (dai->id) {
2008 case 1:
2009 case 2:
2010 break;
2011
2012 default:
2013 /* AIF3 shares clocking with AIF1/2 */
2014 return -EINVAL;
2015 }
2016
2017 switch (clk_id) {
2018 case WM8994_SYSCLK_MCLK1:
2019 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
2020 wm8994->mclk[0] = freq;
2021 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
2022 dai->id, freq);
2023 break;
2024
2025 case WM8994_SYSCLK_MCLK2:
2026 /* TODO: Set GPIO AF */
2027 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
2028 wm8994->mclk[1] = freq;
2029 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
2030 dai->id, freq);
2031 break;
2032
2033 case WM8994_SYSCLK_FLL1:
2034 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
2035 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
2036 break;
2037
2038 case WM8994_SYSCLK_FLL2:
2039 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
2040 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
2041 break;
2042
2043 case WM8994_SYSCLK_OPCLK:
2044 /* Special case - a division (times 10) is given and
2045 * no effect on main clocking.
2046 */
2047 if (freq) {
2048 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
2049 if (opclk_divs[i] == freq)
2050 break;
2051 if (i == ARRAY_SIZE(opclk_divs))
2052 return -EINVAL;
2053 snd_soc_update_bits(codec, WM8994_CLOCKING_2,
2054 WM8994_OPCLK_DIV_MASK, i);
2055 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2056 WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
2057 } else {
2058 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2059 WM8994_OPCLK_ENA, 0);
2060 }
2061
2062 default:
2063 return -EINVAL;
2064 }
2065
2066 configure_clock(codec);
2067
2068 return 0;
2069 }
2070
2071 static int wm8994_set_bias_level(struct snd_soc_codec *codec,
2072 enum snd_soc_bias_level level)
2073 {
2074 struct wm8994 *control = codec->control_data;
2075 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2076
2077 switch (level) {
2078 case SND_SOC_BIAS_ON:
2079 break;
2080
2081 case SND_SOC_BIAS_PREPARE:
2082 /* VMID=2x40k */
2083 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
2084 WM8994_VMID_SEL_MASK, 0x2);
2085 break;
2086
2087 case SND_SOC_BIAS_STANDBY:
2088 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
2089 pm_runtime_get_sync(codec->dev);
2090
2091 switch (control->type) {
2092 case WM8994:
2093 if (wm8994->revision < 4) {
2094 /* Tweak DC servo and DSP
2095 * configuration for improved
2096 * performance. */
2097 snd_soc_write(codec, 0x102, 0x3);
2098 snd_soc_write(codec, 0x56, 0x3);
2099 snd_soc_write(codec, 0x817, 0);
2100 snd_soc_write(codec, 0x102, 0);
2101 }
2102 break;
2103
2104 case WM8958:
2105 if (wm8994->revision == 0) {
2106 /* Optimise performance for rev A */
2107 snd_soc_write(codec, 0x102, 0x3);
2108 snd_soc_write(codec, 0xcb, 0x81);
2109 snd_soc_write(codec, 0x817, 0);
2110 snd_soc_write(codec, 0x102, 0);
2111
2112 snd_soc_update_bits(codec,
2113 WM8958_CHARGE_PUMP_2,
2114 WM8958_CP_DISCH,
2115 WM8958_CP_DISCH);
2116 }
2117 break;
2118 }
2119
2120 /* Discharge LINEOUT1 & 2 */
2121 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
2122 WM8994_LINEOUT1_DISCH |
2123 WM8994_LINEOUT2_DISCH,
2124 WM8994_LINEOUT1_DISCH |
2125 WM8994_LINEOUT2_DISCH);
2126
2127 /* Startup bias, VMID ramp & buffer */
2128 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
2129 WM8994_STARTUP_BIAS_ENA |
2130 WM8994_VMID_BUF_ENA |
2131 WM8994_VMID_RAMP_MASK,
2132 WM8994_STARTUP_BIAS_ENA |
2133 WM8994_VMID_BUF_ENA |
2134 (0x11 << WM8994_VMID_RAMP_SHIFT));
2135
2136 /* Main bias enable, VMID=2x40k */
2137 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
2138 WM8994_BIAS_ENA |
2139 WM8994_VMID_SEL_MASK,
2140 WM8994_BIAS_ENA | 0x2);
2141
2142 msleep(20);
2143 }
2144
2145 /* VMID=2x500k */
2146 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
2147 WM8994_VMID_SEL_MASK, 0x4);
2148
2149 break;
2150
2151 case SND_SOC_BIAS_OFF:
2152 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
2153 /* Switch over to startup biases */
2154 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
2155 WM8994_BIAS_SRC |
2156 WM8994_STARTUP_BIAS_ENA |
2157 WM8994_VMID_BUF_ENA |
2158 WM8994_VMID_RAMP_MASK,
2159 WM8994_BIAS_SRC |
2160 WM8994_STARTUP_BIAS_ENA |
2161 WM8994_VMID_BUF_ENA |
2162 (1 << WM8994_VMID_RAMP_SHIFT));
2163
2164 /* Disable main biases */
2165 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
2166 WM8994_BIAS_ENA |
2167 WM8994_VMID_SEL_MASK, 0);
2168
2169 /* Discharge line */
2170 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
2171 WM8994_LINEOUT1_DISCH |
2172 WM8994_LINEOUT2_DISCH,
2173 WM8994_LINEOUT1_DISCH |
2174 WM8994_LINEOUT2_DISCH);
2175
2176 msleep(5);
2177
2178 /* Switch off startup biases */
2179 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
2180 WM8994_BIAS_SRC |
2181 WM8994_STARTUP_BIAS_ENA |
2182 WM8994_VMID_BUF_ENA |
2183 WM8994_VMID_RAMP_MASK, 0);
2184
2185 pm_runtime_put(codec->dev);
2186 }
2187 break;
2188 }
2189 codec->dapm.bias_level = level;
2190 return 0;
2191 }
2192
2193 static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2194 {
2195 struct snd_soc_codec *codec = dai->codec;
2196 struct wm8994 *control = codec->control_data;
2197 int ms_reg;
2198 int aif1_reg;
2199 int ms = 0;
2200 int aif1 = 0;
2201
2202 switch (dai->id) {
2203 case 1:
2204 ms_reg = WM8994_AIF1_MASTER_SLAVE;
2205 aif1_reg = WM8994_AIF1_CONTROL_1;
2206 break;
2207 case 2:
2208 ms_reg = WM8994_AIF2_MASTER_SLAVE;
2209 aif1_reg = WM8994_AIF2_CONTROL_1;
2210 break;
2211 default:
2212 return -EINVAL;
2213 }
2214
2215 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2216 case SND_SOC_DAIFMT_CBS_CFS:
2217 break;
2218 case SND_SOC_DAIFMT_CBM_CFM:
2219 ms = WM8994_AIF1_MSTR;
2220 break;
2221 default:
2222 return -EINVAL;
2223 }
2224
2225 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2226 case SND_SOC_DAIFMT_DSP_B:
2227 aif1 |= WM8994_AIF1_LRCLK_INV;
2228 case SND_SOC_DAIFMT_DSP_A:
2229 aif1 |= 0x18;
2230 break;
2231 case SND_SOC_DAIFMT_I2S:
2232 aif1 |= 0x10;
2233 break;
2234 case SND_SOC_DAIFMT_RIGHT_J:
2235 break;
2236 case SND_SOC_DAIFMT_LEFT_J:
2237 aif1 |= 0x8;
2238 break;
2239 default:
2240 return -EINVAL;
2241 }
2242
2243 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2244 case SND_SOC_DAIFMT_DSP_A:
2245 case SND_SOC_DAIFMT_DSP_B:
2246 /* frame inversion not valid for DSP modes */
2247 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2248 case SND_SOC_DAIFMT_NB_NF:
2249 break;
2250 case SND_SOC_DAIFMT_IB_NF:
2251 aif1 |= WM8994_AIF1_BCLK_INV;
2252 break;
2253 default:
2254 return -EINVAL;
2255 }
2256 break;
2257
2258 case SND_SOC_DAIFMT_I2S:
2259 case SND_SOC_DAIFMT_RIGHT_J:
2260 case SND_SOC_DAIFMT_LEFT_J:
2261 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2262 case SND_SOC_DAIFMT_NB_NF:
2263 break;
2264 case SND_SOC_DAIFMT_IB_IF:
2265 aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
2266 break;
2267 case SND_SOC_DAIFMT_IB_NF:
2268 aif1 |= WM8994_AIF1_BCLK_INV;
2269 break;
2270 case SND_SOC_DAIFMT_NB_IF:
2271 aif1 |= WM8994_AIF1_LRCLK_INV;
2272 break;
2273 default:
2274 return -EINVAL;
2275 }
2276 break;
2277 default:
2278 return -EINVAL;
2279 }
2280
2281 /* The AIF2 format configuration needs to be mirrored to AIF3
2282 * on WM8958 if it's in use so just do it all the time. */
2283 if (control->type == WM8958 && dai->id == 2)
2284 snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2285 WM8994_AIF1_LRCLK_INV |
2286 WM8958_AIF3_FMT_MASK, aif1);
2287
2288 snd_soc_update_bits(codec, aif1_reg,
2289 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2290 WM8994_AIF1_FMT_MASK,
2291 aif1);
2292 snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
2293 ms);
2294
2295 return 0;
2296 }
2297
2298 static struct {
2299 int val, rate;
2300 } srs[] = {
2301 { 0, 8000 },
2302 { 1, 11025 },
2303 { 2, 12000 },
2304 { 3, 16000 },
2305 { 4, 22050 },
2306 { 5, 24000 },
2307 { 6, 32000 },
2308 { 7, 44100 },
2309 { 8, 48000 },
2310 { 9, 88200 },
2311 { 10, 96000 },
2312 };
2313
2314 static int fs_ratios[] = {
2315 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2316 };
2317
2318 static int bclk_divs[] = {
2319 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2320 640, 880, 960, 1280, 1760, 1920
2321 };
2322
2323 static int wm8994_hw_params(struct snd_pcm_substream *substream,
2324 struct snd_pcm_hw_params *params,
2325 struct snd_soc_dai *dai)
2326 {
2327 struct snd_soc_codec *codec = dai->codec;
2328 struct wm8994 *control = codec->control_data;
2329 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2330 int aif1_reg;
2331 int aif2_reg;
2332 int bclk_reg;
2333 int lrclk_reg;
2334 int rate_reg;
2335 int aif1 = 0;
2336 int aif2 = 0;
2337 int bclk = 0;
2338 int lrclk = 0;
2339 int rate_val = 0;
2340 int id = dai->id - 1;
2341
2342 int i, cur_val, best_val, bclk_rate, best;
2343
2344 switch (dai->id) {
2345 case 1:
2346 aif1_reg = WM8994_AIF1_CONTROL_1;
2347 aif2_reg = WM8994_AIF1_CONTROL_2;
2348 bclk_reg = WM8994_AIF1_BCLK;
2349 rate_reg = WM8994_AIF1_RATE;
2350 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2351 wm8994->lrclk_shared[0]) {
2352 lrclk_reg = WM8994_AIF1DAC_LRCLK;
2353 } else {
2354 lrclk_reg = WM8994_AIF1ADC_LRCLK;
2355 dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2356 }
2357 break;
2358 case 2:
2359 aif1_reg = WM8994_AIF2_CONTROL_1;
2360 aif2_reg = WM8994_AIF2_CONTROL_2;
2361 bclk_reg = WM8994_AIF2_BCLK;
2362 rate_reg = WM8994_AIF2_RATE;
2363 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2364 wm8994->lrclk_shared[1]) {
2365 lrclk_reg = WM8994_AIF2DAC_LRCLK;
2366 } else {
2367 lrclk_reg = WM8994_AIF2ADC_LRCLK;
2368 dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2369 }
2370 break;
2371 case 3:
2372 switch (control->type) {
2373 case WM8958:
2374 aif1_reg = WM8958_AIF3_CONTROL_1;
2375 break;
2376 default:
2377 return 0;
2378 }
2379 default:
2380 return -EINVAL;
2381 }
2382
2383 bclk_rate = params_rate(params) * 2;
2384 switch (params_format(params)) {
2385 case SNDRV_PCM_FORMAT_S16_LE:
2386 bclk_rate *= 16;
2387 break;
2388 case SNDRV_PCM_FORMAT_S20_3LE:
2389 bclk_rate *= 20;
2390 aif1 |= 0x20;
2391 break;
2392 case SNDRV_PCM_FORMAT_S24_LE:
2393 bclk_rate *= 24;
2394 aif1 |= 0x40;
2395 break;
2396 case SNDRV_PCM_FORMAT_S32_LE:
2397 bclk_rate *= 32;
2398 aif1 |= 0x60;
2399 break;
2400 default:
2401 return -EINVAL;
2402 }
2403
2404 /* Try to find an appropriate sample rate; look for an exact match. */
2405 for (i = 0; i < ARRAY_SIZE(srs); i++)
2406 if (srs[i].rate == params_rate(params))
2407 break;
2408 if (i == ARRAY_SIZE(srs))
2409 return -EINVAL;
2410 rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2411
2412 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2413 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2414 dai->id, wm8994->aifclk[id], bclk_rate);
2415
2416 if (params_channels(params) == 1 &&
2417 (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2418 aif2 |= WM8994_AIF1_MONO;
2419
2420 if (wm8994->aifclk[id] == 0) {
2421 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2422 return -EINVAL;
2423 }
2424
2425 /* AIFCLK/fs ratio; look for a close match in either direction */
2426 best = 0;
2427 best_val = abs((fs_ratios[0] * params_rate(params))
2428 - wm8994->aifclk[id]);
2429 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2430 cur_val = abs((fs_ratios[i] * params_rate(params))
2431 - wm8994->aifclk[id]);
2432 if (cur_val >= best_val)
2433 continue;
2434 best = i;
2435 best_val = cur_val;
2436 }
2437 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2438 dai->id, fs_ratios[best]);
2439 rate_val |= best;
2440
2441 /* We may not get quite the right frequency if using
2442 * approximate clocks so look for the closest match that is
2443 * higher than the target (we need to ensure that there enough
2444 * BCLKs to clock out the samples).
2445 */
2446 best = 0;
2447 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
2448 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
2449 if (cur_val < 0) /* BCLK table is sorted */
2450 break;
2451 best = i;
2452 }
2453 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
2454 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2455 bclk_divs[best], bclk_rate);
2456 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2457
2458 lrclk = bclk_rate / params_rate(params);
2459 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2460 lrclk, bclk_rate / lrclk);
2461
2462 snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2463 snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
2464 snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2465 snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2466 lrclk);
2467 snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2468 WM8994_AIF1CLK_RATE_MASK, rate_val);
2469
2470 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2471 switch (dai->id) {
2472 case 1:
2473 wm8994->dac_rates[0] = params_rate(params);
2474 wm8994_set_retune_mobile(codec, 0);
2475 wm8994_set_retune_mobile(codec, 1);
2476 break;
2477 case 2:
2478 wm8994->dac_rates[1] = params_rate(params);
2479 wm8994_set_retune_mobile(codec, 2);
2480 break;
2481 }
2482 }
2483
2484 return 0;
2485 }
2486
2487 static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2488 struct snd_pcm_hw_params *params,
2489 struct snd_soc_dai *dai)
2490 {
2491 struct snd_soc_codec *codec = dai->codec;
2492 struct wm8994 *control = codec->control_data;
2493 int aif1_reg;
2494 int aif1 = 0;
2495
2496 switch (dai->id) {
2497 case 3:
2498 switch (control->type) {
2499 case WM8958:
2500 aif1_reg = WM8958_AIF3_CONTROL_1;
2501 break;
2502 default:
2503 return 0;
2504 }
2505 default:
2506 return 0;
2507 }
2508
2509 switch (params_format(params)) {
2510 case SNDRV_PCM_FORMAT_S16_LE:
2511 break;
2512 case SNDRV_PCM_FORMAT_S20_3LE:
2513 aif1 |= 0x20;
2514 break;
2515 case SNDRV_PCM_FORMAT_S24_LE:
2516 aif1 |= 0x40;
2517 break;
2518 case SNDRV_PCM_FORMAT_S32_LE:
2519 aif1 |= 0x60;
2520 break;
2521 default:
2522 return -EINVAL;
2523 }
2524
2525 return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2526 }
2527
2528 static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2529 {
2530 struct snd_soc_codec *codec = codec_dai->codec;
2531 int mute_reg;
2532 int reg;
2533
2534 switch (codec_dai->id) {
2535 case 1:
2536 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2537 break;
2538 case 2:
2539 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
2540 break;
2541 default:
2542 return -EINVAL;
2543 }
2544
2545 if (mute)
2546 reg = WM8994_AIF1DAC1_MUTE;
2547 else
2548 reg = 0;
2549
2550 snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
2551
2552 return 0;
2553 }
2554
2555 static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
2556 {
2557 struct snd_soc_codec *codec = codec_dai->codec;
2558 int reg, val, mask;
2559
2560 switch (codec_dai->id) {
2561 case 1:
2562 reg = WM8994_AIF1_MASTER_SLAVE;
2563 mask = WM8994_AIF1_TRI;
2564 break;
2565 case 2:
2566 reg = WM8994_AIF2_MASTER_SLAVE;
2567 mask = WM8994_AIF2_TRI;
2568 break;
2569 case 3:
2570 reg = WM8994_POWER_MANAGEMENT_6;
2571 mask = WM8994_AIF3_TRI;
2572 break;
2573 default:
2574 return -EINVAL;
2575 }
2576
2577 if (tristate)
2578 val = mask;
2579 else
2580 val = 0;
2581
2582 return snd_soc_update_bits(codec, reg, mask, val);
2583 }
2584
2585 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000
2586
2587 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2588 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2589
2590 static struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
2591 .set_sysclk = wm8994_set_dai_sysclk,
2592 .set_fmt = wm8994_set_dai_fmt,
2593 .hw_params = wm8994_hw_params,
2594 .digital_mute = wm8994_aif_mute,
2595 .set_pll = wm8994_set_fll,
2596 .set_tristate = wm8994_set_tristate,
2597 };
2598
2599 static struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
2600 .set_sysclk = wm8994_set_dai_sysclk,
2601 .set_fmt = wm8994_set_dai_fmt,
2602 .hw_params = wm8994_hw_params,
2603 .digital_mute = wm8994_aif_mute,
2604 .set_pll = wm8994_set_fll,
2605 .set_tristate = wm8994_set_tristate,
2606 };
2607
2608 static struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
2609 .hw_params = wm8994_aif3_hw_params,
2610 .set_tristate = wm8994_set_tristate,
2611 };
2612
2613 static struct snd_soc_dai_driver wm8994_dai[] = {
2614 {
2615 .name = "wm8994-aif1",
2616 .id = 1,
2617 .playback = {
2618 .stream_name = "AIF1 Playback",
2619 .channels_min = 1,
2620 .channels_max = 2,
2621 .rates = WM8994_RATES,
2622 .formats = WM8994_FORMATS,
2623 },
2624 .capture = {
2625 .stream_name = "AIF1 Capture",
2626 .channels_min = 1,
2627 .channels_max = 2,
2628 .rates = WM8994_RATES,
2629 .formats = WM8994_FORMATS,
2630 },
2631 .ops = &wm8994_aif1_dai_ops,
2632 },
2633 {
2634 .name = "wm8994-aif2",
2635 .id = 2,
2636 .playback = {
2637 .stream_name = "AIF2 Playback",
2638 .channels_min = 1,
2639 .channels_max = 2,
2640 .rates = WM8994_RATES,
2641 .formats = WM8994_FORMATS,
2642 },
2643 .capture = {
2644 .stream_name = "AIF2 Capture",
2645 .channels_min = 1,
2646 .channels_max = 2,
2647 .rates = WM8994_RATES,
2648 .formats = WM8994_FORMATS,
2649 },
2650 .ops = &wm8994_aif2_dai_ops,
2651 },
2652 {
2653 .name = "wm8994-aif3",
2654 .id = 3,
2655 .playback = {
2656 .stream_name = "AIF3 Playback",
2657 .channels_min = 1,
2658 .channels_max = 2,
2659 .rates = WM8994_RATES,
2660 .formats = WM8994_FORMATS,
2661 },
2662 .capture = {
2663 .stream_name = "AIF3 Capture",
2664 .channels_min = 1,
2665 .channels_max = 2,
2666 .rates = WM8994_RATES,
2667 .formats = WM8994_FORMATS,
2668 },
2669 .ops = &wm8994_aif3_dai_ops,
2670 }
2671 };
2672
2673 #ifdef CONFIG_PM
2674 static int wm8994_suspend(struct snd_soc_codec *codec, pm_message_t state)
2675 {
2676 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2677 int i, ret;
2678
2679 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2680 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
2681 sizeof(struct fll_config));
2682 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
2683 if (ret < 0)
2684 dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
2685 i + 1, ret);
2686 }
2687
2688 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
2689
2690 return 0;
2691 }
2692
2693 static int wm8994_resume(struct snd_soc_codec *codec)
2694 {
2695 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2696 int i, ret;
2697 unsigned int val, mask;
2698
2699 if (wm8994->revision < 4) {
2700 /* force a HW read */
2701 val = wm8994_reg_read(codec->control_data,
2702 WM8994_POWER_MANAGEMENT_5);
2703
2704 /* modify the cache only */
2705 codec->cache_only = 1;
2706 mask = WM8994_DAC1R_ENA | WM8994_DAC1L_ENA |
2707 WM8994_DAC2R_ENA | WM8994_DAC2L_ENA;
2708 val &= mask;
2709 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
2710 mask, val);
2711 codec->cache_only = 0;
2712 }
2713
2714 /* Restore the registers */
2715 ret = snd_soc_cache_sync(codec);
2716 if (ret != 0)
2717 dev_err(codec->dev, "Failed to sync cache: %d\n", ret);
2718
2719 wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2720
2721 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2722 if (!wm8994->fll_suspend[i].out)
2723 continue;
2724
2725 ret = _wm8994_set_fll(codec, i + 1,
2726 wm8994->fll_suspend[i].src,
2727 wm8994->fll_suspend[i].in,
2728 wm8994->fll_suspend[i].out);
2729 if (ret < 0)
2730 dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
2731 i + 1, ret);
2732 }
2733
2734 return 0;
2735 }
2736 #else
2737 #define wm8994_suspend NULL
2738 #define wm8994_resume NULL
2739 #endif
2740
2741 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
2742 {
2743 struct snd_soc_codec *codec = wm8994->codec;
2744 struct wm8994_pdata *pdata = wm8994->pdata;
2745 struct snd_kcontrol_new controls[] = {
2746 SOC_ENUM_EXT("AIF1.1 EQ Mode",
2747 wm8994->retune_mobile_enum,
2748 wm8994_get_retune_mobile_enum,
2749 wm8994_put_retune_mobile_enum),
2750 SOC_ENUM_EXT("AIF1.2 EQ Mode",
2751 wm8994->retune_mobile_enum,
2752 wm8994_get_retune_mobile_enum,
2753 wm8994_put_retune_mobile_enum),
2754 SOC_ENUM_EXT("AIF2 EQ Mode",
2755 wm8994->retune_mobile_enum,
2756 wm8994_get_retune_mobile_enum,
2757 wm8994_put_retune_mobile_enum),
2758 };
2759 int ret, i, j;
2760 const char **t;
2761
2762 /* We need an array of texts for the enum API but the number
2763 * of texts is likely to be less than the number of
2764 * configurations due to the sample rate dependency of the
2765 * configurations. */
2766 wm8994->num_retune_mobile_texts = 0;
2767 wm8994->retune_mobile_texts = NULL;
2768 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2769 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
2770 if (strcmp(pdata->retune_mobile_cfgs[i].name,
2771 wm8994->retune_mobile_texts[j]) == 0)
2772 break;
2773 }
2774
2775 if (j != wm8994->num_retune_mobile_texts)
2776 continue;
2777
2778 /* Expand the array... */
2779 t = krealloc(wm8994->retune_mobile_texts,
2780 sizeof(char *) *
2781 (wm8994->num_retune_mobile_texts + 1),
2782 GFP_KERNEL);
2783 if (t == NULL)
2784 continue;
2785
2786 /* ...store the new entry... */
2787 t[wm8994->num_retune_mobile_texts] =
2788 pdata->retune_mobile_cfgs[i].name;
2789
2790 /* ...and remember the new version. */
2791 wm8994->num_retune_mobile_texts++;
2792 wm8994->retune_mobile_texts = t;
2793 }
2794
2795 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
2796 wm8994->num_retune_mobile_texts);
2797
2798 wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
2799 wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
2800
2801 ret = snd_soc_add_controls(wm8994->codec, controls,
2802 ARRAY_SIZE(controls));
2803 if (ret != 0)
2804 dev_err(wm8994->codec->dev,
2805 "Failed to add ReTune Mobile controls: %d\n", ret);
2806 }
2807
2808 static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
2809 {
2810 struct snd_soc_codec *codec = wm8994->codec;
2811 struct wm8994_pdata *pdata = wm8994->pdata;
2812 int ret, i;
2813
2814 if (!pdata)
2815 return;
2816
2817 wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
2818 pdata->lineout2_diff,
2819 pdata->lineout1fb,
2820 pdata->lineout2fb,
2821 pdata->jd_scthr,
2822 pdata->jd_thr,
2823 pdata->micbias1_lvl,
2824 pdata->micbias2_lvl);
2825
2826 dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
2827
2828 if (pdata->num_drc_cfgs) {
2829 struct snd_kcontrol_new controls[] = {
2830 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
2831 wm8994_get_drc_enum, wm8994_put_drc_enum),
2832 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
2833 wm8994_get_drc_enum, wm8994_put_drc_enum),
2834 SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
2835 wm8994_get_drc_enum, wm8994_put_drc_enum),
2836 };
2837
2838 /* We need an array of texts for the enum API */
2839 wm8994->drc_texts = kmalloc(sizeof(char *)
2840 * pdata->num_drc_cfgs, GFP_KERNEL);
2841 if (!wm8994->drc_texts) {
2842 dev_err(wm8994->codec->dev,
2843 "Failed to allocate %d DRC config texts\n",
2844 pdata->num_drc_cfgs);
2845 return;
2846 }
2847
2848 for (i = 0; i < pdata->num_drc_cfgs; i++)
2849 wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
2850
2851 wm8994->drc_enum.max = pdata->num_drc_cfgs;
2852 wm8994->drc_enum.texts = wm8994->drc_texts;
2853
2854 ret = snd_soc_add_controls(wm8994->codec, controls,
2855 ARRAY_SIZE(controls));
2856 if (ret != 0)
2857 dev_err(wm8994->codec->dev,
2858 "Failed to add DRC mode controls: %d\n", ret);
2859
2860 for (i = 0; i < WM8994_NUM_DRC; i++)
2861 wm8994_set_drc(codec, i);
2862 }
2863
2864 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
2865 pdata->num_retune_mobile_cfgs);
2866
2867 if (pdata->num_mbc_cfgs) {
2868 struct snd_kcontrol_new control[] = {
2869 SOC_ENUM_EXT("MBC Mode", wm8994->mbc_enum,
2870 wm8958_get_mbc_enum, wm8958_put_mbc_enum),
2871 };
2872
2873 /* We need an array of texts for the enum API */
2874 wm8994->mbc_texts = kmalloc(sizeof(char *)
2875 * pdata->num_mbc_cfgs, GFP_KERNEL);
2876 if (!wm8994->mbc_texts) {
2877 dev_err(wm8994->codec->dev,
2878 "Failed to allocate %d MBC config texts\n",
2879 pdata->num_mbc_cfgs);
2880 return;
2881 }
2882
2883 for (i = 0; i < pdata->num_mbc_cfgs; i++)
2884 wm8994->mbc_texts[i] = pdata->mbc_cfgs[i].name;
2885
2886 wm8994->mbc_enum.max = pdata->num_mbc_cfgs;
2887 wm8994->mbc_enum.texts = wm8994->mbc_texts;
2888
2889 ret = snd_soc_add_controls(wm8994->codec, control, 1);
2890 if (ret != 0)
2891 dev_err(wm8994->codec->dev,
2892 "Failed to add MBC mode controls: %d\n", ret);
2893 }
2894
2895 if (pdata->num_retune_mobile_cfgs)
2896 wm8994_handle_retune_mobile_pdata(wm8994);
2897 else
2898 snd_soc_add_controls(wm8994->codec, wm8994_eq_controls,
2899 ARRAY_SIZE(wm8994_eq_controls));
2900
2901 for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
2902 if (pdata->micbias[i]) {
2903 snd_soc_write(codec, WM8958_MICBIAS1 + i,
2904 pdata->micbias[i] & 0xffff);
2905 }
2906 }
2907 }
2908
2909 /**
2910 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
2911 *
2912 * @codec: WM8994 codec
2913 * @jack: jack to report detection events on
2914 * @micbias: microphone bias to detect on
2915 * @det: value to report for presence detection
2916 * @shrt: value to report for short detection
2917 *
2918 * Enable microphone detection via IRQ on the WM8994. If GPIOs are
2919 * being used to bring out signals to the processor then only platform
2920 * data configuration is needed for WM8994 and processor GPIOs should
2921 * be configured using snd_soc_jack_add_gpios() instead.
2922 *
2923 * Configuration of detection levels is available via the micbias1_lvl
2924 * and micbias2_lvl platform data members.
2925 */
2926 int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2927 int micbias, int det, int shrt)
2928 {
2929 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2930 struct wm8994_micdet *micdet;
2931 struct wm8994 *control = codec->control_data;
2932 int reg;
2933
2934 if (control->type != WM8994)
2935 return -EINVAL;
2936
2937 switch (micbias) {
2938 case 1:
2939 micdet = &wm8994->micdet[0];
2940 break;
2941 case 2:
2942 micdet = &wm8994->micdet[1];
2943 break;
2944 default:
2945 return -EINVAL;
2946 }
2947
2948 dev_dbg(codec->dev, "Configuring microphone detection on %d: %x %x\n",
2949 micbias, det, shrt);
2950
2951 /* Store the configuration */
2952 micdet->jack = jack;
2953 micdet->det = det;
2954 micdet->shrt = shrt;
2955
2956 /* If either of the jacks is set up then enable detection */
2957 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
2958 reg = WM8994_MICD_ENA;
2959 else
2960 reg = 0;
2961
2962 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
2963
2964 return 0;
2965 }
2966 EXPORT_SYMBOL_GPL(wm8994_mic_detect);
2967
2968 static irqreturn_t wm8994_mic_irq(int irq, void *data)
2969 {
2970 struct wm8994_priv *priv = data;
2971 struct snd_soc_codec *codec = priv->codec;
2972 int reg;
2973 int report;
2974
2975 #ifndef CONFIG_SND_SOC_WM8994_MODULE
2976 trace_snd_soc_jack_irq(dev_name(codec->dev));
2977 #endif
2978
2979 reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2);
2980 if (reg < 0) {
2981 dev_err(codec->dev, "Failed to read microphone status: %d\n",
2982 reg);
2983 return IRQ_HANDLED;
2984 }
2985
2986 dev_dbg(codec->dev, "Microphone status: %x\n", reg);
2987
2988 report = 0;
2989 if (reg & WM8994_MIC1_DET_STS)
2990 report |= priv->micdet[0].det;
2991 if (reg & WM8994_MIC1_SHRT_STS)
2992 report |= priv->micdet[0].shrt;
2993 snd_soc_jack_report(priv->micdet[0].jack, report,
2994 priv->micdet[0].det | priv->micdet[0].shrt);
2995
2996 report = 0;
2997 if (reg & WM8994_MIC2_DET_STS)
2998 report |= priv->micdet[1].det;
2999 if (reg & WM8994_MIC2_SHRT_STS)
3000 report |= priv->micdet[1].shrt;
3001 snd_soc_jack_report(priv->micdet[1].jack, report,
3002 priv->micdet[1].det | priv->micdet[1].shrt);
3003
3004 return IRQ_HANDLED;
3005 }
3006
3007 /* Default microphone detection handler for WM8958 - the user can
3008 * override this if they wish.
3009 */
3010 static void wm8958_default_micdet(u16 status, void *data)
3011 {
3012 struct snd_soc_codec *codec = data;
3013 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3014 int report = 0;
3015
3016 /* If nothing present then clear our statuses */
3017 if (!(status & WM8958_MICD_STS))
3018 goto done;
3019
3020 report = SND_JACK_MICROPHONE;
3021
3022 /* Everything else is buttons; just assign slots */
3023 if (status & 0x1c0)
3024 report |= SND_JACK_BTN_0;
3025
3026 done:
3027 snd_soc_jack_report(wm8994->micdet[0].jack, report,
3028 SND_JACK_BTN_0 | SND_JACK_MICROPHONE);
3029 }
3030
3031 /**
3032 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
3033 *
3034 * @codec: WM8958 codec
3035 * @jack: jack to report detection events on
3036 *
3037 * Enable microphone detection functionality for the WM8958. By
3038 * default simple detection which supports the detection of up to 6
3039 * buttons plus video and microphone functionality is supported.
3040 *
3041 * The WM8958 has an advanced jack detection facility which is able to
3042 * support complex accessory detection, especially when used in
3043 * conjunction with external circuitry. In order to provide maximum
3044 * flexiblity a callback is provided which allows a completely custom
3045 * detection algorithm.
3046 */
3047 int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3048 wm8958_micdet_cb cb, void *cb_data)
3049 {
3050 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3051 struct wm8994 *control = codec->control_data;
3052
3053 if (control->type != WM8958)
3054 return -EINVAL;
3055
3056 if (jack) {
3057 if (!cb) {
3058 dev_dbg(codec->dev, "Using default micdet callback\n");
3059 cb = wm8958_default_micdet;
3060 cb_data = codec;
3061 }
3062
3063 wm8994->micdet[0].jack = jack;
3064 wm8994->jack_cb = cb;
3065 wm8994->jack_cb_data = cb_data;
3066
3067 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3068 WM8958_MICD_ENA, WM8958_MICD_ENA);
3069 } else {
3070 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3071 WM8958_MICD_ENA, 0);
3072 }
3073
3074 return 0;
3075 }
3076 EXPORT_SYMBOL_GPL(wm8958_mic_detect);
3077
3078 static irqreturn_t wm8958_mic_irq(int irq, void *data)
3079 {
3080 struct wm8994_priv *wm8994 = data;
3081 struct snd_soc_codec *codec = wm8994->codec;
3082 int reg;
3083
3084 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
3085 if (reg < 0) {
3086 dev_err(codec->dev, "Failed to read mic detect status: %d\n",
3087 reg);
3088 return IRQ_NONE;
3089 }
3090
3091 if (!(reg & WM8958_MICD_VALID)) {
3092 dev_dbg(codec->dev, "Mic detect data not valid\n");
3093 goto out;
3094 }
3095
3096 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3097 trace_snd_soc_jack_irq(dev_name(codec->dev));
3098 #endif
3099
3100 if (wm8994->jack_cb)
3101 wm8994->jack_cb(reg, wm8994->jack_cb_data);
3102 else
3103 dev_warn(codec->dev, "Accessory detection with no callback\n");
3104
3105 out:
3106 return IRQ_HANDLED;
3107 }
3108
3109 static int wm8994_codec_probe(struct snd_soc_codec *codec)
3110 {
3111 struct wm8994 *control;
3112 struct wm8994_priv *wm8994;
3113 struct snd_soc_dapm_context *dapm = &codec->dapm;
3114 int ret, i;
3115
3116 codec->control_data = dev_get_drvdata(codec->dev->parent);
3117 control = codec->control_data;
3118
3119 wm8994 = kzalloc(sizeof(struct wm8994_priv), GFP_KERNEL);
3120 if (wm8994 == NULL)
3121 return -ENOMEM;
3122 snd_soc_codec_set_drvdata(codec, wm8994);
3123
3124 wm8994->pdata = dev_get_platdata(codec->dev->parent);
3125 wm8994->codec = codec;
3126
3127 if (wm8994->pdata && wm8994->pdata->micdet_irq)
3128 wm8994->micdet_irq = wm8994->pdata->micdet_irq;
3129 else if (wm8994->pdata && wm8994->pdata->irq_base)
3130 wm8994->micdet_irq = wm8994->pdata->irq_base +
3131 WM8994_IRQ_MIC1_DET;
3132
3133 pm_runtime_enable(codec->dev);
3134 pm_runtime_resume(codec->dev);
3135
3136 /* Read our current status back from the chip - we don't want to
3137 * reset as this may interfere with the GPIO or LDO operation. */
3138 for (i = 0; i < WM8994_CACHE_SIZE; i++) {
3139 if (!wm8994_readable(codec, i) || wm8994_volatile(codec, i))
3140 continue;
3141
3142 ret = wm8994_reg_read(codec->control_data, i);
3143 if (ret <= 0)
3144 continue;
3145
3146 ret = snd_soc_cache_write(codec, i, ret);
3147 if (ret != 0) {
3148 dev_err(codec->dev,
3149 "Failed to initialise cache for 0x%x: %d\n",
3150 i, ret);
3151 goto err;
3152 }
3153 }
3154
3155 /* Set revision-specific configuration */
3156 wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION);
3157 switch (control->type) {
3158 case WM8994:
3159 switch (wm8994->revision) {
3160 case 2:
3161 case 3:
3162 wm8994->hubs.dcs_codes = -5;
3163 wm8994->hubs.hp_startup_mode = 1;
3164 wm8994->hubs.dcs_readback_mode = 1;
3165 break;
3166 default:
3167 wm8994->hubs.dcs_readback_mode = 1;
3168 break;
3169 }
3170
3171 case WM8958:
3172 wm8994->hubs.dcs_readback_mode = 1;
3173 break;
3174
3175 default:
3176 break;
3177 }
3178
3179 switch (control->type) {
3180 case WM8994:
3181 if (wm8994->micdet_irq) {
3182 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3183 wm8994_mic_irq,
3184 IRQF_TRIGGER_RISING,
3185 "Mic1 detect",
3186 wm8994);
3187 if (ret != 0)
3188 dev_warn(codec->dev,
3189 "Failed to request Mic1 detect IRQ: %d\n",
3190 ret);
3191 }
3192
3193 ret = wm8994_request_irq(codec->control_data,
3194 WM8994_IRQ_MIC1_SHRT,
3195 wm8994_mic_irq, "Mic 1 short",
3196 wm8994);
3197 if (ret != 0)
3198 dev_warn(codec->dev,
3199 "Failed to request Mic1 short IRQ: %d\n",
3200 ret);
3201
3202 ret = wm8994_request_irq(codec->control_data,
3203 WM8994_IRQ_MIC2_DET,
3204 wm8994_mic_irq, "Mic 2 detect",
3205 wm8994);
3206 if (ret != 0)
3207 dev_warn(codec->dev,
3208 "Failed to request Mic2 detect IRQ: %d\n",
3209 ret);
3210
3211 ret = wm8994_request_irq(codec->control_data,
3212 WM8994_IRQ_MIC2_SHRT,
3213 wm8994_mic_irq, "Mic 2 short",
3214 wm8994);
3215 if (ret != 0)
3216 dev_warn(codec->dev,
3217 "Failed to request Mic2 short IRQ: %d\n",
3218 ret);
3219 break;
3220
3221 case WM8958:
3222 if (wm8994->micdet_irq) {
3223 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3224 wm8958_mic_irq,
3225 IRQF_TRIGGER_RISING,
3226 "Mic detect",
3227 wm8994);
3228 if (ret != 0)
3229 dev_warn(codec->dev,
3230 "Failed to request Mic detect IRQ: %d\n",
3231 ret);
3232 }
3233 }
3234
3235 /* Remember if AIFnLRCLK is configured as a GPIO. This should be
3236 * configured on init - if a system wants to do this dynamically
3237 * at runtime we can deal with that then.
3238 */
3239 ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_1);
3240 if (ret < 0) {
3241 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
3242 goto err_irq;
3243 }
3244 if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3245 wm8994->lrclk_shared[0] = 1;
3246 wm8994_dai[0].symmetric_rates = 1;
3247 } else {
3248 wm8994->lrclk_shared[0] = 0;
3249 }
3250
3251 ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_6);
3252 if (ret < 0) {
3253 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
3254 goto err_irq;
3255 }
3256 if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3257 wm8994->lrclk_shared[1] = 1;
3258 wm8994_dai[1].symmetric_rates = 1;
3259 } else {
3260 wm8994->lrclk_shared[1] = 0;
3261 }
3262
3263 wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
3264
3265 /* Latch volume updates (right only; we always do left then right). */
3266 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_LEFT_VOLUME,
3267 WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
3268 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_RIGHT_VOLUME,
3269 WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
3270 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_LEFT_VOLUME,
3271 WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
3272 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_RIGHT_VOLUME,
3273 WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
3274 snd_soc_update_bits(codec, WM8994_AIF2_DAC_LEFT_VOLUME,
3275 WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
3276 snd_soc_update_bits(codec, WM8994_AIF2_DAC_RIGHT_VOLUME,
3277 WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
3278 snd_soc_update_bits(codec, WM8994_AIF1_ADC1_LEFT_VOLUME,
3279 WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
3280 snd_soc_update_bits(codec, WM8994_AIF1_ADC1_RIGHT_VOLUME,
3281 WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
3282 snd_soc_update_bits(codec, WM8994_AIF1_ADC2_LEFT_VOLUME,
3283 WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
3284 snd_soc_update_bits(codec, WM8994_AIF1_ADC2_RIGHT_VOLUME,
3285 WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
3286 snd_soc_update_bits(codec, WM8994_AIF2_ADC_LEFT_VOLUME,
3287 WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
3288 snd_soc_update_bits(codec, WM8994_AIF2_ADC_RIGHT_VOLUME,
3289 WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
3290 snd_soc_update_bits(codec, WM8994_DAC1_LEFT_VOLUME,
3291 WM8994_DAC1_VU, WM8994_DAC1_VU);
3292 snd_soc_update_bits(codec, WM8994_DAC1_RIGHT_VOLUME,
3293 WM8994_DAC1_VU, WM8994_DAC1_VU);
3294 snd_soc_update_bits(codec, WM8994_DAC2_LEFT_VOLUME,
3295 WM8994_DAC2_VU, WM8994_DAC2_VU);
3296 snd_soc_update_bits(codec, WM8994_DAC2_RIGHT_VOLUME,
3297 WM8994_DAC2_VU, WM8994_DAC2_VU);
3298
3299 /* Set the low bit of the 3D stereo depth so TLV matches */
3300 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
3301 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
3302 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
3303 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
3304 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
3305 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
3306 snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
3307 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
3308 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
3309
3310 /* Unconditionally enable AIF1 ADC TDM mode; it only affects
3311 * behaviour on idle TDM clock cycles. */
3312 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
3313 WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
3314
3315 wm8994_update_class_w(codec);
3316
3317 wm8994_handle_pdata(wm8994);
3318
3319 wm_hubs_add_analogue_controls(codec);
3320 snd_soc_add_controls(codec, wm8994_snd_controls,
3321 ARRAY_SIZE(wm8994_snd_controls));
3322 snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
3323 ARRAY_SIZE(wm8994_dapm_widgets));
3324
3325 switch (control->type) {
3326 case WM8994:
3327 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
3328 ARRAY_SIZE(wm8994_specific_dapm_widgets));
3329 if (wm8994->revision < 4) {
3330 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3331 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
3332 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3333 ARRAY_SIZE(wm8994_adc_revd_widgets));
3334 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3335 ARRAY_SIZE(wm8994_dac_revd_widgets));
3336 } else {
3337 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3338 ARRAY_SIZE(wm8994_lateclk_widgets));
3339 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3340 ARRAY_SIZE(wm8994_adc_widgets));
3341 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3342 ARRAY_SIZE(wm8994_dac_widgets));
3343 }
3344 break;
3345 case WM8958:
3346 snd_soc_add_controls(codec, wm8958_snd_controls,
3347 ARRAY_SIZE(wm8958_snd_controls));
3348 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3349 ARRAY_SIZE(wm8994_lateclk_widgets));
3350 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3351 ARRAY_SIZE(wm8994_adc_widgets));
3352 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3353 ARRAY_SIZE(wm8994_dac_widgets));
3354 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
3355 ARRAY_SIZE(wm8958_dapm_widgets));
3356 break;
3357 }
3358
3359
3360 wm_hubs_add_analogue_routes(codec, 0, 0);
3361 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
3362
3363 switch (control->type) {
3364 case WM8994:
3365 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
3366 ARRAY_SIZE(wm8994_intercon));
3367
3368 if (wm8994->revision < 4) {
3369 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3370 ARRAY_SIZE(wm8994_revd_intercon));
3371 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3372 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3373 } else {
3374 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3375 ARRAY_SIZE(wm8994_lateclk_intercon));
3376 }
3377 break;
3378 case WM8958:
3379 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3380 ARRAY_SIZE(wm8994_lateclk_intercon));
3381 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
3382 ARRAY_SIZE(wm8958_intercon));
3383 break;
3384 }
3385
3386 return 0;
3387
3388 err_irq:
3389 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT, wm8994);
3390 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET, wm8994);
3391 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT, wm8994);
3392 if (wm8994->micdet_irq)
3393 free_irq(wm8994->micdet_irq, wm8994);
3394 err:
3395 kfree(wm8994);
3396 return ret;
3397 }
3398
3399 static int wm8994_codec_remove(struct snd_soc_codec *codec)
3400 {
3401 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3402 struct wm8994 *control = codec->control_data;
3403
3404 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
3405
3406 pm_runtime_disable(codec->dev);
3407
3408 switch (control->type) {
3409 case WM8994:
3410 if (wm8994->micdet_irq)
3411 free_irq(wm8994->micdet_irq, wm8994);
3412 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET,
3413 wm8994);
3414 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT,
3415 wm8994);
3416 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET,
3417 wm8994);
3418 break;
3419
3420 case WM8958:
3421 if (wm8994->micdet_irq)
3422 free_irq(wm8994->micdet_irq, wm8994);
3423 break;
3424 }
3425 kfree(wm8994->retune_mobile_texts);
3426 kfree(wm8994->drc_texts);
3427 kfree(wm8994);
3428
3429 return 0;
3430 }
3431
3432 static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
3433 .probe = wm8994_codec_probe,
3434 .remove = wm8994_codec_remove,
3435 .suspend = wm8994_suspend,
3436 .resume = wm8994_resume,
3437 .read = wm8994_read,
3438 .write = wm8994_write,
3439 .readable_register = wm8994_readable,
3440 .volatile_register = wm8994_volatile,
3441 .set_bias_level = wm8994_set_bias_level,
3442
3443 .reg_cache_size = WM8994_CACHE_SIZE,
3444 .reg_cache_default = wm8994_reg_defaults,
3445 .reg_word_size = 2,
3446 .compress_type = SND_SOC_RBTREE_COMPRESSION,
3447 };
3448
3449 static int __devinit wm8994_probe(struct platform_device *pdev)
3450 {
3451 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
3452 wm8994_dai, ARRAY_SIZE(wm8994_dai));
3453 }
3454
3455 static int __devexit wm8994_remove(struct platform_device *pdev)
3456 {
3457 snd_soc_unregister_codec(&pdev->dev);
3458 return 0;
3459 }
3460
3461 static struct platform_driver wm8994_codec_driver = {
3462 .driver = {
3463 .name = "wm8994-codec",
3464 .owner = THIS_MODULE,
3465 },
3466 .probe = wm8994_probe,
3467 .remove = __devexit_p(wm8994_remove),
3468 };
3469
3470 static __init int wm8994_init(void)
3471 {
3472 return platform_driver_register(&wm8994_codec_driver);
3473 }
3474 module_init(wm8994_init);
3475
3476 static __exit void wm8994_exit(void)
3477 {
3478 platform_driver_unregister(&wm8994_codec_driver);
3479 }
3480 module_exit(wm8994_exit);
3481
3482
3483 MODULE_DESCRIPTION("ASoC WM8994 driver");
3484 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
3485 MODULE_LICENSE("GPL");
3486 MODULE_ALIAS("platform:wm8994-codec");
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree