2 * linux/drivers/video/pxafb.c
4 * Copyright (C) 1999 Eric A. Thomas.
5 * Copyright (C) 2004 Jean-Frederic Clere.
6 * Copyright (C) 2004 Ian Campbell.
7 * Copyright (C) 2004 Jeff Lackey.
8 * Based on sa1100fb.c Copyright (C) 1999 Eric A. Thomas
10 * Based on acornfb.c Copyright (C) Russell King.
12 * This file is subject to the terms and conditions of the GNU General Public
13 * License. See the file COPYING in the main directory of this archive for
16 * Intel PXA250/210 LCD Controller Frame Buffer Driver
18 * Please direct your questions and comments on this driver to the following
21 * linux-arm-kernel@lists.arm.linux.org.uk
25 #include <linux/module.h>
26 #include <linux/moduleparam.h>
27 #include <linux/kernel.h>
28 #include <linux/sched.h>
29 #include <linux/errno.h>
30 #include <linux/string.h>
31 #include <linux/interrupt.h>
32 #include <linux/slab.h>
35 #include <linux/delay.h>
36 #include <linux/init.h>
37 #include <linux/ioport.h>
38 #include <linux/cpufreq.h>
39 #include <linux/platform_device.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/clk.h>
42 #include <linux/err.h>
43 #include <linux/completion.h>
44 #include <linux/kthread.h>
45 #include <linux/freezer.h>
47 #include <asm/hardware.h>
50 #include <asm/div64.h>
51 #include <asm/arch/pxa-regs.h>
52 #include <asm/arch/pxa2xx-gpio.h>
53 #include <asm/arch/bitfield.h>
54 #include <asm/arch/pxafb.h>
57 * Complain if VAR is out of range.
63 /* Bits which should not be set in machine configuration structures */
64 #define LCCR0_INVALID_CONFIG_MASK (LCCR0_OUM | LCCR0_BM | LCCR0_QDM |\
65 LCCR0_DIS | LCCR0_EFM | LCCR0_IUM |\
66 LCCR0_SFM | LCCR0_LDM | LCCR0_ENB)
68 #define LCCR3_INVALID_CONFIG_MASK (LCCR3_HSP | LCCR3_VSP |\
69 LCCR3_PCD | LCCR3_BPP)
71 static void (*pxafb_backlight_power
)(int);
72 static void (*pxafb_lcd_power
)(int, struct fb_var_screeninfo
*);
74 static int pxafb_activate_var(struct fb_var_screeninfo
*var
,
76 static void set_ctrlr_state(struct pxafb_info
*fbi
, u_int state
);
78 static inline unsigned long
79 lcd_readl(struct pxafb_info
*fbi
, unsigned int off
)
81 return __raw_readl(fbi
->mmio_base
+ off
);
85 lcd_writel(struct pxafb_info
*fbi
, unsigned int off
, unsigned long val
)
87 __raw_writel(val
, fbi
->mmio_base
+ off
);
90 static inline void pxafb_schedule_work(struct pxafb_info
*fbi
, u_int state
)
94 local_irq_save(flags
);
96 * We need to handle two requests being made at the same time.
97 * There are two important cases:
98 * 1. When we are changing VT (C_REENABLE) while unblanking
99 * (C_ENABLE) We must perform the unblanking, which will
100 * do our REENABLE for us.
101 * 2. When we are blanking, but immediately unblank before
102 * we have blanked. We do the "REENABLE" thing here as
103 * well, just to be sure.
105 if (fbi
->task_state
== C_ENABLE
&& state
== C_REENABLE
)
107 if (fbi
->task_state
== C_DISABLE
&& state
== C_ENABLE
)
110 if (state
!= (u_int
)-1) {
111 fbi
->task_state
= state
;
112 schedule_work(&fbi
->task
);
114 local_irq_restore(flags
);
117 static inline u_int
chan_to_field(u_int chan
, struct fb_bitfield
*bf
)
120 chan
>>= 16 - bf
->length
;
121 return chan
<< bf
->offset
;
125 pxafb_setpalettereg(u_int regno
, u_int red
, u_int green
, u_int blue
,
126 u_int trans
, struct fb_info
*info
)
128 struct pxafb_info
*fbi
= (struct pxafb_info
*)info
;
131 if (regno
>= fbi
->palette_size
)
134 if (fbi
->fb
.var
.grayscale
) {
135 fbi
->palette_cpu
[regno
] = ((blue
>> 8) & 0x00ff);
139 switch (fbi
->lccr4
& LCCR4_PAL_FOR_MASK
) {
140 case LCCR4_PAL_FOR_0
:
141 val
= ((red
>> 0) & 0xf800);
142 val
|= ((green
>> 5) & 0x07e0);
143 val
|= ((blue
>> 11) & 0x001f);
144 fbi
->palette_cpu
[regno
] = val
;
146 case LCCR4_PAL_FOR_1
:
147 val
= ((red
<< 8) & 0x00f80000);
148 val
|= ((green
>> 0) & 0x0000fc00);
149 val
|= ((blue
>> 8) & 0x000000f8);
150 ((u32
*)(fbi
->palette_cpu
))[regno
] = val
;
152 case LCCR4_PAL_FOR_2
:
153 val
= ((red
<< 8) & 0x00fc0000);
154 val
|= ((green
>> 0) & 0x0000fc00);
155 val
|= ((blue
>> 8) & 0x000000fc);
156 ((u32
*)(fbi
->palette_cpu
))[regno
] = val
;
164 pxafb_setcolreg(u_int regno
, u_int red
, u_int green
, u_int blue
,
165 u_int trans
, struct fb_info
*info
)
167 struct pxafb_info
*fbi
= (struct pxafb_info
*)info
;
172 * If inverse mode was selected, invert all the colours
173 * rather than the register number. The register number
174 * is what you poke into the framebuffer to produce the
175 * colour you requested.
177 if (fbi
->cmap_inverse
) {
179 green
= 0xffff - green
;
180 blue
= 0xffff - blue
;
184 * If greyscale is true, then we convert the RGB value
185 * to greyscale no matter what visual we are using.
187 if (fbi
->fb
.var
.grayscale
)
188 red
= green
= blue
= (19595 * red
+ 38470 * green
+
191 switch (fbi
->fb
.fix
.visual
) {
192 case FB_VISUAL_TRUECOLOR
:
194 * 16-bit True Colour. We encode the RGB value
195 * according to the RGB bitfield information.
198 u32
*pal
= fbi
->fb
.pseudo_palette
;
200 val
= chan_to_field(red
, &fbi
->fb
.var
.red
);
201 val
|= chan_to_field(green
, &fbi
->fb
.var
.green
);
202 val
|= chan_to_field(blue
, &fbi
->fb
.var
.blue
);
209 case FB_VISUAL_STATIC_PSEUDOCOLOR
:
210 case FB_VISUAL_PSEUDOCOLOR
:
211 ret
= pxafb_setpalettereg(regno
, red
, green
, blue
, trans
, info
);
219 * pxafb_bpp_to_lccr3():
220 * Convert a bits per pixel value to the correct bit pattern for LCCR3
222 static int pxafb_bpp_to_lccr3(struct fb_var_screeninfo
*var
)
225 switch (var
->bits_per_pixel
) {
226 case 1: ret
= LCCR3_1BPP
; break;
227 case 2: ret
= LCCR3_2BPP
; break;
228 case 4: ret
= LCCR3_4BPP
; break;
229 case 8: ret
= LCCR3_8BPP
; break;
230 case 16: ret
= LCCR3_16BPP
; break;
232 switch (var
->red
.length
+ var
->green
.length
+
233 var
->blue
.length
+ var
->transp
.length
) {
234 case 18: ret
= LCCR3_18BPP_P
| LCCR3_PDFOR_3
; break;
235 case 19: ret
= LCCR3_19BPP_P
; break;
239 switch (var
->red
.length
+ var
->green
.length
+
240 var
->blue
.length
+ var
->transp
.length
) {
241 case 18: ret
= LCCR3_18BPP
| LCCR3_PDFOR_3
; break;
242 case 19: ret
= LCCR3_19BPP
; break;
243 case 24: ret
= LCCR3_24BPP
| LCCR3_PDFOR_3
; break;
244 case 25: ret
= LCCR3_25BPP
; break;
251 #ifdef CONFIG_CPU_FREQ
253 * pxafb_display_dma_period()
254 * Calculate the minimum period (in picoseconds) between two DMA
255 * requests for the LCD controller. If we hit this, it means we're
256 * doing nothing but LCD DMA.
258 static unsigned int pxafb_display_dma_period(struct fb_var_screeninfo
*var
)
261 * Period = pixclock * bits_per_byte * bytes_per_transfer
262 * / memory_bits_per_pixel;
264 return var
->pixclock
* 8 * 16 / var
->bits_per_pixel
;
269 * Select the smallest mode that allows the desired resolution to be
270 * displayed. If desired parameters can be rounded up.
272 static struct pxafb_mode_info
*pxafb_getmode(struct pxafb_mach_info
*mach
,
273 struct fb_var_screeninfo
*var
)
275 struct pxafb_mode_info
*mode
= NULL
;
276 struct pxafb_mode_info
*modelist
= mach
->modes
;
277 unsigned int best_x
= 0xffffffff, best_y
= 0xffffffff;
280 for (i
= 0; i
< mach
->num_modes
; i
++) {
281 if (modelist
[i
].xres
>= var
->xres
&&
282 modelist
[i
].yres
>= var
->yres
&&
283 modelist
[i
].xres
< best_x
&&
284 modelist
[i
].yres
< best_y
&&
285 modelist
[i
].bpp
>= var
->bits_per_pixel
) {
286 best_x
= modelist
[i
].xres
;
287 best_y
= modelist
[i
].yres
;
295 static void pxafb_setmode(struct fb_var_screeninfo
*var
,
296 struct pxafb_mode_info
*mode
)
298 var
->xres
= mode
->xres
;
299 var
->yres
= mode
->yres
;
300 var
->bits_per_pixel
= mode
->bpp
;
301 var
->pixclock
= mode
->pixclock
;
302 var
->hsync_len
= mode
->hsync_len
;
303 var
->left_margin
= mode
->left_margin
;
304 var
->right_margin
= mode
->right_margin
;
305 var
->vsync_len
= mode
->vsync_len
;
306 var
->upper_margin
= mode
->upper_margin
;
307 var
->lower_margin
= mode
->lower_margin
;
308 var
->sync
= mode
->sync
;
309 var
->grayscale
= mode
->cmap_greyscale
;
310 var
->xres_virtual
= var
->xres
;
311 var
->yres_virtual
= var
->yres
;
316 * Get the video params out of 'var'. If a value doesn't fit, round it up,
317 * if it's too big, return -EINVAL.
319 * Round up in the following order: bits_per_pixel, xres,
320 * yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale,
321 * bitfields, horizontal timing, vertical timing.
323 static int pxafb_check_var(struct fb_var_screeninfo
*var
, struct fb_info
*info
)
325 struct pxafb_info
*fbi
= (struct pxafb_info
*)info
;
326 struct pxafb_mach_info
*inf
= fbi
->dev
->platform_data
;
328 if (var
->xres
< MIN_XRES
)
329 var
->xres
= MIN_XRES
;
330 if (var
->yres
< MIN_YRES
)
331 var
->yres
= MIN_YRES
;
333 if (inf
->fixed_modes
) {
334 struct pxafb_mode_info
*mode
;
336 mode
= pxafb_getmode(inf
, var
);
339 pxafb_setmode(var
, mode
);
341 if (var
->xres
> inf
->modes
->xres
)
343 if (var
->yres
> inf
->modes
->yres
)
345 if (var
->bits_per_pixel
> inf
->modes
->bpp
)
350 max(var
->xres_virtual
, var
->xres
);
352 max(var
->yres_virtual
, var
->yres
);
355 * Setup the RGB parameters for this display.
357 * The pixel packing format is described on page 7-11 of the
358 * PXA2XX Developer's Manual.
360 if (var
->bits_per_pixel
== 16) {
361 var
->red
.offset
= 11; var
->red
.length
= 5;
362 var
->green
.offset
= 5; var
->green
.length
= 6;
363 var
->blue
.offset
= 0; var
->blue
.length
= 5;
364 var
->transp
.offset
= var
->transp
.length
= 0;
365 } else if (var
->bits_per_pixel
> 16) {
366 struct pxafb_mode_info
*mode
;
368 mode
= pxafb_getmode(inf
, var
);
372 switch (mode
->depth
) {
373 case 18: /* RGB666 */
374 var
->transp
.offset
= var
->transp
.length
= 0;
375 var
->red
.offset
= 12; var
->red
.length
= 6;
376 var
->green
.offset
= 6; var
->green
.length
= 6;
377 var
->blue
.offset
= 0; var
->blue
.length
= 6;
379 case 19: /* RGBT666 */
380 var
->transp
.offset
= 18; var
->transp
.length
= 1;
381 var
->red
.offset
= 12; var
->red
.length
= 6;
382 var
->green
.offset
= 6; var
->green
.length
= 6;
383 var
->blue
.offset
= 0; var
->blue
.length
= 6;
385 case 24: /* RGB888 */
386 var
->transp
.offset
= var
->transp
.length
= 0;
387 var
->red
.offset
= 16; var
->red
.length
= 8;
388 var
->green
.offset
= 8; var
->green
.length
= 8;
389 var
->blue
.offset
= 0; var
->blue
.length
= 8;
391 case 25: /* RGBT888 */
392 var
->transp
.offset
= 24; var
->transp
.length
= 1;
393 var
->red
.offset
= 16; var
->red
.length
= 8;
394 var
->green
.offset
= 8; var
->green
.length
= 8;
395 var
->blue
.offset
= 0; var
->blue
.length
= 8;
401 var
->red
.offset
= var
->green
.offset
= 0;
402 var
->blue
.offset
= var
->transp
.offset
= 0;
404 var
->green
.length
= 8;
405 var
->blue
.length
= 8;
406 var
->transp
.length
= 0;
409 #ifdef CONFIG_CPU_FREQ
410 pr_debug("pxafb: dma period = %d ps\n",
411 pxafb_display_dma_period(var
));
417 static inline void pxafb_set_truecolor(u_int is_true_color
)
419 /* do your machine-specific setup if needed */
424 * Set the user defined part of the display for the specified console
426 static int pxafb_set_par(struct fb_info
*info
)
428 struct pxafb_info
*fbi
= (struct pxafb_info
*)info
;
429 struct fb_var_screeninfo
*var
= &info
->var
;
431 if (var
->bits_per_pixel
>= 16)
432 fbi
->fb
.fix
.visual
= FB_VISUAL_TRUECOLOR
;
433 else if (!fbi
->cmap_static
)
434 fbi
->fb
.fix
.visual
= FB_VISUAL_PSEUDOCOLOR
;
437 * Some people have weird ideas about wanting static
438 * pseudocolor maps. I suspect their user space
439 * applications are broken.
441 fbi
->fb
.fix
.visual
= FB_VISUAL_STATIC_PSEUDOCOLOR
;
444 fbi
->fb
.fix
.line_length
= var
->xres_virtual
*
445 var
->bits_per_pixel
/ 8;
446 if (var
->bits_per_pixel
>= 16)
447 fbi
->palette_size
= 0;
449 fbi
->palette_size
= var
->bits_per_pixel
== 1 ?
450 4 : 1 << var
->bits_per_pixel
;
452 fbi
->palette_cpu
= (u16
*)&fbi
->dma_buff
->palette
[0];
455 * Set (any) board control register to handle new color depth
457 pxafb_set_truecolor(fbi
->fb
.fix
.visual
== FB_VISUAL_TRUECOLOR
);
459 if (fbi
->fb
.var
.bits_per_pixel
>= 16)
460 fb_dealloc_cmap(&fbi
->fb
.cmap
);
462 fb_alloc_cmap(&fbi
->fb
.cmap
, 1<<fbi
->fb
.var
.bits_per_pixel
, 0);
464 pxafb_activate_var(var
, fbi
);
471 * Blank the display by setting all palette values to zero. Note, the
472 * 16 bpp mode does not really use the palette, so this will not
473 * blank the display in all modes.
475 static int pxafb_blank(int blank
, struct fb_info
*info
)
477 struct pxafb_info
*fbi
= (struct pxafb_info
*)info
;
481 case FB_BLANK_POWERDOWN
:
482 case FB_BLANK_VSYNC_SUSPEND
:
483 case FB_BLANK_HSYNC_SUSPEND
:
484 case FB_BLANK_NORMAL
:
485 if (fbi
->fb
.fix
.visual
== FB_VISUAL_PSEUDOCOLOR
||
486 fbi
->fb
.fix
.visual
== FB_VISUAL_STATIC_PSEUDOCOLOR
)
487 for (i
= 0; i
< fbi
->palette_size
; i
++)
488 pxafb_setpalettereg(i
, 0, 0, 0, 0, info
);
490 pxafb_schedule_work(fbi
, C_DISABLE
);
491 /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */
494 case FB_BLANK_UNBLANK
:
495 /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */
496 if (fbi
->fb
.fix
.visual
== FB_VISUAL_PSEUDOCOLOR
||
497 fbi
->fb
.fix
.visual
== FB_VISUAL_STATIC_PSEUDOCOLOR
)
498 fb_set_cmap(&fbi
->fb
.cmap
, info
);
499 pxafb_schedule_work(fbi
, C_ENABLE
);
504 static int pxafb_mmap(struct fb_info
*info
,
505 struct vm_area_struct
*vma
)
507 struct pxafb_info
*fbi
= (struct pxafb_info
*)info
;
508 unsigned long off
= vma
->vm_pgoff
<< PAGE_SHIFT
;
510 if (off
< info
->fix
.smem_len
) {
511 vma
->vm_pgoff
+= fbi
->video_offset
/ PAGE_SIZE
;
512 return dma_mmap_writecombine(fbi
->dev
, vma
, fbi
->map_cpu
,
513 fbi
->map_dma
, fbi
->map_size
);
518 static struct fb_ops pxafb_ops
= {
519 .owner
= THIS_MODULE
,
520 .fb_check_var
= pxafb_check_var
,
521 .fb_set_par
= pxafb_set_par
,
522 .fb_setcolreg
= pxafb_setcolreg
,
523 .fb_fillrect
= cfb_fillrect
,
524 .fb_copyarea
= cfb_copyarea
,
525 .fb_imageblit
= cfb_imageblit
,
526 .fb_blank
= pxafb_blank
,
527 .fb_mmap
= pxafb_mmap
,
531 * Calculate the PCD value from the clock rate (in picoseconds).
532 * We take account of the PPCR clock setting.
533 * From PXA Developer's Manual:
544 * LCLK = LCD/Memory Clock
547 * PixelClock here is in Hz while the pixclock argument given is the
548 * period in picoseconds. Hence PixelClock = 1 / ( pixclock * 10^-12 )
550 * The function get_lclk_frequency_10khz returns LCLK in units of
551 * 10khz. Calling the result of this function lclk gives us the
554 * PCD = (lclk * 10^4 ) * ( pixclock * 10^-12 )
555 * -------------------------------------- - 1
558 * Factoring the 10^4 and 10^-12 out gives 10^-8 == 1 / 100000000 as used below.
560 static inline unsigned int get_pcd(struct pxafb_info
*fbi
,
561 unsigned int pixclock
)
563 unsigned long long pcd
;
565 /* FIXME: Need to take into account Double Pixel Clock mode
566 * (DPC) bit? or perhaps set it based on the various clock
568 pcd
= (unsigned long long)(clk_get_rate(fbi
->clk
) / 10000);
570 do_div(pcd
, 100000000 * 2);
571 /* no need for this, since we should subtract 1 anyway. they cancel */
572 /* pcd += 1; */ /* make up for integer math truncations */
573 return (unsigned int)pcd
;
577 * Some touchscreens need hsync information from the video driver to
578 * function correctly. We export it here. Note that 'hsync_time' and
579 * the value returned from pxafb_get_hsync_time() is the *reciprocal*
580 * of the hsync period in seconds.
582 static inline void set_hsync_time(struct pxafb_info
*fbi
, unsigned int pcd
)
586 if ((pcd
== 0) || (fbi
->fb
.var
.hsync_len
== 0)) {
591 htime
= clk_get_rate(fbi
->clk
) / (pcd
* fbi
->fb
.var
.hsync_len
);
593 fbi
->hsync_time
= htime
;
596 unsigned long pxafb_get_hsync_time(struct device
*dev
)
598 struct pxafb_info
*fbi
= dev_get_drvdata(dev
);
600 /* If display is blanked/suspended, hsync isn't active */
601 if (!fbi
|| (fbi
->state
!= C_ENABLE
))
604 return fbi
->hsync_time
;
606 EXPORT_SYMBOL(pxafb_get_hsync_time
);
608 static int setup_frame_dma(struct pxafb_info
*fbi
, int dma
, int pal
,
609 unsigned int offset
, size_t size
)
611 struct pxafb_dma_descriptor
*dma_desc
, *pal_desc
;
612 unsigned int dma_desc_off
, pal_desc_off
;
614 if (dma
< 0 || dma
>= DMA_MAX
)
617 dma_desc
= &fbi
->dma_buff
->dma_desc
[dma
];
618 dma_desc_off
= offsetof(struct pxafb_dma_buff
, dma_desc
[dma
]);
620 dma_desc
->fsadr
= fbi
->screen_dma
+ offset
;
622 dma_desc
->ldcmd
= size
;
624 if (pal
< 0 || pal
>= PAL_MAX
) {
625 dma_desc
->fdadr
= fbi
->dma_buff_phys
+ dma_desc_off
;
626 fbi
->fdadr
[dma
] = fbi
->dma_buff_phys
+ dma_desc_off
;
628 pal_desc
= &fbi
->dma_buff
->pal_desc
[pal
];
629 pal_desc_off
= offsetof(struct pxafb_dma_buff
, pal_desc
[pal
]);
631 pal_desc
->fsadr
= fbi
->dma_buff_phys
+ pal
* PALETTE_SIZE
;
634 if ((fbi
->lccr4
& LCCR4_PAL_FOR_MASK
) == LCCR4_PAL_FOR_0
)
635 pal_desc
->ldcmd
= fbi
->palette_size
* sizeof(u16
);
637 pal_desc
->ldcmd
= fbi
->palette_size
* sizeof(u32
);
639 pal_desc
->ldcmd
|= LDCMD_PAL
;
641 /* flip back and forth between palette and frame buffer */
642 pal_desc
->fdadr
= fbi
->dma_buff_phys
+ dma_desc_off
;
643 dma_desc
->fdadr
= fbi
->dma_buff_phys
+ pal_desc_off
;
644 fbi
->fdadr
[dma
] = fbi
->dma_buff_phys
+ dma_desc_off
;
650 #ifdef CONFIG_FB_PXA_SMARTPANEL
651 static int setup_smart_dma(struct pxafb_info
*fbi
)
653 struct pxafb_dma_descriptor
*dma_desc
;
654 unsigned long dma_desc_off
, cmd_buff_off
;
656 dma_desc
= &fbi
->dma_buff
->dma_desc
[DMA_CMD
];
657 dma_desc_off
= offsetof(struct pxafb_dma_buff
, dma_desc
[DMA_CMD
]);
658 cmd_buff_off
= offsetof(struct pxafb_dma_buff
, cmd_buff
);
660 dma_desc
->fdadr
= fbi
->dma_buff_phys
+ dma_desc_off
;
661 dma_desc
->fsadr
= fbi
->dma_buff_phys
+ cmd_buff_off
;
663 dma_desc
->ldcmd
= fbi
->n_smart_cmds
* sizeof(uint16_t);
665 fbi
->fdadr
[DMA_CMD
] = dma_desc
->fdadr
;
669 int pxafb_smart_flush(struct fb_info
*info
)
671 struct pxafb_info
*fbi
= container_of(info
, struct pxafb_info
, fb
);
675 /* disable controller until all registers are set up */
676 lcd_writel(fbi
, LCCR0
, fbi
->reg_lccr0
& ~LCCR0_ENB
);
678 /* 1. make it an even number of commands to align on 32-bit boundary
679 * 2. add the interrupt command to the end of the chain so we can
680 * keep track of the end of the transfer
683 while (fbi
->n_smart_cmds
& 1)
684 fbi
->smart_cmds
[fbi
->n_smart_cmds
++] = SMART_CMD_NOOP
;
686 fbi
->smart_cmds
[fbi
->n_smart_cmds
++] = SMART_CMD_INTERRUPT
;
687 fbi
->smart_cmds
[fbi
->n_smart_cmds
++] = SMART_CMD_WAIT_FOR_VSYNC
;
688 setup_smart_dma(fbi
);
690 /* continue to execute next command */
691 prsr
= lcd_readl(fbi
, PRSR
) | PRSR_ST_OK
| PRSR_CON_NT
;
692 lcd_writel(fbi
, PRSR
, prsr
);
694 /* stop the processor in case it executed "wait for sync" cmd */
695 lcd_writel(fbi
, CMDCR
, 0x0001);
697 /* don't send interrupts for fifo underruns on channel 6 */
698 lcd_writel(fbi
, LCCR5
, LCCR5_IUM(6));
700 lcd_writel(fbi
, LCCR1
, fbi
->reg_lccr1
);
701 lcd_writel(fbi
, LCCR2
, fbi
->reg_lccr2
);
702 lcd_writel(fbi
, LCCR3
, fbi
->reg_lccr3
);
703 lcd_writel(fbi
, FDADR0
, fbi
->fdadr
[0]);
704 lcd_writel(fbi
, FDADR6
, fbi
->fdadr
[6]);
707 lcd_writel(fbi
, LCCR0
, fbi
->reg_lccr0
| LCCR0_ENB
);
709 if (wait_for_completion_timeout(&fbi
->command_done
, HZ
/2) == 0) {
710 pr_warning("%s: timeout waiting for command done\n",
716 prsr
= lcd_readl(fbi
, PRSR
) & ~(PRSR_ST_OK
| PRSR_CON_NT
);
717 lcd_writel(fbi
, PRSR
, prsr
);
718 lcd_writel(fbi
, LCCR0
, fbi
->reg_lccr0
& ~LCCR0_ENB
);
719 lcd_writel(fbi
, FDADR6
, 0);
720 fbi
->n_smart_cmds
= 0;
724 int pxafb_smart_queue(struct fb_info
*info
, uint16_t *cmds
, int n_cmds
)
727 struct pxafb_info
*fbi
= container_of(info
, struct pxafb_info
, fb
);
729 /* leave 2 commands for INTERRUPT and WAIT_FOR_SYNC */
730 for (i
= 0; i
< n_cmds
; i
++) {
731 if (fbi
->n_smart_cmds
== CMD_BUFF_SIZE
- 8)
732 pxafb_smart_flush(info
);
734 fbi
->smart_cmds
[fbi
->n_smart_cmds
++] = *cmds
++;
740 static unsigned int __smart_timing(unsigned time_ns
, unsigned long lcd_clk
)
742 unsigned int t
= (time_ns
* (lcd_clk
/ 1000000) / 1000);
743 return (t
== 0) ? 1 : t
;
746 static void setup_smart_timing(struct pxafb_info
*fbi
,
747 struct fb_var_screeninfo
*var
)
749 struct pxafb_mach_info
*inf
= fbi
->dev
->platform_data
;
750 struct pxafb_mode_info
*mode
= &inf
->modes
[0];
751 unsigned long lclk
= clk_get_rate(fbi
->clk
);
752 unsigned t1
, t2
, t3
, t4
;
754 t1
= max(mode
->a0csrd_set_hld
, mode
->a0cswr_set_hld
);
755 t2
= max(mode
->rd_pulse_width
, mode
->wr_pulse_width
);
756 t3
= mode
->op_hold_time
;
757 t4
= mode
->cmd_inh_time
;
760 LCCR1_DisWdth(var
->xres
) |
761 LCCR1_BegLnDel(__smart_timing(t1
, lclk
)) |
762 LCCR1_EndLnDel(__smart_timing(t2
, lclk
)) |
763 LCCR1_HorSnchWdth(__smart_timing(t3
, lclk
));
765 fbi
->reg_lccr2
= LCCR2_DisHght(var
->yres
);
766 fbi
->reg_lccr3
= LCCR3_PixClkDiv(__smart_timing(t4
, lclk
));
768 /* FIXME: make this configurable */
772 static int pxafb_smart_thread(void *arg
)
774 struct pxafb_info
*fbi
= arg
;
775 struct pxafb_mach_info
*inf
= fbi
->dev
->platform_data
;
777 if (!fbi
|| !inf
->smart_update
) {
778 pr_err("%s: not properly initialized, thread terminated\n",
783 pr_debug("%s(): task starting\n", __func__
);
786 while (!kthread_should_stop()) {
791 if (fbi
->state
== C_ENABLE
) {
792 inf
->smart_update(&fbi
->fb
);
793 complete(&fbi
->refresh_done
);
796 set_current_state(TASK_INTERRUPTIBLE
);
797 schedule_timeout(30 * HZ
/ 1000);
800 pr_debug("%s(): task ending\n", __func__
);
804 static int pxafb_smart_init(struct pxafb_info
*fbi
)
806 fbi
->smart_thread
= kthread_run(pxafb_smart_thread
, fbi
,
808 if (IS_ERR(fbi
->smart_thread
)) {
809 printk(KERN_ERR
"%s: unable to create kernel thread\n",
811 return PTR_ERR(fbi
->smart_thread
);
816 int pxafb_smart_queue(struct fb_info
*info
, uint16_t *cmds
, int n_cmds
)
821 int pxafb_smart_flush(struct fb_info
*info
)
825 #endif /* CONFIG_FB_SMART_PANEL */
827 static void setup_parallel_timing(struct pxafb_info
*fbi
,
828 struct fb_var_screeninfo
*var
)
830 unsigned int lines_per_panel
, pcd
= get_pcd(fbi
, var
->pixclock
);
833 LCCR1_DisWdth(var
->xres
) +
834 LCCR1_HorSnchWdth(var
->hsync_len
) +
835 LCCR1_BegLnDel(var
->left_margin
) +
836 LCCR1_EndLnDel(var
->right_margin
);
839 * If we have a dual scan LCD, we need to halve
840 * the YRES parameter.
842 lines_per_panel
= var
->yres
;
843 if ((fbi
->lccr0
& LCCR0_SDS
) == LCCR0_Dual
)
844 lines_per_panel
/= 2;
847 LCCR2_DisHght(lines_per_panel
) +
848 LCCR2_VrtSnchWdth(var
->vsync_len
) +
849 LCCR2_BegFrmDel(var
->upper_margin
) +
850 LCCR2_EndFrmDel(var
->lower_margin
);
852 fbi
->reg_lccr3
= fbi
->lccr3
|
853 (var
->sync
& FB_SYNC_HOR_HIGH_ACT
?
854 LCCR3_HorSnchH
: LCCR3_HorSnchL
) |
855 (var
->sync
& FB_SYNC_VERT_HIGH_ACT
?
856 LCCR3_VrtSnchH
: LCCR3_VrtSnchL
);
859 fbi
->reg_lccr3
|= LCCR3_PixClkDiv(pcd
);
860 set_hsync_time(fbi
, pcd
);
865 * pxafb_activate_var():
866 * Configures LCD Controller based on entries in var parameter.
867 * Settings are only written to the controller if changes were made.
869 static int pxafb_activate_var(struct fb_var_screeninfo
*var
,
870 struct pxafb_info
*fbi
)
876 if (!(fbi
->lccr0
& LCCR0_LCDT
)) {
877 if (var
->xres
< 16 || var
->xres
> 1024)
878 printk(KERN_ERR
"%s: invalid xres %d\n",
879 fbi
->fb
.fix
.id
, var
->xres
);
880 switch (var
->bits_per_pixel
) {
890 printk(KERN_ERR
"%s: invalid bit depth %d\n",
891 fbi
->fb
.fix
.id
, var
->bits_per_pixel
);
895 if (var
->hsync_len
< 1 || var
->hsync_len
> 64)
896 printk(KERN_ERR
"%s: invalid hsync_len %d\n",
897 fbi
->fb
.fix
.id
, var
->hsync_len
);
898 if (var
->left_margin
< 1 || var
->left_margin
> 255)
899 printk(KERN_ERR
"%s: invalid left_margin %d\n",
900 fbi
->fb
.fix
.id
, var
->left_margin
);
901 if (var
->right_margin
< 1 || var
->right_margin
> 255)
902 printk(KERN_ERR
"%s: invalid right_margin %d\n",
903 fbi
->fb
.fix
.id
, var
->right_margin
);
904 if (var
->yres
< 1 || var
->yres
> 1024)
905 printk(KERN_ERR
"%s: invalid yres %d\n",
906 fbi
->fb
.fix
.id
, var
->yres
);
907 if (var
->vsync_len
< 1 || var
->vsync_len
> 64)
908 printk(KERN_ERR
"%s: invalid vsync_len %d\n",
909 fbi
->fb
.fix
.id
, var
->vsync_len
);
910 if (var
->upper_margin
< 0 || var
->upper_margin
> 255)
911 printk(KERN_ERR
"%s: invalid upper_margin %d\n",
912 fbi
->fb
.fix
.id
, var
->upper_margin
);
913 if (var
->lower_margin
< 0 || var
->lower_margin
> 255)
914 printk(KERN_ERR
"%s: invalid lower_margin %d\n",
915 fbi
->fb
.fix
.id
, var
->lower_margin
);
918 /* Update shadow copy atomically */
919 local_irq_save(flags
);
921 #ifdef CONFIG_FB_PXA_SMARTPANEL
922 if (fbi
->lccr0
& LCCR0_LCDT
)
923 setup_smart_timing(fbi
, var
);
926 setup_parallel_timing(fbi
, var
);
928 fbi
->reg_lccr0
= fbi
->lccr0
|
929 (LCCR0_LDM
| LCCR0_SFM
| LCCR0_IUM
| LCCR0_EFM
|
930 LCCR0_QDM
| LCCR0_BM
| LCCR0_OUM
);
932 fbi
->reg_lccr3
|= pxafb_bpp_to_lccr3(var
);
934 nbytes
= var
->yres
* fbi
->fb
.fix
.line_length
;
936 if ((fbi
->lccr0
& LCCR0_SDS
) == LCCR0_Dual
) {
938 setup_frame_dma(fbi
, DMA_LOWER
, PAL_NONE
, nbytes
, nbytes
);
941 if ((var
->bits_per_pixel
>= 16) || (fbi
->lccr0
& LCCR0_LCDT
))
942 setup_frame_dma(fbi
, DMA_BASE
, PAL_NONE
, 0, nbytes
);
944 setup_frame_dma(fbi
, DMA_BASE
, PAL_BASE
, 0, nbytes
);
946 fbi
->reg_lccr4
= lcd_readl(fbi
, LCCR4
) & ~LCCR4_PAL_FOR_MASK
;
947 fbi
->reg_lccr4
|= (fbi
->lccr4
& LCCR4_PAL_FOR_MASK
);
948 local_irq_restore(flags
);
951 * Only update the registers if the controller is enabled
952 * and something has changed.
954 if ((lcd_readl(fbi
, LCCR0
) != fbi
->reg_lccr0
) ||
955 (lcd_readl(fbi
, LCCR1
) != fbi
->reg_lccr1
) ||
956 (lcd_readl(fbi
, LCCR2
) != fbi
->reg_lccr2
) ||
957 (lcd_readl(fbi
, LCCR3
) != fbi
->reg_lccr3
) ||
958 (lcd_readl(fbi
, FDADR0
) != fbi
->fdadr
[0]) ||
959 (lcd_readl(fbi
, FDADR1
) != fbi
->fdadr
[1]))
960 pxafb_schedule_work(fbi
, C_REENABLE
);
966 * NOTE! The following functions are purely helpers for set_ctrlr_state.
967 * Do not call them directly; set_ctrlr_state does the correct serialisation
968 * to ensure that things happen in the right way 100% of time time.
971 static inline void __pxafb_backlight_power(struct pxafb_info
*fbi
, int on
)
973 pr_debug("pxafb: backlight o%s\n", on
? "n" : "ff");
975 if (pxafb_backlight_power
)
976 pxafb_backlight_power(on
);
979 static inline void __pxafb_lcd_power(struct pxafb_info
*fbi
, int on
)
981 pr_debug("pxafb: LCD power o%s\n", on
? "n" : "ff");
984 pxafb_lcd_power(on
, &fbi
->fb
.var
);
987 static void pxafb_setup_gpio(struct pxafb_info
*fbi
)
990 unsigned int lccr0
= fbi
->lccr0
;
993 * setup is based on type of panel supported
996 /* 4 bit interface */
997 if ((lccr0
& LCCR0_CMS
) == LCCR0_Mono
&&
998 (lccr0
& LCCR0_SDS
) == LCCR0_Sngl
&&
999 (lccr0
& LCCR0_DPD
) == LCCR0_4PixMono
)
1002 /* 8 bit interface */
1003 else if (((lccr0
& LCCR0_CMS
) == LCCR0_Mono
&&
1004 ((lccr0
& LCCR0_SDS
) == LCCR0_Dual
||
1005 (lccr0
& LCCR0_DPD
) == LCCR0_8PixMono
)) ||
1006 ((lccr0
& LCCR0_CMS
) == LCCR0_Color
&&
1007 (lccr0
& LCCR0_PAS
) == LCCR0_Pas
&&
1008 (lccr0
& LCCR0_SDS
) == LCCR0_Sngl
))
1011 /* 16 bit interface */
1012 else if ((lccr0
& LCCR0_CMS
) == LCCR0_Color
&&
1013 ((lccr0
& LCCR0_SDS
) == LCCR0_Dual
||
1014 (lccr0
& LCCR0_PAS
) == LCCR0_Act
))
1018 printk(KERN_ERR
"pxafb_setup_gpio: unable to determine "
1019 "bits per pixel\n");
1023 for (gpio
= 58; ldd_bits
; gpio
++, ldd_bits
--)
1024 pxa_gpio_mode(gpio
| GPIO_ALT_FN_2_OUT
);
1025 /* 18 bit interface */
1026 if (fbi
->fb
.var
.bits_per_pixel
> 16) {
1027 pxa_gpio_mode(86 | GPIO_ALT_FN_2_OUT
);
1028 pxa_gpio_mode(87 | GPIO_ALT_FN_2_OUT
);
1030 pxa_gpio_mode(GPIO74_LCD_FCLK_MD
);
1031 pxa_gpio_mode(GPIO75_LCD_LCLK_MD
);
1032 pxa_gpio_mode(GPIO76_LCD_PCLK_MD
);
1033 pxa_gpio_mode(GPIO77_LCD_ACBIAS_MD
);
1036 static void pxafb_enable_controller(struct pxafb_info
*fbi
)
1038 pr_debug("pxafb: Enabling LCD controller\n");
1039 pr_debug("fdadr0 0x%08x\n", (unsigned int) fbi
->fdadr
[0]);
1040 pr_debug("fdadr1 0x%08x\n", (unsigned int) fbi
->fdadr
[1]);
1041 pr_debug("reg_lccr0 0x%08x\n", (unsigned int) fbi
->reg_lccr0
);
1042 pr_debug("reg_lccr1 0x%08x\n", (unsigned int) fbi
->reg_lccr1
);
1043 pr_debug("reg_lccr2 0x%08x\n", (unsigned int) fbi
->reg_lccr2
);
1044 pr_debug("reg_lccr3 0x%08x\n", (unsigned int) fbi
->reg_lccr3
);
1046 /* enable LCD controller clock */
1047 clk_enable(fbi
->clk
);
1049 if (fbi
->lccr0
& LCCR0_LCDT
)
1052 /* Sequence from 11.7.10 */
1053 lcd_writel(fbi
, LCCR3
, fbi
->reg_lccr3
);
1054 lcd_writel(fbi
, LCCR2
, fbi
->reg_lccr2
);
1055 lcd_writel(fbi
, LCCR1
, fbi
->reg_lccr1
);
1056 lcd_writel(fbi
, LCCR0
, fbi
->reg_lccr0
& ~LCCR0_ENB
);
1058 lcd_writel(fbi
, FDADR0
, fbi
->fdadr
[0]);
1059 lcd_writel(fbi
, FDADR1
, fbi
->fdadr
[1]);
1060 lcd_writel(fbi
, LCCR0
, fbi
->reg_lccr0
| LCCR0_ENB
);
1063 static void pxafb_disable_controller(struct pxafb_info
*fbi
)
1067 #ifdef CONFIG_FB_PXA_SMARTPANEL
1068 if (fbi
->lccr0
& LCCR0_LCDT
) {
1069 wait_for_completion_timeout(&fbi
->refresh_done
,
1075 /* Clear LCD Status Register */
1076 lcd_writel(fbi
, LCSR
, 0xffffffff);
1078 lccr0
= lcd_readl(fbi
, LCCR0
) & ~LCCR0_LDM
;
1079 lcd_writel(fbi
, LCCR0
, lccr0
);
1080 lcd_writel(fbi
, LCCR0
, lccr0
| LCCR0_DIS
);
1082 wait_for_completion_timeout(&fbi
->disable_done
, 200 * HZ
/ 1000);
1084 /* disable LCD controller clock */
1085 clk_disable(fbi
->clk
);
1089 * pxafb_handle_irq: Handle 'LCD DONE' interrupts.
1091 static irqreturn_t
pxafb_handle_irq(int irq
, void *dev_id
)
1093 struct pxafb_info
*fbi
= dev_id
;
1094 unsigned int lccr0
, lcsr
= lcd_readl(fbi
, LCSR
);
1096 if (lcsr
& LCSR_LDD
) {
1097 lccr0
= lcd_readl(fbi
, LCCR0
);
1098 lcd_writel(fbi
, LCCR0
, lccr0
| LCCR0_LDM
);
1099 complete(&fbi
->disable_done
);
1102 #ifdef CONFIG_FB_PXA_SMARTPANEL
1103 if (lcsr
& LCSR_CMD_INT
)
1104 complete(&fbi
->command_done
);
1107 lcd_writel(fbi
, LCSR
, lcsr
);
1112 * This function must be called from task context only, since it will
1113 * sleep when disabling the LCD controller, or if we get two contending
1114 * processes trying to alter state.
1116 static void set_ctrlr_state(struct pxafb_info
*fbi
, u_int state
)
1120 down(&fbi
->ctrlr_sem
);
1122 old_state
= fbi
->state
;
1125 * Hack around fbcon initialisation.
1127 if (old_state
== C_STARTUP
&& state
== C_REENABLE
)
1131 case C_DISABLE_CLKCHANGE
:
1133 * Disable controller for clock change. If the
1134 * controller is already disabled, then do nothing.
1136 if (old_state
!= C_DISABLE
&& old_state
!= C_DISABLE_PM
) {
1138 /* TODO __pxafb_lcd_power(fbi, 0); */
1139 pxafb_disable_controller(fbi
);
1146 * Disable controller
1148 if (old_state
!= C_DISABLE
) {
1150 __pxafb_backlight_power(fbi
, 0);
1151 __pxafb_lcd_power(fbi
, 0);
1152 if (old_state
!= C_DISABLE_CLKCHANGE
)
1153 pxafb_disable_controller(fbi
);
1157 case C_ENABLE_CLKCHANGE
:
1159 * Enable the controller after clock change. Only
1160 * do this if we were disabled for the clock change.
1162 if (old_state
== C_DISABLE_CLKCHANGE
) {
1163 fbi
->state
= C_ENABLE
;
1164 pxafb_enable_controller(fbi
);
1165 /* TODO __pxafb_lcd_power(fbi, 1); */
1171 * Re-enable the controller only if it was already
1172 * enabled. This is so we reprogram the control
1175 if (old_state
== C_ENABLE
) {
1176 __pxafb_lcd_power(fbi
, 0);
1177 pxafb_disable_controller(fbi
);
1178 pxafb_setup_gpio(fbi
);
1179 pxafb_enable_controller(fbi
);
1180 __pxafb_lcd_power(fbi
, 1);
1186 * Re-enable the controller after PM. This is not
1187 * perfect - think about the case where we were doing
1188 * a clock change, and we suspended half-way through.
1190 if (old_state
!= C_DISABLE_PM
)
1196 * Power up the LCD screen, enable controller, and
1197 * turn on the backlight.
1199 if (old_state
!= C_ENABLE
) {
1200 fbi
->state
= C_ENABLE
;
1201 pxafb_setup_gpio(fbi
);
1202 pxafb_enable_controller(fbi
);
1203 __pxafb_lcd_power(fbi
, 1);
1204 __pxafb_backlight_power(fbi
, 1);
1208 up(&fbi
->ctrlr_sem
);
1212 * Our LCD controller task (which is called when we blank or unblank)
1215 static void pxafb_task(struct work_struct
*work
)
1217 struct pxafb_info
*fbi
=
1218 container_of(work
, struct pxafb_info
, task
);
1219 u_int state
= xchg(&fbi
->task_state
, -1);
1221 set_ctrlr_state(fbi
, state
);
1224 #ifdef CONFIG_CPU_FREQ
1226 * CPU clock speed change handler. We need to adjust the LCD timing
1227 * parameters when the CPU clock is adjusted by the power management
1230 * TODO: Determine why f->new != 10*get_lclk_frequency_10khz()
1233 pxafb_freq_transition(struct notifier_block
*nb
, unsigned long val
, void *data
)
1235 struct pxafb_info
*fbi
= TO_INF(nb
, freq_transition
);
1236 /* TODO struct cpufreq_freqs *f = data; */
1240 case CPUFREQ_PRECHANGE
:
1241 set_ctrlr_state(fbi
, C_DISABLE_CLKCHANGE
);
1244 case CPUFREQ_POSTCHANGE
:
1245 pcd
= get_pcd(fbi
, fbi
->fb
.var
.pixclock
);
1246 set_hsync_time(fbi
, pcd
);
1247 fbi
->reg_lccr3
= (fbi
->reg_lccr3
& ~0xff) |
1248 LCCR3_PixClkDiv(pcd
);
1249 set_ctrlr_state(fbi
, C_ENABLE_CLKCHANGE
);
1256 pxafb_freq_policy(struct notifier_block
*nb
, unsigned long val
, void *data
)
1258 struct pxafb_info
*fbi
= TO_INF(nb
, freq_policy
);
1259 struct fb_var_screeninfo
*var
= &fbi
->fb
.var
;
1260 struct cpufreq_policy
*policy
= data
;
1263 case CPUFREQ_ADJUST
:
1264 case CPUFREQ_INCOMPATIBLE
:
1265 pr_debug("min dma period: %d ps, "
1266 "new clock %d kHz\n", pxafb_display_dma_period(var
),
1268 /* TODO: fill in min/max values */
1277 * Power management hooks. Note that we won't be called from IRQ context,
1278 * unlike the blank functions above, so we may sleep.
1280 static int pxafb_suspend(struct platform_device
*dev
, pm_message_t state
)
1282 struct pxafb_info
*fbi
= platform_get_drvdata(dev
);
1284 set_ctrlr_state(fbi
, C_DISABLE_PM
);
1288 static int pxafb_resume(struct platform_device
*dev
)
1290 struct pxafb_info
*fbi
= platform_get_drvdata(dev
);
1292 set_ctrlr_state(fbi
, C_ENABLE_PM
);
1296 #define pxafb_suspend NULL
1297 #define pxafb_resume NULL
1301 * pxafb_map_video_memory():
1302 * Allocates the DRAM memory for the frame buffer. This buffer is
1303 * remapped into a non-cached, non-buffered, memory region to
1304 * allow palette and pixel writes to occur without flushing the
1305 * cache. Once this area is remapped, all virtual memory
1306 * access to the video memory should occur at the new region.
1308 static int __devinit
pxafb_map_video_memory(struct pxafb_info
*fbi
)
1311 * We reserve one page for the palette, plus the size
1312 * of the framebuffer.
1314 fbi
->video_offset
= PAGE_ALIGN(sizeof(struct pxafb_dma_buff
));
1315 fbi
->map_size
= PAGE_ALIGN(fbi
->fb
.fix
.smem_len
+ fbi
->video_offset
);
1316 fbi
->map_cpu
= dma_alloc_writecombine(fbi
->dev
, fbi
->map_size
,
1317 &fbi
->map_dma
, GFP_KERNEL
);
1320 /* prevent initial garbage on screen */
1321 memset(fbi
->map_cpu
, 0, fbi
->map_size
);
1322 fbi
->fb
.screen_base
= fbi
->map_cpu
+ fbi
->video_offset
;
1323 fbi
->screen_dma
= fbi
->map_dma
+ fbi
->video_offset
;
1326 * FIXME: this is actually the wrong thing to place in
1327 * smem_start. But fbdev suffers from the problem that
1328 * it needs an API which doesn't exist (in this case,
1329 * dma_writecombine_mmap)
1331 fbi
->fb
.fix
.smem_start
= fbi
->screen_dma
;
1332 fbi
->palette_size
= fbi
->fb
.var
.bits_per_pixel
== 8 ? 256 : 16;
1334 fbi
->dma_buff
= (void *) fbi
->map_cpu
;
1335 fbi
->dma_buff_phys
= fbi
->map_dma
;
1336 fbi
->palette_cpu
= (u16
*) fbi
->dma_buff
->palette
;
1338 pr_debug("pxafb: palette_mem_size = 0x%08lx\n", fbi
->palette_size
*sizeof(u16
));
1340 #ifdef CONFIG_FB_PXA_SMARTPANEL
1341 fbi
->smart_cmds
= (uint16_t *) fbi
->dma_buff
->cmd_buff
;
1342 fbi
->n_smart_cmds
= 0;
1346 return fbi
->map_cpu
? 0 : -ENOMEM
;
1349 static void pxafb_decode_mode_info(struct pxafb_info
*fbi
,
1350 struct pxafb_mode_info
*modes
,
1351 unsigned int num_modes
)
1353 unsigned int i
, smemlen
;
1355 pxafb_setmode(&fbi
->fb
.var
, &modes
[0]);
1357 for (i
= 0; i
< num_modes
; i
++) {
1358 smemlen
= modes
[i
].xres
* modes
[i
].yres
* modes
[i
].bpp
/ 8;
1359 if (smemlen
> fbi
->fb
.fix
.smem_len
)
1360 fbi
->fb
.fix
.smem_len
= smemlen
;
1364 static void pxafb_decode_mach_info(struct pxafb_info
*fbi
,
1365 struct pxafb_mach_info
*inf
)
1367 unsigned int lcd_conn
= inf
->lcd_conn
;
1369 fbi
->cmap_inverse
= inf
->cmap_inverse
;
1370 fbi
->cmap_static
= inf
->cmap_static
;
1372 switch (lcd_conn
& 0xf) {
1373 case LCD_TYPE_MONO_STN
:
1374 fbi
->lccr0
= LCCR0_CMS
;
1376 case LCD_TYPE_MONO_DSTN
:
1377 fbi
->lccr0
= LCCR0_CMS
| LCCR0_SDS
;
1379 case LCD_TYPE_COLOR_STN
:
1382 case LCD_TYPE_COLOR_DSTN
:
1383 fbi
->lccr0
= LCCR0_SDS
;
1385 case LCD_TYPE_COLOR_TFT
:
1386 fbi
->lccr0
= LCCR0_PAS
;
1388 case LCD_TYPE_SMART_PANEL
:
1389 fbi
->lccr0
= LCCR0_LCDT
| LCCR0_PAS
;
1392 /* fall back to backward compatibility way */
1393 fbi
->lccr0
= inf
->lccr0
;
1394 fbi
->lccr3
= inf
->lccr3
;
1395 fbi
->lccr4
= inf
->lccr4
;
1399 if (lcd_conn
== LCD_MONO_STN_8BPP
)
1400 fbi
->lccr0
|= LCCR0_DPD
;
1402 fbi
->lccr3
= LCCR3_Acb((inf
->lcd_conn
>> 10) & 0xff);
1403 fbi
->lccr3
|= (lcd_conn
& LCD_BIAS_ACTIVE_LOW
) ? LCCR3_OEP
: 0;
1404 fbi
->lccr3
|= (lcd_conn
& LCD_PCLK_EDGE_FALL
) ? LCCR3_PCP
: 0;
1407 pxafb_decode_mode_info(fbi
, inf
->modes
, inf
->num_modes
);
1410 static struct pxafb_info
* __devinit
pxafb_init_fbinfo(struct device
*dev
)
1412 struct pxafb_info
*fbi
;
1414 struct pxafb_mach_info
*inf
= dev
->platform_data
;
1416 /* Alloc the pxafb_info and pseudo_palette in one step */
1417 fbi
= kmalloc(sizeof(struct pxafb_info
) + sizeof(u32
) * 16, GFP_KERNEL
);
1421 memset(fbi
, 0, sizeof(struct pxafb_info
));
1424 fbi
->clk
= clk_get(dev
, "LCDCLK");
1425 if (IS_ERR(fbi
->clk
)) {
1430 strcpy(fbi
->fb
.fix
.id
, PXA_NAME
);
1432 fbi
->fb
.fix
.type
= FB_TYPE_PACKED_PIXELS
;
1433 fbi
->fb
.fix
.type_aux
= 0;
1434 fbi
->fb
.fix
.xpanstep
= 0;
1435 fbi
->fb
.fix
.ypanstep
= 0;
1436 fbi
->fb
.fix
.ywrapstep
= 0;
1437 fbi
->fb
.fix
.accel
= FB_ACCEL_NONE
;
1439 fbi
->fb
.var
.nonstd
= 0;
1440 fbi
->fb
.var
.activate
= FB_ACTIVATE_NOW
;
1441 fbi
->fb
.var
.height
= -1;
1442 fbi
->fb
.var
.width
= -1;
1443 fbi
->fb
.var
.accel_flags
= 0;
1444 fbi
->fb
.var
.vmode
= FB_VMODE_NONINTERLACED
;
1446 fbi
->fb
.fbops
= &pxafb_ops
;
1447 fbi
->fb
.flags
= FBINFO_DEFAULT
;
1451 addr
= addr
+ sizeof(struct pxafb_info
);
1452 fbi
->fb
.pseudo_palette
= addr
;
1454 fbi
->state
= C_STARTUP
;
1455 fbi
->task_state
= (u_char
)-1;
1457 pxafb_decode_mach_info(fbi
, inf
);
1459 init_waitqueue_head(&fbi
->ctrlr_wait
);
1460 INIT_WORK(&fbi
->task
, pxafb_task
);
1461 init_MUTEX(&fbi
->ctrlr_sem
);
1462 init_completion(&fbi
->disable_done
);
1463 #ifdef CONFIG_FB_PXA_SMARTPANEL
1464 init_completion(&fbi
->command_done
);
1465 init_completion(&fbi
->refresh_done
);
1471 #ifdef CONFIG_FB_PXA_PARAMETERS
1472 static int __devinit
parse_opt_mode(struct device
*dev
, const char *this_opt
)
1474 struct pxafb_mach_info
*inf
= dev
->platform_data
;
1476 const char *name
= this_opt
+5;
1477 unsigned int namelen
= strlen(name
);
1478 int res_specified
= 0, bpp_specified
= 0;
1479 unsigned int xres
= 0, yres
= 0, bpp
= 0;
1480 int yres_specified
= 0;
1482 for (i
= namelen
-1; i
>= 0; i
--) {
1486 if (!bpp_specified
&& !yres_specified
) {
1487 bpp
= simple_strtoul(&name
[i
+1], NULL
, 0);
1493 if (!yres_specified
) {
1494 yres
= simple_strtoul(&name
[i
+1], NULL
, 0);
1505 if (i
< 0 && yres_specified
) {
1506 xres
= simple_strtoul(name
, NULL
, 0);
1510 if (res_specified
) {
1511 dev_info(dev
, "overriding resolution: %dx%d\n", xres
, yres
);
1512 inf
->modes
[0].xres
= xres
; inf
->modes
[0].yres
= yres
;
1521 inf
->modes
[0].bpp
= bpp
;
1522 dev_info(dev
, "overriding bit depth: %d\n", bpp
);
1525 dev_err(dev
, "Depth %d is not valid\n", bpp
);
1531 static int __devinit
parse_opt(struct device
*dev
, char *this_opt
)
1533 struct pxafb_mach_info
*inf
= dev
->platform_data
;
1534 struct pxafb_mode_info
*mode
= &inf
->modes
[0];
1539 if (!strncmp(this_opt
, "mode:", 5)) {
1540 return parse_opt_mode(dev
, this_opt
);
1541 } else if (!strncmp(this_opt
, "pixclock:", 9)) {
1542 mode
->pixclock
= simple_strtoul(this_opt
+9, NULL
, 0);
1543 sprintf(s
, "pixclock: %ld\n", mode
->pixclock
);
1544 } else if (!strncmp(this_opt
, "left:", 5)) {
1545 mode
->left_margin
= simple_strtoul(this_opt
+5, NULL
, 0);
1546 sprintf(s
, "left: %u\n", mode
->left_margin
);
1547 } else if (!strncmp(this_opt
, "right:", 6)) {
1548 mode
->right_margin
= simple_strtoul(this_opt
+6, NULL
, 0);
1549 sprintf(s
, "right: %u\n", mode
->right_margin
);
1550 } else if (!strncmp(this_opt
, "upper:", 6)) {
1551 mode
->upper_margin
= simple_strtoul(this_opt
+6, NULL
, 0);
1552 sprintf(s
, "upper: %u\n", mode
->upper_margin
);
1553 } else if (!strncmp(this_opt
, "lower:", 6)) {
1554 mode
->lower_margin
= simple_strtoul(this_opt
+6, NULL
, 0);
1555 sprintf(s
, "lower: %u\n", mode
->lower_margin
);
1556 } else if (!strncmp(this_opt
, "hsynclen:", 9)) {
1557 mode
->hsync_len
= simple_strtoul(this_opt
+9, NULL
, 0);
1558 sprintf(s
, "hsynclen: %u\n", mode
->hsync_len
);
1559 } else if (!strncmp(this_opt
, "vsynclen:", 9)) {
1560 mode
->vsync_len
= simple_strtoul(this_opt
+9, NULL
, 0);
1561 sprintf(s
, "vsynclen: %u\n", mode
->vsync_len
);
1562 } else if (!strncmp(this_opt
, "hsync:", 6)) {
1563 if (simple_strtoul(this_opt
+6, NULL
, 0) == 0) {
1564 sprintf(s
, "hsync: Active Low\n");
1565 mode
->sync
&= ~FB_SYNC_HOR_HIGH_ACT
;
1567 sprintf(s
, "hsync: Active High\n");
1568 mode
->sync
|= FB_SYNC_HOR_HIGH_ACT
;
1570 } else if (!strncmp(this_opt
, "vsync:", 6)) {
1571 if (simple_strtoul(this_opt
+6, NULL
, 0) == 0) {
1572 sprintf(s
, "vsync: Active Low\n");
1573 mode
->sync
&= ~FB_SYNC_VERT_HIGH_ACT
;
1575 sprintf(s
, "vsync: Active High\n");
1576 mode
->sync
|= FB_SYNC_VERT_HIGH_ACT
;
1578 } else if (!strncmp(this_opt
, "dpc:", 4)) {
1579 if (simple_strtoul(this_opt
+4, NULL
, 0) == 0) {
1580 sprintf(s
, "double pixel clock: false\n");
1581 inf
->lccr3
&= ~LCCR3_DPC
;
1583 sprintf(s
, "double pixel clock: true\n");
1584 inf
->lccr3
|= LCCR3_DPC
;
1586 } else if (!strncmp(this_opt
, "outputen:", 9)) {
1587 if (simple_strtoul(this_opt
+9, NULL
, 0) == 0) {
1588 sprintf(s
, "output enable: active low\n");
1589 inf
->lccr3
= (inf
->lccr3
& ~LCCR3_OEP
) | LCCR3_OutEnL
;
1591 sprintf(s
, "output enable: active high\n");
1592 inf
->lccr3
= (inf
->lccr3
& ~LCCR3_OEP
) | LCCR3_OutEnH
;
1594 } else if (!strncmp(this_opt
, "pixclockpol:", 12)) {
1595 if (simple_strtoul(this_opt
+12, NULL
, 0) == 0) {
1596 sprintf(s
, "pixel clock polarity: falling edge\n");
1597 inf
->lccr3
= (inf
->lccr3
& ~LCCR3_PCP
) | LCCR3_PixFlEdg
;
1599 sprintf(s
, "pixel clock polarity: rising edge\n");
1600 inf
->lccr3
= (inf
->lccr3
& ~LCCR3_PCP
) | LCCR3_PixRsEdg
;
1602 } else if (!strncmp(this_opt
, "color", 5)) {
1603 inf
->lccr0
= (inf
->lccr0
& ~LCCR0_CMS
) | LCCR0_Color
;
1604 } else if (!strncmp(this_opt
, "mono", 4)) {
1605 inf
->lccr0
= (inf
->lccr0
& ~LCCR0_CMS
) | LCCR0_Mono
;
1606 } else if (!strncmp(this_opt
, "active", 6)) {
1607 inf
->lccr0
= (inf
->lccr0
& ~LCCR0_PAS
) | LCCR0_Act
;
1608 } else if (!strncmp(this_opt
, "passive", 7)) {
1609 inf
->lccr0
= (inf
->lccr0
& ~LCCR0_PAS
) | LCCR0_Pas
;
1610 } else if (!strncmp(this_opt
, "single", 6)) {
1611 inf
->lccr0
= (inf
->lccr0
& ~LCCR0_SDS
) | LCCR0_Sngl
;
1612 } else if (!strncmp(this_opt
, "dual", 4)) {
1613 inf
->lccr0
= (inf
->lccr0
& ~LCCR0_SDS
) | LCCR0_Dual
;
1614 } else if (!strncmp(this_opt
, "4pix", 4)) {
1615 inf
->lccr0
= (inf
->lccr0
& ~LCCR0_DPD
) | LCCR0_4PixMono
;
1616 } else if (!strncmp(this_opt
, "8pix", 4)) {
1617 inf
->lccr0
= (inf
->lccr0
& ~LCCR0_DPD
) | LCCR0_8PixMono
;
1619 dev_err(dev
, "unknown option: %s\n", this_opt
);
1624 dev_info(dev
, "override %s", s
);
1629 static int __devinit
pxafb_parse_options(struct device
*dev
, char *options
)
1634 if (!options
|| !*options
)
1637 dev_dbg(dev
, "options are \"%s\"\n", options
? options
: "null");
1639 /* could be made table driven or similar?... */
1640 while ((this_opt
= strsep(&options
, ",")) != NULL
) {
1641 ret
= parse_opt(dev
, this_opt
);
1648 static char g_options
[256] __devinitdata
= "";
1651 static int __init
pxafb_setup_options(void)
1653 char *options
= NULL
;
1655 if (fb_get_options("pxafb", &options
))
1659 strlcpy(g_options
, options
, sizeof(g_options
));
1664 #define pxafb_setup_options() (0)
1666 module_param_string(options
, g_options
, sizeof(g_options
), 0);
1667 MODULE_PARM_DESC(options
, "LCD parameters (see Documentation/fb/pxafb.txt)");
1671 #define pxafb_parse_options(...) (0)
1672 #define pxafb_setup_options() (0)
1675 static int __devinit
pxafb_probe(struct platform_device
*dev
)
1677 struct pxafb_info
*fbi
;
1678 struct pxafb_mach_info
*inf
;
1682 dev_dbg(&dev
->dev
, "pxafb_probe\n");
1684 inf
= dev
->dev
.platform_data
;
1690 ret
= pxafb_parse_options(&dev
->dev
, g_options
);
1695 /* Check for various illegal bit-combinations. Currently only
1696 * a warning is given. */
1698 if (inf
->lccr0
& LCCR0_INVALID_CONFIG_MASK
)
1699 dev_warn(&dev
->dev
, "machine LCCR0 setting contains "
1700 "illegal bits: %08x\n",
1701 inf
->lccr0
& LCCR0_INVALID_CONFIG_MASK
);
1702 if (inf
->lccr3
& LCCR3_INVALID_CONFIG_MASK
)
1703 dev_warn(&dev
->dev
, "machine LCCR3 setting contains "
1704 "illegal bits: %08x\n",
1705 inf
->lccr3
& LCCR3_INVALID_CONFIG_MASK
);
1706 if (inf
->lccr0
& LCCR0_DPD
&&
1707 ((inf
->lccr0
& LCCR0_PAS
) != LCCR0_Pas
||
1708 (inf
->lccr0
& LCCR0_SDS
) != LCCR0_Sngl
||
1709 (inf
->lccr0
& LCCR0_CMS
) != LCCR0_Mono
))
1710 dev_warn(&dev
->dev
, "Double Pixel Data (DPD) mode is "
1711 "only valid in passive mono"
1712 " single panel mode\n");
1713 if ((inf
->lccr0
& LCCR0_PAS
) == LCCR0_Act
&&
1714 (inf
->lccr0
& LCCR0_SDS
) == LCCR0_Dual
)
1715 dev_warn(&dev
->dev
, "Dual panel only valid in passive mode\n");
1716 if ((inf
->lccr0
& LCCR0_PAS
) == LCCR0_Pas
&&
1717 (inf
->modes
->upper_margin
|| inf
->modes
->lower_margin
))
1718 dev_warn(&dev
->dev
, "Upper and lower margins must be 0 in "
1722 dev_dbg(&dev
->dev
, "got a %dx%dx%d LCD\n",
1726 if (inf
->modes
->xres
== 0 ||
1727 inf
->modes
->yres
== 0 ||
1728 inf
->modes
->bpp
== 0) {
1729 dev_err(&dev
->dev
, "Invalid resolution or bit depth\n");
1733 pxafb_backlight_power
= inf
->pxafb_backlight_power
;
1734 pxafb_lcd_power
= inf
->pxafb_lcd_power
;
1735 fbi
= pxafb_init_fbinfo(&dev
->dev
);
1737 /* only reason for pxafb_init_fbinfo to fail is kmalloc */
1738 dev_err(&dev
->dev
, "Failed to initialize framebuffer device\n");
1743 r
= platform_get_resource(dev
, IORESOURCE_MEM
, 0);
1745 dev_err(&dev
->dev
, "no I/O memory resource defined\n");
1750 r
= request_mem_region(r
->start
, r
->end
- r
->start
+ 1, dev
->name
);
1752 dev_err(&dev
->dev
, "failed to request I/O memory\n");
1757 fbi
->mmio_base
= ioremap(r
->start
, r
->end
- r
->start
+ 1);
1758 if (fbi
->mmio_base
== NULL
) {
1759 dev_err(&dev
->dev
, "failed to map I/O memory\n");
1761 goto failed_free_res
;
1764 /* Initialize video memory */
1765 ret
= pxafb_map_video_memory(fbi
);
1767 dev_err(&dev
->dev
, "Failed to allocate video RAM: %d\n", ret
);
1769 goto failed_free_io
;
1772 irq
= platform_get_irq(dev
, 0);
1774 dev_err(&dev
->dev
, "no IRQ defined\n");
1776 goto failed_free_mem
;
1779 ret
= request_irq(irq
, pxafb_handle_irq
, IRQF_DISABLED
, "LCD", fbi
);
1781 dev_err(&dev
->dev
, "request_irq failed: %d\n", ret
);
1783 goto failed_free_mem
;
1786 #ifdef CONFIG_FB_PXA_SMARTPANEL
1787 ret
= pxafb_smart_init(fbi
);
1789 dev_err(&dev
->dev
, "failed to initialize smartpanel\n");
1790 goto failed_free_irq
;
1794 * This makes sure that our colour bitfield
1795 * descriptors are correctly initialised.
1797 ret
= pxafb_check_var(&fbi
->fb
.var
, &fbi
->fb
);
1799 dev_err(&dev
->dev
, "failed to get suitable mode\n");
1800 goto failed_free_irq
;
1803 ret
= pxafb_set_par(&fbi
->fb
);
1805 dev_err(&dev
->dev
, "Failed to set parameters\n");
1806 goto failed_free_irq
;
1809 platform_set_drvdata(dev
, fbi
);
1811 ret
= register_framebuffer(&fbi
->fb
);
1814 "Failed to register framebuffer device: %d\n", ret
);
1815 goto failed_free_cmap
;
1818 #ifdef CONFIG_CPU_FREQ
1819 fbi
->freq_transition
.notifier_call
= pxafb_freq_transition
;
1820 fbi
->freq_policy
.notifier_call
= pxafb_freq_policy
;
1821 cpufreq_register_notifier(&fbi
->freq_transition
,
1822 CPUFREQ_TRANSITION_NOTIFIER
);
1823 cpufreq_register_notifier(&fbi
->freq_policy
,
1824 CPUFREQ_POLICY_NOTIFIER
);
1828 * Ok, now enable the LCD controller
1830 set_ctrlr_state(fbi
, C_ENABLE
);
1835 if (fbi
->fb
.cmap
.len
)
1836 fb_dealloc_cmap(&fbi
->fb
.cmap
);
1840 dma_free_writecombine(&dev
->dev
, fbi
->map_size
,
1841 fbi
->map_cpu
, fbi
->map_dma
);
1843 iounmap(fbi
->mmio_base
);
1845 release_mem_region(r
->start
, r
->end
- r
->start
+ 1);
1848 platform_set_drvdata(dev
, NULL
);
1854 static int __devexit
pxafb_remove(struct platform_device
*dev
)
1856 struct pxafb_info
*fbi
= platform_get_drvdata(dev
);
1859 struct fb_info
*info
;
1866 unregister_framebuffer(info
);
1868 pxafb_disable_controller(fbi
);
1870 if (fbi
->fb
.cmap
.len
)
1871 fb_dealloc_cmap(&fbi
->fb
.cmap
);
1873 irq
= platform_get_irq(dev
, 0);
1876 dma_free_writecombine(&dev
->dev
, fbi
->map_size
,
1877 fbi
->map_cpu
, fbi
->map_dma
);
1879 iounmap(fbi
->mmio_base
);
1881 r
= platform_get_resource(dev
, IORESOURCE_MEM
, 0);
1882 release_mem_region(r
->start
, r
->end
- r
->start
+ 1);
1890 static struct platform_driver pxafb_driver
= {
1891 .probe
= pxafb_probe
,
1892 .remove
= pxafb_remove
,
1893 .suspend
= pxafb_suspend
,
1894 .resume
= pxafb_resume
,
1896 .owner
= THIS_MODULE
,
1897 .name
= "pxa2xx-fb",
1901 static int __init
pxafb_init(void)
1903 if (pxafb_setup_options())
1906 return platform_driver_register(&pxafb_driver
);
1909 static void __exit
pxafb_exit(void)
1911 platform_driver_unregister(&pxafb_driver
);
1914 module_init(pxafb_init
);
1915 module_exit(pxafb_exit
);
1917 MODULE_DESCRIPTION("loadable framebuffer driver for PXA");
1918 MODULE_LICENSE("GPL");