arch/m68k/include/asm/m53xxacr.h

   1 /****************************************************************************/
   2
   3 /*
   4  * m53xxacr.h -- ColdFire version 3 core cache support
   5  *
   6  * (C) Copyright 2010, Greg Ungerer <gerg@snapgear.com>
   7  */
   8
   9 /****************************************************************************/
  10 #ifndef m53xxacr_h
  11 #define m53xxacr_h
  12 /****************************************************************************/
  13
  14 /*
  15  * All varients of the ColdFire using version 3 cores have a similar
  16  * cache setup. They have a unified instruction and data cache, with
  17  * configurable write-through or copy-back operation.
  18  */
  19
  20 /*
  21  * Define the Cache Control register flags.
  22  */
  23 #define CACR_EC         0x80000000      /* Enable cache */
  24 #define CACR_ESB        0x20000000      /* Enable store buffer */
  25 #define CACR_DPI        0x10000000      /* Disable invalidation by CPUSHL */
  26 #define CACR_HLCK       0x08000000      /* Half cache lock mode */
  27 #define CACR_CINVA      0x01000000      /* Invalidate cache */
  28 #define CACR_DNFB       0x00000400      /* Inhibited fill buffer */
  29 #define CACR_DCM_WT     0x00000000      /* Cacheable write-through */
  30 #define CACR_DCM_CB     0x00000100      /* Cacheable copy-back */
  31 #define CACR_DCM_PRE    0x00000200      /* Cache inhibited, precise */
  32 #define CACR_DCM_IMPRE  0x00000300      /* Cache inhibited, imprecise */
  33 #define CACR_WPROTECT   0x00000020      /* Write protect*/
  34 #define CACR_EUSP       0x00000010      /* Eanble separate user a7 */
  35
  36 /*
  37  * Define the Access Control register flags.
  38  */
  39 #define ACR_BASE_POS    24              /* Address Base (upper 8 bits) */
  40 #define ACR_MASK_POS    16              /* Address Mask (next 8 bits) */
  41 #define ACR_ENABLE      0x00008000      /* Enable this ACR */
  42 #define ACR_USER        0x00000000      /* Allow only user accesses */
  43 #define ACR_SUPER       0x00002000      /* Allow supervisor access only */
  44 #define ACR_ANY         0x00004000      /* Allow any access type */
  45 #define ACR_CM_WT       0x00000000      /* Cacheable, write-through */
  46 #define ACR_CM_CB       0x00000020      /* Cacheable, copy-back */
  47 #define ACR_CM_PRE      0x00000040      /* Cache inhibited, precise */
  48 #define ACR_CM_IMPRE    0x00000060      /* Cache inhibited, imprecise */
  49 #define ACR_WPROTECT    0x00000004      /* Write protect region */
  50
  51 /****************************************************************************/
  52 #endif  /* m53xxsim_h */