arch/x86/pci/amd_bus.c

   1 #include <linux/init.h>
   2 #include <linux/pci.h>
   3 #include <linux/topology.h>
   4 #include <linux/cpu.h>
   5 #include <linux/range.h>
   6
   7 #include <asm/pci_x86.h>
   8
   9 #ifdef CONFIG_X86_64
  10 #include <asm/pci-direct.h>
  11 #endif
  12
  13 #include "bus_numa.h"
  14
  15 /*
  16  * This discovers the pcibus <-> node mapping on AMD K8.
  17  * also get peer root bus resource for io,mmio
  18  */
  19
  20 #ifdef CONFIG_X86_64
  21
  22 struct pci_hostbridge_probe {
  23         u32 bus;
  24         u32 slot;
  25         u32 vendor;
  26         u32 device;
  27 };
  28
  29 static struct pci_hostbridge_probe pci_probes[] __initdata = {
  30         { 0, 0x18, PCI_VENDOR_ID_AMD, 0x1100 },
  31         { 0, 0x18, PCI_VENDOR_ID_AMD, 0x1200 },
  32         { 0xff, 0, PCI_VENDOR_ID_AMD, 0x1200 },
  33         { 0, 0x18, PCI_VENDOR_ID_AMD, 0x1300 },
  34 };
  35
  36 static u64 __initdata fam10h_mmconf_start;
  37 static u64 __initdata fam10h_mmconf_end;
  38 static void __init get_pci_mmcfg_amd_fam10h_range(void)
  39 {
  40         u32 address;
  41         u64 base, msr;
  42         unsigned segn_busn_bits;
  43
  44         /* assume all cpus from fam10h have mmconf */
  45         if (boot_cpu_data.x86 < 0x10)
  46                 return;
  47
  48         address = MSR_FAM10H_MMIO_CONF_BASE;
  49         rdmsrl(address, msr);
  50
  51         /* mmconfig is not enable */
  52         if (!(msr & FAM10H_MMIO_CONF_ENABLE))
  53                 return;
  54
  55         base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);
  56
  57         segn_busn_bits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
  58                          FAM10H_MMIO_CONF_BUSRANGE_MASK;
  59
  60         fam10h_mmconf_start = base;
  61         fam10h_mmconf_end = base + (1ULL<<(segn_busn_bits + 20)) - 1;
  62 }
  63
  64 #define RANGE_NUM 16
  65
  66 /**
  67  * early_fill_mp_bus_to_node()
  68  * called before pcibios_scan_root and pci_scan_bus
  69  * fills the mp_bus_to_cpumask array based according to the LDT Bus Number
  70  * Registers found in the K8 northbridge
  71  */
  72 static int __init early_fill_mp_bus_info(void)
  73 {
  74         int i;
  75         int j;
  76         unsigned bus;
  77         unsigned slot;
  78         int node;
  79         int link;
  80         int def_node;
  81         int def_link;
  82         struct pci_root_info *info;
  83         u32 reg;
  84         struct resource *res;
  85         size_t start;
  86         size_t end;
  87         struct range range[RANGE_NUM];
  88         u64 val;
  89         u32 address;
  90
  91         if (!early_pci_allowed())
  92                 return -1;
  93
  94         found_all_numa_early = 0;
  95         for (i = 0; i < ARRAY_SIZE(pci_probes); i++) {
  96                 u32 id;
  97                 u16 device;
  98                 u16 vendor;
  99
 100                 bus = pci_probes[i].bus;
 101                 slot = pci_probes[i].slot;
 102                 id = read_pci_config(bus, slot, 0, PCI_VENDOR_ID);
 103
 104                 vendor = id & 0xffff;
 105                 device = (id>>16) & 0xffff;
 106                 if (pci_probes[i].vendor == vendor &&
 107                     pci_probes[i].device == device) {
 108                         found_all_numa_early = 1;
 109                         break;
 110                 }
 111         }
 112
 113         if (!found_all_numa_early)
 114                 return 0;
 115
 116         pci_root_num = 0;
 117         for (i = 0; i < 4; i++) {
 118                 int min_bus;
 119                 int max_bus;
 120                 reg = read_pci_config(bus, slot, 1, 0xe0 + (i << 2));
 121
 122                 /* Check if that register is enabled for bus range */
 123                 if ((reg & 7) != 3)
 124                         continue;
 125
 126                 min_bus = (reg >> 16) & 0xff;
 127                 max_bus = (reg >> 24) & 0xff;
 128                 node = (reg >> 4) & 0x07;
 129 #ifdef CONFIG_NUMA
 130                 for (j = min_bus; j <= max_bus; j++)
 131                         set_mp_bus_to_node(j, node);
 132 #endif
 133                 link = (reg >> 8) & 0x03;
 134
 135                 info = &pci_root_info[pci_root_num];
 136                 info->bus_min = min_bus;
 137                 info->bus_max = max_bus;
 138                 info->node = node;
 139                 info->link = link;
 140                 sprintf(info->name, "PCI Bus #%02x", min_bus);
 141                 pci_root_num++;
 142         }
 143
 144         /* get the default node and link for left over res */
 145         reg = read_pci_config(bus, slot, 0, 0x60);
 146         def_node = (reg >> 8) & 0x07;
 147         reg = read_pci_config(bus, slot, 0, 0x64);
 148         def_link = (reg >> 8) & 0x03;
 149
 150         memset(range, 0, sizeof(range));
 151         range[0].end = 0xffff;
 152         /* io port resource */
 153         for (i = 0; i < 4; i++) {
 154                 reg = read_pci_config(bus, slot, 1, 0xc0 + (i << 3));
 155                 if (!(reg & 3))
 156                         continue;
 157
 158                 start = reg & 0xfff000;
 159                 reg = read_pci_config(bus, slot, 1, 0xc4 + (i << 3));
 160                 node = reg & 0x07;
 161                 link = (reg >> 4) & 0x03;
 162                 end = (reg & 0xfff000) | 0xfff;
 163
 164                 /* find the position */
 165                 for (j = 0; j < pci_root_num; j++) {
 166                         info = &pci_root_info[j];
 167                         if (info->node == node && info->link == link)
 168                                 break;
 169                 }
 170                 if (j == pci_root_num)
 171                         continue; /* not found */
 172
 173                 info = &pci_root_info[j];
 174                 printk(KERN_DEBUG "node %d link %d: io port [%llx, %llx]\n",
 175                        node, link, (u64)start, (u64)end);
 176
 177                 /* kernel only handle 16 bit only */
 178                 if (end > 0xffff)
 179                         end = 0xffff;
 180                 update_res(info, start, end, IORESOURCE_IO, 1);
 181                 subtract_range(range, RANGE_NUM, start, end);
 182         }
 183         /* add left over io port range to def node/link, [0, 0xffff] */
 184         /* find the position */
 185         for (j = 0; j < pci_root_num; j++) {
 186                 info = &pci_root_info[j];
 187                 if (info->node == def_node && info->link == def_link)
 188                         break;
 189         }
 190         if (j < pci_root_num) {
 191                 info = &pci_root_info[j];
 192                 for (i = 0; i < RANGE_NUM; i++) {
 193                         if (!range[i].end)
 194                                 continue;
 195
 196                         update_res(info, range[i].start, range[i].end,
 197                                    IORESOURCE_IO, 1);
 198                 }
 199         }
 200
 201         memset(range, 0, sizeof(range));
 202         /* 0xfd00000000-0xffffffffff for HT */
 203         range[0].end = (0xfdULL<<32) - 1;
 204
 205         /* need to take out [0, TOM) for RAM*/
 206         address = MSR_K8_TOP_MEM1;
 207         rdmsrl(address, val);
 208         end = (val & 0xffffff800000ULL);
 209         printk(KERN_INFO "TOM: %016lx aka %ldM\n", end, end>>20);
 210         if (end < (1ULL<<32))
 211                 subtract_range(range, RANGE_NUM, 0, end - 1);
 212
 213         /* get mmconfig */
 214         get_pci_mmcfg_amd_fam10h_range();
 215         /* need to take out mmconf range */
 216         if (fam10h_mmconf_end) {
 217                 printk(KERN_DEBUG "Fam 10h mmconf [%llx, %llx]\n", fam10h_mmconf_start, fam10h_mmconf_end);
 218                 subtract_range(range, RANGE_NUM, fam10h_mmconf_start, fam10h_mmconf_end);
 219         }
 220
 221         /* mmio resource */
 222         for (i = 0; i < 8; i++) {
 223                 reg = read_pci_config(bus, slot, 1, 0x80 + (i << 3));
 224                 if (!(reg & 3))
 225                         continue;
 226
 227                 start = reg & 0xffffff00; /* 39:16 on 31:8*/
 228                 start <<= 8;
 229                 reg = read_pci_config(bus, slot, 1, 0x84 + (i << 3));
 230                 node = reg & 0x07;
 231                 link = (reg >> 4) & 0x03;
 232                 end = (reg & 0xffffff00);
 233                 end <<= 8;
 234                 end |= 0xffff;
 235
 236                 /* find the position */
 237                 for (j = 0; j < pci_root_num; j++) {
 238                         info = &pci_root_info[j];
 239                         if (info->node == node && info->link == link)
 240                                 break;
 241                 }
 242                 if (j == pci_root_num)
 243                         continue; /* not found */
 244
 245                 info = &pci_root_info[j];
 246
 247                 printk(KERN_DEBUG "node %d link %d: mmio [%llx, %llx]",
 248                        node, link, (u64)start, (u64)end);
 249                 /*
 250                  * some sick allocation would have range overlap with fam10h
 251                  * mmconf range, so need to update start and end.
 252                  */
 253                 if (fam10h_mmconf_end) {
 254                         int changed = 0;
 255                         u64 endx = 0;
 256                         if (start >= fam10h_mmconf_start &&
 257                             start <= fam10h_mmconf_end) {
 258                                 start = fam10h_mmconf_end + 1;
 259                                 changed = 1;
 260                         }
 261
 262                         if (end >= fam10h_mmconf_start &&
 263                             end <= fam10h_mmconf_end) {
 264                                 end = fam10h_mmconf_start - 1;
 265                                 changed = 1;
 266                         }
 267
 268                         if (start < fam10h_mmconf_start &&
 269                             end > fam10h_mmconf_end) {
 270                                 /* we got a hole */
 271                                 endx = fam10h_mmconf_start - 1;
 272                                 update_res(info, start, endx, IORESOURCE_MEM, 0);
 273                                 subtract_range(range, RANGE_NUM, start, endx);
 274                                 printk(KERN_CONT " ==> [%llx, %llx]", (u64)start, endx);
 275                                 start = fam10h_mmconf_end + 1;
 276                                 changed = 1;
 277                         }
 278                         if (changed) {
 279                                 if (start <= end) {
 280                                         printk(KERN_CONT " %s [%llx, %llx]", endx?"and":"==>", (u64)start, (u64)end);
 281                                 } else {
 282                                         printk(KERN_CONT "%s\n", endx?"":" ==> none");
 283                                         continue;
 284                                 }
 285                         }
 286                 }
 287
 288                 update_res(info, start, end, IORESOURCE_MEM, 1);
 289                 subtract_range(range, RANGE_NUM, start, end);
 290                 printk(KERN_CONT "\n");
 291         }
 292
 293         /* need to take out [4G, TOM2) for RAM*/
 294         /* SYS_CFG */
 295         address = MSR_K8_SYSCFG;
 296         rdmsrl(address, val);
 297         /* TOP_MEM2 is enabled? */
 298         if (val & (1<<21)) {
 299                 /* TOP_MEM2 */
 300                 address = MSR_K8_TOP_MEM2;
 301                 rdmsrl(address, val);
 302                 end = (val & 0xffffff800000ULL);
 303                 printk(KERN_INFO "TOM2: %016lx aka %ldM\n", end, end>>20);
 304                 subtract_range(range, RANGE_NUM, 1ULL<<32, end - 1);
 305         }
 306
 307         /*
 308          * add left over mmio range to def node/link ?
 309          * that is tricky, just record range in from start_min to 4G
 310          */
 311         for (j = 0; j < pci_root_num; j++) {
 312                 info = &pci_root_info[j];
 313                 if (info->node == def_node && info->link == def_link)
 314                         break;
 315         }
 316         if (j < pci_root_num) {
 317                 info = &pci_root_info[j];
 318
 319                 for (i = 0; i < RANGE_NUM; i++) {
 320                         if (!range[i].end)
 321                                 continue;
 322
 323                         update_res(info, range[i].start, range[i].end,
 324                                    IORESOURCE_MEM, 1);
 325                 }
 326         }
 327
 328         for (i = 0; i < pci_root_num; i++) {
 329                 int res_num;
 330                 int busnum;
 331
 332                 info = &pci_root_info[i];
 333                 res_num = info->res_num;
 334                 busnum = info->bus_min;
 335                 printk(KERN_DEBUG "bus: [%02x, %02x] on node %x link %x\n",
 336                        info->bus_min, info->bus_max, info->node, info->link);
 337                 for (j = 0; j < res_num; j++) {
 338                         res = &info->res[j];
 339                         printk(KERN_DEBUG "bus: %02x index %x %s: [%llx, %llx]\n",
 340                                busnum, j,
 341                                (res->flags & IORESOURCE_IO)?"io port":"mmio",
 342                                res->start, res->end);
 343                 }
 344         }
 345
 346         return 0;
 347 }
 348
 349 #else  /* !CONFIG_X86_64 */
 350
 351 static int __init early_fill_mp_bus_info(void) { return 0; }
 352
 353 #endif /* !CONFIG_X86_64 */
 354
 355 /* common 32/64 bit code */
 356
 357 #define ENABLE_CF8_EXT_CFG      (1ULL << 46)
 358
 359 static void enable_pci_io_ecs(void *unused)
 360 {
 361         u64 reg;
 362         rdmsrl(MSR_AMD64_NB_CFG, reg);
 363         if (!(reg & ENABLE_CF8_EXT_CFG)) {
 364                 reg |= ENABLE_CF8_EXT_CFG;
 365                 wrmsrl(MSR_AMD64_NB_CFG, reg);
 366         }
 367 }
 368
 369 static int __cpuinit amd_cpu_notify(struct notifier_block *self,
 370                                     unsigned long action, void *hcpu)
 371 {
 372         int cpu = (long)hcpu;
 373         switch (action) {
 374         case CPU_ONLINE:
 375         case CPU_ONLINE_FROZEN:
 376                 smp_call_function_single(cpu, enable_pci_io_ecs, NULL, 0);
 377                 break;
 378         default:
 379                 break;
 380         }
 381         return NOTIFY_OK;
 382 }
 383
 384 static struct notifier_block __cpuinitdata amd_cpu_notifier = {
 385         .notifier_call  = amd_cpu_notify,
 386 };
 387
 388 static int __init pci_io_ecs_init(void)
 389 {
 390         int cpu;
 391
 392         /* assume all cpus from fam10h have IO ECS */
 393         if (boot_cpu_data.x86 < 0x10)
 394                 return 0;
 395
 396         register_cpu_notifier(&amd_cpu_notifier);
 397         for_each_online_cpu(cpu)
 398                 amd_cpu_notify(&amd_cpu_notifier, (unsigned long)CPU_ONLINE,
 399                                (void *)(long)cpu);
 400         pci_probe |= PCI_HAS_IO_ECS;
 401
 402         return 0;
 403 }
 404
 405 static int __init amd_postcore_init(void)
 406 {
 407         if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
 408                 return 0;
 409
 410         early_fill_mp_bus_info();
 411         pci_io_ecs_init();
 412
 413         return 0;
 414 }
 415
 416 postcore_initcall(amd_postcore_init);