arch/arm/plat-nomadik/timer.c

   1 /*
   2  *  linux/arch/arm/mach-nomadik/timer.c
   3  *
   4  * Copyright (C) 2008 STMicroelectronics
   5  * Copyright (C) 2010 Alessandro Rubini
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2, as
   9  * published by the Free Software Foundation.
  10  */
  11 #include <linux/init.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/irq.h>
  14 #include <linux/io.h>
  15 #include <linux/clockchips.h>
  16 #include <linux/jiffies.h>
  17 #include <asm/mach/time.h>
  18
  19 #include <plat/mtu.h>
  20
  21 void __iomem *mtu_base; /* ssigned by machine code */
  22
  23 /*
  24  * Kernel assumes that sched_clock can be called early
  25  * but the MTU may not yet be initialized.
  26  */
  27 static cycle_t nmdk_read_timer_dummy(struct clocksource *cs)
  28 {
  29         return 0;
  30 }
  31
  32 /* clocksource: MTU decrements, so we negate the value being read. */
  33 static cycle_t nmdk_read_timer(struct clocksource *cs)
  34 {
  35         return -readl(mtu_base + MTU_VAL(0));
  36 }
  37
  38 static struct clocksource nmdk_clksrc = {
  39         .name           = "mtu_0",
  40         .rating         = 200,
  41         .read           = nmdk_read_timer_dummy,
  42         .mask           = CLOCKSOURCE_MASK(32),
  43         .shift          = 20,
  44         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
  45 };
  46
  47 /*
  48  * Override the global weak sched_clock symbol with this
  49  * local implementation which uses the clocksource to get some
  50  * better resolution when scheduling the kernel. We accept that
  51  * this wraps around for now, since it is just a relative time
  52  * stamp. (Inspired by OMAP implementation.)
  53  */
  54 unsigned long long notrace sched_clock(void)
  55 {
  56         return clocksource_cyc2ns(nmdk_clksrc.read(
  57                                   &nmdk_clksrc),
  58                                   nmdk_clksrc.mult,
  59                                   nmdk_clksrc.shift);
  60 }
  61
  62 /* Clockevent device: use one-shot mode */
  63 static void nmdk_clkevt_mode(enum clock_event_mode mode,
  64                              struct clock_event_device *dev)
  65 {
  66         u32 cr;
  67
  68         switch (mode) {
  69         case CLOCK_EVT_MODE_PERIODIC:
  70                 pr_err("%s: periodic mode not supported\n", __func__);
  71                 break;
  72         case CLOCK_EVT_MODE_ONESHOT:
  73                 /* Load highest value, enable device, enable interrupts */
  74                 cr = readl(mtu_base + MTU_CR(1));
  75                 writel(0, mtu_base + MTU_LR(1));
  76                 writel(cr | MTU_CRn_ENA, mtu_base + MTU_CR(1));
  77                 writel(0x2, mtu_base + MTU_IMSC);
  78                 break;
  79         case CLOCK_EVT_MODE_SHUTDOWN:
  80         case CLOCK_EVT_MODE_UNUSED:
  81                 /* disable irq */
  82                 writel(0, mtu_base + MTU_IMSC);
  83                 break;
  84         case CLOCK_EVT_MODE_RESUME:
  85                 break;
  86         }
  87 }
  88
  89 static int nmdk_clkevt_next(unsigned long evt, struct clock_event_device *ev)
  90 {
  91         /* writing the value has immediate effect */
  92         writel(evt, mtu_base + MTU_LR(1));
  93         return 0;
  94 }
  95
  96 static struct clock_event_device nmdk_clkevt = {
  97         .name           = "mtu_1",
  98         .features       = CLOCK_EVT_FEAT_ONESHOT,
  99         .shift          = 32,
 100         .rating         = 200,
 101         .set_mode       = nmdk_clkevt_mode,
 102         .set_next_event = nmdk_clkevt_next,
 103 };
 104
 105 /*
 106  * IRQ Handler for timer 1 of the MTU block.
 107  */
 108 static irqreturn_t nmdk_timer_interrupt(int irq, void *dev_id)
 109 {
 110         struct clock_event_device *evdev = dev_id;
 111
 112         writel(1 << 1, mtu_base + MTU_ICR); /* Interrupt clear reg */
 113         evdev->event_handler(evdev);
 114         return IRQ_HANDLED;
 115 }
 116
 117 static struct irqaction nmdk_timer_irq = {
 118         .name           = "Nomadik Timer Tick",
 119         .flags          = IRQF_DISABLED | IRQF_TIMER,
 120         .handler        = nmdk_timer_interrupt,
 121         .dev_id         = &nmdk_clkevt,
 122 };
 123
 124 void __init nmdk_timer_init(void)
 125 {
 126         unsigned long rate;
 127         u32 cr = MTU_CRn_32BITS;;
 128
 129         /*
 130          * Tick rate is 2.4MHz for Nomadik and 110MHz for ux500:
 131          * use a divide-by-16 counter if it's more than 16MHz
 132          */
 133         rate = CLOCK_TICK_RATE;
 134         if (rate > 16 << 20) {
 135                 rate /= 16;
 136                 cr |= MTU_CRn_PRESCALE_16;
 137         } else {
 138                 cr |= MTU_CRn_PRESCALE_1;
 139         }
 140
 141         /* Timer 0 is the free running clocksource */
 142         writel(cr, mtu_base + MTU_CR(0));
 143         writel(0, mtu_base + MTU_LR(0));
 144         writel(0, mtu_base + MTU_BGLR(0));
 145         writel(cr | MTU_CRn_ENA, mtu_base + MTU_CR(0));
 146
 147         nmdk_clksrc.mult = clocksource_hz2mult(rate, nmdk_clksrc.shift);
 148         /* Now the scheduling clock is ready */
 149         nmdk_clksrc.read = nmdk_read_timer;
 150
 151         if (clocksource_register(&nmdk_clksrc))
 152                 pr_err("timer: failed to initialize clock source %s\n",
 153                        nmdk_clksrc.name);
 154
 155         /* Timer 1 is used for events, fix according to rate */
 156         writel(cr | MTU_CRn_ONESHOT, mtu_base + MTU_CR(1)); /* off, currently */
 157         nmdk_clkevt.mult = div_sc(rate, NSEC_PER_SEC, nmdk_clkevt.shift);
 158         nmdk_clkevt.max_delta_ns =
 159                 clockevent_delta2ns(0xffffffff, &nmdk_clkevt);
 160         nmdk_clkevt.min_delta_ns =
 161                 clockevent_delta2ns(0x00000002, &nmdk_clkevt);
 162         nmdk_clkevt.cpumask     = cpumask_of(0);
 163
 164         /* Register irq and clockevents */
 165         setup_irq(IRQ_MTU0, &nmdk_timer_irq);
 166         clockevents_register_device(&nmdk_clkevt);
 167 }