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Merge branch 'cpus4096-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / arch / x86 / kernel / io_apic_64.c
blob8269434d170765a6466eb7039e2b849d8b0b5b18
1 /*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
22
23 #include <linux/mm.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/acpi.h>
31 #include <linux/sysdev.h>
32 #include <linux/msi.h>
33 #include <linux/htirq.h>
34 #include <linux/dmar.h>
35 #include <linux/jiffies.h>
36 #ifdef CONFIG_ACPI
37 #include <acpi/acpi_bus.h>
38 #endif
39 #include <linux/bootmem.h>
40
41 #include <asm/idle.h>
42 #include <asm/io.h>
43 #include <asm/smp.h>
44 #include <asm/desc.h>
45 #include <asm/proto.h>
46 #include <asm/acpi.h>
47 #include <asm/dma.h>
48 #include <asm/i8259.h>
49 #include <asm/nmi.h>
50 #include <asm/msidef.h>
51 #include <asm/hypertransport.h>
52
53 #include <mach_ipi.h>
54 #include <mach_apic.h>
55
56 struct irq_cfg {
57 cpumask_t domain;
58 cpumask_t old_domain;
59 unsigned move_cleanup_count;
60 u8 vector;
61 u8 move_in_progress : 1;
62 };
63
64 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
65 static struct irq_cfg irq_cfg[NR_IRQS] __read_mostly = {
66 [0] = { .domain = CPU_MASK_ALL, .vector = IRQ0_VECTOR, },
67 [1] = { .domain = CPU_MASK_ALL, .vector = IRQ1_VECTOR, },
68 [2] = { .domain = CPU_MASK_ALL, .vector = IRQ2_VECTOR, },
69 [3] = { .domain = CPU_MASK_ALL, .vector = IRQ3_VECTOR, },
70 [4] = { .domain = CPU_MASK_ALL, .vector = IRQ4_VECTOR, },
71 [5] = { .domain = CPU_MASK_ALL, .vector = IRQ5_VECTOR, },
72 [6] = { .domain = CPU_MASK_ALL, .vector = IRQ6_VECTOR, },
73 [7] = { .domain = CPU_MASK_ALL, .vector = IRQ7_VECTOR, },
74 [8] = { .domain = CPU_MASK_ALL, .vector = IRQ8_VECTOR, },
75 [9] = { .domain = CPU_MASK_ALL, .vector = IRQ9_VECTOR, },
76 [10] = { .domain = CPU_MASK_ALL, .vector = IRQ10_VECTOR, },
77 [11] = { .domain = CPU_MASK_ALL, .vector = IRQ11_VECTOR, },
78 [12] = { .domain = CPU_MASK_ALL, .vector = IRQ12_VECTOR, },
79 [13] = { .domain = CPU_MASK_ALL, .vector = IRQ13_VECTOR, },
80 [14] = { .domain = CPU_MASK_ALL, .vector = IRQ14_VECTOR, },
81 [15] = { .domain = CPU_MASK_ALL, .vector = IRQ15_VECTOR, },
82 };
83
84 static int assign_irq_vector(int irq, cpumask_t mask);
85
86 int first_system_vector = 0xfe;
87
88 char system_vectors[NR_VECTORS] = { [0 ... NR_VECTORS-1] = SYS_VECTOR_FREE};
89
90 #define __apicdebuginit __init
91
92 int sis_apic_bug; /* not actually supported, dummy for compile */
93
94 static int no_timer_check;
95
96 static int disable_timer_pin_1 __initdata;
97
98 int timer_through_8259 __initdata;
99
100 /* Where if anywhere is the i8259 connect in external int mode */
101 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
102
103 static DEFINE_SPINLOCK(ioapic_lock);
104 DEFINE_SPINLOCK(vector_lock);
105
106 /*
107 * # of IRQ routing registers
108 */
109 int nr_ioapic_registers[MAX_IO_APICS];
110
111 /* I/O APIC entries */
112 struct mp_config_ioapic mp_ioapics[MAX_IO_APICS];
113 int nr_ioapics;
114
115 /* MP IRQ source entries */
116 struct mp_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
117
118 /* # of MP IRQ source entries */
119 int mp_irq_entries;
120
121 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
122
123 /*
124 * Rough estimation of how many shared IRQs there are, can
125 * be changed anytime.
126 */
127 #define MAX_PLUS_SHARED_IRQS NR_IRQS
128 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
129
130 /*
131 * This is performance-critical, we want to do it O(1)
132 *
133 * the indexing order of this array favors 1:1 mappings
134 * between pins and IRQs.
135 */
136
137 static struct irq_pin_list {
138 short apic, pin, next;
139 } irq_2_pin[PIN_MAP_SIZE];
140
141 struct io_apic {
142 unsigned int index;
143 unsigned int unused[3];
144 unsigned int data;
145 };
146
147 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
148 {
149 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
150 + (mp_ioapics[idx].mp_apicaddr & ~PAGE_MASK);
151 }
152
153 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
154 {
155 struct io_apic __iomem *io_apic = io_apic_base(apic);
156 writel(reg, &io_apic->index);
157 return readl(&io_apic->data);
158 }
159
160 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
161 {
162 struct io_apic __iomem *io_apic = io_apic_base(apic);
163 writel(reg, &io_apic->index);
164 writel(value, &io_apic->data);
165 }
166
167 /*
168 * Re-write a value: to be used for read-modify-write
169 * cycles where the read already set up the index register.
170 */
171 static inline void io_apic_modify(unsigned int apic, unsigned int value)
172 {
173 struct io_apic __iomem *io_apic = io_apic_base(apic);
174 writel(value, &io_apic->data);
175 }
176
177 static bool io_apic_level_ack_pending(unsigned int irq)
178 {
179 struct irq_pin_list *entry;
180 unsigned long flags;
181
182 spin_lock_irqsave(&ioapic_lock, flags);
183 entry = irq_2_pin + irq;
184 for (;;) {
185 unsigned int reg;
186 int pin;
187
188 pin = entry->pin;
189 if (pin == -1)
190 break;
191 reg = io_apic_read(entry->apic, 0x10 + pin*2);
192 /* Is the remote IRR bit set? */
193 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
194 spin_unlock_irqrestore(&ioapic_lock, flags);
195 return true;
196 }
197 if (!entry->next)
198 break;
199 entry = irq_2_pin + entry->next;
200 }
201 spin_unlock_irqrestore(&ioapic_lock, flags);
202
203 return false;
204 }
205
206 /*
207 * Synchronize the IO-APIC and the CPU by doing
208 * a dummy read from the IO-APIC
209 */
210 static inline void io_apic_sync(unsigned int apic)
211 {
212 struct io_apic __iomem *io_apic = io_apic_base(apic);
213 readl(&io_apic->data);
214 }
215
216 #define __DO_ACTION(R, ACTION, FINAL) \
217 \
218 { \
219 int pin; \
220 struct irq_pin_list *entry = irq_2_pin + irq; \
221 \
222 BUG_ON(irq >= NR_IRQS); \
223 for (;;) { \
224 unsigned int reg; \
225 pin = entry->pin; \
226 if (pin == -1) \
227 break; \
228 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
229 reg ACTION; \
230 io_apic_modify(entry->apic, reg); \
231 FINAL; \
232 if (!entry->next) \
233 break; \
234 entry = irq_2_pin + entry->next; \
235 } \
236 }
237
238 union entry_union {
239 struct { u32 w1, w2; };
240 struct IO_APIC_route_entry entry;
241 };
242
243 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
244 {
245 union entry_union eu;
246 unsigned long flags;
247 spin_lock_irqsave(&ioapic_lock, flags);
248 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
249 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
250 spin_unlock_irqrestore(&ioapic_lock, flags);
251 return eu.entry;
252 }
253
254 /*
255 * When we write a new IO APIC routing entry, we need to write the high
256 * word first! If the mask bit in the low word is clear, we will enable
257 * the interrupt, and we need to make sure the entry is fully populated
258 * before that happens.
259 */
260 static void
261 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
262 {
263 union entry_union eu;
264 eu.entry = e;
265 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
266 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
267 }
268
269 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
270 {
271 unsigned long flags;
272 spin_lock_irqsave(&ioapic_lock, flags);
273 __ioapic_write_entry(apic, pin, e);
274 spin_unlock_irqrestore(&ioapic_lock, flags);
275 }
276
277 /*
278 * When we mask an IO APIC routing entry, we need to write the low
279 * word first, in order to set the mask bit before we change the
280 * high bits!
281 */
282 static void ioapic_mask_entry(int apic, int pin)
283 {
284 unsigned long flags;
285 union entry_union eu = { .entry.mask = 1 };
286
287 spin_lock_irqsave(&ioapic_lock, flags);
288 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
289 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
290 spin_unlock_irqrestore(&ioapic_lock, flags);
291 }
292
293 #ifdef CONFIG_SMP
294 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
295 {
296 int apic, pin;
297 struct irq_pin_list *entry = irq_2_pin + irq;
298
299 BUG_ON(irq >= NR_IRQS);
300 for (;;) {
301 unsigned int reg;
302 apic = entry->apic;
303 pin = entry->pin;
304 if (pin == -1)
305 break;
306 io_apic_write(apic, 0x11 + pin*2, dest);
307 reg = io_apic_read(apic, 0x10 + pin*2);
308 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
309 reg |= vector;
310 io_apic_modify(apic, reg);
311 if (!entry->next)
312 break;
313 entry = irq_2_pin + entry->next;
314 }
315 }
316
317 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
318 {
319 struct irq_cfg *cfg = irq_cfg + irq;
320 unsigned long flags;
321 unsigned int dest;
322 cpumask_t tmp;
323
324 cpus_and(tmp, mask, cpu_online_map);
325 if (cpus_empty(tmp))
326 return;
327
328 if (assign_irq_vector(irq, mask))
329 return;
330
331 cpus_and(tmp, cfg->domain, mask);
332 dest = cpu_mask_to_apicid(tmp);
333
334 /*
335 * Only the high 8 bits are valid.
336 */
337 dest = SET_APIC_LOGICAL_ID(dest);
338
339 spin_lock_irqsave(&ioapic_lock, flags);
340 __target_IO_APIC_irq(irq, dest, cfg->vector);
341 irq_desc[irq].affinity = mask;
342 spin_unlock_irqrestore(&ioapic_lock, flags);
343 }
344 #endif
345
346 /*
347 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
348 * shared ISA-space IRQs, so we have to support them. We are super
349 * fast in the common case, and fast for shared ISA-space IRQs.
350 */
351 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
352 {
353 static int first_free_entry = NR_IRQS;
354 struct irq_pin_list *entry = irq_2_pin + irq;
355
356 BUG_ON(irq >= NR_IRQS);
357 while (entry->next)
358 entry = irq_2_pin + entry->next;
359
360 if (entry->pin != -1) {
361 entry->next = first_free_entry;
362 entry = irq_2_pin + entry->next;
363 if (++first_free_entry >= PIN_MAP_SIZE)
364 panic("io_apic.c: ran out of irq_2_pin entries!");
365 }
366 entry->apic = apic;
367 entry->pin = pin;
368 }
369
370 /*
371 * Reroute an IRQ to a different pin.
372 */
373 static void __init replace_pin_at_irq(unsigned int irq,
374 int oldapic, int oldpin,
375 int newapic, int newpin)
376 {
377 struct irq_pin_list *entry = irq_2_pin + irq;
378
379 while (1) {
380 if (entry->apic == oldapic && entry->pin == oldpin) {
381 entry->apic = newapic;
382 entry->pin = newpin;
383 }
384 if (!entry->next)
385 break;
386 entry = irq_2_pin + entry->next;
387 }
388 }
389
390
391 #define DO_ACTION(name,R,ACTION, FINAL) \
392 \
393 static void name##_IO_APIC_irq (unsigned int irq) \
394 __DO_ACTION(R, ACTION, FINAL)
395
396 /* mask = 1 */
397 DO_ACTION(__mask, 0, |= IO_APIC_REDIR_MASKED, io_apic_sync(entry->apic))
398
399 /* mask = 0 */
400 DO_ACTION(__unmask, 0, &= ~IO_APIC_REDIR_MASKED, )
401
402 static void mask_IO_APIC_irq (unsigned int irq)
403 {
404 unsigned long flags;
405
406 spin_lock_irqsave(&ioapic_lock, flags);
407 __mask_IO_APIC_irq(irq);
408 spin_unlock_irqrestore(&ioapic_lock, flags);
409 }
410
411 static void unmask_IO_APIC_irq (unsigned int irq)
412 {
413 unsigned long flags;
414
415 spin_lock_irqsave(&ioapic_lock, flags);
416 __unmask_IO_APIC_irq(irq);
417 spin_unlock_irqrestore(&ioapic_lock, flags);
418 }
419
420 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
421 {
422 struct IO_APIC_route_entry entry;
423
424 /* Check delivery_mode to be sure we're not clearing an SMI pin */
425 entry = ioapic_read_entry(apic, pin);
426 if (entry.delivery_mode == dest_SMI)
427 return;
428 /*
429 * Disable it in the IO-APIC irq-routing table:
430 */
431 ioapic_mask_entry(apic, pin);
432 }
433
434 static void clear_IO_APIC (void)
435 {
436 int apic, pin;
437
438 for (apic = 0; apic < nr_ioapics; apic++)
439 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
440 clear_IO_APIC_pin(apic, pin);
441 }
442
443 int skip_ioapic_setup;
444 int ioapic_force;
445
446 static int __init parse_noapic(char *str)
447 {
448 disable_ioapic_setup();
449 return 0;
450 }
451 early_param("noapic", parse_noapic);
452
453 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
454 static int __init disable_timer_pin_setup(char *arg)
455 {
456 disable_timer_pin_1 = 1;
457 return 1;
458 }
459 __setup("disable_timer_pin_1", disable_timer_pin_setup);
460
461
462 /*
463 * Find the IRQ entry number of a certain pin.
464 */
465 static int find_irq_entry(int apic, int pin, int type)
466 {
467 int i;
468
469 for (i = 0; i < mp_irq_entries; i++)
470 if (mp_irqs[i].mp_irqtype == type &&
471 (mp_irqs[i].mp_dstapic == mp_ioapics[apic].mp_apicid ||
472 mp_irqs[i].mp_dstapic == MP_APIC_ALL) &&
473 mp_irqs[i].mp_dstirq == pin)
474 return i;
475
476 return -1;
477 }
478
479 /*
480 * Find the pin to which IRQ[irq] (ISA) is connected
481 */
482 static int __init find_isa_irq_pin(int irq, int type)
483 {
484 int i;
485
486 for (i = 0; i < mp_irq_entries; i++) {
487 int lbus = mp_irqs[i].mp_srcbus;
488
489 if (test_bit(lbus, mp_bus_not_pci) &&
490 (mp_irqs[i].mp_irqtype == type) &&
491 (mp_irqs[i].mp_srcbusirq == irq))
492
493 return mp_irqs[i].mp_dstirq;
494 }
495 return -1;
496 }
497
498 static int __init find_isa_irq_apic(int irq, int type)
499 {
500 int i;
501
502 for (i = 0; i < mp_irq_entries; i++) {
503 int lbus = mp_irqs[i].mp_srcbus;
504
505 if (test_bit(lbus, mp_bus_not_pci) &&
506 (mp_irqs[i].mp_irqtype == type) &&
507 (mp_irqs[i].mp_srcbusirq == irq))
508 break;
509 }
510 if (i < mp_irq_entries) {
511 int apic;
512 for(apic = 0; apic < nr_ioapics; apic++) {
513 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic)
514 return apic;
515 }
516 }
517
518 return -1;
519 }
520
521 /*
522 * Find a specific PCI IRQ entry.
523 * Not an __init, possibly needed by modules
524 */
525 static int pin_2_irq(int idx, int apic, int pin);
526
527 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
528 {
529 int apic, i, best_guess = -1;
530
531 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
532 bus, slot, pin);
533 if (test_bit(bus, mp_bus_not_pci)) {
534 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
535 return -1;
536 }
537 for (i = 0; i < mp_irq_entries; i++) {
538 int lbus = mp_irqs[i].mp_srcbus;
539
540 for (apic = 0; apic < nr_ioapics; apic++)
541 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic ||
542 mp_irqs[i].mp_dstapic == MP_APIC_ALL)
543 break;
544
545 if (!test_bit(lbus, mp_bus_not_pci) &&
546 !mp_irqs[i].mp_irqtype &&
547 (bus == lbus) &&
548 (slot == ((mp_irqs[i].mp_srcbusirq >> 2) & 0x1f))) {
549 int irq = pin_2_irq(i,apic,mp_irqs[i].mp_dstirq);
550
551 if (!(apic || IO_APIC_IRQ(irq)))
552 continue;
553
554 if (pin == (mp_irqs[i].mp_srcbusirq & 3))
555 return irq;
556 /*
557 * Use the first all-but-pin matching entry as a
558 * best-guess fuzzy result for broken mptables.
559 */
560 if (best_guess < 0)
561 best_guess = irq;
562 }
563 }
564 BUG_ON(best_guess >= NR_IRQS);
565 return best_guess;
566 }
567
568 /* ISA interrupts are always polarity zero edge triggered,
569 * when listed as conforming in the MP table. */
570
571 #define default_ISA_trigger(idx) (0)
572 #define default_ISA_polarity(idx) (0)
573
574 /* PCI interrupts are always polarity one level triggered,
575 * when listed as conforming in the MP table. */
576
577 #define default_PCI_trigger(idx) (1)
578 #define default_PCI_polarity(idx) (1)
579
580 static int MPBIOS_polarity(int idx)
581 {
582 int bus = mp_irqs[idx].mp_srcbus;
583 int polarity;
584
585 /*
586 * Determine IRQ line polarity (high active or low active):
587 */
588 switch (mp_irqs[idx].mp_irqflag & 3)
589 {
590 case 0: /* conforms, ie. bus-type dependent polarity */
591 if (test_bit(bus, mp_bus_not_pci))
592 polarity = default_ISA_polarity(idx);
593 else
594 polarity = default_PCI_polarity(idx);
595 break;
596 case 1: /* high active */
597 {
598 polarity = 0;
599 break;
600 }
601 case 2: /* reserved */
602 {
603 printk(KERN_WARNING "broken BIOS!!\n");
604 polarity = 1;
605 break;
606 }
607 case 3: /* low active */
608 {
609 polarity = 1;
610 break;
611 }
612 default: /* invalid */
613 {
614 printk(KERN_WARNING "broken BIOS!!\n");
615 polarity = 1;
616 break;
617 }
618 }
619 return polarity;
620 }
621
622 static int MPBIOS_trigger(int idx)
623 {
624 int bus = mp_irqs[idx].mp_srcbus;
625 int trigger;
626
627 /*
628 * Determine IRQ trigger mode (edge or level sensitive):
629 */
630 switch ((mp_irqs[idx].mp_irqflag>>2) & 3)
631 {
632 case 0: /* conforms, ie. bus-type dependent */
633 if (test_bit(bus, mp_bus_not_pci))
634 trigger = default_ISA_trigger(idx);
635 else
636 trigger = default_PCI_trigger(idx);
637 break;
638 case 1: /* edge */
639 {
640 trigger = 0;
641 break;
642 }
643 case 2: /* reserved */
644 {
645 printk(KERN_WARNING "broken BIOS!!\n");
646 trigger = 1;
647 break;
648 }
649 case 3: /* level */
650 {
651 trigger = 1;
652 break;
653 }
654 default: /* invalid */
655 {
656 printk(KERN_WARNING "broken BIOS!!\n");
657 trigger = 0;
658 break;
659 }
660 }
661 return trigger;
662 }
663
664 static inline int irq_polarity(int idx)
665 {
666 return MPBIOS_polarity(idx);
667 }
668
669 static inline int irq_trigger(int idx)
670 {
671 return MPBIOS_trigger(idx);
672 }
673
674 static int pin_2_irq(int idx, int apic, int pin)
675 {
676 int irq, i;
677 int bus = mp_irqs[idx].mp_srcbus;
678
679 /*
680 * Debugging check, we are in big trouble if this message pops up!
681 */
682 if (mp_irqs[idx].mp_dstirq != pin)
683 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
684
685 if (test_bit(bus, mp_bus_not_pci)) {
686 irq = mp_irqs[idx].mp_srcbusirq;
687 } else {
688 /*
689 * PCI IRQs are mapped in order
690 */
691 i = irq = 0;
692 while (i < apic)
693 irq += nr_ioapic_registers[i++];
694 irq += pin;
695 }
696 BUG_ON(irq >= NR_IRQS);
697 return irq;
698 }
699
700 static int __assign_irq_vector(int irq, cpumask_t mask)
701 {
702 /*
703 * NOTE! The local APIC isn't very good at handling
704 * multiple interrupts at the same interrupt level.
705 * As the interrupt level is determined by taking the
706 * vector number and shifting that right by 4, we
707 * want to spread these out a bit so that they don't
708 * all fall in the same interrupt level.
709 *
710 * Also, we've got to be careful not to trash gate
711 * 0x80, because int 0x80 is hm, kind of importantish. ;)
712 */
713 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
714 unsigned int old_vector;
715 int cpu;
716 struct irq_cfg *cfg;
717
718 BUG_ON((unsigned)irq >= NR_IRQS);
719 cfg = &irq_cfg[irq];
720
721 /* Only try and allocate irqs on cpus that are present */
722 cpus_and(mask, mask, cpu_online_map);
723
724 if ((cfg->move_in_progress) || cfg->move_cleanup_count)
725 return -EBUSY;
726
727 old_vector = cfg->vector;
728 if (old_vector) {
729 cpumask_t tmp;
730 cpus_and(tmp, cfg->domain, mask);
731 if (!cpus_empty(tmp))
732 return 0;
733 }
734
735 for_each_cpu_mask_nr(cpu, mask) {
736 cpumask_t domain, new_mask;
737 int new_cpu;
738 int vector, offset;
739
740 domain = vector_allocation_domain(cpu);
741 cpus_and(new_mask, domain, cpu_online_map);
742
743 vector = current_vector;
744 offset = current_offset;
745 next:
746 vector += 8;
747 if (vector >= first_system_vector) {
748 /* If we run out of vectors on large boxen, must share them. */
749 offset = (offset + 1) % 8;
750 vector = FIRST_DEVICE_VECTOR + offset;
751 }
752 if (unlikely(current_vector == vector))
753 continue;
754 if (vector == IA32_SYSCALL_VECTOR)
755 goto next;
756 for_each_cpu_mask_nr(new_cpu, new_mask)
757 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
758 goto next;
759 /* Found one! */
760 current_vector = vector;
761 current_offset = offset;
762 if (old_vector) {
763 cfg->move_in_progress = 1;
764 cfg->old_domain = cfg->domain;
765 }
766 for_each_cpu_mask_nr(new_cpu, new_mask)
767 per_cpu(vector_irq, new_cpu)[vector] = irq;
768 cfg->vector = vector;
769 cfg->domain = domain;
770 return 0;
771 }
772 return -ENOSPC;
773 }
774
775 static int assign_irq_vector(int irq, cpumask_t mask)
776 {
777 int err;
778 unsigned long flags;
779
780 spin_lock_irqsave(&vector_lock, flags);
781 err = __assign_irq_vector(irq, mask);
782 spin_unlock_irqrestore(&vector_lock, flags);
783 return err;
784 }
785
786 static void __clear_irq_vector(int irq)
787 {
788 struct irq_cfg *cfg;
789 cpumask_t mask;
790 int cpu, vector;
791
792 BUG_ON((unsigned)irq >= NR_IRQS);
793 cfg = &irq_cfg[irq];
794 BUG_ON(!cfg->vector);
795
796 vector = cfg->vector;
797 cpus_and(mask, cfg->domain, cpu_online_map);
798 for_each_cpu_mask_nr(cpu, mask)
799 per_cpu(vector_irq, cpu)[vector] = -1;
800
801 cfg->vector = 0;
802 cpus_clear(cfg->domain);
803 }
804
805 static void __setup_vector_irq(int cpu)
806 {
807 /* Initialize vector_irq on a new cpu */
808 /* This function must be called with vector_lock held */
809 int irq, vector;
810
811 /* Mark the inuse vectors */
812 for (irq = 0; irq < NR_IRQS; ++irq) {
813 if (!cpu_isset(cpu, irq_cfg[irq].domain))
814 continue;
815 vector = irq_cfg[irq].vector;
816 per_cpu(vector_irq, cpu)[vector] = irq;
817 }
818 /* Mark the free vectors */
819 for (vector = 0; vector < NR_VECTORS; ++vector) {
820 irq = per_cpu(vector_irq, cpu)[vector];
821 if (irq < 0)
822 continue;
823 if (!cpu_isset(cpu, irq_cfg[irq].domain))
824 per_cpu(vector_irq, cpu)[vector] = -1;
825 }
826 }
827
828 void setup_vector_irq(int cpu)
829 {
830 spin_lock(&vector_lock);
831 __setup_vector_irq(smp_processor_id());
832 spin_unlock(&vector_lock);
833 }
834
835
836 static struct irq_chip ioapic_chip;
837
838 static void ioapic_register_intr(int irq, unsigned long trigger)
839 {
840 if (trigger) {
841 irq_desc[irq].status |= IRQ_LEVEL;
842 set_irq_chip_and_handler_name(irq, &ioapic_chip,
843 handle_fasteoi_irq, "fasteoi");
844 } else {
845 irq_desc[irq].status &= ~IRQ_LEVEL;
846 set_irq_chip_and_handler_name(irq, &ioapic_chip,
847 handle_edge_irq, "edge");
848 }
849 }
850
851 static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq,
852 int trigger, int polarity)
853 {
854 struct irq_cfg *cfg = irq_cfg + irq;
855 struct IO_APIC_route_entry entry;
856 cpumask_t mask;
857
858 if (!IO_APIC_IRQ(irq))
859 return;
860
861 mask = TARGET_CPUS;
862 if (assign_irq_vector(irq, mask))
863 return;
864
865 cpus_and(mask, cfg->domain, mask);
866
867 apic_printk(APIC_VERBOSE,KERN_DEBUG
868 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
869 "IRQ %d Mode:%i Active:%i)\n",
870 apic, mp_ioapics[apic].mp_apicid, pin, cfg->vector,
871 irq, trigger, polarity);
872
873 /*
874 * add it to the IO-APIC irq-routing table:
875 */
876 memset(&entry,0,sizeof(entry));
877
878 entry.delivery_mode = INT_DELIVERY_MODE;
879 entry.dest_mode = INT_DEST_MODE;
880 entry.dest = cpu_mask_to_apicid(mask);
881 entry.mask = 0; /* enable IRQ */
882 entry.trigger = trigger;
883 entry.polarity = polarity;
884 entry.vector = cfg->vector;
885
886 /* Mask level triggered irqs.
887 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
888 */
889 if (trigger)
890 entry.mask = 1;
891
892 ioapic_register_intr(irq, trigger);
893 if (irq < 16)
894 disable_8259A_irq(irq);
895
896 ioapic_write_entry(apic, pin, entry);
897 }
898
899 static void __init setup_IO_APIC_irqs(void)
900 {
901 int apic, pin, idx, irq, first_notcon = 1;
902
903 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
904
905 for (apic = 0; apic < nr_ioapics; apic++) {
906 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
907
908 idx = find_irq_entry(apic,pin,mp_INT);
909 if (idx == -1) {
910 if (first_notcon) {
911 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mp_apicid, pin);
912 first_notcon = 0;
913 } else
914 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mp_apicid, pin);
915 continue;
916 }
917 if (!first_notcon) {
918 apic_printk(APIC_VERBOSE, " not connected.\n");
919 first_notcon = 1;
920 }
921
922 irq = pin_2_irq(idx, apic, pin);
923 add_pin_to_irq(irq, apic, pin);
924
925 setup_IO_APIC_irq(apic, pin, irq,
926 irq_trigger(idx), irq_polarity(idx));
927 }
928 }
929
930 if (!first_notcon)
931 apic_printk(APIC_VERBOSE, " not connected.\n");
932 }
933
934 /*
935 * Set up the timer pin, possibly with the 8259A-master behind.
936 */
937 static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin,
938 int vector)
939 {
940 struct IO_APIC_route_entry entry;
941
942 memset(&entry, 0, sizeof(entry));
943
944 /*
945 * We use logical delivery to get the timer IRQ
946 * to the first CPU.
947 */
948 entry.dest_mode = INT_DEST_MODE;
949 entry.mask = 1; /* mask IRQ now */
950 entry.dest = cpu_mask_to_apicid(TARGET_CPUS);
951 entry.delivery_mode = INT_DELIVERY_MODE;
952 entry.polarity = 0;
953 entry.trigger = 0;
954 entry.vector = vector;
955
956 /*
957 * The timer IRQ doesn't have to know that behind the
958 * scene we may have a 8259A-master in AEOI mode ...
959 */
960 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
961
962 /*
963 * Add it to the IO-APIC irq-routing table:
964 */
965 ioapic_write_entry(apic, pin, entry);
966 }
967
968 void __apicdebuginit print_IO_APIC(void)
969 {
970 int apic, i;
971 union IO_APIC_reg_00 reg_00;
972 union IO_APIC_reg_01 reg_01;
973 union IO_APIC_reg_02 reg_02;
974 unsigned long flags;
975
976 if (apic_verbosity == APIC_QUIET)
977 return;
978
979 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
980 for (i = 0; i < nr_ioapics; i++)
981 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
982 mp_ioapics[i].mp_apicid, nr_ioapic_registers[i]);
983
984 /*
985 * We are a bit conservative about what we expect. We have to
986 * know about every hardware change ASAP.
987 */
988 printk(KERN_INFO "testing the IO APIC.......................\n");
989
990 for (apic = 0; apic < nr_ioapics; apic++) {
991
992 spin_lock_irqsave(&ioapic_lock, flags);
993 reg_00.raw = io_apic_read(apic, 0);
994 reg_01.raw = io_apic_read(apic, 1);
995 if (reg_01.bits.version >= 0x10)
996 reg_02.raw = io_apic_read(apic, 2);
997 spin_unlock_irqrestore(&ioapic_lock, flags);
998
999 printk("\n");
1000 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mp_apicid);
1001 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1002 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1003
1004 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
1005 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1006
1007 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1008 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1009
1010 if (reg_01.bits.version >= 0x10) {
1011 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1012 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1013 }
1014
1015 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1016
1017 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1018 " Stat Dmod Deli Vect: \n");
1019
1020 for (i = 0; i <= reg_01.bits.entries; i++) {
1021 struct IO_APIC_route_entry entry;
1022
1023 entry = ioapic_read_entry(apic, i);
1024
1025 printk(KERN_DEBUG " %02x %03X ",
1026 i,
1027 entry.dest
1028 );
1029
1030 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1031 entry.mask,
1032 entry.trigger,
1033 entry.irr,
1034 entry.polarity,
1035 entry.delivery_status,
1036 entry.dest_mode,
1037 entry.delivery_mode,
1038 entry.vector
1039 );
1040 }
1041 }
1042 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1043 for (i = 0; i < NR_IRQS; i++) {
1044 struct irq_pin_list *entry = irq_2_pin + i;
1045 if (entry->pin < 0)
1046 continue;
1047 printk(KERN_DEBUG "IRQ%d ", i);
1048 for (;;) {
1049 printk("-> %d:%d", entry->apic, entry->pin);
1050 if (!entry->next)
1051 break;
1052 entry = irq_2_pin + entry->next;
1053 }
1054 printk("\n");
1055 }
1056
1057 printk(KERN_INFO ".................................... done.\n");
1058
1059 return;
1060 }
1061
1062 #if 0
1063
1064 static __apicdebuginit void print_APIC_bitfield (int base)
1065 {
1066 unsigned int v;
1067 int i, j;
1068
1069 if (apic_verbosity == APIC_QUIET)
1070 return;
1071
1072 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1073 for (i = 0; i < 8; i++) {
1074 v = apic_read(base + i*0x10);
1075 for (j = 0; j < 32; j++) {
1076 if (v & (1<<j))
1077 printk("1");
1078 else
1079 printk("0");
1080 }
1081 printk("\n");
1082 }
1083 }
1084
1085 void __apicdebuginit print_local_APIC(void * dummy)
1086 {
1087 unsigned int v, ver, maxlvt;
1088
1089 if (apic_verbosity == APIC_QUIET)
1090 return;
1091
1092 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1093 smp_processor_id(), hard_smp_processor_id());
1094 v = apic_read(APIC_ID);
1095 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(read_apic_id()));
1096 v = apic_read(APIC_LVR);
1097 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1098 ver = GET_APIC_VERSION(v);
1099 maxlvt = lapic_get_maxlvt();
1100
1101 v = apic_read(APIC_TASKPRI);
1102 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1103
1104 v = apic_read(APIC_ARBPRI);
1105 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1106 v & APIC_ARBPRI_MASK);
1107 v = apic_read(APIC_PROCPRI);
1108 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1109
1110 v = apic_read(APIC_EOI);
1111 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1112 v = apic_read(APIC_RRR);
1113 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1114 v = apic_read(APIC_LDR);
1115 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1116 v = apic_read(APIC_DFR);
1117 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1118 v = apic_read(APIC_SPIV);
1119 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1120
1121 printk(KERN_DEBUG "... APIC ISR field:\n");
1122 print_APIC_bitfield(APIC_ISR);
1123 printk(KERN_DEBUG "... APIC TMR field:\n");
1124 print_APIC_bitfield(APIC_TMR);
1125 printk(KERN_DEBUG "... APIC IRR field:\n");
1126 print_APIC_bitfield(APIC_IRR);
1127
1128 v = apic_read(APIC_ESR);
1129 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1130
1131 v = apic_read(APIC_ICR);
1132 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1133 v = apic_read(APIC_ICR2);
1134 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1135
1136 v = apic_read(APIC_LVTT);
1137 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1138
1139 if (maxlvt > 3) { /* PC is LVT#4. */
1140 v = apic_read(APIC_LVTPC);
1141 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1142 }
1143 v = apic_read(APIC_LVT0);
1144 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1145 v = apic_read(APIC_LVT1);
1146 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1147
1148 if (maxlvt > 2) { /* ERR is LVT#3. */
1149 v = apic_read(APIC_LVTERR);
1150 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1151 }
1152
1153 v = apic_read(APIC_TMICT);
1154 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1155 v = apic_read(APIC_TMCCT);
1156 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1157 v = apic_read(APIC_TDCR);
1158 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1159 printk("\n");
1160 }
1161
1162 void print_all_local_APICs (void)
1163 {
1164 on_each_cpu(print_local_APIC, NULL, 1);
1165 }
1166
1167 void __apicdebuginit print_PIC(void)
1168 {
1169 unsigned int v;
1170 unsigned long flags;
1171
1172 if (apic_verbosity == APIC_QUIET)
1173 return;
1174
1175 printk(KERN_DEBUG "\nprinting PIC contents\n");
1176
1177 spin_lock_irqsave(&i8259A_lock, flags);
1178
1179 v = inb(0xa1) << 8 | inb(0x21);
1180 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1181
1182 v = inb(0xa0) << 8 | inb(0x20);
1183 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1184
1185 outb(0x0b,0xa0);
1186 outb(0x0b,0x20);
1187 v = inb(0xa0) << 8 | inb(0x20);
1188 outb(0x0a,0xa0);
1189 outb(0x0a,0x20);
1190
1191 spin_unlock_irqrestore(&i8259A_lock, flags);
1192
1193 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1194
1195 v = inb(0x4d1) << 8 | inb(0x4d0);
1196 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1197 }
1198
1199 #endif /* 0 */
1200
1201 void __init enable_IO_APIC(void)
1202 {
1203 union IO_APIC_reg_01 reg_01;
1204 int i8259_apic, i8259_pin;
1205 int i, apic;
1206 unsigned long flags;
1207
1208 for (i = 0; i < PIN_MAP_SIZE; i++) {
1209 irq_2_pin[i].pin = -1;
1210 irq_2_pin[i].next = 0;
1211 }
1212
1213 /*
1214 * The number of IO-APIC IRQ registers (== #pins):
1215 */
1216 for (apic = 0; apic < nr_ioapics; apic++) {
1217 spin_lock_irqsave(&ioapic_lock, flags);
1218 reg_01.raw = io_apic_read(apic, 1);
1219 spin_unlock_irqrestore(&ioapic_lock, flags);
1220 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1221 }
1222 for(apic = 0; apic < nr_ioapics; apic++) {
1223 int pin;
1224 /* See if any of the pins is in ExtINT mode */
1225 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1226 struct IO_APIC_route_entry entry;
1227 entry = ioapic_read_entry(apic, pin);
1228
1229 /* If the interrupt line is enabled and in ExtInt mode
1230 * I have found the pin where the i8259 is connected.
1231 */
1232 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1233 ioapic_i8259.apic = apic;
1234 ioapic_i8259.pin = pin;
1235 goto found_i8259;
1236 }
1237 }
1238 }
1239 found_i8259:
1240 /* Look to see what if the MP table has reported the ExtINT */
1241 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1242 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1243 /* Trust the MP table if nothing is setup in the hardware */
1244 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1245 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1246 ioapic_i8259.pin = i8259_pin;
1247 ioapic_i8259.apic = i8259_apic;
1248 }
1249 /* Complain if the MP table and the hardware disagree */
1250 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1251 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1252 {
1253 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1254 }
1255
1256 /*
1257 * Do not trust the IO-APIC being empty at bootup
1258 */
1259 clear_IO_APIC();
1260 }
1261
1262 /*
1263 * Not an __init, needed by the reboot code
1264 */
1265 void disable_IO_APIC(void)
1266 {
1267 /*
1268 * Clear the IO-APIC before rebooting:
1269 */
1270 clear_IO_APIC();
1271
1272 /*
1273 * If the i8259 is routed through an IOAPIC
1274 * Put that IOAPIC in virtual wire mode
1275 * so legacy interrupts can be delivered.
1276 */
1277 if (ioapic_i8259.pin != -1) {
1278 struct IO_APIC_route_entry entry;
1279
1280 memset(&entry, 0, sizeof(entry));
1281 entry.mask = 0; /* Enabled */
1282 entry.trigger = 0; /* Edge */
1283 entry.irr = 0;
1284 entry.polarity = 0; /* High */
1285 entry.delivery_status = 0;
1286 entry.dest_mode = 0; /* Physical */
1287 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1288 entry.vector = 0;
1289 entry.dest = GET_APIC_ID(read_apic_id());
1290
1291 /*
1292 * Add it to the IO-APIC irq-routing table:
1293 */
1294 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1295 }
1296
1297 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1298 }
1299
1300 /*
1301 * There is a nasty bug in some older SMP boards, their mptable lies
1302 * about the timer IRQ. We do the following to work around the situation:
1303 *
1304 * - timer IRQ defaults to IO-APIC IRQ
1305 * - if this function detects that timer IRQs are defunct, then we fall
1306 * back to ISA timer IRQs
1307 */
1308 static int __init timer_irq_works(void)
1309 {
1310 unsigned long t1 = jiffies;
1311 unsigned long flags;
1312
1313 local_save_flags(flags);
1314 local_irq_enable();
1315 /* Let ten ticks pass... */
1316 mdelay((10 * 1000) / HZ);
1317 local_irq_restore(flags);
1318
1319 /*
1320 * Expect a few ticks at least, to be sure some possible
1321 * glue logic does not lock up after one or two first
1322 * ticks in a non-ExtINT mode. Also the local APIC
1323 * might have cached one ExtINT interrupt. Finally, at
1324 * least one tick may be lost due to delays.
1325 */
1326
1327 /* jiffies wrap? */
1328 if (time_after(jiffies, t1 + 4))
1329 return 1;
1330 return 0;
1331 }
1332
1333 /*
1334 * In the SMP+IOAPIC case it might happen that there are an unspecified
1335 * number of pending IRQ events unhandled. These cases are very rare,
1336 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1337 * better to do it this way as thus we do not have to be aware of
1338 * 'pending' interrupts in the IRQ path, except at this point.
1339 */
1340 /*
1341 * Edge triggered needs to resend any interrupt
1342 * that was delayed but this is now handled in the device
1343 * independent code.
1344 */
1345
1346 /*
1347 * Starting up a edge-triggered IO-APIC interrupt is
1348 * nasty - we need to make sure that we get the edge.
1349 * If it is already asserted for some reason, we need
1350 * return 1 to indicate that is was pending.
1351 *
1352 * This is not complete - we should be able to fake
1353 * an edge even if it isn't on the 8259A...
1354 */
1355
1356 static unsigned int startup_ioapic_irq(unsigned int irq)
1357 {
1358 int was_pending = 0;
1359 unsigned long flags;
1360
1361 spin_lock_irqsave(&ioapic_lock, flags);
1362 if (irq < 16) {
1363 disable_8259A_irq(irq);
1364 if (i8259A_irq_pending(irq))
1365 was_pending = 1;
1366 }
1367 __unmask_IO_APIC_irq(irq);
1368 spin_unlock_irqrestore(&ioapic_lock, flags);
1369
1370 return was_pending;
1371 }
1372
1373 static int ioapic_retrigger_irq(unsigned int irq)
1374 {
1375 struct irq_cfg *cfg = &irq_cfg[irq];
1376 unsigned long flags;
1377
1378 spin_lock_irqsave(&vector_lock, flags);
1379 send_IPI_mask(cpumask_of_cpu(first_cpu(cfg->domain)), cfg->vector);
1380 spin_unlock_irqrestore(&vector_lock, flags);
1381
1382 return 1;
1383 }
1384
1385 /*
1386 * Level and edge triggered IO-APIC interrupts need different handling,
1387 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1388 * handled with the level-triggered descriptor, but that one has slightly
1389 * more overhead. Level-triggered interrupts cannot be handled with the
1390 * edge-triggered handler, without risking IRQ storms and other ugly
1391 * races.
1392 */
1393
1394 #ifdef CONFIG_SMP
1395 asmlinkage void smp_irq_move_cleanup_interrupt(void)
1396 {
1397 unsigned vector, me;
1398 ack_APIC_irq();
1399 exit_idle();
1400 irq_enter();
1401
1402 me = smp_processor_id();
1403 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
1404 unsigned int irq;
1405 struct irq_desc *desc;
1406 struct irq_cfg *cfg;
1407 irq = __get_cpu_var(vector_irq)[vector];
1408 if (irq >= NR_IRQS)
1409 continue;
1410
1411 desc = irq_desc + irq;
1412 cfg = irq_cfg + irq;
1413 spin_lock(&desc->lock);
1414 if (!cfg->move_cleanup_count)
1415 goto unlock;
1416
1417 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain))
1418 goto unlock;
1419
1420 __get_cpu_var(vector_irq)[vector] = -1;
1421 cfg->move_cleanup_count--;
1422 unlock:
1423 spin_unlock(&desc->lock);
1424 }
1425
1426 irq_exit();
1427 }
1428
1429 static void irq_complete_move(unsigned int irq)
1430 {
1431 struct irq_cfg *cfg = irq_cfg + irq;
1432 unsigned vector, me;
1433
1434 if (likely(!cfg->move_in_progress))
1435 return;
1436
1437 vector = ~get_irq_regs()->orig_ax;
1438 me = smp_processor_id();
1439 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) {
1440 cpumask_t cleanup_mask;
1441
1442 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
1443 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
1444 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
1445 cfg->move_in_progress = 0;
1446 }
1447 }
1448 #else
1449 static inline void irq_complete_move(unsigned int irq) {}
1450 #endif
1451
1452 static void ack_apic_edge(unsigned int irq)
1453 {
1454 irq_complete_move(irq);
1455 move_native_irq(irq);
1456 ack_APIC_irq();
1457 }
1458
1459 static void ack_apic_level(unsigned int irq)
1460 {
1461 int do_unmask_irq = 0;
1462
1463 irq_complete_move(irq);
1464 #ifdef CONFIG_GENERIC_PENDING_IRQ
1465 /* If we are moving the irq we need to mask it */
1466 if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING)) {
1467 do_unmask_irq = 1;
1468 mask_IO_APIC_irq(irq);
1469 }
1470 #endif
1471
1472 /*
1473 * We must acknowledge the irq before we move it or the acknowledge will
1474 * not propagate properly.
1475 */
1476 ack_APIC_irq();
1477
1478 /* Now we can move and renable the irq */
1479 if (unlikely(do_unmask_irq)) {
1480 /* Only migrate the irq if the ack has been received.
1481 *
1482 * On rare occasions the broadcast level triggered ack gets
1483 * delayed going to ioapics, and if we reprogram the
1484 * vector while Remote IRR is still set the irq will never
1485 * fire again.
1486 *
1487 * To prevent this scenario we read the Remote IRR bit
1488 * of the ioapic. This has two effects.
1489 * - On any sane system the read of the ioapic will
1490 * flush writes (and acks) going to the ioapic from
1491 * this cpu.
1492 * - We get to see if the ACK has actually been delivered.
1493 *
1494 * Based on failed experiments of reprogramming the
1495 * ioapic entry from outside of irq context starting
1496 * with masking the ioapic entry and then polling until
1497 * Remote IRR was clear before reprogramming the
1498 * ioapic I don't trust the Remote IRR bit to be
1499 * completey accurate.
1500 *
1501 * However there appears to be no other way to plug
1502 * this race, so if the Remote IRR bit is not
1503 * accurate and is causing problems then it is a hardware bug
1504 * and you can go talk to the chipset vendor about it.
1505 */
1506 if (!io_apic_level_ack_pending(irq))
1507 move_masked_irq(irq);
1508 unmask_IO_APIC_irq(irq);
1509 }
1510 }
1511
1512 static struct irq_chip ioapic_chip __read_mostly = {
1513 .name = "IO-APIC",
1514 .startup = startup_ioapic_irq,
1515 .mask = mask_IO_APIC_irq,
1516 .unmask = unmask_IO_APIC_irq,
1517 .ack = ack_apic_edge,
1518 .eoi = ack_apic_level,
1519 #ifdef CONFIG_SMP
1520 .set_affinity = set_ioapic_affinity_irq,
1521 #endif
1522 .retrigger = ioapic_retrigger_irq,
1523 };
1524
1525 static inline void init_IO_APIC_traps(void)
1526 {
1527 int irq;
1528
1529 /*
1530 * NOTE! The local APIC isn't very good at handling
1531 * multiple interrupts at the same interrupt level.
1532 * As the interrupt level is determined by taking the
1533 * vector number and shifting that right by 4, we
1534 * want to spread these out a bit so that they don't
1535 * all fall in the same interrupt level.
1536 *
1537 * Also, we've got to be careful not to trash gate
1538 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1539 */
1540 for (irq = 0; irq < NR_IRQS ; irq++) {
1541 if (IO_APIC_IRQ(irq) && !irq_cfg[irq].vector) {
1542 /*
1543 * Hmm.. We don't have an entry for this,
1544 * so default to an old-fashioned 8259
1545 * interrupt if we can..
1546 */
1547 if (irq < 16)
1548 make_8259A_irq(irq);
1549 else
1550 /* Strange. Oh, well.. */
1551 irq_desc[irq].chip = &no_irq_chip;
1552 }
1553 }
1554 }
1555
1556 static void unmask_lapic_irq(unsigned int irq)
1557 {
1558 unsigned long v;
1559
1560 v = apic_read(APIC_LVT0);
1561 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1562 }
1563
1564 static void mask_lapic_irq(unsigned int irq)
1565 {
1566 unsigned long v;
1567
1568 v = apic_read(APIC_LVT0);
1569 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1570 }
1571
1572 static void ack_lapic_irq (unsigned int irq)
1573 {
1574 ack_APIC_irq();
1575 }
1576
1577 static struct irq_chip lapic_chip __read_mostly = {
1578 .name = "local-APIC",
1579 .mask = mask_lapic_irq,
1580 .unmask = unmask_lapic_irq,
1581 .ack = ack_lapic_irq,
1582 };
1583
1584 static void lapic_register_intr(int irq)
1585 {
1586 irq_desc[irq].status &= ~IRQ_LEVEL;
1587 set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
1588 "edge");
1589 }
1590
1591 static void __init setup_nmi(void)
1592 {
1593 /*
1594 * Dirty trick to enable the NMI watchdog ...
1595 * We put the 8259A master into AEOI mode and
1596 * unmask on all local APICs LVT0 as NMI.
1597 *
1598 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1599 * is from Maciej W. Rozycki - so we do not have to EOI from
1600 * the NMI handler or the timer interrupt.
1601 */
1602 printk(KERN_INFO "activating NMI Watchdog ...");
1603
1604 enable_NMI_through_LVT0();
1605
1606 printk(" done.\n");
1607 }
1608
1609 /*
1610 * This looks a bit hackish but it's about the only one way of sending
1611 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1612 * not support the ExtINT mode, unfortunately. We need to send these
1613 * cycles as some i82489DX-based boards have glue logic that keeps the
1614 * 8259A interrupt line asserted until INTA. --macro
1615 */
1616 static inline void __init unlock_ExtINT_logic(void)
1617 {
1618 int apic, pin, i;
1619 struct IO_APIC_route_entry entry0, entry1;
1620 unsigned char save_control, save_freq_select;
1621
1622 pin = find_isa_irq_pin(8, mp_INT);
1623 apic = find_isa_irq_apic(8, mp_INT);
1624 if (pin == -1)
1625 return;
1626
1627 entry0 = ioapic_read_entry(apic, pin);
1628
1629 clear_IO_APIC_pin(apic, pin);
1630
1631 memset(&entry1, 0, sizeof(entry1));
1632
1633 entry1.dest_mode = 0; /* physical delivery */
1634 entry1.mask = 0; /* unmask IRQ now */
1635 entry1.dest = hard_smp_processor_id();
1636 entry1.delivery_mode = dest_ExtINT;
1637 entry1.polarity = entry0.polarity;
1638 entry1.trigger = 0;
1639 entry1.vector = 0;
1640
1641 ioapic_write_entry(apic, pin, entry1);
1642
1643 save_control = CMOS_READ(RTC_CONTROL);
1644 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1645 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1646 RTC_FREQ_SELECT);
1647 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1648
1649 i = 100;
1650 while (i-- > 0) {
1651 mdelay(10);
1652 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1653 i -= 10;
1654 }
1655
1656 CMOS_WRITE(save_control, RTC_CONTROL);
1657 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1658 clear_IO_APIC_pin(apic, pin);
1659
1660 ioapic_write_entry(apic, pin, entry0);
1661 }
1662
1663 /*
1664 * This code may look a bit paranoid, but it's supposed to cooperate with
1665 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1666 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1667 * fanatically on his truly buggy board.
1668 *
1669 * FIXME: really need to revamp this for modern platforms only.
1670 */
1671 static inline void __init check_timer(void)
1672 {
1673 struct irq_cfg *cfg = irq_cfg + 0;
1674 int apic1, pin1, apic2, pin2;
1675 unsigned long flags;
1676 int no_pin1 = 0;
1677
1678 local_irq_save(flags);
1679
1680 /*
1681 * get/set the timer IRQ vector:
1682 */
1683 disable_8259A_irq(0);
1684 assign_irq_vector(0, TARGET_CPUS);
1685
1686 /*
1687 * As IRQ0 is to be enabled in the 8259A, the virtual
1688 * wire has to be disabled in the local APIC.
1689 */
1690 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1691 init_8259A(1);
1692
1693 pin1 = find_isa_irq_pin(0, mp_INT);
1694 apic1 = find_isa_irq_apic(0, mp_INT);
1695 pin2 = ioapic_i8259.pin;
1696 apic2 = ioapic_i8259.apic;
1697
1698 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
1699 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
1700 cfg->vector, apic1, pin1, apic2, pin2);
1701
1702 /*
1703 * Some BIOS writers are clueless and report the ExtINTA
1704 * I/O APIC input from the cascaded 8259A as the timer
1705 * interrupt input. So just in case, if only one pin
1706 * was found above, try it both directly and through the
1707 * 8259A.
1708 */
1709 if (pin1 == -1) {
1710 pin1 = pin2;
1711 apic1 = apic2;
1712 no_pin1 = 1;
1713 } else if (pin2 == -1) {
1714 pin2 = pin1;
1715 apic2 = apic1;
1716 }
1717
1718 if (pin1 != -1) {
1719 /*
1720 * Ok, does IRQ0 through the IOAPIC work?
1721 */
1722 if (no_pin1) {
1723 add_pin_to_irq(0, apic1, pin1);
1724 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
1725 }
1726 unmask_IO_APIC_irq(0);
1727 if (!no_timer_check && timer_irq_works()) {
1728 if (nmi_watchdog == NMI_IO_APIC) {
1729 setup_nmi();
1730 enable_8259A_irq(0);
1731 }
1732 if (disable_timer_pin_1 > 0)
1733 clear_IO_APIC_pin(0, pin1);
1734 goto out;
1735 }
1736 clear_IO_APIC_pin(apic1, pin1);
1737 if (!no_pin1)
1738 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
1739 "8254 timer not connected to IO-APIC\n");
1740
1741 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
1742 "(IRQ0) through the 8259A ...\n");
1743 apic_printk(APIC_QUIET, KERN_INFO
1744 "..... (found apic %d pin %d) ...\n", apic2, pin2);
1745 /*
1746 * legacy devices should be connected to IO APIC #0
1747 */
1748 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
1749 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
1750 unmask_IO_APIC_irq(0);
1751 enable_8259A_irq(0);
1752 if (timer_irq_works()) {
1753 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
1754 timer_through_8259 = 1;
1755 if (nmi_watchdog == NMI_IO_APIC) {
1756 disable_8259A_irq(0);
1757 setup_nmi();
1758 enable_8259A_irq(0);
1759 }
1760 goto out;
1761 }
1762 /*
1763 * Cleanup, just in case ...
1764 */
1765 disable_8259A_irq(0);
1766 clear_IO_APIC_pin(apic2, pin2);
1767 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
1768 }
1769
1770 if (nmi_watchdog == NMI_IO_APIC) {
1771 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
1772 "through the IO-APIC - disabling NMI Watchdog!\n");
1773 nmi_watchdog = NMI_NONE;
1774 }
1775
1776 apic_printk(APIC_QUIET, KERN_INFO
1777 "...trying to set up timer as Virtual Wire IRQ...\n");
1778
1779 lapic_register_intr(0);
1780 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
1781 enable_8259A_irq(0);
1782
1783 if (timer_irq_works()) {
1784 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
1785 goto out;
1786 }
1787 disable_8259A_irq(0);
1788 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
1789 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
1790
1791 apic_printk(APIC_QUIET, KERN_INFO
1792 "...trying to set up timer as ExtINT IRQ...\n");
1793
1794 init_8259A(0);
1795 make_8259A_irq(0);
1796 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1797
1798 unlock_ExtINT_logic();
1799
1800 if (timer_irq_works()) {
1801 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
1802 goto out;
1803 }
1804 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
1805 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
1806 "report. Then try booting with the 'noapic' option.\n");
1807 out:
1808 local_irq_restore(flags);
1809 }
1810
1811 static int __init notimercheck(char *s)
1812 {
1813 no_timer_check = 1;
1814 return 1;
1815 }
1816 __setup("no_timer_check", notimercheck);
1817
1818 /*
1819 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
1820 * to devices. However there may be an I/O APIC pin available for
1821 * this interrupt regardless. The pin may be left unconnected, but
1822 * typically it will be reused as an ExtINT cascade interrupt for
1823 * the master 8259A. In the MPS case such a pin will normally be
1824 * reported as an ExtINT interrupt in the MP table. With ACPI
1825 * there is no provision for ExtINT interrupts, and in the absence
1826 * of an override it would be treated as an ordinary ISA I/O APIC
1827 * interrupt, that is edge-triggered and unmasked by default. We
1828 * used to do this, but it caused problems on some systems because
1829 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
1830 * the same ExtINT cascade interrupt to drive the local APIC of the
1831 * bootstrap processor. Therefore we refrain from routing IRQ2 to
1832 * the I/O APIC in all cases now. No actual device should request
1833 * it anyway. --macro
1834 */
1835 #define PIC_IRQS (1<<2)
1836
1837 void __init setup_IO_APIC(void)
1838 {
1839
1840 /*
1841 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
1842 */
1843
1844 io_apic_irqs = ~PIC_IRQS;
1845
1846 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
1847
1848 sync_Arb_IDs();
1849 setup_IO_APIC_irqs();
1850 init_IO_APIC_traps();
1851 check_timer();
1852 if (!acpi_ioapic)
1853 print_IO_APIC();
1854 }
1855
1856 struct sysfs_ioapic_data {
1857 struct sys_device dev;
1858 struct IO_APIC_route_entry entry[0];
1859 };
1860 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1861
1862 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1863 {
1864 struct IO_APIC_route_entry *entry;
1865 struct sysfs_ioapic_data *data;
1866 int i;
1867
1868 data = container_of(dev, struct sysfs_ioapic_data, dev);
1869 entry = data->entry;
1870 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
1871 *entry = ioapic_read_entry(dev->id, i);
1872
1873 return 0;
1874 }
1875
1876 static int ioapic_resume(struct sys_device *dev)
1877 {
1878 struct IO_APIC_route_entry *entry;
1879 struct sysfs_ioapic_data *data;
1880 unsigned long flags;
1881 union IO_APIC_reg_00 reg_00;
1882 int i;
1883
1884 data = container_of(dev, struct sysfs_ioapic_data, dev);
1885 entry = data->entry;
1886
1887 spin_lock_irqsave(&ioapic_lock, flags);
1888 reg_00.raw = io_apic_read(dev->id, 0);
1889 if (reg_00.bits.ID != mp_ioapics[dev->id].mp_apicid) {
1890 reg_00.bits.ID = mp_ioapics[dev->id].mp_apicid;
1891 io_apic_write(dev->id, 0, reg_00.raw);
1892 }
1893 spin_unlock_irqrestore(&ioapic_lock, flags);
1894 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
1895 ioapic_write_entry(dev->id, i, entry[i]);
1896
1897 return 0;
1898 }
1899
1900 static struct sysdev_class ioapic_sysdev_class = {
1901 .name = "ioapic",
1902 .suspend = ioapic_suspend,
1903 .resume = ioapic_resume,
1904 };
1905
1906 static int __init ioapic_init_sysfs(void)
1907 {
1908 struct sys_device * dev;
1909 int i, size, error;
1910
1911 error = sysdev_class_register(&ioapic_sysdev_class);
1912 if (error)
1913 return error;
1914
1915 for (i = 0; i < nr_ioapics; i++ ) {
1916 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
1917 * sizeof(struct IO_APIC_route_entry);
1918 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
1919 if (!mp_ioapic_data[i]) {
1920 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1921 continue;
1922 }
1923 dev = &mp_ioapic_data[i]->dev;
1924 dev->id = i;
1925 dev->cls = &ioapic_sysdev_class;
1926 error = sysdev_register(dev);
1927 if (error) {
1928 kfree(mp_ioapic_data[i]);
1929 mp_ioapic_data[i] = NULL;
1930 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1931 continue;
1932 }
1933 }
1934
1935 return 0;
1936 }
1937
1938 device_initcall(ioapic_init_sysfs);
1939
1940 /*
1941 * Dynamic irq allocate and deallocation
1942 */
1943 int create_irq(void)
1944 {
1945 /* Allocate an unused irq */
1946 int irq;
1947 int new;
1948 unsigned long flags;
1949
1950 irq = -ENOSPC;
1951 spin_lock_irqsave(&vector_lock, flags);
1952 for (new = (NR_IRQS - 1); new >= 0; new--) {
1953 if (platform_legacy_irq(new))
1954 continue;
1955 if (irq_cfg[new].vector != 0)
1956 continue;
1957 if (__assign_irq_vector(new, TARGET_CPUS) == 0)
1958 irq = new;
1959 break;
1960 }
1961 spin_unlock_irqrestore(&vector_lock, flags);
1962
1963 if (irq >= 0) {
1964 dynamic_irq_init(irq);
1965 }
1966 return irq;
1967 }
1968
1969 void destroy_irq(unsigned int irq)
1970 {
1971 unsigned long flags;
1972
1973 dynamic_irq_cleanup(irq);
1974
1975 spin_lock_irqsave(&vector_lock, flags);
1976 __clear_irq_vector(irq);
1977 spin_unlock_irqrestore(&vector_lock, flags);
1978 }
1979
1980 /*
1981 * MSI message composition
1982 */
1983 #ifdef CONFIG_PCI_MSI
1984 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
1985 {
1986 struct irq_cfg *cfg = irq_cfg + irq;
1987 int err;
1988 unsigned dest;
1989 cpumask_t tmp;
1990
1991 tmp = TARGET_CPUS;
1992 err = assign_irq_vector(irq, tmp);
1993 if (!err) {
1994 cpus_and(tmp, cfg->domain, tmp);
1995 dest = cpu_mask_to_apicid(tmp);
1996
1997 msg->address_hi = MSI_ADDR_BASE_HI;
1998 msg->address_lo =
1999 MSI_ADDR_BASE_LO |
2000 ((INT_DEST_MODE == 0) ?
2001 MSI_ADDR_DEST_MODE_PHYSICAL:
2002 MSI_ADDR_DEST_MODE_LOGICAL) |
2003 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2004 MSI_ADDR_REDIRECTION_CPU:
2005 MSI_ADDR_REDIRECTION_LOWPRI) |
2006 MSI_ADDR_DEST_ID(dest);
2007
2008 msg->data =
2009 MSI_DATA_TRIGGER_EDGE |
2010 MSI_DATA_LEVEL_ASSERT |
2011 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2012 MSI_DATA_DELIVERY_FIXED:
2013 MSI_DATA_DELIVERY_LOWPRI) |
2014 MSI_DATA_VECTOR(cfg->vector);
2015 }
2016 return err;
2017 }
2018
2019 #ifdef CONFIG_SMP
2020 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
2021 {
2022 struct irq_cfg *cfg = irq_cfg + irq;
2023 struct msi_msg msg;
2024 unsigned int dest;
2025 cpumask_t tmp;
2026
2027 cpus_and(tmp, mask, cpu_online_map);
2028 if (cpus_empty(tmp))
2029 return;
2030
2031 if (assign_irq_vector(irq, mask))
2032 return;
2033
2034 cpus_and(tmp, cfg->domain, mask);
2035 dest = cpu_mask_to_apicid(tmp);
2036
2037 read_msi_msg(irq, &msg);
2038
2039 msg.data &= ~MSI_DATA_VECTOR_MASK;
2040 msg.data |= MSI_DATA_VECTOR(cfg->vector);
2041 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2042 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2043
2044 write_msi_msg(irq, &msg);
2045 irq_desc[irq].affinity = mask;
2046 }
2047 #endif /* CONFIG_SMP */
2048
2049 /*
2050 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2051 * which implement the MSI or MSI-X Capability Structure.
2052 */
2053 static struct irq_chip msi_chip = {
2054 .name = "PCI-MSI",
2055 .unmask = unmask_msi_irq,
2056 .mask = mask_msi_irq,
2057 .ack = ack_apic_edge,
2058 #ifdef CONFIG_SMP
2059 .set_affinity = set_msi_irq_affinity,
2060 #endif
2061 .retrigger = ioapic_retrigger_irq,
2062 };
2063
2064 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
2065 {
2066 struct msi_msg msg;
2067 int irq, ret;
2068 irq = create_irq();
2069 if (irq < 0)
2070 return irq;
2071
2072 ret = msi_compose_msg(dev, irq, &msg);
2073 if (ret < 0) {
2074 destroy_irq(irq);
2075 return ret;
2076 }
2077
2078 set_irq_msi(irq, desc);
2079 write_msi_msg(irq, &msg);
2080
2081 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
2082
2083 return 0;
2084 }
2085
2086 void arch_teardown_msi_irq(unsigned int irq)
2087 {
2088 destroy_irq(irq);
2089 }
2090
2091 #ifdef CONFIG_DMAR
2092 #ifdef CONFIG_SMP
2093 static void dmar_msi_set_affinity(unsigned int irq, cpumask_t mask)
2094 {
2095 struct irq_cfg *cfg = irq_cfg + irq;
2096 struct msi_msg msg;
2097 unsigned int dest;
2098 cpumask_t tmp;
2099
2100 cpus_and(tmp, mask, cpu_online_map);
2101 if (cpus_empty(tmp))
2102 return;
2103
2104 if (assign_irq_vector(irq, mask))
2105 return;
2106
2107 cpus_and(tmp, cfg->domain, mask);
2108 dest = cpu_mask_to_apicid(tmp);
2109
2110 dmar_msi_read(irq, &msg);
2111
2112 msg.data &= ~MSI_DATA_VECTOR_MASK;
2113 msg.data |= MSI_DATA_VECTOR(cfg->vector);
2114 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2115 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2116
2117 dmar_msi_write(irq, &msg);
2118 irq_desc[irq].affinity = mask;
2119 }
2120 #endif /* CONFIG_SMP */
2121
2122 struct irq_chip dmar_msi_type = {
2123 .name = "DMAR_MSI",
2124 .unmask = dmar_msi_unmask,
2125 .mask = dmar_msi_mask,
2126 .ack = ack_apic_edge,
2127 #ifdef CONFIG_SMP
2128 .set_affinity = dmar_msi_set_affinity,
2129 #endif
2130 .retrigger = ioapic_retrigger_irq,
2131 };
2132
2133 int arch_setup_dmar_msi(unsigned int irq)
2134 {
2135 int ret;
2136 struct msi_msg msg;
2137
2138 ret = msi_compose_msg(NULL, irq, &msg);
2139 if (ret < 0)
2140 return ret;
2141 dmar_msi_write(irq, &msg);
2142 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
2143 "edge");
2144 return 0;
2145 }
2146 #endif
2147
2148 #endif /* CONFIG_PCI_MSI */
2149 /*
2150 * Hypertransport interrupt support
2151 */
2152 #ifdef CONFIG_HT_IRQ
2153
2154 #ifdef CONFIG_SMP
2155
2156 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
2157 {
2158 struct ht_irq_msg msg;
2159 fetch_ht_irq_msg(irq, &msg);
2160
2161 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
2162 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
2163
2164 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
2165 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
2166
2167 write_ht_irq_msg(irq, &msg);
2168 }
2169
2170 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2171 {
2172 struct irq_cfg *cfg = irq_cfg + irq;
2173 unsigned int dest;
2174 cpumask_t tmp;
2175
2176 cpus_and(tmp, mask, cpu_online_map);
2177 if (cpus_empty(tmp))
2178 return;
2179
2180 if (assign_irq_vector(irq, mask))
2181 return;
2182
2183 cpus_and(tmp, cfg->domain, mask);
2184 dest = cpu_mask_to_apicid(tmp);
2185
2186 target_ht_irq(irq, dest, cfg->vector);
2187 irq_desc[irq].affinity = mask;
2188 }
2189 #endif
2190
2191 static struct irq_chip ht_irq_chip = {
2192 .name = "PCI-HT",
2193 .mask = mask_ht_irq,
2194 .unmask = unmask_ht_irq,
2195 .ack = ack_apic_edge,
2196 #ifdef CONFIG_SMP
2197 .set_affinity = set_ht_irq_affinity,
2198 #endif
2199 .retrigger = ioapic_retrigger_irq,
2200 };
2201
2202 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2203 {
2204 struct irq_cfg *cfg = irq_cfg + irq;
2205 int err;
2206 cpumask_t tmp;
2207
2208 tmp = TARGET_CPUS;
2209 err = assign_irq_vector(irq, tmp);
2210 if (!err) {
2211 struct ht_irq_msg msg;
2212 unsigned dest;
2213
2214 cpus_and(tmp, cfg->domain, tmp);
2215 dest = cpu_mask_to_apicid(tmp);
2216
2217 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
2218
2219 msg.address_lo =
2220 HT_IRQ_LOW_BASE |
2221 HT_IRQ_LOW_DEST_ID(dest) |
2222 HT_IRQ_LOW_VECTOR(cfg->vector) |
2223 ((INT_DEST_MODE == 0) ?
2224 HT_IRQ_LOW_DM_PHYSICAL :
2225 HT_IRQ_LOW_DM_LOGICAL) |
2226 HT_IRQ_LOW_RQEOI_EDGE |
2227 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2228 HT_IRQ_LOW_MT_FIXED :
2229 HT_IRQ_LOW_MT_ARBITRATED) |
2230 HT_IRQ_LOW_IRQ_MASKED;
2231
2232 write_ht_irq_msg(irq, &msg);
2233
2234 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2235 handle_edge_irq, "edge");
2236 }
2237 return err;
2238 }
2239 #endif /* CONFIG_HT_IRQ */
2240
2241 /* --------------------------------------------------------------------------
2242 ACPI-based IOAPIC Configuration
2243 -------------------------------------------------------------------------- */
2244
2245 #ifdef CONFIG_ACPI
2246
2247 #define IO_APIC_MAX_ID 0xFE
2248
2249 int __init io_apic_get_redir_entries (int ioapic)
2250 {
2251 union IO_APIC_reg_01 reg_01;
2252 unsigned long flags;
2253
2254 spin_lock_irqsave(&ioapic_lock, flags);
2255 reg_01.raw = io_apic_read(ioapic, 1);
2256 spin_unlock_irqrestore(&ioapic_lock, flags);
2257
2258 return reg_01.bits.entries;
2259 }
2260
2261
2262 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
2263 {
2264 if (!IO_APIC_IRQ(irq)) {
2265 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2266 ioapic);
2267 return -EINVAL;
2268 }
2269
2270 /*
2271 * IRQs < 16 are already in the irq_2_pin[] map
2272 */
2273 if (irq >= 16)
2274 add_pin_to_irq(irq, ioapic, pin);
2275
2276 setup_IO_APIC_irq(ioapic, pin, irq, triggering, polarity);
2277
2278 return 0;
2279 }
2280
2281
2282 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
2283 {
2284 int i;
2285
2286 if (skip_ioapic_setup)
2287 return -1;
2288
2289 for (i = 0; i < mp_irq_entries; i++)
2290 if (mp_irqs[i].mp_irqtype == mp_INT &&
2291 mp_irqs[i].mp_srcbusirq == bus_irq)
2292 break;
2293 if (i >= mp_irq_entries)
2294 return -1;
2295
2296 *trigger = irq_trigger(i);
2297 *polarity = irq_polarity(i);
2298 return 0;
2299 }
2300
2301 #endif /* CONFIG_ACPI */
2302
2303 /*
2304 * This function currently is only a helper for the i386 smp boot process where
2305 * we need to reprogram the ioredtbls to cater for the cpus which have come online
2306 * so mask in all cases should simply be TARGET_CPUS
2307 */
2308 #ifdef CONFIG_SMP
2309 void __init setup_ioapic_dest(void)
2310 {
2311 int pin, ioapic, irq, irq_entry;
2312
2313 if (skip_ioapic_setup == 1)
2314 return;
2315
2316 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
2317 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
2318 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2319 if (irq_entry == -1)
2320 continue;
2321 irq = pin_2_irq(irq_entry, ioapic, pin);
2322
2323 /* setup_IO_APIC_irqs could fail to get vector for some device
2324 * when you have too many devices, because at that time only boot
2325 * cpu is online.
2326 */
2327 if (!irq_cfg[irq].vector)
2328 setup_IO_APIC_irq(ioapic, pin, irq,
2329 irq_trigger(irq_entry),
2330 irq_polarity(irq_entry));
2331 else
2332 set_ioapic_affinity_irq(irq, TARGET_CPUS);
2333 }
2334
2335 }
2336 }
2337 #endif
2338
2339 #define IOAPIC_RESOURCE_NAME_SIZE 11
2340
2341 static struct resource *ioapic_resources;
2342
2343 static struct resource * __init ioapic_setup_resources(void)
2344 {
2345 unsigned long n;
2346 struct resource *res;
2347 char *mem;
2348 int i;
2349
2350 if (nr_ioapics <= 0)
2351 return NULL;
2352
2353 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
2354 n *= nr_ioapics;
2355
2356 mem = alloc_bootmem(n);
2357 res = (void *)mem;
2358
2359 if (mem != NULL) {
2360 mem += sizeof(struct resource) * nr_ioapics;
2361
2362 for (i = 0; i < nr_ioapics; i++) {
2363 res[i].name = mem;
2364 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
2365 sprintf(mem, "IOAPIC %u", i);
2366 mem += IOAPIC_RESOURCE_NAME_SIZE;
2367 }
2368 }
2369
2370 ioapic_resources = res;
2371
2372 return res;
2373 }
2374
2375 void __init ioapic_init_mappings(void)
2376 {
2377 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
2378 struct resource *ioapic_res;
2379 int i;
2380
2381 ioapic_res = ioapic_setup_resources();
2382 for (i = 0; i < nr_ioapics; i++) {
2383 if (smp_found_config) {
2384 ioapic_phys = mp_ioapics[i].mp_apicaddr;
2385 } else {
2386 ioapic_phys = (unsigned long)
2387 alloc_bootmem_pages(PAGE_SIZE);
2388 ioapic_phys = __pa(ioapic_phys);
2389 }
2390 set_fixmap_nocache(idx, ioapic_phys);
2391 apic_printk(APIC_VERBOSE,
2392 "mapped IOAPIC to %016lx (%016lx)\n",
2393 __fix_to_virt(idx), ioapic_phys);
2394 idx++;
2395
2396 if (ioapic_res != NULL) {
2397 ioapic_res->start = ioapic_phys;
2398 ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
2399 ioapic_res++;
2400 }
2401 }
2402 }
2403
2404 static int __init ioapic_insert_resources(void)
2405 {
2406 int i;
2407 struct resource *r = ioapic_resources;
2408
2409 if (!r) {
2410 printk(KERN_ERR
2411 "IO APIC resources could be not be allocated.\n");
2412 return -1;
2413 }
2414
2415 for (i = 0; i < nr_ioapics; i++) {
2416 insert_resource(&iomem_resource, r);
2417 r++;
2418 }
2419
2420 return 0;
2421 }
2422
2423 /* Insert the IO APIC resources after PCI initialization has occured to handle
2424 * IO APICS that are mapped in on a BAR in PCI space. */
2425 late_initcall(ioapic_insert_resources);
2426
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