arch/arm/plat-mxc/include/mach/mx27.h

   1 /*
   2  * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
   3  * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
   4  *
   5  * This contains i.MX27-specific hardware definitions. For those
   6  * hardware pieces that are common between i.MX21 and i.MX27, have a
   7  * look at mx2x.h.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * as published by the Free Software Foundation; either version 2
  12  * of the License, or (at your option) any later version.
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  21  * MA  02110-1301, USA.
  22  */
  23
  24 #ifndef __ASM_ARCH_MXC_MX27_H__
  25 #define __ASM_ARCH_MXC_MX27_H__
  26
  27 #define MX27_MSHC_BASE_ADDR                     (MX2x_AIPI_BASE_ADDR + 0x18000)
  28 #define MX27_GPT5_BASE_ADDR                     (MX2x_AIPI_BASE_ADDR + 0x19000)
  29 #define MX27_GPT4_BASE_ADDR                     (MX2x_AIPI_BASE_ADDR + 0x1a000)
  30 #define MX27_UART5_BASE_ADDR                    (MX2x_AIPI_BASE_ADDR + 0x1b000)
  31 #define MX27_UART6_BASE_ADDR                    (MX2x_AIPI_BASE_ADDR + 0x1c000)
  32 #define MX27_I2C2_BASE_ADDR                     (MX2x_AIPI_BASE_ADDR + 0x1d000)
  33 #define MX27_SDHC3_BASE_ADDR                    (MX2x_AIPI_BASE_ADDR + 0x1e000)
  34 #define MX27_GPT6_BASE_ADDR                     (MX2x_AIPI_BASE_ADDR + 0x1f000)
  35 #define MX27_VPU_BASE_ADDR                      (MX2x_AIPI_BASE_ADDR + 0x23000)
  36 #define MX27_OTG_BASE_ADDR                      MX2x_USBOTG_BASE_ADDR
  37 #define MX27_SAHARA_BASE_ADDR                   (MX2x_AIPI_BASE_ADDR + 0x25000)
  38 #define MX27_IIM_BASE_ADDR                      (MX2x_AIPI_BASE_ADDR + 0x28000)
  39 #define MX27_RTIC_BASE_ADDR                     (MX2x_AIPI_BASE_ADDR + 0x2a000)
  40 #define MX27_FEC_BASE_ADDR                      (MX2x_AIPI_BASE_ADDR + 0x2b000)
  41 #define MX27_SCC_BASE_ADDR                      (MX2x_AIPI_BASE_ADDR + 0x2c000)
  42 #define MX27_ETB_BASE_ADDR                      (MX2x_AIPI_BASE_ADDR + 0x3b000)
  43 #define MX27_ETB_RAM_BASE_ADDR                  (MX2x_AIPI_BASE_ADDR + 0x3c000)
  44
  45 /* ROM patch */
  46 #define MX27_ROMP_BASE_ADDR             0x10041000
  47
  48 #define MX27_ATA_BASE_ADDR                      (MX2x_SAHB1_BASE_ADDR + 0x1000)
  49
  50 /* Memory regions and CS */
  51 #define MX27_SDRAM_BASE_ADDR            0xa0000000
  52 #define MX27_CSD1_BASE_ADDR             0xb0000000
  53
  54 #define MX27_CS0_BASE_ADDR              0xc0000000
  55 #define MX27_CS1_BASE_ADDR              0xc8000000
  56 #define MX27_CS2_BASE_ADDR              0xd0000000
  57 #define MX27_CS3_BASE_ADDR              0xd2000000
  58 #define MX27_CS4_BASE_ADDR              0xd4000000
  59 #define MX27_CS5_BASE_ADDR              0xd6000000
  60
  61 /* NAND, SDRAM, WEIM, M3IF, EMI controllers */
  62 #define MX27_X_MEMC_BASE_ADDR           0xd8000000
  63 #define MX27_X_MEMC_BASE_ADDR_VIRT      0xf4200000
  64 #define MX27_X_MEMC_SIZE                SZ_1M
  65 #define MX27_NFC_BASE_ADDR                      (MX27_X_MEMC_BASE_ADDR)
  66 #define MX27_SDRAMC_BASE_ADDR                   (MX27_X_MEMC_BASE_ADDR + 0x1000)
  67 #define MX27_WEIM_BASE_ADDR                     (MX27_X_MEMC_BASE_ADDR + 0x2000)
  68 #define MX27_M3IF_BASE_ADDR                     (MX27_X_MEMC_BASE_ADDR + 0x3000)
  69 #define MX27_PCMCIA_CTL_BASE_ADDR               (MX27_X_MEMC_BASE_ADDR + 0x4000)
  70
  71 #define MX27_PCMCIA_MEM_BASE_ADDR       0xdc000000
  72
  73 /* IRAM */
  74 #define MX27_IRAM_BASE_ADDR             0xffff4c00      /* internal ram */
  75
  76 /* fixed interrupt numbers */
  77 #define MX27_INT_I2C2           1
  78 #define MX27_INT_GPT6           2
  79 #define MX27_INT_GPT5           3
  80 #define MX27_INT_GPT4           4
  81 #define MX27_INT_RTIC           5
  82 #define MX27_INT_SDHC           7
  83 #define MX27_INT_SDHC3          9
  84 #define MX27_INT_ATA            30
  85 #define MX27_INT_UART6          48
  86 #define MX27_INT_UART5          49
  87 #define MX27_INT_FEC            50
  88 #define MX27_INT_VPU            53
  89 #define MX27_INT_USB1           54
  90 #define MX27_INT_USB2           55
  91 #define MX27_INT_USB3           56
  92 #define MX27_INT_SCC_SMN        57
  93 #define MX27_INT_SCC_SCM        58
  94 #define MX27_INT_SAHARA         59
  95 #define MX27_INT_IIM            62
  96 #define MX27_INT_CCM            63
  97
  98 /* fixed DMA request numbers */
  99 #define MX27_DMA_REQ_MSHC       4
 100 #define MX27_DMA_REQ_ATA_TX     28
 101 #define MX27_DMA_REQ_ATA_RCV    29
 102 #define MX27_DMA_REQ_UART5_TX   32
 103 #define MX27_DMA_REQ_UART5_RX   33
 104 #define MX27_DMA_REQ_UART6_TX   34
 105 #define MX27_DMA_REQ_UART6_RX   35
 106 #define MX27_DMA_REQ_SDHC3      36
 107 #define MX27_DMA_REQ_NFC        37
 108
 109 /* silicon revisions specific to i.MX27 */
 110 #define CHIP_REV_1_0            0x00
 111 #define CHIP_REV_2_0            0x01
 112
 113 #ifndef __ASSEMBLY__
 114 extern int mx27_revision(void);
 115 #endif
 116
 117 /* these should go away */
 118 #define MSHC_BASE_ADDR MX27_MSHC_BASE_ADDR
 119 #define GPT5_BASE_ADDR MX27_GPT5_BASE_ADDR
 120 #define GPT4_BASE_ADDR MX27_GPT4_BASE_ADDR
 121 #define UART5_BASE_ADDR MX27_UART5_BASE_ADDR
 122 #define UART6_BASE_ADDR MX27_UART6_BASE_ADDR
 123 #define I2C2_BASE_ADDR MX27_I2C2_BASE_ADDR
 124 #define SDHC3_BASE_ADDR MX27_SDHC3_BASE_ADDR
 125 #define GPT6_BASE_ADDR MX27_GPT6_BASE_ADDR
 126 #define VPU_BASE_ADDR MX27_VPU_BASE_ADDR
 127 #define OTG_BASE_ADDR MX27_OTG_BASE_ADDR
 128 #define SAHARA_BASE_ADDR MX27_SAHARA_BASE_ADDR
 129 #define IIM_BASE_ADDR MX27_IIM_BASE_ADDR
 130 #define RTIC_BASE_ADDR MX27_RTIC_BASE_ADDR
 131 #define FEC_BASE_ADDR MX27_FEC_BASE_ADDR
 132 #define SCC_BASE_ADDR MX27_SCC_BASE_ADDR
 133 #define ETB_BASE_ADDR MX27_ETB_BASE_ADDR
 134 #define ETB_RAM_BASE_ADDR MX27_ETB_RAM_BASE_ADDR
 135 #define ROMP_BASE_ADDR MX27_ROMP_BASE_ADDR
 136 #define ATA_BASE_ADDR MX27_ATA_BASE_ADDR
 137 #define SDRAM_BASE_ADDR MX27_SDRAM_BASE_ADDR
 138 #define CSD1_BASE_ADDR MX27_CSD1_BASE_ADDR
 139 #define CS0_BASE_ADDR MX27_CS0_BASE_ADDR
 140 #define CS1_BASE_ADDR MX27_CS1_BASE_ADDR
 141 #define CS2_BASE_ADDR MX27_CS2_BASE_ADDR
 142 #define CS3_BASE_ADDR MX27_CS3_BASE_ADDR
 143 #define CS4_BASE_ADDR MX27_CS4_BASE_ADDR
 144 #define CS5_BASE_ADDR MX27_CS5_BASE_ADDR
 145 #define X_MEMC_BASE_ADDR MX27_X_MEMC_BASE_ADDR
 146 #define X_MEMC_BASE_ADDR_VIRT MX27_X_MEMC_BASE_ADDR_VIRT
 147 #define X_MEMC_SIZE MX27_X_MEMC_SIZE
 148 #define NFC_BASE_ADDR MX27_NFC_BASE_ADDR
 149 #define SDRAMC_BASE_ADDR MX27_SDRAMC_BASE_ADDR
 150 #define WEIM_BASE_ADDR MX27_WEIM_BASE_ADDR
 151 #define M3IF_BASE_ADDR MX27_M3IF_BASE_ADDR
 152 #define PCMCIA_CTL_BASE_ADDR MX27_PCMCIA_CTL_BASE_ADDR
 153 #define PCMCIA_MEM_BASE_ADDR MX27_PCMCIA_MEM_BASE_ADDR
 154 #define IRAM_BASE_ADDR MX27_IRAM_BASE_ADDR
 155 #define MXC_INT_I2C2 MX27_INT_I2C2
 156 #define MXC_INT_GPT6 MX27_INT_GPT6
 157 #define MXC_INT_GPT5 MX27_INT_GPT5
 158 #define MXC_INT_GPT4 MX27_INT_GPT4
 159 #define MXC_INT_RTIC MX27_INT_RTIC
 160 #define MXC_INT_SDHC MX27_INT_SDHC
 161 #define MXC_INT_SDHC3 MX27_INT_SDHC3
 162 #define MXC_INT_ATA MX27_INT_ATA
 163 #define MXC_INT_UART6 MX27_INT_UART6
 164 #define MXC_INT_UART5 MX27_INT_UART5
 165 #define MXC_INT_FEC MX27_INT_FEC
 166 #define MXC_INT_VPU MX27_INT_VPU
 167 #define MXC_INT_USB1 MX27_INT_USB1
 168 #define MXC_INT_USB2 MX27_INT_USB2
 169 #define MXC_INT_USB3 MX27_INT_USB3
 170 #define MXC_INT_SCC_SMN MX27_INT_SCC_SMN
 171 #define MXC_INT_SCC_SCM MX27_INT_SCC_SCM
 172 #define MXC_INT_SAHARA MX27_INT_SAHARA
 173 #define MXC_INT_IIM MX27_INT_IIM
 174 #define MXC_INT_CCM MX27_INT_CCM
 175 #define DMA_REQ_MSHC MX27_DMA_REQ_MSHC
 176 #define DMA_REQ_ATA_TX MX27_DMA_REQ_ATA_TX
 177 #define DMA_REQ_ATA_RCV MX27_DMA_REQ_ATA_RCV
 178 #define DMA_REQ_UART5_TX MX27_DMA_REQ_UART5_TX
 179 #define DMA_REQ_UART5_RX MX27_DMA_REQ_UART5_RX
 180 #define DMA_REQ_UART6_TX MX27_DMA_REQ_UART6_TX
 181 #define DMA_REQ_UART6_RX MX27_DMA_REQ_UART6_RX
 182 #define DMA_REQ_SDHC3 MX27_DMA_REQ_SDHC3
 183 #define DMA_REQ_NFC MX27_DMA_REQ_NFC
 184
 185 #endif /* __ASM_ARCH_MXC_MX27_H__ */