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STAGING: brcm80211 fix TX Queue overflow
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / staging / brcm80211 / brcmfmac / dhd_sdio.c
blobf25e5b3011196d47b60a2405708b40dc4b959ac5
1 /*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/types.h>
18 #include <bcmdefs.h>
19 #include <linux/netdevice.h>
20 #include <bcmsdh.h>
21
22 #ifdef BCMEMBEDIMAGE
23 #include BCMEMBEDIMAGE
24 #endif /* BCMEMBEDIMAGE */
25
26 #include <bcmdefs.h>
27 #include <bcmutils.h>
28 #include <bcmdevs.h>
29
30 #include <siutils.h>
31 #include <hndpmu.h>
32 #include <hndsoc.h>
33 #ifdef DHD_DEBUG
34 #include <hndrte_armtrap.h>
35 #include <hndrte_cons.h>
36 #endif /* DHD_DEBUG */
37 #include <sbchipc.h>
38 #include <sbhnddma.h>
39
40 #include <sdio.h>
41 #include <sbsdio.h>
42 #include <sbsdpcmdev.h>
43 #include <bcmsdpcm.h>
44
45 #include <proto/802.11.h>
46
47 #include <dngl_stats.h>
48 #include <dhd.h>
49 #include <dhd_bus.h>
50 #include <dhd_proto.h>
51 #include <dhd_dbg.h>
52 #include <dhdioctl.h>
53 #include <sdiovar.h>
54 #include <siutils_priv.h>
55
56 #ifndef DHDSDIO_MEM_DUMP_FNAME
57 #define DHDSDIO_MEM_DUMP_FNAME "mem_dump"
58 #endif
59
60 #define TXQLEN 2048 /* bulk tx queue length */
61 #define TXHI (TXQLEN - 256) /* turn on flow control above TXHI */
62 #define TXLOW (TXHI - 256) /* turn off flow control below TXLOW */
63 #define PRIOMASK 7
64
65 #define TXRETRIES 2 /* # of retries for tx frames */
66
67 #if defined(CONFIG_MACH_SANDGATE2G)
68 #define DHD_RXBOUND 250 /* Default for max rx frames in
69 one scheduling */
70 #else
71 #define DHD_RXBOUND 50 /* Default for max rx frames in
72 one scheduling */
73 #endif /* defined(CONFIG_MACH_SANDGATE2G) */
74
75 #define DHD_TXBOUND 20 /* Default for max tx frames in
76 one scheduling */
77
78 #define DHD_TXMINMAX 1 /* Max tx frames if rx still pending */
79
80 #define MEMBLOCK 2048 /* Block size used for downloading
81 of dongle image */
82 #define MAX_DATA_BUF (32 * 1024) /* Must be large enough to hold
83 biggest possible glom */
84
85 /* Packet alignment for most efficient SDIO (can change based on platform) */
86 #ifndef DHD_SDALIGN
87 #define DHD_SDALIGN 32
88 #endif
89 #if !ISPOWEROF2(DHD_SDALIGN)
90 #error DHD_SDALIGN is not a power of 2!
91 #endif
92
93 #ifndef DHD_FIRSTREAD
94 #define DHD_FIRSTREAD 32
95 #endif
96 #if !ISPOWEROF2(DHD_FIRSTREAD)
97 #error DHD_FIRSTREAD is not a power of 2!
98 #endif
99
100 /* Total length of frame header for dongle protocol */
101 #define SDPCM_HDRLEN (SDPCM_FRAMETAG_LEN + SDPCM_SWHEADER_LEN)
102 #ifdef SDTEST
103 #define SDPCM_RESERVE (SDPCM_HDRLEN + SDPCM_TEST_HDRLEN + DHD_SDALIGN)
104 #else
105 #define SDPCM_RESERVE (SDPCM_HDRLEN + DHD_SDALIGN)
106 #endif
107
108 /* Space for header read, limit for data packets */
109 #ifndef MAX_HDR_READ
110 #define MAX_HDR_READ 32
111 #endif
112 #if !ISPOWEROF2(MAX_HDR_READ)
113 #error MAX_HDR_READ is not a power of 2!
114 #endif
115
116 #define MAX_RX_DATASZ 2048
117
118 /* Maximum milliseconds to wait for F2 to come up */
119 #define DHD_WAIT_F2RDY 3000
120
121 /* Bump up limit on waiting for HT to account for first startup;
122 * if the image is doing a CRC calculation before programming the PMU
123 * for HT availability, it could take a couple hundred ms more, so
124 * max out at a 1 second (1000000us).
125 */
126 #if (PMU_MAX_TRANSITION_DLY <= 1000000)
127 #undef PMU_MAX_TRANSITION_DLY
128 #define PMU_MAX_TRANSITION_DLY 1000000
129 #endif
130
131 /* Value for ChipClockCSR during initial setup */
132 #define DHD_INIT_CLKCTL1 (SBSDIO_FORCE_HW_CLKREQ_OFF | \
133 SBSDIO_ALP_AVAIL_REQ)
134 #define DHD_INIT_CLKCTL2 (SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_FORCE_ALP)
135
136 /* Flags for SDH calls */
137 #define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED)
138
139 /* Packet free applicable unconditionally for sdio and sdspi. Conditional if
140 * bufpool was present for gspi bus.
141 */
142 #define PKTFREE2() if ((bus->bus != SPI_BUS) || bus->usebufpool) \
143 pkt_buf_free_skb(pkt);
144
145 /*
146 * Conversion of 802.1D priority to precedence level
147 */
148 #define PRIO2PREC(prio) \
149 (((prio) == PRIO_8021D_NONE || (prio) == PRIO_8021D_BE) ? \
150 ((prio^2)) : (prio))
151
152 DHD_SPINWAIT_SLEEP_INIT(sdioh_spinwait_sleep);
153 extern int dhdcdc_set_ioctl(dhd_pub_t *dhd, int ifidx, uint cmd, void *buf,
154 uint len);
155
156 #ifdef DHD_DEBUG
157 /* Device console log buffer state */
158 typedef struct dhd_console {
159 uint count; /* Poll interval msec counter */
160 uint log_addr; /* Log struct address (fixed) */
161 hndrte_log_t log; /* Log struct (host copy) */
162 uint bufsize; /* Size of log buffer */
163 u8 *buf; /* Log buffer (host copy) */
164 uint last; /* Last buffer read index */
165 } dhd_console_t;
166 #endif /* DHD_DEBUG */
167
168 /* Private data for SDIO bus interaction */
169 typedef struct dhd_bus {
170 dhd_pub_t *dhd;
171
172 bcmsdh_info_t *sdh; /* Handle for BCMSDH calls */
173 si_t *sih; /* Handle for SI calls */
174 char *vars; /* Variables (from CIS and/or other) */
175 uint varsz; /* Size of variables buffer */
176 u32 sbaddr; /* Current SB window pointer (-1, invalid) */
177
178 sdpcmd_regs_t *regs; /* Registers for SDIO core */
179 uint sdpcmrev; /* SDIO core revision */
180 uint armrev; /* CPU core revision */
181 uint ramrev; /* SOCRAM core revision */
182 u32 ramsize; /* Size of RAM in SOCRAM (bytes) */
183 u32 orig_ramsize; /* Size of RAM in SOCRAM (bytes) */
184
185 u32 bus; /* gSPI or SDIO bus */
186 u32 hostintmask; /* Copy of Host Interrupt Mask */
187 u32 intstatus; /* Intstatus bits (events) pending */
188 bool dpc_sched; /* Indicates DPC schedule (intrpt rcvd) */
189 bool fcstate; /* State of dongle flow-control */
190
191 u16 cl_devid; /* cached devid for dhdsdio_probe_attach() */
192 char *fw_path; /* module_param: path to firmware image */
193 char *nv_path; /* module_param: path to nvram vars file */
194 const char *nvram_params; /* user specified nvram params. */
195
196 uint blocksize; /* Block size of SDIO transfers */
197 uint roundup; /* Max roundup limit */
198
199 struct pktq txq; /* Queue length used for flow-control */
200 u8 flowcontrol; /* per prio flow control bitmask */
201 u8 tx_seq; /* Transmit sequence number (next) */
202 u8 tx_max; /* Maximum transmit sequence allowed */
203
204 u8 hdrbuf[MAX_HDR_READ + DHD_SDALIGN];
205 u8 *rxhdr; /* Header of current rx frame (in hdrbuf) */
206 u16 nextlen; /* Next Read Len from last header */
207 u8 rx_seq; /* Receive sequence number (expected) */
208 bool rxskip; /* Skip receive (awaiting NAK ACK) */
209
210 struct sk_buff *glomd; /* Packet containing glomming descriptor */
211 struct sk_buff *glom; /* Packet chain for glommed superframe */
212 uint glomerr; /* Glom packet read errors */
213
214 u8 *rxbuf; /* Buffer for receiving control packets */
215 uint rxblen; /* Allocated length of rxbuf */
216 u8 *rxctl; /* Aligned pointer into rxbuf */
217 u8 *databuf; /* Buffer for receiving big glom packet */
218 u8 *dataptr; /* Aligned pointer into databuf */
219 uint rxlen; /* Length of valid data in buffer */
220
221 u8 sdpcm_ver; /* Bus protocol reported by dongle */
222
223 bool intr; /* Use interrupts */
224 bool poll; /* Use polling */
225 bool ipend; /* Device interrupt is pending */
226 bool intdis; /* Interrupts disabled by isr */
227 uint intrcount; /* Count of device interrupt callbacks */
228 uint lastintrs; /* Count as of last watchdog timer */
229 uint spurious; /* Count of spurious interrupts */
230 uint pollrate; /* Ticks between device polls */
231 uint polltick; /* Tick counter */
232 uint pollcnt; /* Count of active polls */
233
234 #ifdef DHD_DEBUG
235 dhd_console_t console; /* Console output polling support */
236 uint console_addr; /* Console address from shared struct */
237 #endif /* DHD_DEBUG */
238
239 uint regfails; /* Count of R_REG/W_REG failures */
240
241 uint clkstate; /* State of sd and backplane clock(s) */
242 bool activity; /* Activity flag for clock down */
243 s32 idletime; /* Control for activity timeout */
244 s32 idlecount; /* Activity timeout counter */
245 s32 idleclock; /* How to set bus driver when idle */
246 s32 sd_divisor; /* Speed control to bus driver */
247 s32 sd_mode; /* Mode control to bus driver */
248 s32 sd_rxchain; /* If bcmsdh api accepts PKT chains */
249 bool use_rxchain; /* If dhd should use PKT chains */
250 bool sleeping; /* Is SDIO bus sleeping? */
251 bool rxflow_mode; /* Rx flow control mode */
252 bool rxflow; /* Is rx flow control on */
253 uint prev_rxlim_hit; /* Is prev rx limit exceeded
254 (per dpc schedule) */
255 bool alp_only; /* Don't use HT clock (ALP only) */
256 /* Field to decide if rx of control frames happen in rxbuf or lb-pool */
257 bool usebufpool;
258
259 #ifdef SDTEST
260 /* external loopback */
261 bool ext_loop;
262 u8 loopid;
263
264 /* pktgen configuration */
265 uint pktgen_freq; /* Ticks between bursts */
266 uint pktgen_count; /* Packets to send each burst */
267 uint pktgen_print; /* Bursts between count displays */
268 uint pktgen_total; /* Stop after this many */
269 uint pktgen_minlen; /* Minimum packet data len */
270 uint pktgen_maxlen; /* Maximum packet data len */
271 uint pktgen_mode; /* Configured mode: tx, rx, or echo */
272 uint pktgen_stop; /* Number of tx failures causing stop */
273
274 /* active pktgen fields */
275 uint pktgen_tick; /* Tick counter for bursts */
276 uint pktgen_ptick; /* Burst counter for printing */
277 uint pktgen_sent; /* Number of test packets generated */
278 uint pktgen_rcvd; /* Number of test packets received */
279 uint pktgen_fail; /* Number of failed send attempts */
280 u16 pktgen_len; /* Length of next packet to send */
281 #endif /* SDTEST */
282
283 /* Some additional counters */
284 uint tx_sderrs; /* Count of tx attempts with sd errors */
285 uint fcqueued; /* Tx packets that got queued */
286 uint rxrtx; /* Count of rtx requests (NAK to dongle) */
287 uint rx_toolong; /* Receive frames too long to receive */
288 uint rxc_errors; /* SDIO errors when reading control frames */
289 uint rx_hdrfail; /* SDIO errors on header reads */
290 uint rx_badhdr; /* Bad received headers (roosync?) */
291 uint rx_badseq; /* Mismatched rx sequence number */
292 uint fc_rcvd; /* Number of flow-control events received */
293 uint fc_xoff; /* Number which turned on flow-control */
294 uint fc_xon; /* Number which turned off flow-control */
295 uint rxglomfail; /* Failed deglom attempts */
296 uint rxglomframes; /* Number of glom frames (superframes) */
297 uint rxglompkts; /* Number of packets from glom frames */
298 uint f2rxhdrs; /* Number of header reads */
299 uint f2rxdata; /* Number of frame data reads */
300 uint f2txdata; /* Number of f2 frame writes */
301 uint f1regdata; /* Number of f1 register accesses */
302
303 u8 *ctrl_frame_buf;
304 u32 ctrl_frame_len;
305 bool ctrl_frame_stat;
306 } dhd_bus_t;
307
308 /* clkstate */
309 #define CLK_NONE 0
310 #define CLK_SDONLY 1
311 #define CLK_PENDING 2 /* Not used yet */
312 #define CLK_AVAIL 3
313
314 #define DHD_NOPMU(dhd) (false)
315
316 #ifdef DHD_DEBUG
317 static int qcount[NUMPRIO];
318 static int tx_packets[NUMPRIO];
319 #endif /* DHD_DEBUG */
320
321 /* Deferred transmit */
322 const uint dhd_deferred_tx = 1;
323
324 extern uint dhd_watchdog_ms;
325 extern void dhd_os_wd_timer(void *bus, uint wdtick);
326
327 /* Tx/Rx bounds */
328 uint dhd_txbound;
329 uint dhd_rxbound;
330 uint dhd_txminmax;
331
332 /* override the RAM size if possible */
333 #define DONGLE_MIN_MEMSIZE (128 * 1024)
334 int dhd_dongle_memsize;
335
336 static bool dhd_doflow;
337 static bool dhd_alignctl;
338
339 static bool sd1idle;
340
341 static bool retrydata;
342 #define RETRYCHAN(chan) (((chan) == SDPCM_EVENT_CHANNEL) || retrydata)
343
344 static const uint watermark = 8;
345 static const uint firstread = DHD_FIRSTREAD;
346
347 #define HDATLEN (firstread - (SDPCM_HDRLEN))
348
349 /* Retry count for register access failures */
350 static const uint retry_limit = 2;
351
352 /* Force even SD lengths (some host controllers mess up on odd bytes) */
353 static bool forcealign;
354
355 #define ALIGNMENT 4
356
357 #if defined(OOB_INTR_ONLY) && defined(HW_OOB)
358 extern void bcmsdh_enable_hw_oob_intr(void *sdh, bool enable);
359 #endif
360
361 #if defined(OOB_INTR_ONLY) && defined(SDIO_ISR_THREAD)
362 #error OOB_INTR_ONLY is NOT working with SDIO_ISR_THREAD
363 #endif /* defined(OOB_INTR_ONLY) && defined(SDIO_ISR_THREAD) */
364 #define PKTALIGN(_p, _len, _align) \
365 do { \
366 uint datalign; \
367 datalign = (unsigned long)((_p)->data); \
368 datalign = roundup(datalign, (_align)) - datalign; \
369 ASSERT(datalign < (_align)); \
370 ASSERT((_p)->len >= ((_len) + datalign)); \
371 if (datalign) \
372 skb_pull((_p), datalign); \
373 __skb_trim((_p), (_len)); \
374 } while (0)
375
376 /* Limit on rounding up frames */
377 static const uint max_roundup = 512;
378
379 /* Try doing readahead */
380 static bool dhd_readahead;
381
382 /* To check if there's window offered */
383 #define DATAOK(bus) \
384 (((u8)(bus->tx_max - bus->tx_seq) != 0) && \
385 (((u8)(bus->tx_max - bus->tx_seq) & 0x80) == 0))
386
387 /* Macros to get register read/write status */
388 /* NOTE: these assume a local dhdsdio_bus_t *bus! */
389 #define R_SDREG(regvar, regaddr, retryvar) \
390 do { \
391 retryvar = 0; \
392 do { \
393 regvar = R_REG(regaddr); \
394 } while (bcmsdh_regfail(bus->sdh) && (++retryvar <= retry_limit)); \
395 if (retryvar) { \
396 bus->regfails += (retryvar-1); \
397 if (retryvar > retry_limit) { \
398 DHD_ERROR(("%s: FAILED" #regvar "READ, LINE %d\n", \
399 __func__, __LINE__)); \
400 regvar = 0; \
401 } \
402 } \
403 } while (0)
404
405 #define W_SDREG(regval, regaddr, retryvar) \
406 do { \
407 retryvar = 0; \
408 do { \
409 W_REG(regaddr, regval); \
410 } while (bcmsdh_regfail(bus->sdh) && (++retryvar <= retry_limit)); \
411 if (retryvar) { \
412 bus->regfails += (retryvar-1); \
413 if (retryvar > retry_limit) \
414 DHD_ERROR(("%s: FAILED REGISTER WRITE, LINE %d\n", \
415 __func__, __LINE__)); \
416 } \
417 } while (0)
418
419 #define DHD_BUS SDIO_BUS
420
421 #define PKT_AVAILABLE() (intstatus & I_HMB_FRAME_IND)
422
423 #define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE)
424
425 #define GSPI_PR55150_BAILOUT
426
427 #ifdef SDTEST
428 static void dhdsdio_testrcv(dhd_bus_t *bus, void *pkt, uint seq);
429 static void dhdsdio_sdtest_set(dhd_bus_t *bus, bool start);
430 #endif
431
432 #ifdef DHD_DEBUG
433 static int dhdsdio_checkdied(dhd_bus_t *bus, u8 *data, uint size);
434 static int dhdsdio_mem_dump(dhd_bus_t *bus);
435 #endif /* DHD_DEBUG */
436 static int dhdsdio_download_state(dhd_bus_t *bus, bool enter);
437
438 static void dhdsdio_release(dhd_bus_t *bus);
439 static void dhdsdio_release_malloc(dhd_bus_t *bus);
440 static void dhdsdio_disconnect(void *ptr);
441 static bool dhdsdio_chipmatch(u16 chipid);
442 static bool dhdsdio_probe_attach(dhd_bus_t *bus, void *sdh,
443 void *regsva, u16 devid);
444 static bool dhdsdio_probe_malloc(dhd_bus_t *bus, void *sdh);
445 static bool dhdsdio_probe_init(dhd_bus_t *bus, void *sdh);
446 static void dhdsdio_release_dongle(dhd_bus_t *bus);
447
448 static uint process_nvram_vars(char *varbuf, uint len);
449
450 static void dhd_dongle_setmemsize(struct dhd_bus *bus, int mem_size);
451 static int dhd_bcmsdh_recv_buf(dhd_bus_t *bus, u32 addr, uint fn,
452 uint flags, u8 *buf, uint nbytes,
453 struct sk_buff *pkt, bcmsdh_cmplt_fn_t complete,
454 void *handle);
455 static int dhd_bcmsdh_send_buf(dhd_bus_t *bus, u32 addr, uint fn,
456 uint flags, u8 *buf, uint nbytes,
457 struct sk_buff *pkt, bcmsdh_cmplt_fn_t complete,
458 void *handle);
459
460 static bool dhdsdio_download_firmware(struct dhd_bus *bus, void *sdh);
461 static int _dhdsdio_download_firmware(struct dhd_bus *bus);
462
463 static int dhdsdio_download_code_file(struct dhd_bus *bus, char *image_path);
464 static int dhdsdio_download_nvram(struct dhd_bus *bus);
465 #ifdef BCMEMBEDIMAGE
466 static int dhdsdio_download_code_array(struct dhd_bus *bus);
467 #endif
468
469 static void dhd_dongle_setmemsize(struct dhd_bus *bus, int mem_size)
470 {
471 s32 min_size = DONGLE_MIN_MEMSIZE;
472 /* Restrict the memsize to user specified limit */
473 DHD_ERROR(("user: Restrict the dongle ram size to %d, min %d\n",
474 dhd_dongle_memsize, min_size));
475 if ((dhd_dongle_memsize > min_size) &&
476 (dhd_dongle_memsize < (s32) bus->orig_ramsize))
477 bus->ramsize = dhd_dongle_memsize;
478 }
479
480 static int dhdsdio_set_siaddr_window(dhd_bus_t *bus, u32 address)
481 {
482 int err = 0;
483 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRLOW,
484 (address >> 8) & SBSDIO_SBADDRLOW_MASK, &err);
485 if (!err)
486 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRMID,
487 (address >> 16) & SBSDIO_SBADDRMID_MASK, &err);
488 if (!err)
489 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRHIGH,
490 (address >> 24) & SBSDIO_SBADDRHIGH_MASK,
491 &err);
492 return err;
493 }
494
495 /* Turn backplane clock on or off */
496 static int dhdsdio_htclk(dhd_bus_t *bus, bool on, bool pendok)
497 {
498 int err;
499 u8 clkctl, clkreq, devctl;
500 bcmsdh_info_t *sdh;
501
502 DHD_TRACE(("%s: Enter\n", __func__));
503
504 #if defined(OOB_INTR_ONLY)
505 pendok = false;
506 #endif
507 clkctl = 0;
508 sdh = bus->sdh;
509
510 if (on) {
511 /* Request HT Avail */
512 clkreq =
513 bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ;
514
515 if ((bus->sih->chip == BCM4329_CHIP_ID)
516 && (bus->sih->chiprev == 0))
517 clkreq |= SBSDIO_FORCE_ALP;
518
519 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
520 clkreq, &err);
521 if (err) {
522 DHD_ERROR(("%s: HT Avail request error: %d\n",
523 __func__, err));
524 return BCME_ERROR;
525 }
526
527 if (pendok && ((bus->sih->buscoretype == PCMCIA_CORE_ID)
528 && (bus->sih->buscorerev == 9))) {
529 u32 dummy, retries;
530 R_SDREG(dummy, &bus->regs->clockctlstatus, retries);
531 }
532
533 /* Check current status */
534 clkctl =
535 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
536 &err);
537 if (err) {
538 DHD_ERROR(("%s: HT Avail read error: %d\n",
539 __func__, err));
540 return BCME_ERROR;
541 }
542
543 /* Go to pending and await interrupt if appropriate */
544 if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) {
545 /* Allow only clock-available interrupt */
546 devctl =
547 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
548 &err);
549 if (err) {
550 DHD_ERROR(("%s: Devctl error setting CA: %d\n",
551 __func__, err));
552 return BCME_ERROR;
553 }
554
555 devctl |= SBSDIO_DEVCTL_CA_INT_ONLY;
556 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
557 devctl, &err);
558 DHD_INFO(("CLKCTL: set PENDING\n"));
559 bus->clkstate = CLK_PENDING;
560
561 return BCME_OK;
562 } else if (bus->clkstate == CLK_PENDING) {
563 /* Cancel CA-only interrupt filter */
564 devctl =
565 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
566 &err);
567 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
568 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
569 devctl, &err);
570 }
571
572 /* Otherwise, wait here (polling) for HT Avail */
573 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
574 SPINWAIT_SLEEP(sdioh_spinwait_sleep,
575 ((clkctl =
576 bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
577 SBSDIO_FUNC1_CHIPCLKCSR,
578 &err)),
579 !SBSDIO_CLKAV(clkctl, bus->alp_only)),
580 PMU_MAX_TRANSITION_DLY);
581 }
582 if (err) {
583 DHD_ERROR(("%s: HT Avail request error: %d\n",
584 __func__, err));
585 return BCME_ERROR;
586 }
587 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
588 DHD_ERROR(("%s: HT Avail timeout (%d): clkctl 0x%02x\n",
589 __func__, PMU_MAX_TRANSITION_DLY, clkctl));
590 return BCME_ERROR;
591 }
592
593 /* Mark clock available */
594 bus->clkstate = CLK_AVAIL;
595 DHD_INFO(("CLKCTL: turned ON\n"));
596
597 #if defined(DHD_DEBUG)
598 if (bus->alp_only == true) {
599 #if !defined(BCMLXSDMMC)
600 if (!SBSDIO_ALPONLY(clkctl)) {
601 DHD_ERROR(("%s: HT Clock, when ALP Only\n",
602 __func__));
603 }
604 #endif /* !defined(BCMLXSDMMC) */
605 } else {
606 if (SBSDIO_ALPONLY(clkctl)) {
607 DHD_ERROR(("%s: HT Clock should be on.\n",
608 __func__));
609 }
610 }
611 #endif /* defined (DHD_DEBUG) */
612
613 bus->activity = true;
614 } else {
615 clkreq = 0;
616
617 if (bus->clkstate == CLK_PENDING) {
618 /* Cancel CA-only interrupt filter */
619 devctl =
620 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
621 &err);
622 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
623 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
624 devctl, &err);
625 }
626
627 bus->clkstate = CLK_SDONLY;
628 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
629 clkreq, &err);
630 DHD_INFO(("CLKCTL: turned OFF\n"));
631 if (err) {
632 DHD_ERROR(("%s: Failed access turning clock off: %d\n",
633 __func__, err));
634 return BCME_ERROR;
635 }
636 }
637 return BCME_OK;
638 }
639
640 /* Change idle/active SD state */
641 static int dhdsdio_sdclk(dhd_bus_t *bus, bool on)
642 {
643 int err;
644 s32 iovalue;
645
646 DHD_TRACE(("%s: Enter\n", __func__));
647
648 if (on) {
649 if (bus->idleclock == DHD_IDLE_STOP) {
650 /* Turn on clock and restore mode */
651 iovalue = 1;
652 err = bcmsdh_iovar_op(bus->sdh, "sd_clock", NULL, 0,
653 &iovalue, sizeof(iovalue), true);
654 if (err) {
655 DHD_ERROR(("%s: error enabling sd_clock: %d\n",
656 __func__, err));
657 return BCME_ERROR;
658 }
659
660 iovalue = bus->sd_mode;
661 err = bcmsdh_iovar_op(bus->sdh, "sd_mode", NULL, 0,
662 &iovalue, sizeof(iovalue), true);
663 if (err) {
664 DHD_ERROR(("%s: error changing sd_mode: %d\n",
665 __func__, err));
666 return BCME_ERROR;
667 }
668 } else if (bus->idleclock != DHD_IDLE_ACTIVE) {
669 /* Restore clock speed */
670 iovalue = bus->sd_divisor;
671 err = bcmsdh_iovar_op(bus->sdh, "sd_divisor", NULL, 0,
672 &iovalue, sizeof(iovalue), true);
673 if (err) {
674 DHD_ERROR(("%s: error restoring sd_divisor: %d\n",
675 __func__, err));
676 return BCME_ERROR;
677 }
678 }
679 bus->clkstate = CLK_SDONLY;
680 } else {
681 /* Stop or slow the SD clock itself */
682 if ((bus->sd_divisor == -1) || (bus->sd_mode == -1)) {
683 DHD_TRACE(("%s: can't idle clock, divisor %d mode %d\n",
684 __func__, bus->sd_divisor, bus->sd_mode));
685 return BCME_ERROR;
686 }
687 if (bus->idleclock == DHD_IDLE_STOP) {
688 if (sd1idle) {
689 /* Change to SD1 mode and turn off clock */
690 iovalue = 1;
691 err =
692 bcmsdh_iovar_op(bus->sdh, "sd_mode", NULL,
693 0, &iovalue,
694 sizeof(iovalue), true);
695 if (err) {
696 DHD_ERROR(("%s: error changing sd_clock: %d\n",
697 __func__, err));
698 return BCME_ERROR;
699 }
700 }
701
702 iovalue = 0;
703 err = bcmsdh_iovar_op(bus->sdh, "sd_clock", NULL, 0,
704 &iovalue, sizeof(iovalue), true);
705 if (err) {
706 DHD_ERROR(("%s: error disabling sd_clock: %d\n",
707 __func__, err));
708 return BCME_ERROR;
709 }
710 } else if (bus->idleclock != DHD_IDLE_ACTIVE) {
711 /* Set divisor to idle value */
712 iovalue = bus->idleclock;
713 err = bcmsdh_iovar_op(bus->sdh, "sd_divisor", NULL, 0,
714 &iovalue, sizeof(iovalue), true);
715 if (err) {
716 DHD_ERROR(("%s: error changing sd_divisor: %d\n",
717 __func__, err));
718 return BCME_ERROR;
719 }
720 }
721 bus->clkstate = CLK_NONE;
722 }
723
724 return BCME_OK;
725 }
726
727 /* Transition SD and backplane clock readiness */
728 static int dhdsdio_clkctl(dhd_bus_t *bus, uint target, bool pendok)
729 {
730 #ifdef DHD_DEBUG
731 uint oldstate = bus->clkstate;
732 #endif /* DHD_DEBUG */
733
734 DHD_TRACE(("%s: Enter\n", __func__));
735
736 /* Early exit if we're already there */
737 if (bus->clkstate == target) {
738 if (target == CLK_AVAIL) {
739 dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
740 bus->activity = true;
741 }
742 return BCME_OK;
743 }
744
745 switch (target) {
746 case CLK_AVAIL:
747 /* Make sure SD clock is available */
748 if (bus->clkstate == CLK_NONE)
749 dhdsdio_sdclk(bus, true);
750 /* Now request HT Avail on the backplane */
751 dhdsdio_htclk(bus, true, pendok);
752 dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
753 bus->activity = true;
754 break;
755
756 case CLK_SDONLY:
757 /* Remove HT request, or bring up SD clock */
758 if (bus->clkstate == CLK_NONE)
759 dhdsdio_sdclk(bus, true);
760 else if (bus->clkstate == CLK_AVAIL)
761 dhdsdio_htclk(bus, false, false);
762 else
763 DHD_ERROR(("dhdsdio_clkctl: request for %d -> %d\n",
764 bus->clkstate, target));
765 dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
766 break;
767
768 case CLK_NONE:
769 /* Make sure to remove HT request */
770 if (bus->clkstate == CLK_AVAIL)
771 dhdsdio_htclk(bus, false, false);
772 /* Now remove the SD clock */
773 dhdsdio_sdclk(bus, false);
774 dhd_os_wd_timer(bus->dhd, 0);
775 break;
776 }
777 #ifdef DHD_DEBUG
778 DHD_INFO(("dhdsdio_clkctl: %d -> %d\n", oldstate, bus->clkstate));
779 #endif /* DHD_DEBUG */
780
781 return BCME_OK;
782 }
783
784 int dhdsdio_bussleep(dhd_bus_t *bus, bool sleep)
785 {
786 bcmsdh_info_t *sdh = bus->sdh;
787 sdpcmd_regs_t *regs = bus->regs;
788 uint retries = 0;
789
790 DHD_INFO(("dhdsdio_bussleep: request %s (currently %s)\n",
791 (sleep ? "SLEEP" : "WAKE"),
792 (bus->sleeping ? "SLEEP" : "WAKE")));
793
794 /* Done if we're already in the requested state */
795 if (sleep == bus->sleeping)
796 return BCME_OK;
797
798 /* Going to sleep: set the alarm and turn off the lights... */
799 if (sleep) {
800 /* Don't sleep if something is pending */
801 if (bus->dpc_sched || bus->rxskip || pktq_len(&bus->txq))
802 return BCME_BUSY;
803
804 /* Disable SDIO interrupts (no longer interested) */
805 bcmsdh_intr_disable(bus->sdh);
806
807 /* Make sure the controller has the bus up */
808 dhdsdio_clkctl(bus, CLK_AVAIL, false);
809
810 /* Tell device to start using OOB wakeup */
811 W_SDREG(SMB_USE_OOB, &regs->tosbmailbox, retries);
812 if (retries > retry_limit)
813 DHD_ERROR(("CANNOT SIGNAL CHIP, WILL NOT WAKE UP!!\n"));
814
815 /* Turn off our contribution to the HT clock request */
816 dhdsdio_clkctl(bus, CLK_SDONLY, false);
817
818 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
819 SBSDIO_FORCE_HW_CLKREQ_OFF, NULL);
820
821 /* Isolate the bus */
822 if (bus->sih->chip != BCM4329_CHIP_ID
823 && bus->sih->chip != BCM4319_CHIP_ID) {
824 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
825 SBSDIO_DEVCTL_PADS_ISO, NULL);
826 }
827
828 /* Change state */
829 bus->sleeping = true;
830
831 } else {
832 /* Waking up: bus power up is ok, set local state */
833
834 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
835 0, NULL);
836
837 /* Force pad isolation off if possible
838 (in case power never toggled) */
839 if ((bus->sih->buscoretype == PCMCIA_CORE_ID)
840 && (bus->sih->buscorerev >= 10))
841 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, 0,
842 NULL);
843
844 /* Make sure the controller has the bus up */
845 dhdsdio_clkctl(bus, CLK_AVAIL, false);
846
847 /* Send misc interrupt to indicate OOB not needed */
848 W_SDREG(0, &regs->tosbmailboxdata, retries);
849 if (retries <= retry_limit)
850 W_SDREG(SMB_DEV_INT, &regs->tosbmailbox, retries);
851
852 if (retries > retry_limit)
853 DHD_ERROR(("CANNOT SIGNAL CHIP TO CLEAR OOB!!\n"));
854
855 /* Make sure we have SD bus access */
856 dhdsdio_clkctl(bus, CLK_SDONLY, false);
857
858 /* Change state */
859 bus->sleeping = false;
860
861 /* Enable interrupts again */
862 if (bus->intr && (bus->dhd->busstate == DHD_BUS_DATA)) {
863 bus->intdis = false;
864 bcmsdh_intr_enable(bus->sdh);
865 }
866 }
867
868 return BCME_OK;
869 }
870
871 #if defined(OOB_INTR_ONLY)
872 void dhd_enable_oob_intr(struct dhd_bus *bus, bool enable)
873 {
874 #if defined(HW_OOB)
875 bcmsdh_enable_hw_oob_intr(bus->sdh, enable);
876 #else
877 sdpcmd_regs_t *regs = bus->regs;
878 uint retries = 0;
879
880 dhdsdio_clkctl(bus, CLK_AVAIL, false);
881 if (enable == true) {
882
883 /* Tell device to start using OOB wakeup */
884 W_SDREG(SMB_USE_OOB, &regs->tosbmailbox, retries);
885 if (retries > retry_limit)
886 DHD_ERROR(("CANNOT SIGNAL CHIP, WILL NOT WAKE UP!!\n"));
887
888 } else {
889 /* Send misc interrupt to indicate OOB not needed */
890 W_SDREG(0, &regs->tosbmailboxdata, retries);
891 if (retries <= retry_limit)
892 W_SDREG(SMB_DEV_INT, &regs->tosbmailbox, retries);
893 }
894
895 /* Turn off our contribution to the HT clock request */
896 dhdsdio_clkctl(bus, CLK_SDONLY, false);
897 #endif /* !defined(HW_OOB) */
898 }
899 #endif /* defined(OOB_INTR_ONLY) */
900
901 #define BUS_WAKE(bus) \
902 do { \
903 if ((bus)->sleeping) \
904 dhdsdio_bussleep((bus), false); \
905 } while (0);
906
907 /* Writes a HW/SW header into the packet and sends it. */
908 /* Assumes: (a) header space already there, (b) caller holds lock */
909 static int dhdsdio_txpkt(dhd_bus_t *bus, struct sk_buff *pkt, uint chan,
910 bool free_pkt)
911 {
912 int ret;
913 u8 *frame;
914 u16 len, pad = 0;
915 u32 swheader;
916 uint retries = 0;
917 bcmsdh_info_t *sdh;
918 struct sk_buff *new;
919 int i;
920
921 DHD_TRACE(("%s: Enter\n", __func__));
922
923 sdh = bus->sdh;
924
925 if (bus->dhd->dongle_reset) {
926 ret = BCME_NOTREADY;
927 goto done;
928 }
929
930 frame = (u8 *) (pkt->data);
931
932 /* Add alignment padding, allocate new packet if needed */
933 pad = ((unsigned long)frame % DHD_SDALIGN);
934 if (pad) {
935 if (skb_headroom(pkt) < pad) {
936 DHD_INFO(("%s: insufficient headroom %d for %d pad\n",
937 __func__, skb_headroom(pkt), pad));
938 bus->dhd->tx_realloc++;
939 new = pkt_buf_get_skb(pkt->len + DHD_SDALIGN);
940 if (!new) {
941 DHD_ERROR(("%s: couldn't allocate new %d-byte "
942 "packet\n",
943 __func__, pkt->len + DHD_SDALIGN));
944 ret = BCME_NOMEM;
945 goto done;
946 }
947
948 PKTALIGN(new, pkt->len, DHD_SDALIGN);
949 memcpy(new->data, pkt->data, pkt->len);
950 if (free_pkt)
951 pkt_buf_free_skb(pkt);
952 /* free the pkt if canned one is not used */
953 free_pkt = true;
954 pkt = new;
955 frame = (u8 *) (pkt->data);
956 ASSERT(((unsigned long)frame % DHD_SDALIGN) == 0);
957 pad = 0;
958 } else {
959 skb_push(pkt, pad);
960 frame = (u8 *) (pkt->data);
961
962 ASSERT((pad + SDPCM_HDRLEN) <= (int)(pkt->len));
963 memset(frame, 0, pad + SDPCM_HDRLEN);
964 }
965 }
966 ASSERT(pad < DHD_SDALIGN);
967
968 /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
969 len = (u16) (pkt->len);
970 *(u16 *) frame = cpu_to_le16(len);
971 *(((u16 *) frame) + 1) = cpu_to_le16(~len);
972
973 /* Software tag: channel, sequence number, data offset */
974 swheader =
975 ((chan << SDPCM_CHANNEL_SHIFT) & SDPCM_CHANNEL_MASK) | bus->tx_seq |
976 (((pad +
977 SDPCM_HDRLEN) << SDPCM_DOFFSET_SHIFT) & SDPCM_DOFFSET_MASK);
978
979 put_unaligned_le32(swheader, frame + SDPCM_FRAMETAG_LEN);
980 put_unaligned_le32(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
981
982 #ifdef DHD_DEBUG
983 tx_packets[pkt->priority]++;
984 if (DHD_BYTES_ON() &&
985 (((DHD_CTL_ON() && (chan == SDPCM_CONTROL_CHANNEL)) ||
986 (DHD_DATA_ON() && (chan != SDPCM_CONTROL_CHANNEL))))) {
987 prhex("Tx Frame", frame, len);
988 } else if (DHD_HDRS_ON()) {
989 prhex("TxHdr", frame, min_t(u16, len, 16));
990 }
991 #endif
992
993 /* Raise len to next SDIO block to eliminate tail command */
994 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
995 u16 pad = bus->blocksize - (len % bus->blocksize);
996 if ((pad <= bus->roundup) && (pad < bus->blocksize))
997 #ifdef NOTUSED
998 if (pad <= skb_tailroom(pkt))
999 #endif /* NOTUSED */
1000 len += pad;
1001 } else if (len % DHD_SDALIGN) {
1002 len += DHD_SDALIGN - (len % DHD_SDALIGN);
1003 }
1004
1005 /* Some controllers have trouble with odd bytes -- round to even */
1006 if (forcealign && (len & (ALIGNMENT - 1))) {
1007 #ifdef NOTUSED
1008 if (skb_tailroom(pkt))
1009 #endif
1010 len = roundup(len, ALIGNMENT);
1011 #ifdef NOTUSED
1012 else
1013 DHD_ERROR(("%s: sending unrounded %d-byte packet\n",
1014 __func__, len));
1015 #endif
1016 }
1017
1018 do {
1019 ret =
1020 dhd_bcmsdh_send_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2,
1021 F2SYNC, frame, len, pkt, NULL, NULL);
1022 bus->f2txdata++;
1023 ASSERT(ret != BCME_PENDING);
1024
1025 if (ret < 0) {
1026 /* On failure, abort the command
1027 and terminate the frame */
1028 DHD_INFO(("%s: sdio error %d, abort command and "
1029 "terminate frame.\n", __func__, ret));
1030 bus->tx_sderrs++;
1031
1032 bcmsdh_abort(sdh, SDIO_FUNC_2);
1033 bcmsdh_cfg_write(sdh, SDIO_FUNC_1,
1034 SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM,
1035 NULL);
1036 bus->f1regdata++;
1037
1038 for (i = 0; i < 3; i++) {
1039 u8 hi, lo;
1040 hi = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
1041 SBSDIO_FUNC1_WFRAMEBCHI,
1042 NULL);
1043 lo = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
1044 SBSDIO_FUNC1_WFRAMEBCLO,
1045 NULL);
1046 bus->f1regdata += 2;
1047 if ((hi == 0) && (lo == 0))
1048 break;
1049 }
1050
1051 }
1052 if (ret == 0)
1053 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
1054
1055 } while ((ret < 0) && retrydata && retries++ < TXRETRIES);
1056
1057 done:
1058 /* restore pkt buffer pointer before calling tx complete routine */
1059 skb_pull(pkt, SDPCM_HDRLEN + pad);
1060 dhd_os_sdunlock(bus->dhd);
1061 dhd_txcomplete(bus->dhd, pkt, ret != 0);
1062 dhd_os_sdlock(bus->dhd);
1063
1064 if (free_pkt)
1065 pkt_buf_free_skb(pkt);
1066
1067 return ret;
1068 }
1069
1070 int dhd_bus_txdata(struct dhd_bus *bus, struct sk_buff *pkt)
1071 {
1072 int ret = BCME_ERROR;
1073 uint datalen, prec;
1074
1075 DHD_TRACE(("%s: Enter\n", __func__));
1076
1077 datalen = pkt->len;
1078
1079 #ifdef SDTEST
1080 /* Push the test header if doing loopback */
1081 if (bus->ext_loop) {
1082 u8 *data;
1083 skb_push(pkt, SDPCM_TEST_HDRLEN);
1084 data = pkt->data;
1085 *data++ = SDPCM_TEST_ECHOREQ;
1086 *data++ = (u8) bus->loopid++;
1087 *data++ = (datalen >> 0);
1088 *data++ = (datalen >> 8);
1089 datalen += SDPCM_TEST_HDRLEN;
1090 }
1091 #endif /* SDTEST */
1092
1093 /* Add space for the header */
1094 skb_push(pkt, SDPCM_HDRLEN);
1095 ASSERT(IS_ALIGNED((unsigned long)(pkt->data), 2));
1096
1097 prec = PRIO2PREC((pkt->priority & PRIOMASK));
1098
1099 /* Check for existing queue, current flow-control,
1100 pending event, or pending clock */
1101 if (dhd_deferred_tx || bus->fcstate || pktq_len(&bus->txq)
1102 || bus->dpc_sched || (!DATAOK(bus))
1103 || (bus->flowcontrol & NBITVAL(prec))
1104 || (bus->clkstate != CLK_AVAIL)) {
1105 DHD_TRACE(("%s: deferring pktq len %d\n", __func__,
1106 pktq_len(&bus->txq)));
1107 bus->fcqueued++;
1108
1109 /* Priority based enq */
1110 dhd_os_sdlock_txq(bus->dhd);
1111 if (dhd_prec_enq(bus->dhd, &bus->txq, pkt, prec) == false) {
1112 skb_pull(pkt, SDPCM_HDRLEN);
1113 dhd_txcomplete(bus->dhd, pkt, false);
1114 pkt_buf_free_skb(pkt);
1115 DHD_ERROR(("%s: out of bus->txq !!!\n", __func__));
1116 ret = BCME_NORESOURCE;
1117 } else {
1118 ret = BCME_OK;
1119 }
1120 dhd_os_sdunlock_txq(bus->dhd);
1121
1122 if ((pktq_len(&bus->txq) >= TXHI) && dhd_doflow)
1123 dhd_txflowcontrol(bus->dhd, 0, ON);
1124
1125 #ifdef DHD_DEBUG
1126 if (pktq_plen(&bus->txq, prec) > qcount[prec])
1127 qcount[prec] = pktq_plen(&bus->txq, prec);
1128 #endif
1129 /* Schedule DPC if needed to send queued packet(s) */
1130 if (dhd_deferred_tx && !bus->dpc_sched) {
1131 bus->dpc_sched = true;
1132 dhd_sched_dpc(bus->dhd);
1133 }
1134 } else {
1135 /* Lock: we're about to use shared data/code (and SDIO) */
1136 dhd_os_sdlock(bus->dhd);
1137
1138 /* Otherwise, send it now */
1139 BUS_WAKE(bus);
1140 /* Make sure back plane ht clk is on, no pending allowed */
1141 dhdsdio_clkctl(bus, CLK_AVAIL, true);
1142
1143 #ifndef SDTEST
1144 DHD_TRACE(("%s: calling txpkt\n", __func__));
1145 ret = dhdsdio_txpkt(bus, pkt, SDPCM_DATA_CHANNEL, true);
1146 #else
1147 ret = dhdsdio_txpkt(bus, pkt,
1148 (bus->ext_loop ? SDPCM_TEST_CHANNEL :
1149 SDPCM_DATA_CHANNEL), true);
1150 #endif
1151 if (ret)
1152 bus->dhd->tx_errors++;
1153 else
1154 bus->dhd->dstats.tx_bytes += datalen;
1155
1156 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
1157 bus->activity = false;
1158 dhdsdio_clkctl(bus, CLK_NONE, true);
1159 }
1160
1161 dhd_os_sdunlock(bus->dhd);
1162 }
1163
1164 return ret;
1165 }
1166
1167 static uint dhdsdio_sendfromq(dhd_bus_t *bus, uint maxframes)
1168 {
1169 struct sk_buff *pkt;
1170 u32 intstatus = 0;
1171 uint retries = 0;
1172 int ret = 0, prec_out;
1173 uint cnt = 0;
1174 uint datalen;
1175 u8 tx_prec_map;
1176
1177 dhd_pub_t *dhd = bus->dhd;
1178 sdpcmd_regs_t *regs = bus->regs;
1179
1180 DHD_TRACE(("%s: Enter\n", __func__));
1181
1182 tx_prec_map = ~bus->flowcontrol;
1183
1184 /* Send frames until the limit or some other event */
1185 for (cnt = 0; (cnt < maxframes) && DATAOK(bus); cnt++) {
1186 dhd_os_sdlock_txq(bus->dhd);
1187 pkt = pktq_mdeq(&bus->txq, tx_prec_map, &prec_out);
1188 if (pkt == NULL) {
1189 dhd_os_sdunlock_txq(bus->dhd);
1190 break;
1191 }
1192 dhd_os_sdunlock_txq(bus->dhd);
1193 datalen = pkt->len - SDPCM_HDRLEN;
1194
1195 #ifndef SDTEST
1196 ret = dhdsdio_txpkt(bus, pkt, SDPCM_DATA_CHANNEL, true);
1197 #else
1198 ret = dhdsdio_txpkt(bus, pkt,
1199 (bus->ext_loop ? SDPCM_TEST_CHANNEL :
1200 SDPCM_DATA_CHANNEL), true);
1201 #endif
1202 if (ret)
1203 bus->dhd->tx_errors++;
1204 else
1205 bus->dhd->dstats.tx_bytes += datalen;
1206
1207 /* In poll mode, need to check for other events */
1208 if (!bus->intr && cnt) {
1209 /* Check device status, signal pending interrupt */
1210 R_SDREG(intstatus, &regs->intstatus, retries);
1211 bus->f2txdata++;
1212 if (bcmsdh_regfail(bus->sdh))
1213 break;
1214 if (intstatus & bus->hostintmask)
1215 bus->ipend = true;
1216 }
1217 }
1218
1219 /* Deflow-control stack if needed */
1220 if (dhd_doflow && dhd->up && (dhd->busstate == DHD_BUS_DATA) &&
1221 dhd->txoff && (pktq_len(&bus->txq) < TXLOW))
1222 dhd_txflowcontrol(dhd, 0, OFF);
1223
1224 return cnt;
1225 }
1226
1227 int dhd_bus_txctl(struct dhd_bus *bus, unsigned char *msg, uint msglen)
1228 {
1229 u8 *frame;
1230 u16 len;
1231 u32 swheader;
1232 uint retries = 0;
1233 bcmsdh_info_t *sdh = bus->sdh;
1234 u8 doff = 0;
1235 int ret = -1;
1236 int i;
1237
1238 DHD_TRACE(("%s: Enter\n", __func__));
1239
1240 if (bus->dhd->dongle_reset)
1241 return -EIO;
1242
1243 /* Back the pointer to make a room for bus header */
1244 frame = msg - SDPCM_HDRLEN;
1245 len = (msglen += SDPCM_HDRLEN);
1246
1247 /* Add alignment padding (optional for ctl frames) */
1248 if (dhd_alignctl) {
1249 doff = ((unsigned long)frame % DHD_SDALIGN);
1250 if (doff) {
1251 frame -= doff;
1252 len += doff;
1253 msglen += doff;
1254 memset(frame, 0, doff + SDPCM_HDRLEN);
1255 }
1256 ASSERT(doff < DHD_SDALIGN);
1257 }
1258 doff += SDPCM_HDRLEN;
1259
1260 /* Round send length to next SDIO block */
1261 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
1262 u16 pad = bus->blocksize - (len % bus->blocksize);
1263 if ((pad <= bus->roundup) && (pad < bus->blocksize))
1264 len += pad;
1265 } else if (len % DHD_SDALIGN) {
1266 len += DHD_SDALIGN - (len % DHD_SDALIGN);
1267 }
1268
1269 /* Satisfy length-alignment requirements */
1270 if (forcealign && (len & (ALIGNMENT - 1)))
1271 len = roundup(len, ALIGNMENT);
1272
1273 ASSERT(IS_ALIGNED((unsigned long)frame, 2));
1274
1275 /* Need to lock here to protect txseq and SDIO tx calls */
1276 dhd_os_sdlock(bus->dhd);
1277
1278 BUS_WAKE(bus);
1279
1280 /* Make sure backplane clock is on */
1281 dhdsdio_clkctl(bus, CLK_AVAIL, false);
1282
1283 /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
1284 *(u16 *) frame = cpu_to_le16((u16) msglen);
1285 *(((u16 *) frame) + 1) = cpu_to_le16(~msglen);
1286
1287 /* Software tag: channel, sequence number, data offset */
1288 swheader =
1289 ((SDPCM_CONTROL_CHANNEL << SDPCM_CHANNEL_SHIFT) &
1290 SDPCM_CHANNEL_MASK)
1291 | bus->tx_seq | ((doff << SDPCM_DOFFSET_SHIFT) &
1292 SDPCM_DOFFSET_MASK);
1293 put_unaligned_le32(swheader, frame + SDPCM_FRAMETAG_LEN);
1294 put_unaligned_le32(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
1295
1296 if (!DATAOK(bus)) {
1297 DHD_INFO(("%s: No bus credit bus->tx_max %d, bus->tx_seq %d\n",
1298 __func__, bus->tx_max, bus->tx_seq));
1299 bus->ctrl_frame_stat = true;
1300 /* Send from dpc */
1301 bus->ctrl_frame_buf = frame;
1302 bus->ctrl_frame_len = len;
1303
1304 dhd_wait_for_event(bus->dhd, &bus->ctrl_frame_stat);
1305
1306 if (bus->ctrl_frame_stat == false) {
1307 DHD_INFO(("%s: ctrl_frame_stat == false\n", __func__));
1308 ret = 0;
1309 } else {
1310 DHD_INFO(("%s: ctrl_frame_stat == true\n", __func__));
1311 ret = -1;
1312 }
1313 }
1314
1315 if (ret == -1) {
1316 #ifdef DHD_DEBUG
1317 if (DHD_BYTES_ON() && DHD_CTL_ON())
1318 prhex("Tx Frame", frame, len);
1319 else if (DHD_HDRS_ON())
1320 prhex("TxHdr", frame, min_t(u16, len, 16));
1321 #endif
1322
1323 do {
1324 bus->ctrl_frame_stat = false;
1325 ret =
1326 dhd_bcmsdh_send_buf(bus, bcmsdh_cur_sbwad(sdh),
1327 SDIO_FUNC_2, F2SYNC, frame, len,
1328 NULL, NULL, NULL);
1329
1330 ASSERT(ret != BCME_PENDING);
1331
1332 if (ret < 0) {
1333 /* On failure, abort the command and
1334 terminate the frame */
1335 DHD_INFO(("%s: sdio error %d, abort command and terminate frame.\n",
1336 __func__, ret));
1337 bus->tx_sderrs++;
1338
1339 bcmsdh_abort(sdh, SDIO_FUNC_2);
1340
1341 bcmsdh_cfg_write(sdh, SDIO_FUNC_1,
1342 SBSDIO_FUNC1_FRAMECTRL,
1343 SFC_WF_TERM, NULL);
1344 bus->f1regdata++;
1345
1346 for (i = 0; i < 3; i++) {
1347 u8 hi, lo;
1348 hi = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
1349 SBSDIO_FUNC1_WFRAMEBCHI,
1350 NULL);
1351 lo = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
1352 SBSDIO_FUNC1_WFRAMEBCLO,
1353 NULL);
1354 bus->f1regdata += 2;
1355 if ((hi == 0) && (lo == 0))
1356 break;
1357 }
1358
1359 }
1360 if (ret == 0) {
1361 bus->tx_seq =
1362 (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
1363 }
1364 } while ((ret < 0) && retries++ < TXRETRIES);
1365 }
1366
1367 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
1368 bus->activity = false;
1369 dhdsdio_clkctl(bus, CLK_NONE, true);
1370 }
1371
1372 dhd_os_sdunlock(bus->dhd);
1373
1374 if (ret)
1375 bus->dhd->tx_ctlerrs++;
1376 else
1377 bus->dhd->tx_ctlpkts++;
1378
1379 return ret ? -EIO : 0;
1380 }
1381
1382 int dhd_bus_rxctl(struct dhd_bus *bus, unsigned char *msg, uint msglen)
1383 {
1384 int timeleft;
1385 uint rxlen = 0;
1386 bool pending;
1387
1388 DHD_TRACE(("%s: Enter\n", __func__));
1389
1390 if (bus->dhd->dongle_reset)
1391 return -EIO;
1392
1393 /* Wait until control frame is available */
1394 timeleft = dhd_os_ioctl_resp_wait(bus->dhd, &bus->rxlen, &pending);
1395
1396 dhd_os_sdlock(bus->dhd);
1397 rxlen = bus->rxlen;
1398 memcpy(msg, bus->rxctl, min(msglen, rxlen));
1399 bus->rxlen = 0;
1400 dhd_os_sdunlock(bus->dhd);
1401
1402 if (rxlen) {
1403 DHD_CTL(("%s: resumed on rxctl frame, got %d expected %d\n",
1404 __func__, rxlen, msglen));
1405 } else if (timeleft == 0) {
1406 DHD_ERROR(("%s: resumed on timeout\n", __func__));
1407 #ifdef DHD_DEBUG
1408 dhd_os_sdlock(bus->dhd);
1409 dhdsdio_checkdied(bus, NULL, 0);
1410 dhd_os_sdunlock(bus->dhd);
1411 #endif /* DHD_DEBUG */
1412 } else if (pending == true) {
1413 DHD_CTL(("%s: cancelled\n", __func__));
1414 return -ERESTARTSYS;
1415 } else {
1416 DHD_CTL(("%s: resumed for unknown reason?\n", __func__));
1417 #ifdef DHD_DEBUG
1418 dhd_os_sdlock(bus->dhd);
1419 dhdsdio_checkdied(bus, NULL, 0);
1420 dhd_os_sdunlock(bus->dhd);
1421 #endif /* DHD_DEBUG */
1422 }
1423
1424 if (rxlen)
1425 bus->dhd->rx_ctlpkts++;
1426 else
1427 bus->dhd->rx_ctlerrs++;
1428
1429 return rxlen ? (int)rxlen : -ETIMEDOUT;
1430 }
1431
1432 /* IOVar table */
1433 enum {
1434 IOV_INTR = 1,
1435 IOV_POLLRATE,
1436 IOV_SDREG,
1437 IOV_SBREG,
1438 IOV_SDCIS,
1439 IOV_MEMBYTES,
1440 IOV_MEMSIZE,
1441 #ifdef DHD_DEBUG
1442 IOV_CHECKDIED,
1443 #endif
1444 IOV_DOWNLOAD,
1445 IOV_FORCEEVEN,
1446 IOV_SDIOD_DRIVE,
1447 IOV_READAHEAD,
1448 IOV_SDRXCHAIN,
1449 IOV_ALIGNCTL,
1450 IOV_SDALIGN,
1451 IOV_DEVRESET,
1452 IOV_CPU,
1453 #ifdef SDTEST
1454 IOV_PKTGEN,
1455 IOV_EXTLOOP,
1456 #endif /* SDTEST */
1457 IOV_SPROM,
1458 IOV_TXBOUND,
1459 IOV_RXBOUND,
1460 IOV_TXMINMAX,
1461 IOV_IDLETIME,
1462 IOV_IDLECLOCK,
1463 IOV_SD1IDLE,
1464 IOV_SLEEP,
1465 IOV_VARS
1466 };
1467
1468 const bcm_iovar_t dhdsdio_iovars[] = {
1469 {"intr", IOV_INTR, 0, IOVT_BOOL, 0},
1470 {"sleep", IOV_SLEEP, 0, IOVT_BOOL, 0},
1471 {"pollrate", IOV_POLLRATE, 0, IOVT_UINT32, 0},
1472 {"idletime", IOV_IDLETIME, 0, IOVT_INT32, 0},
1473 {"idleclock", IOV_IDLECLOCK, 0, IOVT_INT32, 0},
1474 {"sd1idle", IOV_SD1IDLE, 0, IOVT_BOOL, 0},
1475 {"membytes", IOV_MEMBYTES, 0, IOVT_BUFFER, 2 * sizeof(int)},
1476 {"memsize", IOV_MEMSIZE, 0, IOVT_UINT32, 0},
1477 {"download", IOV_DOWNLOAD, 0, IOVT_BOOL, 0},
1478 {"vars", IOV_VARS, 0, IOVT_BUFFER, 0},
1479 {"sdiod_drive", IOV_SDIOD_DRIVE, 0, IOVT_UINT32, 0},
1480 {"readahead", IOV_READAHEAD, 0, IOVT_BOOL, 0},
1481 {"sdrxchain", IOV_SDRXCHAIN, 0, IOVT_BOOL, 0},
1482 {"alignctl", IOV_ALIGNCTL, 0, IOVT_BOOL, 0},
1483 {"sdalign", IOV_SDALIGN, 0, IOVT_BOOL, 0},
1484 {"devreset", IOV_DEVRESET, 0, IOVT_BOOL, 0},
1485 #ifdef DHD_DEBUG
1486 {"sdreg", IOV_SDREG, 0, IOVT_BUFFER, sizeof(sdreg_t)}
1487 ,
1488 {"sbreg", IOV_SBREG, 0, IOVT_BUFFER, sizeof(sdreg_t)}
1489 ,
1490 {"sd_cis", IOV_SDCIS, 0, IOVT_BUFFER, DHD_IOCTL_MAXLEN}
1491 ,
1492 {"forcealign", IOV_FORCEEVEN, 0, IOVT_BOOL, 0}
1493 ,
1494 {"txbound", IOV_TXBOUND, 0, IOVT_UINT32, 0}
1495 ,
1496 {"rxbound", IOV_RXBOUND, 0, IOVT_UINT32, 0}
1497 ,
1498 {"txminmax", IOV_TXMINMAX, 0, IOVT_UINT32, 0}
1499 ,
1500 {"cpu", IOV_CPU, 0, IOVT_BOOL, 0}
1501 ,
1502 #ifdef DHD_DEBUG
1503 {"checkdied", IOV_CHECKDIED, 0, IOVT_BUFFER, 0}
1504 ,
1505 #endif /* DHD_DEBUG */
1506 #endif /* DHD_DEBUG */
1507 #ifdef SDTEST
1508 {"extloop", IOV_EXTLOOP, 0, IOVT_BOOL, 0}
1509 ,
1510 {"pktgen", IOV_PKTGEN, 0, IOVT_BUFFER, sizeof(dhd_pktgen_t)}
1511 ,
1512 #endif /* SDTEST */
1513
1514 {NULL, 0, 0, 0, 0}
1515 };
1516
1517 static void
1518 dhd_dump_pct(struct bcmstrbuf *strbuf, char *desc, uint num, uint div)
1519 {
1520 uint q1, q2;
1521
1522 if (!div) {
1523 bcm_bprintf(strbuf, "%s N/A", desc);
1524 } else {
1525 q1 = num / div;
1526 q2 = (100 * (num - (q1 * div))) / div;
1527 bcm_bprintf(strbuf, "%s %d.%02d", desc, q1, q2);
1528 }
1529 }
1530
1531 void dhd_bus_dump(dhd_pub_t *dhdp, struct bcmstrbuf *strbuf)
1532 {
1533 dhd_bus_t *bus = dhdp->bus;
1534
1535 bcm_bprintf(strbuf, "Bus SDIO structure:\n");
1536 bcm_bprintf(strbuf,
1537 "hostintmask 0x%08x intstatus 0x%08x sdpcm_ver %d\n",
1538 bus->hostintmask, bus->intstatus, bus->sdpcm_ver);
1539 bcm_bprintf(strbuf,
1540 "fcstate %d qlen %d tx_seq %d, max %d, rxskip %d rxlen %d rx_seq %d\n",
1541 bus->fcstate, pktq_len(&bus->txq), bus->tx_seq, bus->tx_max,
1542 bus->rxskip, bus->rxlen, bus->rx_seq);
1543 bcm_bprintf(strbuf, "intr %d intrcount %d lastintrs %d spurious %d\n",
1544 bus->intr, bus->intrcount, bus->lastintrs, bus->spurious);
1545 bcm_bprintf(strbuf, "pollrate %d pollcnt %d regfails %d\n",
1546 bus->pollrate, bus->pollcnt, bus->regfails);
1547
1548 bcm_bprintf(strbuf, "\nAdditional counters:\n");
1549 bcm_bprintf(strbuf,
1550 "tx_sderrs %d fcqueued %d rxrtx %d rx_toolong %d rxc_errors %d\n",
1551 bus->tx_sderrs, bus->fcqueued, bus->rxrtx, bus->rx_toolong,
1552 bus->rxc_errors);
1553 bcm_bprintf(strbuf, "rx_hdrfail %d badhdr %d badseq %d\n",
1554 bus->rx_hdrfail, bus->rx_badhdr, bus->rx_badseq);
1555 bcm_bprintf(strbuf, "fc_rcvd %d, fc_xoff %d, fc_xon %d\n", bus->fc_rcvd,
1556 bus->fc_xoff, bus->fc_xon);
1557 bcm_bprintf(strbuf, "rxglomfail %d, rxglomframes %d, rxglompkts %d\n",
1558 bus->rxglomfail, bus->rxglomframes, bus->rxglompkts);
1559 bcm_bprintf(strbuf, "f2rx (hdrs/data) %d (%d/%d), f2tx %d f1regs %d\n",
1560 (bus->f2rxhdrs + bus->f2rxdata), bus->f2rxhdrs,
1561 bus->f2rxdata, bus->f2txdata, bus->f1regdata);
1562 {
1563 dhd_dump_pct(strbuf, "\nRx: pkts/f2rd", bus->dhd->rx_packets,
1564 (bus->f2rxhdrs + bus->f2rxdata));
1565 dhd_dump_pct(strbuf, ", pkts/f1sd", bus->dhd->rx_packets,
1566 bus->f1regdata);
1567 dhd_dump_pct(strbuf, ", pkts/sd", bus->dhd->rx_packets,
1568 (bus->f2rxhdrs + bus->f2rxdata + bus->f1regdata));
1569 dhd_dump_pct(strbuf, ", pkts/int", bus->dhd->rx_packets,
1570 bus->intrcount);
1571 bcm_bprintf(strbuf, "\n");
1572
1573 dhd_dump_pct(strbuf, "Rx: glom pct", (100 * bus->rxglompkts),
1574 bus->dhd->rx_packets);
1575 dhd_dump_pct(strbuf, ", pkts/glom", bus->rxglompkts,
1576 bus->rxglomframes);
1577 bcm_bprintf(strbuf, "\n");
1578
1579 dhd_dump_pct(strbuf, "Tx: pkts/f2wr", bus->dhd->tx_packets,
1580 bus->f2txdata);
1581 dhd_dump_pct(strbuf, ", pkts/f1sd", bus->dhd->tx_packets,
1582 bus->f1regdata);
1583 dhd_dump_pct(strbuf, ", pkts/sd", bus->dhd->tx_packets,
1584 (bus->f2txdata + bus->f1regdata));
1585 dhd_dump_pct(strbuf, ", pkts/int", bus->dhd->tx_packets,
1586 bus->intrcount);
1587 bcm_bprintf(strbuf, "\n");
1588
1589 dhd_dump_pct(strbuf, "Total: pkts/f2rw",
1590 (bus->dhd->tx_packets + bus->dhd->rx_packets),
1591 (bus->f2txdata + bus->f2rxhdrs + bus->f2rxdata));
1592 dhd_dump_pct(strbuf, ", pkts/f1sd",
1593 (bus->dhd->tx_packets + bus->dhd->rx_packets),
1594 bus->f1regdata);
1595 dhd_dump_pct(strbuf, ", pkts/sd",
1596 (bus->dhd->tx_packets + bus->dhd->rx_packets),
1597 (bus->f2txdata + bus->f2rxhdrs + bus->f2rxdata +
1598 bus->f1regdata));
1599 dhd_dump_pct(strbuf, ", pkts/int",
1600 (bus->dhd->tx_packets + bus->dhd->rx_packets),
1601 bus->intrcount);
1602 bcm_bprintf(strbuf, "\n\n");
1603 }
1604
1605 #ifdef SDTEST
1606 if (bus->pktgen_count) {
1607 bcm_bprintf(strbuf, "pktgen config and count:\n");
1608 bcm_bprintf(strbuf,
1609 "freq %d count %d print %d total %d min %d len %d\n",
1610 bus->pktgen_freq, bus->pktgen_count,
1611 bus->pktgen_print, bus->pktgen_total,
1612 bus->pktgen_minlen, bus->pktgen_maxlen);
1613 bcm_bprintf(strbuf, "send attempts %d rcvd %d fail %d\n",
1614 bus->pktgen_sent, bus->pktgen_rcvd,
1615 bus->pktgen_fail);
1616 }
1617 #endif /* SDTEST */
1618 #ifdef DHD_DEBUG
1619 bcm_bprintf(strbuf, "dpc_sched %d host interrupt%spending\n",
1620 bus->dpc_sched,
1621 (bcmsdh_intr_pending(bus->sdh) ? " " : " not "));
1622 bcm_bprintf(strbuf, "blocksize %d roundup %d\n", bus->blocksize,
1623 bus->roundup);
1624 #endif /* DHD_DEBUG */
1625 bcm_bprintf(strbuf,
1626 "clkstate %d activity %d idletime %d idlecount %d sleeping %d\n",
1627 bus->clkstate, bus->activity, bus->idletime, bus->idlecount,
1628 bus->sleeping);
1629 }
1630
1631 void dhd_bus_clearcounts(dhd_pub_t *dhdp)
1632 {
1633 dhd_bus_t *bus = (dhd_bus_t *) dhdp->bus;
1634
1635 bus->intrcount = bus->lastintrs = bus->spurious = bus->regfails = 0;
1636 bus->rxrtx = bus->rx_toolong = bus->rxc_errors = 0;
1637 bus->rx_hdrfail = bus->rx_badhdr = bus->rx_badseq = 0;
1638 bus->tx_sderrs = bus->fc_rcvd = bus->fc_xoff = bus->fc_xon = 0;
1639 bus->rxglomfail = bus->rxglomframes = bus->rxglompkts = 0;
1640 bus->f2rxhdrs = bus->f2rxdata = bus->f2txdata = bus->f1regdata = 0;
1641 }
1642
1643 #ifdef SDTEST
1644 static int dhdsdio_pktgen_get(dhd_bus_t *bus, u8 *arg)
1645 {
1646 dhd_pktgen_t pktgen;
1647
1648 pktgen.version = DHD_PKTGEN_VERSION;
1649 pktgen.freq = bus->pktgen_freq;
1650 pktgen.count = bus->pktgen_count;
1651 pktgen.print = bus->pktgen_print;
1652 pktgen.total = bus->pktgen_total;
1653 pktgen.minlen = bus->pktgen_minlen;
1654 pktgen.maxlen = bus->pktgen_maxlen;
1655 pktgen.numsent = bus->pktgen_sent;
1656 pktgen.numrcvd = bus->pktgen_rcvd;
1657 pktgen.numfail = bus->pktgen_fail;
1658 pktgen.mode = bus->pktgen_mode;
1659 pktgen.stop = bus->pktgen_stop;
1660
1661 memcpy(arg, &pktgen, sizeof(pktgen));
1662
1663 return 0;
1664 }
1665
1666 static int dhdsdio_pktgen_set(dhd_bus_t *bus, u8 *arg)
1667 {
1668 dhd_pktgen_t pktgen;
1669 uint oldcnt, oldmode;
1670
1671 memcpy(&pktgen, arg, sizeof(pktgen));
1672 if (pktgen.version != DHD_PKTGEN_VERSION)
1673 return BCME_BADARG;
1674
1675 oldcnt = bus->pktgen_count;
1676 oldmode = bus->pktgen_mode;
1677
1678 bus->pktgen_freq = pktgen.freq;
1679 bus->pktgen_count = pktgen.count;
1680 bus->pktgen_print = pktgen.print;
1681 bus->pktgen_total = pktgen.total;
1682 bus->pktgen_minlen = pktgen.minlen;
1683 bus->pktgen_maxlen = pktgen.maxlen;
1684 bus->pktgen_mode = pktgen.mode;
1685 bus->pktgen_stop = pktgen.stop;
1686
1687 bus->pktgen_tick = bus->pktgen_ptick = 0;
1688 bus->pktgen_len = max(bus->pktgen_len, bus->pktgen_minlen);
1689 bus->pktgen_len = min(bus->pktgen_len, bus->pktgen_maxlen);
1690
1691 /* Clear counts for a new pktgen (mode change, or was stopped) */
1692 if (bus->pktgen_count && (!oldcnt || oldmode != bus->pktgen_mode))
1693 bus->pktgen_sent = bus->pktgen_rcvd = bus->pktgen_fail = 0;
1694
1695 return 0;
1696 }
1697 #endif /* SDTEST */
1698
1699 static int
1700 dhdsdio_membytes(dhd_bus_t *bus, bool write, u32 address, u8 *data,
1701 uint size)
1702 {
1703 int bcmerror = 0;
1704 u32 sdaddr;
1705 uint dsize;
1706
1707 /* Determine initial transfer parameters */
1708 sdaddr = address & SBSDIO_SB_OFT_ADDR_MASK;
1709 if ((sdaddr + size) & SBSDIO_SBWINDOW_MASK)
1710 dsize = (SBSDIO_SB_OFT_ADDR_LIMIT - sdaddr);
1711 else
1712 dsize = size;
1713
1714 /* Set the backplane window to include the start address */
1715 bcmerror = dhdsdio_set_siaddr_window(bus, address);
1716 if (bcmerror) {
1717 DHD_ERROR(("%s: window change failed\n", __func__));
1718 goto xfer_done;
1719 }
1720
1721 /* Do the transfer(s) */
1722 while (size) {
1723 DHD_INFO(("%s: %s %d bytes at offset 0x%08x in window 0x%08x\n",
1724 __func__, (write ? "write" : "read"), dsize,
1725 sdaddr, (address & SBSDIO_SBWINDOW_MASK)));
1726 bcmerror =
1727 bcmsdh_rwdata(bus->sdh, write, sdaddr, data, dsize);
1728 if (bcmerror) {
1729 DHD_ERROR(("%s: membytes transfer failed\n", __func__));
1730 break;
1731 }
1732
1733 /* Adjust for next transfer (if any) */
1734 size -= dsize;
1735 if (size) {
1736 data += dsize;
1737 address += dsize;
1738 bcmerror = dhdsdio_set_siaddr_window(bus, address);
1739 if (bcmerror) {
1740 DHD_ERROR(("%s: window change failed\n",
1741 __func__));
1742 break;
1743 }
1744 sdaddr = 0;
1745 dsize = min_t(uint, SBSDIO_SB_OFT_ADDR_LIMIT, size);
1746 }
1747 }
1748
1749 xfer_done:
1750 /* Return the window to backplane enumeration space for core access */
1751 if (dhdsdio_set_siaddr_window(bus, bcmsdh_cur_sbwad(bus->sdh))) {
1752 DHD_ERROR(("%s: FAILED to set window back to 0x%x\n",
1753 __func__, bcmsdh_cur_sbwad(bus->sdh)));
1754 }
1755
1756 return bcmerror;
1757 }
1758
1759 #ifdef DHD_DEBUG
1760 static int dhdsdio_readshared(dhd_bus_t *bus, sdpcm_shared_t *sh)
1761 {
1762 u32 addr;
1763 int rv;
1764
1765 /* Read last word in memory to determine address of
1766 sdpcm_shared structure */
1767 rv = dhdsdio_membytes(bus, false, bus->ramsize - 4, (u8 *)&addr, 4);
1768 if (rv < 0)
1769 return rv;
1770
1771 addr = le32_to_cpu(addr);
1772
1773 DHD_INFO(("sdpcm_shared address 0x%08X\n", addr));
1774
1775 /*
1776 * Check if addr is valid.
1777 * NVRAM length at the end of memory should have been overwritten.
1778 */
1779 if (addr == 0 || ((~addr >> 16) & 0xffff) == (addr & 0xffff)) {
1780 DHD_ERROR(("%s: address (0x%08x) of sdpcm_shared invalid\n",
1781 __func__, addr));
1782 return BCME_ERROR;
1783 }
1784
1785 /* Read hndrte_shared structure */
1786 rv = dhdsdio_membytes(bus, false, addr, (u8 *) sh,
1787 sizeof(sdpcm_shared_t));
1788 if (rv < 0)
1789 return rv;
1790
1791 /* Endianness */
1792 sh->flags = le32_to_cpu(sh->flags);
1793 sh->trap_addr = le32_to_cpu(sh->trap_addr);
1794 sh->assert_exp_addr = le32_to_cpu(sh->assert_exp_addr);
1795 sh->assert_file_addr = le32_to_cpu(sh->assert_file_addr);
1796 sh->assert_line = le32_to_cpu(sh->assert_line);
1797 sh->console_addr = le32_to_cpu(sh->console_addr);
1798 sh->msgtrace_addr = le32_to_cpu(sh->msgtrace_addr);
1799
1800 if ((sh->flags & SDPCM_SHARED_VERSION_MASK) != SDPCM_SHARED_VERSION) {
1801 DHD_ERROR(("%s: sdpcm_shared version %d in dhd "
1802 "is different than sdpcm_shared version %d in dongle\n",
1803 __func__, SDPCM_SHARED_VERSION,
1804 sh->flags & SDPCM_SHARED_VERSION_MASK));
1805 return BCME_ERROR;
1806 }
1807
1808 return BCME_OK;
1809 }
1810
1811 static int dhdsdio_checkdied(dhd_bus_t *bus, u8 *data, uint size)
1812 {
1813 int bcmerror = 0;
1814 uint msize = 512;
1815 char *mbuffer = NULL;
1816 uint maxstrlen = 256;
1817 char *str = NULL;
1818 trap_t tr;
1819 sdpcm_shared_t sdpcm_shared;
1820 struct bcmstrbuf strbuf;
1821
1822 DHD_TRACE(("%s: Enter\n", __func__));
1823
1824 if (data == NULL) {
1825 /*
1826 * Called after a rx ctrl timeout. "data" is NULL.
1827 * allocate memory to trace the trap or assert.
1828 */
1829 size = msize;
1830 mbuffer = data = kmalloc(msize, GFP_ATOMIC);
1831 if (mbuffer == NULL) {
1832 DHD_ERROR(("%s: kmalloc(%d) failed\n", __func__,
1833 msize));
1834 bcmerror = BCME_NOMEM;
1835 goto done;
1836 }
1837 }
1838
1839 str = kmalloc(maxstrlen, GFP_ATOMIC);
1840 if (str == NULL) {
1841 DHD_ERROR(("%s: kmalloc(%d) failed\n", __func__, maxstrlen));
1842 bcmerror = BCME_NOMEM;
1843 goto done;
1844 }
1845
1846 bcmerror = dhdsdio_readshared(bus, &sdpcm_shared);
1847 if (bcmerror < 0)
1848 goto done;
1849
1850 bcm_binit(&strbuf, data, size);
1851
1852 bcm_bprintf(&strbuf,
1853 "msgtrace address : 0x%08X\nconsole address : 0x%08X\n",
1854 sdpcm_shared.msgtrace_addr, sdpcm_shared.console_addr);
1855
1856 if ((sdpcm_shared.flags & SDPCM_SHARED_ASSERT_BUILT) == 0) {
1857 /* NOTE: Misspelled assert is intentional - DO NOT FIX.
1858 * (Avoids conflict with real asserts for programmatic
1859 * parsing of output.)
1860 */
1861 bcm_bprintf(&strbuf, "Assrt not built in dongle\n");
1862 }
1863
1864 if ((sdpcm_shared.flags & (SDPCM_SHARED_ASSERT | SDPCM_SHARED_TRAP)) ==
1865 0) {
1866 /* NOTE: Misspelled assert is intentional - DO NOT FIX.
1867 * (Avoids conflict with real asserts for programmatic
1868 * parsing of output.)
1869 */
1870 bcm_bprintf(&strbuf, "No trap%s in dongle",
1871 (sdpcm_shared.flags & SDPCM_SHARED_ASSERT_BUILT)
1872 ? "/assrt" : "");
1873 } else {
1874 if (sdpcm_shared.flags & SDPCM_SHARED_ASSERT) {
1875 /* Download assert */
1876 bcm_bprintf(&strbuf, "Dongle assert");
1877 if (sdpcm_shared.assert_exp_addr != 0) {
1878 str[0] = '\0';
1879 bcmerror = dhdsdio_membytes(bus, false,
1880 sdpcm_shared.assert_exp_addr,
1881 (u8 *) str, maxstrlen);
1882 if (bcmerror < 0)
1883 goto done;
1884
1885 str[maxstrlen - 1] = '\0';
1886 bcm_bprintf(&strbuf, " expr \"%s\"", str);
1887 }
1888
1889 if (sdpcm_shared.assert_file_addr != 0) {
1890 str[0] = '\0';
1891 bcmerror = dhdsdio_membytes(bus, false,
1892 sdpcm_shared.assert_file_addr,
1893 (u8 *) str, maxstrlen);
1894 if (bcmerror < 0)
1895 goto done;
1896
1897 str[maxstrlen - 1] = '\0';
1898 bcm_bprintf(&strbuf, " file \"%s\"", str);
1899 }
1900
1901 bcm_bprintf(&strbuf, " line %d ",
1902 sdpcm_shared.assert_line);
1903 }
1904
1905 if (sdpcm_shared.flags & SDPCM_SHARED_TRAP) {
1906 bcmerror = dhdsdio_membytes(bus, false,
1907 sdpcm_shared.trap_addr, (u8 *)&tr,
1908 sizeof(trap_t));
1909 if (bcmerror < 0)
1910 goto done;
1911
1912 bcm_bprintf(&strbuf,
1913 "Dongle trap type 0x%x @ epc 0x%x, cpsr 0x%x, spsr 0x%x, sp 0x%x,"
1914 "lp 0x%x, rpc 0x%x Trap offset 0x%x, "
1915 "r0 0x%x, r1 0x%x, r2 0x%x, r3 0x%x, r4 0x%x, r5 0x%x, r6 0x%x, r7 0x%x\n",
1916 tr.type, tr.epc, tr.cpsr, tr.spsr, tr.r13,
1917 tr.r14, tr.pc, sdpcm_shared.trap_addr,
1918 tr.r0, tr.r1, tr.r2, tr.r3, tr.r4, tr.r5,
1919 tr.r6, tr.r7);
1920 }
1921 }
1922
1923 if (sdpcm_shared.flags & (SDPCM_SHARED_ASSERT | SDPCM_SHARED_TRAP))
1924 DHD_ERROR(("%s: %s\n", __func__, strbuf.origbuf));
1925
1926 #ifdef DHD_DEBUG
1927 if (sdpcm_shared.flags & SDPCM_SHARED_TRAP) {
1928 /* Mem dump to a file on device */
1929 dhdsdio_mem_dump(bus);
1930 }
1931 #endif /* DHD_DEBUG */
1932
1933 done:
1934 if (mbuffer)
1935 kfree(mbuffer);
1936 if (str)
1937 kfree(str);
1938
1939 return bcmerror;
1940 }
1941
1942 static int dhdsdio_mem_dump(dhd_bus_t *bus)
1943 {
1944 int ret = 0;
1945 int size; /* Full mem size */
1946 int start = 0; /* Start address */
1947 int read_size = 0; /* Read size of each iteration */
1948 u8 *buf = NULL, *databuf = NULL;
1949
1950 /* Get full mem size */
1951 size = bus->ramsize;
1952 buf = kmalloc(size, GFP_ATOMIC);
1953 if (!buf) {
1954 DHD_ERROR(("%s: Out of memory (%d bytes)\n", __func__, size));
1955 return -1;
1956 }
1957
1958 /* Read mem content */
1959 printk(KERN_DEBUG "Dump dongle memory");
1960 databuf = buf;
1961 while (size) {
1962 read_size = min(MEMBLOCK, size);
1963 ret = dhdsdio_membytes(bus, false, start, databuf, read_size);
1964 if (ret) {
1965 DHD_ERROR(("%s: Error membytes %d\n", __func__, ret));
1966 if (buf)
1967 kfree(buf);
1968 return -1;
1969 }
1970 printk(".");
1971
1972 /* Decrement size and increment start address */
1973 size -= read_size;
1974 start += read_size;
1975 databuf += read_size;
1976 }
1977 printk(KERN_DEBUG "Done\n");
1978
1979 /* free buf before return !!! */
1980 if (write_to_file(bus->dhd, buf, bus->ramsize)) {
1981 DHD_ERROR(("%s: Error writing to files\n", __func__));
1982 return -1;
1983 }
1984
1985 /* buf free handled in write_to_file, not here */
1986 return 0;
1987 }
1988
1989 #define CONSOLE_LINE_MAX 192
1990
1991 static int dhdsdio_readconsole(dhd_bus_t *bus)
1992 {
1993 dhd_console_t *c = &bus->console;
1994 u8 line[CONSOLE_LINE_MAX], ch;
1995 u32 n, idx, addr;
1996 int rv;
1997
1998 /* Don't do anything until FWREADY updates console address */
1999 if (bus->console_addr == 0)
2000 return 0;
2001
2002 /* Read console log struct */
2003 addr = bus->console_addr + offsetof(hndrte_cons_t, log);
2004 rv = dhdsdio_membytes(bus, false, addr, (u8 *)&c->log,
2005 sizeof(c->log));
2006 if (rv < 0)
2007 return rv;
2008
2009 /* Allocate console buffer (one time only) */
2010 if (c->buf == NULL) {
2011 c->bufsize = le32_to_cpu(c->log.buf_size);
2012 c->buf = kmalloc(c->bufsize, GFP_ATOMIC);
2013 if (c->buf == NULL)
2014 return BCME_NOMEM;
2015 }
2016
2017 idx = le32_to_cpu(c->log.idx);
2018
2019 /* Protect against corrupt value */
2020 if (idx > c->bufsize)
2021 return BCME_ERROR;
2022
2023 /* Skip reading the console buffer if the index pointer
2024 has not moved */
2025 if (idx == c->last)
2026 return BCME_OK;
2027
2028 /* Read the console buffer */
2029 addr = le32_to_cpu(c->log.buf);
2030 rv = dhdsdio_membytes(bus, false, addr, c->buf, c->bufsize);
2031 if (rv < 0)
2032 return rv;
2033
2034 while (c->last != idx) {
2035 for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) {
2036 if (c->last == idx) {
2037 /* This would output a partial line.
2038 * Instead, back up
2039 * the buffer pointer and output this
2040 * line next time around.
2041 */
2042 if (c->last >= n)
2043 c->last -= n;
2044 else
2045 c->last = c->bufsize - n;
2046 goto break2;
2047 }
2048 ch = c->buf[c->last];
2049 c->last = (c->last + 1) % c->bufsize;
2050 if (ch == '\n')
2051 break;
2052 line[n] = ch;
2053 }
2054
2055 if (n > 0) {
2056 if (line[n - 1] == '\r')
2057 n--;
2058 line[n] = 0;
2059 printk(KERN_DEBUG "CONSOLE: %s\n", line);
2060 }
2061 }
2062 break2:
2063
2064 return BCME_OK;
2065 }
2066 #endif /* DHD_DEBUG */
2067
2068 int dhdsdio_downloadvars(dhd_bus_t *bus, void *arg, int len)
2069 {
2070 int bcmerror = BCME_OK;
2071
2072 DHD_TRACE(("%s: Enter\n", __func__));
2073
2074 /* Basic sanity checks */
2075 if (bus->dhd->up) {
2076 bcmerror = BCME_NOTDOWN;
2077 goto err;
2078 }
2079 if (!len) {
2080 bcmerror = BCME_BUFTOOSHORT;
2081 goto err;
2082 }
2083
2084 /* Free the old ones and replace with passed variables */
2085 if (bus->vars)
2086 kfree(bus->vars);
2087
2088 bus->vars = kmalloc(len, GFP_ATOMIC);
2089 bus->varsz = bus->vars ? len : 0;
2090 if (bus->vars == NULL) {
2091 bcmerror = BCME_NOMEM;
2092 goto err;
2093 }
2094
2095 /* Copy the passed variables, which should include the
2096 terminating double-null */
2097 memcpy(bus->vars, arg, bus->varsz);
2098 err:
2099 return bcmerror;
2100 }
2101
2102 static int
2103 dhdsdio_doiovar(dhd_bus_t *bus, const bcm_iovar_t *vi, u32 actionid,
2104 const char *name, void *params, int plen, void *arg, int len,
2105 int val_size)
2106 {
2107 int bcmerror = 0;
2108 s32 int_val = 0;
2109 bool bool_val = 0;
2110
2111 DHD_TRACE(("%s: Enter, action %d name %s params %p plen %d arg %p "
2112 "len %d val_size %d\n",
2113 __func__, actionid, name, params, plen, arg, len, val_size));
2114
2115 bcmerror = bcm_iovar_lencheck(vi, arg, len, IOV_ISSET(actionid));
2116 if (bcmerror != 0)
2117 goto exit;
2118
2119 if (plen >= (int)sizeof(int_val))
2120 memcpy(&int_val, params, sizeof(int_val));
2121
2122 bool_val = (int_val != 0) ? true : false;
2123
2124 /* Some ioctls use the bus */
2125 dhd_os_sdlock(bus->dhd);
2126
2127 /* Check if dongle is in reset. If so, only allow DEVRESET iovars */
2128 if (bus->dhd->dongle_reset && !(actionid == IOV_SVAL(IOV_DEVRESET) ||
2129 actionid == IOV_GVAL(IOV_DEVRESET))) {
2130 bcmerror = BCME_NOTREADY;
2131 goto exit;
2132 }
2133
2134 /* Handle sleep stuff before any clock mucking */
2135 if (vi->varid == IOV_SLEEP) {
2136 if (IOV_ISSET(actionid)) {
2137 bcmerror = dhdsdio_bussleep(bus, bool_val);
2138 } else {
2139 int_val = (s32) bus->sleeping;
2140 memcpy(arg, &int_val, val_size);
2141 }
2142 goto exit;
2143 }
2144
2145 /* Request clock to allow SDIO accesses */
2146 if (!bus->dhd->dongle_reset) {
2147 BUS_WAKE(bus);
2148 dhdsdio_clkctl(bus, CLK_AVAIL, false);
2149 }
2150
2151 switch (actionid) {
2152 case IOV_GVAL(IOV_INTR):
2153 int_val = (s32) bus->intr;
2154 memcpy(arg, &int_val, val_size);
2155 break;
2156
2157 case IOV_SVAL(IOV_INTR):
2158 bus->intr = bool_val;
2159 bus->intdis = false;
2160 if (bus->dhd->up) {
2161 if (bus->intr) {
2162 DHD_INTR(("%s: enable SDIO device interrupts\n",
2163 __func__));
2164 bcmsdh_intr_enable(bus->sdh);
2165 } else {
2166 DHD_INTR(("%s: disable SDIO interrupts\n",
2167 __func__));
2168 bcmsdh_intr_disable(bus->sdh);
2169 }
2170 }
2171 break;
2172
2173 case IOV_GVAL(IOV_POLLRATE):
2174 int_val = (s32) bus->pollrate;
2175 memcpy(arg, &int_val, val_size);
2176 break;
2177
2178 case IOV_SVAL(IOV_POLLRATE):
2179 bus->pollrate = (uint) int_val;
2180 bus->poll = (bus->pollrate != 0);
2181 break;
2182
2183 case IOV_GVAL(IOV_IDLETIME):
2184 int_val = bus->idletime;
2185 memcpy(arg, &int_val, val_size);
2186 break;
2187
2188 case IOV_SVAL(IOV_IDLETIME):
2189 if ((int_val < 0) && (int_val != DHD_IDLE_IMMEDIATE))
2190 bcmerror = BCME_BADARG;
2191 else
2192 bus->idletime = int_val;
2193 break;
2194
2195 case IOV_GVAL(IOV_IDLECLOCK):
2196 int_val = (s32) bus->idleclock;
2197 memcpy(arg, &int_val, val_size);
2198 break;
2199
2200 case IOV_SVAL(IOV_IDLECLOCK):
2201 bus->idleclock = int_val;
2202 break;
2203
2204 case IOV_GVAL(IOV_SD1IDLE):
2205 int_val = (s32) sd1idle;
2206 memcpy(arg, &int_val, val_size);
2207 break;
2208
2209 case IOV_SVAL(IOV_SD1IDLE):
2210 sd1idle = bool_val;
2211 break;
2212
2213 case IOV_SVAL(IOV_MEMBYTES):
2214 case IOV_GVAL(IOV_MEMBYTES):
2215 {
2216 u32 address;
2217 uint size, dsize;
2218 u8 *data;
2219
2220 bool set = (actionid == IOV_SVAL(IOV_MEMBYTES));
2221
2222 ASSERT(plen >= 2 * sizeof(int));
2223
2224 address = (u32) int_val;
2225 memcpy(&int_val, (char *)params + sizeof(int_val),
2226 sizeof(int_val));
2227 size = (uint) int_val;
2228
2229 /* Do some validation */
2230 dsize = set ? plen - (2 * sizeof(int)) : len;
2231 if (dsize < size) {
2232 DHD_ERROR(("%s: error on %s membytes, addr "
2233 "0x%08x size %d dsize %d\n",
2234 __func__, (set ? "set" : "get"),
2235 address, size, dsize));
2236 bcmerror = BCME_BADARG;
2237 break;
2238 }
2239
2240 DHD_INFO(("%s: Request to %s %d bytes at address "
2241 "0x%08x\n",
2242 __func__, (set ? "write" : "read"), size, address));
2243
2244 /* If we know about SOCRAM, check for a fit */
2245 if ((bus->orig_ramsize) &&
2246 ((address > bus->orig_ramsize)
2247 || (address + size > bus->orig_ramsize))) {
2248 DHD_ERROR(("%s: ramsize 0x%08x doesn't have %d "
2249 "bytes at 0x%08x\n",
2250 __func__, bus->orig_ramsize, size, address));
2251 bcmerror = BCME_BADARG;
2252 break;
2253 }
2254
2255 /* Generate the actual data pointer */
2256 data =
2257 set ? (u8 *) params +
2258 2 * sizeof(int) : (u8 *) arg;
2259
2260 /* Call to do the transfer */
2261 bcmerror =
2262 dhdsdio_membytes(bus, set, address, data, size);
2263
2264 break;
2265 }
2266
2267 case IOV_GVAL(IOV_MEMSIZE):
2268 int_val = (s32) bus->ramsize;
2269 memcpy(arg, &int_val, val_size);
2270 break;
2271
2272 case IOV_GVAL(IOV_SDIOD_DRIVE):
2273 int_val = (s32) dhd_sdiod_drive_strength;
2274 memcpy(arg, &int_val, val_size);
2275 break;
2276
2277 case IOV_SVAL(IOV_SDIOD_DRIVE):
2278 dhd_sdiod_drive_strength = int_val;
2279 si_sdiod_drive_strength_init(bus->sih,
2280 dhd_sdiod_drive_strength);
2281 break;
2282
2283 case IOV_SVAL(IOV_DOWNLOAD):
2284 bcmerror = dhdsdio_download_state(bus, bool_val);
2285 break;
2286
2287 case IOV_SVAL(IOV_VARS):
2288 bcmerror = dhdsdio_downloadvars(bus, arg, len);
2289 break;
2290
2291 case IOV_GVAL(IOV_READAHEAD):
2292 int_val = (s32) dhd_readahead;
2293 memcpy(arg, &int_val, val_size);
2294 break;
2295
2296 case IOV_SVAL(IOV_READAHEAD):
2297 if (bool_val && !dhd_readahead)
2298 bus->nextlen = 0;
2299 dhd_readahead = bool_val;
2300 break;
2301
2302 case IOV_GVAL(IOV_SDRXCHAIN):
2303 int_val = (s32) bus->use_rxchain;
2304 memcpy(arg, &int_val, val_size);
2305 break;
2306
2307 case IOV_SVAL(IOV_SDRXCHAIN):
2308 if (bool_val && !bus->sd_rxchain)
2309 bcmerror = BCME_UNSUPPORTED;
2310 else
2311 bus->use_rxchain = bool_val;
2312 break;
2313 case IOV_GVAL(IOV_ALIGNCTL):
2314 int_val = (s32) dhd_alignctl;
2315 memcpy(arg, &int_val, val_size);
2316 break;
2317
2318 case IOV_SVAL(IOV_ALIGNCTL):
2319 dhd_alignctl = bool_val;
2320 break;
2321
2322 case IOV_GVAL(IOV_SDALIGN):
2323 int_val = DHD_SDALIGN;
2324 memcpy(arg, &int_val, val_size);
2325 break;
2326
2327 #ifdef DHD_DEBUG
2328 case IOV_GVAL(IOV_VARS):
2329 if (bus->varsz < (uint) len)
2330 memcpy(arg, bus->vars, bus->varsz);
2331 else
2332 bcmerror = BCME_BUFTOOSHORT;
2333 break;
2334 #endif /* DHD_DEBUG */
2335
2336 #ifdef DHD_DEBUG
2337 case IOV_GVAL(IOV_SDREG):
2338 {
2339 sdreg_t *sd_ptr;
2340 u32 addr, size;
2341
2342 sd_ptr = (sdreg_t *) params;
2343
2344 addr = (unsigned long)bus->regs + sd_ptr->offset;
2345 size = sd_ptr->func;
2346 int_val = (s32) bcmsdh_reg_read(bus->sdh, addr, size);
2347 if (bcmsdh_regfail(bus->sdh))
2348 bcmerror = BCME_SDIO_ERROR;
2349 memcpy(arg, &int_val, sizeof(s32));
2350 break;
2351 }
2352
2353 case IOV_SVAL(IOV_SDREG):
2354 {
2355 sdreg_t *sd_ptr;
2356 u32 addr, size;
2357
2358 sd_ptr = (sdreg_t *) params;
2359
2360 addr = (unsigned long)bus->regs + sd_ptr->offset;
2361 size = sd_ptr->func;
2362 bcmsdh_reg_write(bus->sdh, addr, size, sd_ptr->value);
2363 if (bcmsdh_regfail(bus->sdh))
2364 bcmerror = BCME_SDIO_ERROR;
2365 break;
2366 }
2367
2368 /* Same as above, but offset is not backplane
2369 (not SDIO core) */
2370 case IOV_GVAL(IOV_SBREG):
2371 {
2372 sdreg_t sdreg;
2373 u32 addr, size;
2374
2375 memcpy(&sdreg, params, sizeof(sdreg));
2376
2377 addr = SI_ENUM_BASE + sdreg.offset;
2378 size = sdreg.func;
2379 int_val = (s32) bcmsdh_reg_read(bus->sdh, addr, size);
2380 if (bcmsdh_regfail(bus->sdh))
2381 bcmerror = BCME_SDIO_ERROR;
2382 memcpy(arg, &int_val, sizeof(s32));
2383 break;
2384 }
2385
2386 case IOV_SVAL(IOV_SBREG):
2387 {
2388 sdreg_t sdreg;
2389 u32 addr, size;
2390
2391 memcpy(&sdreg, params, sizeof(sdreg));
2392
2393 addr = SI_ENUM_BASE + sdreg.offset;
2394 size = sdreg.func;
2395 bcmsdh_reg_write(bus->sdh, addr, size, sdreg.value);
2396 if (bcmsdh_regfail(bus->sdh))
2397 bcmerror = BCME_SDIO_ERROR;
2398 break;
2399 }
2400
2401 case IOV_GVAL(IOV_SDCIS):
2402 {
2403 *(char *)arg = 0;
2404
2405 strcat(arg, "\nFunc 0\n");
2406 bcmsdh_cis_read(bus->sdh, 0x10,
2407 (u8 *) arg + strlen(arg),
2408 SBSDIO_CIS_SIZE_LIMIT);
2409 strcat(arg, "\nFunc 1\n");
2410 bcmsdh_cis_read(bus->sdh, 0x11,
2411 (u8 *) arg + strlen(arg),
2412 SBSDIO_CIS_SIZE_LIMIT);
2413 strcat(arg, "\nFunc 2\n");
2414 bcmsdh_cis_read(bus->sdh, 0x12,
2415 (u8 *) arg + strlen(arg),
2416 SBSDIO_CIS_SIZE_LIMIT);
2417 break;
2418 }
2419
2420 case IOV_GVAL(IOV_FORCEEVEN):
2421 int_val = (s32) forcealign;
2422 memcpy(arg, &int_val, val_size);
2423 break;
2424
2425 case IOV_SVAL(IOV_FORCEEVEN):
2426 forcealign = bool_val;
2427 break;
2428
2429 case IOV_GVAL(IOV_TXBOUND):
2430 int_val = (s32) dhd_txbound;
2431 memcpy(arg, &int_val, val_size);
2432 break;
2433
2434 case IOV_SVAL(IOV_TXBOUND):
2435 dhd_txbound = (uint) int_val;
2436 break;
2437
2438 case IOV_GVAL(IOV_RXBOUND):
2439 int_val = (s32) dhd_rxbound;
2440 memcpy(arg, &int_val, val_size);
2441 break;
2442
2443 case IOV_SVAL(IOV_RXBOUND):
2444 dhd_rxbound = (uint) int_val;
2445 break;
2446
2447 case IOV_GVAL(IOV_TXMINMAX):
2448 int_val = (s32) dhd_txminmax;
2449 memcpy(arg, &int_val, val_size);
2450 break;
2451
2452 case IOV_SVAL(IOV_TXMINMAX):
2453 dhd_txminmax = (uint) int_val;
2454 break;
2455 #endif /* DHD_DEBUG */
2456
2457 #ifdef SDTEST
2458 case IOV_GVAL(IOV_EXTLOOP):
2459 int_val = (s32) bus->ext_loop;
2460 memcpy(arg, &int_val, val_size);
2461 break;
2462
2463 case IOV_SVAL(IOV_EXTLOOP):
2464 bus->ext_loop = bool_val;
2465 break;
2466
2467 case IOV_GVAL(IOV_PKTGEN):
2468 bcmerror = dhdsdio_pktgen_get(bus, arg);
2469 break;
2470
2471 case IOV_SVAL(IOV_PKTGEN):
2472 bcmerror = dhdsdio_pktgen_set(bus, arg);
2473 break;
2474 #endif /* SDTEST */
2475
2476 case IOV_SVAL(IOV_DEVRESET):
2477 DHD_TRACE(("%s: Called set IOV_DEVRESET=%d dongle_reset=%d "
2478 "busstate=%d\n",
2479 __func__, bool_val, bus->dhd->dongle_reset,
2480 bus->dhd->busstate));
2481
2482 dhd_bus_devreset(bus->dhd, (u8) bool_val);
2483
2484 break;
2485
2486 case IOV_GVAL(IOV_DEVRESET):
2487 DHD_TRACE(("%s: Called get IOV_DEVRESET\n", __func__));
2488
2489 /* Get its status */
2490 int_val = (bool) bus->dhd->dongle_reset;
2491 memcpy(arg, &int_val, val_size);
2492
2493 break;
2494
2495 default:
2496 bcmerror = BCME_UNSUPPORTED;
2497 break;
2498 }
2499
2500 exit:
2501 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
2502 bus->activity = false;
2503 dhdsdio_clkctl(bus, CLK_NONE, true);
2504 }
2505
2506 dhd_os_sdunlock(bus->dhd);
2507
2508 if (actionid == IOV_SVAL(IOV_DEVRESET) && bool_val == false)
2509 dhd_preinit_ioctls((dhd_pub_t *) bus->dhd);
2510
2511 return bcmerror;
2512 }
2513
2514 static int dhdsdio_write_vars(dhd_bus_t *bus)
2515 {
2516 int bcmerror = 0;
2517 u32 varsize;
2518 u32 varaddr;
2519 u8 *vbuffer;
2520 u32 varsizew;
2521 #ifdef DHD_DEBUG
2522 char *nvram_ularray;
2523 #endif /* DHD_DEBUG */
2524
2525 /* Even if there are no vars are to be written, we still
2526 need to set the ramsize. */
2527 varsize = bus->varsz ? roundup(bus->varsz, 4) : 0;
2528 varaddr = (bus->ramsize - 4) - varsize;
2529
2530 if (bus->vars) {
2531 vbuffer = kzalloc(varsize, GFP_ATOMIC);
2532 if (!vbuffer)
2533 return BCME_NOMEM;
2534
2535 memcpy(vbuffer, bus->vars, bus->varsz);
2536
2537 /* Write the vars list */
2538 bcmerror =
2539 dhdsdio_membytes(bus, true, varaddr, vbuffer, varsize);
2540 #ifdef DHD_DEBUG
2541 /* Verify NVRAM bytes */
2542 DHD_INFO(("Compare NVRAM dl & ul; varsize=%d\n", varsize));
2543 nvram_ularray = kmalloc(varsize, GFP_ATOMIC);
2544 if (!nvram_ularray)
2545 return BCME_NOMEM;
2546
2547 /* Upload image to verify downloaded contents. */
2548 memset(nvram_ularray, 0xaa, varsize);
2549
2550 /* Read the vars list to temp buffer for comparison */
2551 bcmerror =
2552 dhdsdio_membytes(bus, false, varaddr, nvram_ularray,
2553 varsize);
2554 if (bcmerror) {
2555 DHD_ERROR(("%s: error %d on reading %d nvram bytes at "
2556 "0x%08x\n", __func__, bcmerror, varsize, varaddr));
2557 }
2558 /* Compare the org NVRAM with the one read from RAM */
2559 if (memcmp(vbuffer, nvram_ularray, varsize)) {
2560 DHD_ERROR(("%s: Downloaded NVRAM image is corrupted.\n",
2561 __func__));
2562 } else
2563 DHD_ERROR(("%s: Download/Upload/Compare of NVRAM ok.\n",
2564 __func__));
2565
2566 kfree(nvram_ularray);
2567 #endif /* DHD_DEBUG */
2568
2569 kfree(vbuffer);
2570 }
2571
2572 /* adjust to the user specified RAM */
2573 DHD_INFO(("Physical memory size: %d, usable memory size: %d\n",
2574 bus->orig_ramsize, bus->ramsize));
2575 DHD_INFO(("Vars are at %d, orig varsize is %d\n", varaddr, varsize));
2576 varsize = ((bus->orig_ramsize - 4) - varaddr);
2577
2578 /*
2579 * Determine the length token:
2580 * Varsize, converted to words, in lower 16-bits, checksum
2581 * in upper 16-bits.
2582 */
2583 if (bcmerror) {
2584 varsizew = 0;
2585 } else {
2586 varsizew = varsize / 4;
2587 varsizew = (~varsizew << 16) | (varsizew & 0x0000FFFF);
2588 varsizew = cpu_to_le32(varsizew);
2589 }
2590
2591 DHD_INFO(("New varsize is %d, length token=0x%08x\n", varsize,
2592 varsizew));
2593
2594 /* Write the length token to the last word */
2595 bcmerror = dhdsdio_membytes(bus, true, (bus->orig_ramsize - 4),
2596 (u8 *)&varsizew, 4);
2597
2598 return bcmerror;
2599 }
2600
2601 static int dhdsdio_download_state(dhd_bus_t *bus, bool enter)
2602 {
2603 uint retries;
2604 int bcmerror = 0;
2605
2606 /* To enter download state, disable ARM and reset SOCRAM.
2607 * To exit download state, simply reset ARM (default is RAM boot).
2608 */
2609 if (enter) {
2610
2611 bus->alp_only = true;
2612
2613 if (!(si_setcore(bus->sih, ARM7S_CORE_ID, 0)) &&
2614 !(si_setcore(bus->sih, ARMCM3_CORE_ID, 0))) {
2615 DHD_ERROR(("%s: Failed to find ARM core!\n", __func__));
2616 bcmerror = BCME_ERROR;
2617 goto fail;
2618 }
2619
2620 si_core_disable(bus->sih, 0);
2621 if (bcmsdh_regfail(bus->sdh)) {
2622 bcmerror = BCME_SDIO_ERROR;
2623 goto fail;
2624 }
2625
2626 if (!(si_setcore(bus->sih, SOCRAM_CORE_ID, 0))) {
2627 DHD_ERROR(("%s: Failed to find SOCRAM core!\n",
2628 __func__));
2629 bcmerror = BCME_ERROR;
2630 goto fail;
2631 }
2632
2633 si_core_reset(bus->sih, 0, 0);
2634 if (bcmsdh_regfail(bus->sdh)) {
2635 DHD_ERROR(("%s: Failure trying reset SOCRAM core?\n",
2636 __func__));
2637 bcmerror = BCME_SDIO_ERROR;
2638 goto fail;
2639 }
2640
2641 /* Clear the top bit of memory */
2642 if (bus->ramsize) {
2643 u32 zeros = 0;
2644 dhdsdio_membytes(bus, true, bus->ramsize - 4,
2645 (u8 *)&zeros, 4);
2646 }
2647 } else {
2648 if (!(si_setcore(bus->sih, SOCRAM_CORE_ID, 0))) {
2649 DHD_ERROR(("%s: Failed to find SOCRAM core!\n",
2650 __func__));
2651 bcmerror = BCME_ERROR;
2652 goto fail;
2653 }
2654
2655 if (!si_iscoreup(bus->sih)) {
2656 DHD_ERROR(("%s: SOCRAM core is down after reset?\n",
2657 __func__));
2658 bcmerror = BCME_ERROR;
2659 goto fail;
2660 }
2661
2662 bcmerror = dhdsdio_write_vars(bus);
2663 if (bcmerror) {
2664 DHD_ERROR(("%s: no vars written to RAM\n", __func__));
2665 bcmerror = 0;
2666 }
2667
2668 if (!si_setcore(bus->sih, PCMCIA_CORE_ID, 0) &&
2669 !si_setcore(bus->sih, SDIOD_CORE_ID, 0)) {
2670 DHD_ERROR(("%s: Can't change back to SDIO core?\n",
2671 __func__));
2672 bcmerror = BCME_ERROR;
2673 goto fail;
2674 }
2675 W_SDREG(0xFFFFFFFF, &bus->regs->intstatus, retries);
2676
2677 if (!(si_setcore(bus->sih, ARM7S_CORE_ID, 0)) &&
2678 !(si_setcore(bus->sih, ARMCM3_CORE_ID, 0))) {
2679 DHD_ERROR(("%s: Failed to find ARM core!\n", __func__));
2680 bcmerror = BCME_ERROR;
2681 goto fail;
2682 }
2683
2684 si_core_reset(bus->sih, 0, 0);
2685 if (bcmsdh_regfail(bus->sdh)) {
2686 DHD_ERROR(("%s: Failure trying to reset ARM core?\n",
2687 __func__));
2688 bcmerror = BCME_SDIO_ERROR;
2689 goto fail;
2690 }
2691
2692 /* Allow HT Clock now that the ARM is running. */
2693 bus->alp_only = false;
2694
2695 bus->dhd->busstate = DHD_BUS_LOAD;
2696 }
2697
2698 fail:
2699 /* Always return to SDIOD core */
2700 if (!si_setcore(bus->sih, PCMCIA_CORE_ID, 0))
2701 si_setcore(bus->sih, SDIOD_CORE_ID, 0);
2702
2703 return bcmerror;
2704 }
2705
2706 int
2707 dhd_bus_iovar_op(dhd_pub_t *dhdp, const char *name,
2708 void *params, int plen, void *arg, int len, bool set)
2709 {
2710 dhd_bus_t *bus = dhdp->bus;
2711 const bcm_iovar_t *vi = NULL;
2712 int bcmerror = 0;
2713 int val_size;
2714 u32 actionid;
2715
2716 DHD_TRACE(("%s: Enter\n", __func__));
2717
2718 ASSERT(name);
2719 ASSERT(len >= 0);
2720
2721 /* Get MUST have return space */
2722 ASSERT(set || (arg && len));
2723
2724 /* Set does NOT take qualifiers */
2725 ASSERT(!set || (!params && !plen));
2726
2727 /* Look up var locally; if not found pass to host driver */
2728 vi = bcm_iovar_lookup(dhdsdio_iovars, name);
2729 if (vi == NULL) {
2730 dhd_os_sdlock(bus->dhd);
2731
2732 BUS_WAKE(bus);
2733
2734 /* Turn on clock in case SD command needs backplane */
2735 dhdsdio_clkctl(bus, CLK_AVAIL, false);
2736
2737 bcmerror =
2738 bcmsdh_iovar_op(bus->sdh, name, params, plen, arg, len,
2739 set);
2740
2741 /* Check for bus configuration changes of interest */
2742
2743 /* If it was divisor change, read the new one */
2744 if (set && strcmp(name, "sd_divisor") == 0) {
2745 if (bcmsdh_iovar_op(bus->sdh, "sd_divisor", NULL, 0,
2746 &bus->sd_divisor, sizeof(s32),
2747 false) != BCME_OK) {
2748 bus->sd_divisor = -1;
2749 DHD_ERROR(("%s: fail on %s get\n", __func__,
2750 name));
2751 } else {
2752 DHD_INFO(("%s: noted %s update, value now %d\n",
2753 __func__, name, bus->sd_divisor));
2754 }
2755 }
2756 /* If it was a mode change, read the new one */
2757 if (set && strcmp(name, "sd_mode") == 0) {
2758 if (bcmsdh_iovar_op(bus->sdh, "sd_mode", NULL, 0,
2759 &bus->sd_mode, sizeof(s32),
2760 false) != BCME_OK) {
2761 bus->sd_mode = -1;
2762 DHD_ERROR(("%s: fail on %s get\n", __func__,
2763 name));
2764 } else {
2765 DHD_INFO(("%s: noted %s update, value now %d\n",
2766 __func__, name, bus->sd_mode));
2767 }
2768 }
2769 /* Similar check for blocksize change */
2770 if (set && strcmp(name, "sd_blocksize") == 0) {
2771 s32 fnum = 2;
2772 if (bcmsdh_iovar_op
2773 (bus->sdh, "sd_blocksize", &fnum, sizeof(s32),
2774 &bus->blocksize, sizeof(s32),
2775 false) != BCME_OK) {
2776 bus->blocksize = 0;
2777 DHD_ERROR(("%s: fail on %s get\n", __func__,
2778 "sd_blocksize"));
2779 } else {
2780 DHD_INFO(("%s: noted %s update, value now %d\n",
2781 __func__, "sd_blocksize",
2782 bus->blocksize));
2783 }
2784 }
2785 bus->roundup = min(max_roundup, bus->blocksize);
2786
2787 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
2788 bus->activity = false;
2789 dhdsdio_clkctl(bus, CLK_NONE, true);
2790 }
2791
2792 dhd_os_sdunlock(bus->dhd);
2793 goto exit;
2794 }
2795
2796 DHD_CTL(("%s: %s %s, len %d plen %d\n", __func__,
2797 name, (set ? "set" : "get"), len, plen));
2798
2799 /* set up 'params' pointer in case this is a set command so that
2800 * the convenience int and bool code can be common to set and get
2801 */
2802 if (params == NULL) {
2803 params = arg;
2804 plen = len;
2805 }
2806
2807 if (vi->type == IOVT_VOID)
2808 val_size = 0;
2809 else if (vi->type == IOVT_BUFFER)
2810 val_size = len;
2811 else
2812 /* all other types are integer sized */
2813 val_size = sizeof(int);
2814
2815 actionid = set ? IOV_SVAL(vi->varid) : IOV_GVAL(vi->varid);
2816 bcmerror =
2817 dhdsdio_doiovar(bus, vi, actionid, name, params, plen, arg, len,
2818 val_size);
2819
2820 exit:
2821 return bcmerror;
2822 }
2823
2824 void dhd_bus_stop(struct dhd_bus *bus, bool enforce_mutex)
2825 {
2826 u32 local_hostintmask;
2827 u8 saveclk;
2828 uint retries;
2829 int err;
2830
2831 DHD_TRACE(("%s: Enter\n", __func__));
2832
2833 if (enforce_mutex)
2834 dhd_os_sdlock(bus->dhd);
2835
2836 BUS_WAKE(bus);
2837
2838 /* Enable clock for device interrupts */
2839 dhdsdio_clkctl(bus, CLK_AVAIL, false);
2840
2841 /* Disable and clear interrupts at the chip level also */
2842 W_SDREG(0, &bus->regs->hostintmask, retries);
2843 local_hostintmask = bus->hostintmask;
2844 bus->hostintmask = 0;
2845
2846 /* Change our idea of bus state */
2847 bus->dhd->busstate = DHD_BUS_DOWN;
2848
2849 /* Force clocks on backplane to be sure F2 interrupt propagates */
2850 saveclk =
2851 bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
2852 &err);
2853 if (!err) {
2854 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
2855 (saveclk | SBSDIO_FORCE_HT), &err);
2856 }
2857 if (err) {
2858 DHD_ERROR(("%s: Failed to force clock for F2: err %d\n",
2859 __func__, err));
2860 }
2861
2862 /* Turn off the bus (F2), free any pending packets */
2863 DHD_INTR(("%s: disable SDIO interrupts\n", __func__));
2864 bcmsdh_intr_disable(bus->sdh);
2865 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_0, SDIOD_CCCR_IOEN,
2866 SDIO_FUNC_ENABLE_1, NULL);
2867
2868 /* Clear any pending interrupts now that F2 is disabled */
2869 W_SDREG(local_hostintmask, &bus->regs->intstatus, retries);
2870
2871 /* Turn off the backplane clock (only) */
2872 dhdsdio_clkctl(bus, CLK_SDONLY, false);
2873
2874 /* Clear the data packet queues */
2875 pktq_flush(&bus->txq, true);
2876
2877 /* Clear any held glomming stuff */
2878 if (bus->glomd)
2879 pkt_buf_free_skb(bus->glomd);
2880
2881 if (bus->glom)
2882 pkt_buf_free_skb(bus->glom);
2883
2884 bus->glom = bus->glomd = NULL;
2885
2886 /* Clear rx control and wake any waiters */
2887 bus->rxlen = 0;
2888 dhd_os_ioctl_resp_wake(bus->dhd);
2889
2890 /* Reset some F2 state stuff */
2891 bus->rxskip = false;
2892 bus->tx_seq = bus->rx_seq = 0;
2893
2894 if (enforce_mutex)
2895 dhd_os_sdunlock(bus->dhd);
2896 }
2897
2898 int dhd_bus_init(dhd_pub_t *dhdp, bool enforce_mutex)
2899 {
2900 dhd_bus_t *bus = dhdp->bus;
2901 dhd_timeout_t tmo;
2902 uint retries = 0;
2903 u8 ready, enable;
2904 int err, ret = 0;
2905 u8 saveclk;
2906
2907 DHD_TRACE(("%s: Enter\n", __func__));
2908
2909 ASSERT(bus->dhd);
2910 if (!bus->dhd)
2911 return 0;
2912
2913 if (enforce_mutex)
2914 dhd_os_sdlock(bus->dhd);
2915
2916 /* Make sure backplane clock is on, needed to generate F2 interrupt */
2917 dhdsdio_clkctl(bus, CLK_AVAIL, false);
2918 if (bus->clkstate != CLK_AVAIL)
2919 goto exit;
2920
2921 /* Force clocks on backplane to be sure F2 interrupt propagates */
2922 saveclk =
2923 bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
2924 &err);
2925 if (!err) {
2926 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
2927 (saveclk | SBSDIO_FORCE_HT), &err);
2928 }
2929 if (err) {
2930 DHD_ERROR(("%s: Failed to force clock for F2: err %d\n",
2931 __func__, err));
2932 goto exit;
2933 }
2934
2935 /* Enable function 2 (frame transfers) */
2936 W_SDREG((SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT),
2937 &bus->regs->tosbmailboxdata, retries);
2938 enable = (SDIO_FUNC_ENABLE_1 | SDIO_FUNC_ENABLE_2);
2939
2940 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_0, SDIOD_CCCR_IOEN, enable, NULL);
2941
2942 /* Give the dongle some time to do its thing and set IOR2 */
2943 dhd_timeout_start(&tmo, DHD_WAIT_F2RDY * 1000);
2944
2945 ready = 0;
2946 while (ready != enable && !dhd_timeout_expired(&tmo))
2947 ready =
2948 bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_0, SDIOD_CCCR_IORDY,
2949 NULL);
2950
2951 DHD_INFO(("%s: enable 0x%02x, ready 0x%02x (waited %uus)\n",
2952 __func__, enable, ready, tmo.elapsed));
2953
2954 /* If F2 successfully enabled, set core and enable interrupts */
2955 if (ready == enable) {
2956 /* Make sure we're talking to the core. */
2957 bus->regs = si_setcore(bus->sih, PCMCIA_CORE_ID, 0);
2958 if (!(bus->regs))
2959 bus->regs = si_setcore(bus->sih, SDIOD_CORE_ID, 0);
2960
2961 /* Set up the interrupt mask and enable interrupts */
2962 bus->hostintmask = HOSTINTMASK;
2963 W_SDREG(bus->hostintmask, &bus->regs->hostintmask, retries);
2964
2965 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_WATERMARK,
2966 (u8) watermark, &err);
2967
2968 /* Set bus state according to enable result */
2969 dhdp->busstate = DHD_BUS_DATA;
2970
2971 /* bcmsdh_intr_unmask(bus->sdh); */
2972
2973 bus->intdis = false;
2974 if (bus->intr) {
2975 DHD_INTR(("%s: enable SDIO device interrupts\n",
2976 __func__));
2977 bcmsdh_intr_enable(bus->sdh);
2978 } else {
2979 DHD_INTR(("%s: disable SDIO interrupts\n", __func__));
2980 bcmsdh_intr_disable(bus->sdh);
2981 }
2982
2983 }
2984
2985 else {
2986 /* Disable F2 again */
2987 enable = SDIO_FUNC_ENABLE_1;
2988 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_0, SDIOD_CCCR_IOEN, enable,
2989 NULL);
2990 }
2991
2992 /* Restore previous clock setting */
2993 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
2994 saveclk, &err);
2995
2996 /* If we didn't come up, turn off backplane clock */
2997 if (dhdp->busstate != DHD_BUS_DATA)
2998 dhdsdio_clkctl(bus, CLK_NONE, false);
2999
3000 exit:
3001 if (enforce_mutex)
3002 dhd_os_sdunlock(bus->dhd);
3003
3004 return ret;
3005 }
3006
3007 static void dhdsdio_rxfail(dhd_bus_t *bus, bool abort, bool rtx)
3008 {
3009 bcmsdh_info_t *sdh = bus->sdh;
3010 sdpcmd_regs_t *regs = bus->regs;
3011 uint retries = 0;
3012 u16 lastrbc;
3013 u8 hi, lo;
3014 int err;
3015
3016 DHD_ERROR(("%s: %sterminate frame%s\n", __func__,
3017 (abort ? "abort command, " : ""),
3018 (rtx ? ", send NAK" : "")));
3019
3020 if (abort)
3021 bcmsdh_abort(sdh, SDIO_FUNC_2);
3022
3023 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_FRAMECTRL, SFC_RF_TERM,
3024 &err);
3025 bus->f1regdata++;
3026
3027 /* Wait until the packet has been flushed (device/FIFO stable) */
3028 for (lastrbc = retries = 0xffff; retries > 0; retries--) {
3029 hi = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_RFRAMEBCHI,
3030 NULL);
3031 lo = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_RFRAMEBCLO,
3032 NULL);
3033 bus->f1regdata += 2;
3034
3035 if ((hi == 0) && (lo == 0))
3036 break;
3037
3038 if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) {
3039 DHD_ERROR(("%s: count growing: last 0x%04x now "
3040 "0x%04x\n",
3041 __func__, lastrbc, ((hi << 8) + lo)));
3042 }
3043 lastrbc = (hi << 8) + lo;
3044 }
3045
3046 if (!retries) {
3047 DHD_ERROR(("%s: count never zeroed: last 0x%04x\n",
3048 __func__, lastrbc));
3049 } else {
3050 DHD_INFO(("%s: flush took %d iterations\n", __func__,
3051 (0xffff - retries)));
3052 }
3053
3054 if (rtx) {
3055 bus->rxrtx++;
3056 W_SDREG(SMB_NAK, &regs->tosbmailbox, retries);
3057 bus->f1regdata++;
3058 if (retries <= retry_limit)
3059 bus->rxskip = true;
3060 }
3061
3062 /* Clear partial in any case */
3063 bus->nextlen = 0;
3064
3065 /* If we can't reach the device, signal failure */
3066 if (err || bcmsdh_regfail(sdh))
3067 bus->dhd->busstate = DHD_BUS_DOWN;
3068 }
3069
3070 static void
3071 dhdsdio_read_control(dhd_bus_t *bus, u8 *hdr, uint len, uint doff)
3072 {
3073 bcmsdh_info_t *sdh = bus->sdh;
3074 uint rdlen, pad;
3075
3076 int sdret;
3077
3078 DHD_TRACE(("%s: Enter\n", __func__));
3079
3080 /* Control data already received in aligned rxctl */
3081 if ((bus->bus == SPI_BUS) && (!bus->usebufpool))
3082 goto gotpkt;
3083
3084 ASSERT(bus->rxbuf);
3085 /* Set rxctl for frame (w/optional alignment) */
3086 bus->rxctl = bus->rxbuf;
3087 if (dhd_alignctl) {
3088 bus->rxctl += firstread;
3089 pad = ((unsigned long)bus->rxctl % DHD_SDALIGN);
3090 if (pad)
3091 bus->rxctl += (DHD_SDALIGN - pad);
3092 bus->rxctl -= firstread;
3093 }
3094 ASSERT(bus->rxctl >= bus->rxbuf);
3095
3096 /* Copy the already-read portion over */
3097 memcpy(bus->rxctl, hdr, firstread);
3098 if (len <= firstread)
3099 goto gotpkt;
3100
3101 /* Copy the full data pkt in gSPI case and process ioctl. */
3102 if (bus->bus == SPI_BUS) {
3103 memcpy(bus->rxctl, hdr, len);
3104 goto gotpkt;
3105 }
3106
3107 /* Raise rdlen to next SDIO block to avoid tail command */
3108 rdlen = len - firstread;
3109 if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) {
3110 pad = bus->blocksize - (rdlen % bus->blocksize);
3111 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
3112 ((len + pad) < bus->dhd->maxctl))
3113 rdlen += pad;
3114 } else if (rdlen % DHD_SDALIGN) {
3115 rdlen += DHD_SDALIGN - (rdlen % DHD_SDALIGN);
3116 }
3117
3118 /* Satisfy length-alignment requirements */
3119 if (forcealign && (rdlen & (ALIGNMENT - 1)))
3120 rdlen = roundup(rdlen, ALIGNMENT);
3121
3122 /* Drop if the read is too big or it exceeds our maximum */
3123 if ((rdlen + firstread) > bus->dhd->maxctl) {
3124 DHD_ERROR(("%s: %d-byte control read exceeds %d-byte buffer\n",
3125 __func__, rdlen, bus->dhd->maxctl));
3126 bus->dhd->rx_errors++;
3127 dhdsdio_rxfail(bus, false, false);
3128 goto done;
3129 }
3130
3131 if ((len - doff) > bus->dhd->maxctl) {
3132 DHD_ERROR(("%s: %d-byte ctl frame (%d-byte ctl data) exceeds "
3133 "%d-byte limit\n",
3134 __func__, len, (len - doff), bus->dhd->maxctl));
3135 bus->dhd->rx_errors++;
3136 bus->rx_toolong++;
3137 dhdsdio_rxfail(bus, false, false);
3138 goto done;
3139 }
3140
3141 /* Read remainder of frame body into the rxctl buffer */
3142 sdret =
3143 dhd_bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2, F2SYNC,
3144 (bus->rxctl + firstread), rdlen, NULL, NULL,
3145 NULL);
3146 bus->f2rxdata++;
3147 ASSERT(sdret != BCME_PENDING);
3148
3149 /* Control frame failures need retransmission */
3150 if (sdret < 0) {
3151 DHD_ERROR(("%s: read %d control bytes failed: %d\n",
3152 __func__, rdlen, sdret));
3153 bus->rxc_errors++; /* dhd.rx_ctlerrs is higher level */
3154 dhdsdio_rxfail(bus, true, true);
3155 goto done;
3156 }
3157
3158 gotpkt:
3159
3160 #ifdef DHD_DEBUG
3161 if (DHD_BYTES_ON() && DHD_CTL_ON())
3162 prhex("RxCtrl", bus->rxctl, len);
3163 #endif
3164
3165 /* Point to valid data and indicate its length */
3166 bus->rxctl += doff;
3167 bus->rxlen = len - doff;
3168
3169 done:
3170 /* Awake any waiters */
3171 dhd_os_ioctl_resp_wake(bus->dhd);
3172 }
3173
3174 static u8 dhdsdio_rxglom(dhd_bus_t *bus, u8 rxseq)
3175 {
3176 u16 dlen, totlen;
3177 u8 *dptr, num = 0;
3178
3179 u16 sublen, check;
3180 struct sk_buff *pfirst, *plast, *pnext, *save_pfirst;
3181
3182 int errcode;
3183 u8 chan, seq, doff, sfdoff;
3184 u8 txmax;
3185
3186 int ifidx = 0;
3187 bool usechain = bus->use_rxchain;
3188
3189 /* If packets, issue read(s) and send up packet chain */
3190 /* Return sequence numbers consumed? */
3191
3192 DHD_TRACE(("dhdsdio_rxglom: start: glomd %p glom %p\n", bus->glomd,
3193 bus->glom));
3194
3195 /* If there's a descriptor, generate the packet chain */
3196 if (bus->glomd) {
3197 dhd_os_sdlock_rxq(bus->dhd);
3198
3199 pfirst = plast = pnext = NULL;
3200 dlen = (u16) (bus->glomd->len);
3201 dptr = bus->glomd->data;
3202 if (!dlen || (dlen & 1)) {
3203 DHD_ERROR(("%s: bad glomd len(%d), ignore descriptor\n",
3204 __func__, dlen));
3205 dlen = 0;
3206 }
3207
3208 for (totlen = num = 0; dlen; num++) {
3209 /* Get (and move past) next length */
3210 sublen = get_unaligned_le16(dptr);
3211 dlen -= sizeof(u16);
3212 dptr += sizeof(u16);
3213 if ((sublen < SDPCM_HDRLEN) ||
3214 ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) {
3215 DHD_ERROR(("%s: descriptor len %d bad: %d\n",
3216 __func__, num, sublen));
3217 pnext = NULL;
3218 break;
3219 }
3220 if (sublen % DHD_SDALIGN) {
3221 DHD_ERROR(("%s: sublen %d not multiple of %d\n",
3222 __func__, sublen, DHD_SDALIGN));
3223 usechain = false;
3224 }
3225 totlen += sublen;
3226
3227 /* For last frame, adjust read len so total
3228 is a block multiple */
3229 if (!dlen) {
3230 sublen +=
3231 (roundup(totlen, bus->blocksize) - totlen);
3232 totlen = roundup(totlen, bus->blocksize);
3233 }
3234
3235 /* Allocate/chain packet for next subframe */
3236 pnext = pkt_buf_get_skb(sublen + DHD_SDALIGN);
3237 if (pnext == NULL) {
3238 DHD_ERROR(("%s: pkt_buf_get_skb failed, num %d len %d\n",
3239 __func__, num, sublen));
3240 break;
3241 }
3242 ASSERT(!(pnext->prev));
3243 if (!pfirst) {
3244 ASSERT(!plast);
3245 pfirst = plast = pnext;
3246 } else {
3247 ASSERT(plast);
3248 plast->next = pnext;
3249 plast = pnext;
3250 }
3251
3252 /* Adhere to start alignment requirements */
3253 PKTALIGN(pnext, sublen, DHD_SDALIGN);
3254 }
3255
3256 /* If all allocations succeeded, save packet chain
3257 in bus structure */
3258 if (pnext) {
3259 DHD_GLOM(("%s: allocated %d-byte packet chain for %d "
3260 "subframes\n", __func__, totlen, num));
3261 if (DHD_GLOM_ON() && bus->nextlen) {
3262 if (totlen != bus->nextlen) {
3263 DHD_GLOM(("%s: glomdesc mismatch: nextlen %d glomdesc %d " "rxseq %d\n",
3264 __func__, bus->nextlen,
3265 totlen, rxseq));
3266 }
3267 }
3268 bus->glom = pfirst;
3269 pfirst = pnext = NULL;
3270 } else {
3271 if (pfirst)
3272 pkt_buf_free_skb(pfirst);
3273 bus->glom = NULL;
3274 num = 0;
3275 }
3276
3277 /* Done with descriptor packet */
3278 pkt_buf_free_skb(bus->glomd);
3279 bus->glomd = NULL;
3280 bus->nextlen = 0;
3281
3282 dhd_os_sdunlock_rxq(bus->dhd);
3283 }
3284
3285 /* Ok -- either we just generated a packet chain,
3286 or had one from before */
3287 if (bus->glom) {
3288 if (DHD_GLOM_ON()) {
3289 DHD_GLOM(("%s: try superframe read, packet chain:\n",
3290 __func__));
3291 for (pnext = bus->glom; pnext; pnext = pnext->next) {
3292 DHD_GLOM((" %p: %p len 0x%04x (%d)\n",
3293 pnext, (u8 *) (pnext->data),
3294 pnext->len, pnext->len));
3295 }
3296 }
3297
3298 pfirst = bus->glom;
3299 dlen = (u16) pkttotlen(pfirst);
3300
3301 /* Do an SDIO read for the superframe. Configurable iovar to
3302 * read directly into the chained packet, or allocate a large
3303 * packet and and copy into the chain.
3304 */
3305 if (usechain) {
3306 errcode = dhd_bcmsdh_recv_buf(bus,
3307 bcmsdh_cur_sbwad
3308 (bus->sdh), SDIO_FUNC_2,
3309 F2SYNC,
3310 (u8 *) pfirst->data,
3311 dlen, pfirst, NULL, NULL);
3312 } else if (bus->dataptr) {
3313 errcode = dhd_bcmsdh_recv_buf(bus,
3314 bcmsdh_cur_sbwad
3315 (bus->sdh), SDIO_FUNC_2,
3316 F2SYNC, bus->dataptr,
3317 dlen, NULL, NULL, NULL);
3318 sublen =
3319 (u16) pktfrombuf(pfirst, 0, dlen,
3320 bus->dataptr);
3321 if (sublen != dlen) {
3322 DHD_ERROR(("%s: FAILED TO COPY, dlen %d sublen %d\n",
3323 __func__, dlen, sublen));
3324 errcode = -1;
3325 }
3326 pnext = NULL;
3327 } else {
3328 DHD_ERROR(("COULDN'T ALLOC %d-BYTE GLOM, FORCE FAILURE\n",
3329 dlen));
3330 errcode = -1;
3331 }
3332 bus->f2rxdata++;
3333 ASSERT(errcode != BCME_PENDING);
3334
3335 /* On failure, kill the superframe, allow a couple retries */
3336 if (errcode < 0) {
3337 DHD_ERROR(("%s: glom read of %d bytes failed: %d\n",
3338 __func__, dlen, errcode));
3339 bus->dhd->rx_errors++;
3340
3341 if (bus->glomerr++ < 3) {
3342 dhdsdio_rxfail(bus, true, true);
3343 } else {
3344 bus->glomerr = 0;
3345 dhdsdio_rxfail(bus, true, false);
3346 dhd_os_sdlock_rxq(bus->dhd);
3347 pkt_buf_free_skb(bus->glom);
3348 dhd_os_sdunlock_rxq(bus->dhd);
3349 bus->rxglomfail++;
3350 bus->glom = NULL;
3351 }
3352 return 0;
3353 }
3354 #ifdef DHD_DEBUG
3355 if (DHD_GLOM_ON()) {
3356 prhex("SUPERFRAME", pfirst->data,
3357 min_t(int, pfirst->len, 48));
3358 }
3359 #endif
3360
3361 /* Validate the superframe header */
3362 dptr = (u8 *) (pfirst->data);
3363 sublen = get_unaligned_le16(dptr);
3364 check = get_unaligned_le16(dptr + sizeof(u16));
3365
3366 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
3367 seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
3368 bus->nextlen = dptr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
3369 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
3370 DHD_INFO(("%s: nextlen too large (%d) seq %d\n",
3371 __func__, bus->nextlen, seq));
3372 bus->nextlen = 0;
3373 }
3374 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3375 txmax = SDPCM_WINDOW_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3376
3377 errcode = 0;
3378 if ((u16)~(sublen ^ check)) {
3379 DHD_ERROR(("%s (superframe): HW hdr error: len/check "
3380 "0x%04x/0x%04x\n", __func__, sublen, check));
3381 errcode = -1;
3382 } else if (roundup(sublen, bus->blocksize) != dlen) {
3383 DHD_ERROR(("%s (superframe): len 0x%04x, rounded "
3384 "0x%04x, expect 0x%04x\n",
3385 __func__, sublen,
3386 roundup(sublen, bus->blocksize), dlen));
3387 errcode = -1;
3388 } else if (SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]) !=
3389 SDPCM_GLOM_CHANNEL) {
3390 DHD_ERROR(("%s (superframe): bad channel %d\n",
3391 __func__,
3392 SDPCM_PACKET_CHANNEL(&dptr
3393 [SDPCM_FRAMETAG_LEN])));
3394 errcode = -1;
3395 } else if (SDPCM_GLOMDESC(&dptr[SDPCM_FRAMETAG_LEN])) {
3396 DHD_ERROR(("%s (superframe): got second descriptor?\n",
3397 __func__));
3398 errcode = -1;
3399 } else if ((doff < SDPCM_HDRLEN) ||
3400 (doff > (pfirst->len - SDPCM_HDRLEN))) {
3401 DHD_ERROR(("%s (superframe): Bad data offset %d: HW %d "
3402 "pkt %d min %d\n",
3403 __func__, doff, sublen,
3404 pfirst->len, SDPCM_HDRLEN));
3405 errcode = -1;
3406 }
3407
3408 /* Check sequence number of superframe SW header */
3409 if (rxseq != seq) {
3410 DHD_INFO(("%s: (superframe) rx_seq %d, expected %d\n",
3411 __func__, seq, rxseq));
3412 bus->rx_badseq++;
3413 rxseq = seq;
3414 }
3415
3416 /* Check window for sanity */
3417 if ((u8) (txmax - bus->tx_seq) > 0x40) {
3418 DHD_ERROR(("%s: unlikely tx max %d with tx_seq %d\n",
3419 __func__, txmax, bus->tx_seq));
3420 txmax = bus->tx_seq + 2;
3421 }
3422 bus->tx_max = txmax;
3423
3424 /* Remove superframe header, remember offset */
3425 skb_pull(pfirst, doff);
3426 sfdoff = doff;
3427
3428 /* Validate all the subframe headers */
3429 for (num = 0, pnext = pfirst; pnext && !errcode;
3430 num++, pnext = pnext->next) {
3431 dptr = (u8 *) (pnext->data);
3432 dlen = (u16) (pnext->len);
3433 sublen = get_unaligned_le16(dptr);
3434 check = get_unaligned_le16(dptr + sizeof(u16));
3435 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
3436 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3437 #ifdef DHD_DEBUG
3438 if (DHD_GLOM_ON())
3439 prhex("subframe", dptr, 32);
3440 #endif
3441
3442 if ((u16)~(sublen ^ check)) {
3443 DHD_ERROR(("%s (subframe %d): HW hdr error: "
3444 "len/check 0x%04x/0x%04x\n",
3445 __func__, num, sublen, check));
3446 errcode = -1;
3447 } else if ((sublen > dlen) || (sublen < SDPCM_HDRLEN)) {
3448 DHD_ERROR(("%s (subframe %d): length mismatch: "
3449 "len 0x%04x, expect 0x%04x\n",
3450 __func__, num, sublen, dlen));
3451 errcode = -1;
3452 } else if ((chan != SDPCM_DATA_CHANNEL) &&
3453 (chan != SDPCM_EVENT_CHANNEL)) {
3454 DHD_ERROR(("%s (subframe %d): bad channel %d\n",
3455 __func__, num, chan));
3456 errcode = -1;
3457 } else if ((doff < SDPCM_HDRLEN) || (doff > sublen)) {
3458 DHD_ERROR(("%s (subframe %d): Bad data offset %d: HW %d min %d\n",
3459 __func__, num, doff, sublen,
3460 SDPCM_HDRLEN));
3461 errcode = -1;
3462 }
3463 }
3464
3465 if (errcode) {
3466 /* Terminate frame on error, request
3467 a couple retries */
3468 if (bus->glomerr++ < 3) {
3469 /* Restore superframe header space */
3470 skb_push(pfirst, sfdoff);
3471 dhdsdio_rxfail(bus, true, true);
3472 } else {
3473 bus->glomerr = 0;
3474 dhdsdio_rxfail(bus, true, false);
3475 dhd_os_sdlock_rxq(bus->dhd);
3476 pkt_buf_free_skb(bus->glom);
3477 dhd_os_sdunlock_rxq(bus->dhd);
3478 bus->rxglomfail++;
3479 bus->glom = NULL;
3480 }
3481 bus->nextlen = 0;
3482 return 0;
3483 }
3484
3485 /* Basic SD framing looks ok - process each packet (header) */
3486 save_pfirst = pfirst;
3487 bus->glom = NULL;
3488 plast = NULL;
3489
3490 dhd_os_sdlock_rxq(bus->dhd);
3491 for (num = 0; pfirst; rxseq++, pfirst = pnext) {
3492 pnext = pfirst->next;
3493 pfirst->next = NULL;
3494
3495 dptr = (u8 *) (pfirst->data);
3496 sublen = get_unaligned_le16(dptr);
3497 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
3498 seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
3499 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3500
3501 DHD_GLOM(("%s: Get subframe %d, %p(%p/%d), sublen %d "
3502 "chan %d seq %d\n",
3503 __func__, num, pfirst, pfirst->data,
3504 pfirst->len, sublen, chan, seq));
3505
3506 ASSERT((chan == SDPCM_DATA_CHANNEL)
3507 || (chan == SDPCM_EVENT_CHANNEL));
3508
3509 if (rxseq != seq) {
3510 DHD_GLOM(("%s: rx_seq %d, expected %d\n",
3511 __func__, seq, rxseq));
3512 bus->rx_badseq++;
3513 rxseq = seq;
3514 }
3515 #ifdef DHD_DEBUG
3516 if (DHD_BYTES_ON() && DHD_DATA_ON())
3517 prhex("Rx Subframe Data", dptr, dlen);
3518 #endif
3519
3520 __skb_trim(pfirst, sublen);
3521 skb_pull(pfirst, doff);
3522
3523 if (pfirst->len == 0) {
3524 pkt_buf_free_skb(pfirst);
3525 if (plast) {
3526 plast->next = pnext;
3527 } else {
3528 ASSERT(save_pfirst == pfirst);
3529 save_pfirst = pnext;
3530 }
3531 continue;
3532 } else if (dhd_prot_hdrpull(bus->dhd, &ifidx, pfirst) !=
3533 0) {
3534 DHD_ERROR(("%s: rx protocol error\n",
3535 __func__));
3536 bus->dhd->rx_errors++;
3537 pkt_buf_free_skb(pfirst);
3538 if (plast) {
3539 plast->next = pnext;
3540 } else {
3541 ASSERT(save_pfirst == pfirst);
3542 save_pfirst = pnext;
3543 }
3544 continue;
3545 }
3546
3547 /* this packet will go up, link back into
3548 chain and count it */
3549 pfirst->next = pnext;
3550 plast = pfirst;
3551 num++;
3552
3553 #ifdef DHD_DEBUG
3554 if (DHD_GLOM_ON()) {
3555 DHD_GLOM(("%s subframe %d to stack, %p(%p/%d) "
3556 "nxt/lnk %p/%p\n",
3557 __func__, num, pfirst, pfirst->data,
3558 pfirst->len, pfirst->next,
3559 pfirst->prev));
3560 prhex("", (u8 *) pfirst->data,
3561 min_t(int, pfirst->len, 32));
3562 }
3563 #endif /* DHD_DEBUG */
3564 }
3565 dhd_os_sdunlock_rxq(bus->dhd);
3566 if (num) {
3567 dhd_os_sdunlock(bus->dhd);
3568 dhd_rx_frame(bus->dhd, ifidx, save_pfirst, num);
3569 dhd_os_sdlock(bus->dhd);
3570 }
3571
3572 bus->rxglomframes++;
3573 bus->rxglompkts += num;
3574 }
3575 return num;
3576 }
3577
3578 /* Return true if there may be more frames to read */
3579 static uint dhdsdio_readframes(dhd_bus_t *bus, uint maxframes, bool *finished)
3580 {
3581 bcmsdh_info_t *sdh = bus->sdh;
3582
3583 u16 len, check; /* Extracted hardware header fields */
3584 u8 chan, seq, doff; /* Extracted software header fields */
3585 u8 fcbits; /* Extracted fcbits from software header */
3586 u8 delta;
3587
3588 struct sk_buff *pkt; /* Packet for event or data frames */
3589 u16 pad; /* Number of pad bytes to read */
3590 u16 rdlen; /* Total number of bytes to read */
3591 u8 rxseq; /* Next sequence number to expect */
3592 uint rxleft = 0; /* Remaining number of frames allowed */
3593 int sdret; /* Return code from bcmsdh calls */
3594 u8 txmax; /* Maximum tx sequence offered */
3595 bool len_consistent; /* Result of comparing readahead len and
3596 len from hw-hdr */
3597 u8 *rxbuf;
3598 int ifidx = 0;
3599 uint rxcount = 0; /* Total frames read */
3600
3601 #if defined(DHD_DEBUG) || defined(SDTEST)
3602 bool sdtest = false; /* To limit message spew from test mode */
3603 #endif
3604
3605 DHD_TRACE(("%s: Enter\n", __func__));
3606
3607 ASSERT(maxframes);
3608
3609 #ifdef SDTEST
3610 /* Allow pktgen to override maxframes */
3611 if (bus->pktgen_count && (bus->pktgen_mode == DHD_PKTGEN_RECV)) {
3612 maxframes = bus->pktgen_count;
3613 sdtest = true;
3614 }
3615 #endif
3616
3617 /* Not finished unless we encounter no more frames indication */
3618 *finished = false;
3619
3620 for (rxseq = bus->rx_seq, rxleft = maxframes;
3621 !bus->rxskip && rxleft && bus->dhd->busstate != DHD_BUS_DOWN;
3622 rxseq++, rxleft--) {
3623
3624 /* Handle glomming separately */
3625 if (bus->glom || bus->glomd) {
3626 u8 cnt;
3627 DHD_GLOM(("%s: calling rxglom: glomd %p, glom %p\n",
3628 __func__, bus->glomd, bus->glom));
3629 cnt = dhdsdio_rxglom(bus, rxseq);
3630 DHD_GLOM(("%s: rxglom returned %d\n", __func__, cnt));
3631 rxseq += cnt - 1;
3632 rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1;
3633 continue;
3634 }
3635
3636 /* Try doing single read if we can */
3637 if (dhd_readahead && bus->nextlen) {
3638 u16 nextlen = bus->nextlen;
3639 bus->nextlen = 0;
3640
3641 if (bus->bus == SPI_BUS) {
3642 rdlen = len = nextlen;
3643 } else {
3644 rdlen = len = nextlen << 4;
3645
3646 /* Pad read to blocksize for efficiency */
3647 if (bus->roundup && bus->blocksize
3648 && (rdlen > bus->blocksize)) {
3649 pad =
3650 bus->blocksize -
3651 (rdlen % bus->blocksize);
3652 if ((pad <= bus->roundup)
3653 && (pad < bus->blocksize)
3654 && ((rdlen + pad + firstread) <
3655 MAX_RX_DATASZ))
3656 rdlen += pad;
3657 } else if (rdlen % DHD_SDALIGN) {
3658 rdlen +=
3659 DHD_SDALIGN - (rdlen % DHD_SDALIGN);
3660 }
3661 }
3662
3663 /* We use bus->rxctl buffer in WinXP for initial
3664 * control pkt receives.
3665 * Later we use buffer-poll for data as well
3666 * as control packets.
3667 * This is required becuase dhd receives full
3668 * frame in gSPI unlike SDIO.
3669 * After the frame is received we have to
3670 * distinguish whether it is data
3671 * or non-data frame.
3672 */
3673 /* Allocate a packet buffer */
3674 dhd_os_sdlock_rxq(bus->dhd);
3675 pkt = pkt_buf_get_skb(rdlen + DHD_SDALIGN);
3676 if (!pkt) {
3677 if (bus->bus == SPI_BUS) {
3678 bus->usebufpool = false;
3679 bus->rxctl = bus->rxbuf;
3680 if (dhd_alignctl) {
3681 bus->rxctl += firstread;
3682 pad = ((unsigned long)bus->rxctl %
3683 DHD_SDALIGN);
3684 if (pad)
3685 bus->rxctl +=
3686 (DHD_SDALIGN - pad);
3687 bus->rxctl -= firstread;
3688 }
3689 ASSERT(bus->rxctl >= bus->rxbuf);
3690 rxbuf = bus->rxctl;
3691 /* Read the entire frame */
3692 sdret = dhd_bcmsdh_recv_buf(bus,
3693 bcmsdh_cur_sbwad
3694 (sdh),
3695 SDIO_FUNC_2,
3696 F2SYNC,
3697 rxbuf,
3698 rdlen, NULL,
3699 NULL, NULL);
3700 bus->f2rxdata++;
3701 ASSERT(sdret != BCME_PENDING);
3702
3703 /* Control frame failures need
3704 retransmission */
3705 if (sdret < 0) {
3706 DHD_ERROR(("%s: read %d control bytes failed: %d\n",
3707 __func__,
3708 rdlen, sdret));
3709 /* dhd.rx_ctlerrs is higher */
3710 bus->rxc_errors++;
3711 dhd_os_sdunlock_rxq(bus->dhd);
3712 dhdsdio_rxfail(bus, true,
3713 (bus->bus ==
3714 SPI_BUS) ? false
3715 : true);
3716 continue;
3717 }
3718 } else {
3719 /* Give up on data,
3720 request rtx of events */
3721 DHD_ERROR(("%s (nextlen): pkt_buf_get_skb failed: len %d rdlen %d " "expected rxseq %d\n",
3722 __func__, len, rdlen, rxseq));
3723 /* Just go try again w/normal
3724 header read */
3725 dhd_os_sdunlock_rxq(bus->dhd);
3726 continue;
3727 }
3728 } else {
3729 if (bus->bus == SPI_BUS)
3730 bus->usebufpool = true;
3731
3732 ASSERT(!(pkt->prev));
3733 PKTALIGN(pkt, rdlen, DHD_SDALIGN);
3734 rxbuf = (u8 *) (pkt->data);
3735 /* Read the entire frame */
3736 sdret =
3737 dhd_bcmsdh_recv_buf(bus,
3738 bcmsdh_cur_sbwad(sdh),
3739 SDIO_FUNC_2, F2SYNC,
3740 rxbuf, rdlen, pkt, NULL,
3741 NULL);
3742 bus->f2rxdata++;
3743 ASSERT(sdret != BCME_PENDING);
3744
3745 if (sdret < 0) {
3746 DHD_ERROR(("%s (nextlen): read %d bytes failed: %d\n",
3747 __func__, rdlen, sdret));
3748 pkt_buf_free_skb(pkt);
3749 bus->dhd->rx_errors++;
3750 dhd_os_sdunlock_rxq(bus->dhd);
3751 /* Force retry w/normal header read.
3752 * Don't attemp NAK for
3753 * gSPI
3754 */
3755 dhdsdio_rxfail(bus, true,
3756 (bus->bus ==
3757 SPI_BUS) ? false :
3758 true);
3759 continue;
3760 }
3761 }
3762 dhd_os_sdunlock_rxq(bus->dhd);
3763
3764 /* Now check the header */
3765 memcpy(bus->rxhdr, rxbuf, SDPCM_HDRLEN);
3766
3767 /* Extract hardware header fields */
3768 len = get_unaligned_le16(bus->rxhdr);
3769 check = get_unaligned_le16(bus->rxhdr + sizeof(u16));
3770
3771 /* All zeros means readahead info was bad */
3772 if (!(len | check)) {
3773 DHD_INFO(("%s (nextlen): read zeros in HW "
3774 "header???\n", __func__));
3775 dhd_os_sdlock_rxq(bus->dhd);
3776 PKTFREE2();
3777 dhd_os_sdunlock_rxq(bus->dhd);
3778 GSPI_PR55150_BAILOUT;
3779 continue;
3780 }
3781
3782 /* Validate check bytes */
3783 if ((u16)~(len ^ check)) {
3784 DHD_ERROR(("%s (nextlen): HW hdr error: nextlen/len/check" " 0x%04x/0x%04x/0x%04x\n",
3785 __func__, nextlen, len, check));
3786 dhd_os_sdlock_rxq(bus->dhd);
3787 PKTFREE2();
3788 dhd_os_sdunlock_rxq(bus->dhd);
3789 bus->rx_badhdr++;
3790 dhdsdio_rxfail(bus, false, false);
3791 GSPI_PR55150_BAILOUT;
3792 continue;
3793 }
3794
3795 /* Validate frame length */
3796 if (len < SDPCM_HDRLEN) {
3797 DHD_ERROR(("%s (nextlen): HW hdr length "
3798 "invalid: %d\n", __func__, len));
3799 dhd_os_sdlock_rxq(bus->dhd);
3800 PKTFREE2();
3801 dhd_os_sdunlock_rxq(bus->dhd);
3802 GSPI_PR55150_BAILOUT;
3803 continue;
3804 }
3805
3806 /* Check for consistency withreadahead info */
3807 len_consistent = (nextlen != (roundup(len, 16) >> 4));
3808 if (len_consistent) {
3809 /* Mismatch, force retry w/normal
3810 header (may be >4K) */
3811 DHD_ERROR(("%s (nextlen): mismatch, nextlen %d len %d rnd %d; " "expected rxseq %d\n",
3812 __func__, nextlen,
3813 len, roundup(len, 16), rxseq));
3814 dhd_os_sdlock_rxq(bus->dhd);
3815 PKTFREE2();
3816 dhd_os_sdunlock_rxq(bus->dhd);
3817 dhdsdio_rxfail(bus, true,
3818 (bus->bus ==
3819 SPI_BUS) ? false : true);
3820 GSPI_PR55150_BAILOUT;
3821 continue;
3822 }
3823
3824 /* Extract software header fields */
3825 chan =
3826 SDPCM_PACKET_CHANNEL(&bus->rxhdr
3827 [SDPCM_FRAMETAG_LEN]);
3828 seq =
3829 SDPCM_PACKET_SEQUENCE(&bus->rxhdr
3830 [SDPCM_FRAMETAG_LEN]);
3831 doff =
3832 SDPCM_DOFFSET_VALUE(&bus->rxhdr
3833 [SDPCM_FRAMETAG_LEN]);
3834 txmax =
3835 SDPCM_WINDOW_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3836
3837 bus->nextlen =
3838 bus->rxhdr[SDPCM_FRAMETAG_LEN +
3839 SDPCM_NEXTLEN_OFFSET];
3840 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
3841 DHD_INFO(("%s (nextlen): got frame w/nextlen too large" " (%d), seq %d\n",
3842 __func__, bus->nextlen, seq));
3843 bus->nextlen = 0;
3844 }
3845
3846 bus->dhd->rx_readahead_cnt++;
3847 /* Handle Flow Control */
3848 fcbits =
3849 SDPCM_FCMASK_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3850
3851 delta = 0;
3852 if (~bus->flowcontrol & fcbits) {
3853 bus->fc_xoff++;
3854 delta = 1;
3855 }
3856 if (bus->flowcontrol & ~fcbits) {
3857 bus->fc_xon++;
3858 delta = 1;
3859 }
3860
3861 if (delta) {
3862 bus->fc_rcvd++;
3863 bus->flowcontrol = fcbits;
3864 }
3865
3866 /* Check and update sequence number */
3867 if (rxseq != seq) {
3868 DHD_INFO(("%s (nextlen): rx_seq %d, expected "
3869 "%d\n", __func__, seq, rxseq));
3870 bus->rx_badseq++;
3871 rxseq = seq;
3872 }
3873
3874 /* Check window for sanity */
3875 if ((u8) (txmax - bus->tx_seq) > 0x40) {
3876 DHD_ERROR(("%s: got unlikely tx max %d with "
3877 "tx_seq %d\n",
3878 __func__, txmax, bus->tx_seq));
3879 txmax = bus->tx_seq + 2;
3880 }
3881 bus->tx_max = txmax;
3882
3883 #ifdef DHD_DEBUG
3884 if (DHD_BYTES_ON() && DHD_DATA_ON())
3885 prhex("Rx Data", rxbuf, len);
3886 else if (DHD_HDRS_ON())
3887 prhex("RxHdr", bus->rxhdr, SDPCM_HDRLEN);
3888 #endif
3889
3890 if (chan == SDPCM_CONTROL_CHANNEL) {
3891 if (bus->bus == SPI_BUS) {
3892 dhdsdio_read_control(bus, rxbuf, len,
3893 doff);
3894 if (bus->usebufpool) {
3895 dhd_os_sdlock_rxq(bus->dhd);
3896 pkt_buf_free_skb(pkt);
3897 dhd_os_sdunlock_rxq(bus->dhd);
3898 }
3899 continue;
3900 } else {
3901 DHD_ERROR(("%s (nextlen): readahead on control" " packet %d?\n",
3902 __func__, seq));
3903 /* Force retry w/normal header read */
3904 bus->nextlen = 0;
3905 dhdsdio_rxfail(bus, false, true);
3906 dhd_os_sdlock_rxq(bus->dhd);
3907 PKTFREE2();
3908 dhd_os_sdunlock_rxq(bus->dhd);
3909 continue;
3910 }
3911 }
3912
3913 if ((bus->bus == SPI_BUS) && !bus->usebufpool) {
3914 DHD_ERROR(("Received %d bytes on %d channel. Running out of " "rx pktbuf's or not yet malloced.\n",
3915 len, chan));
3916 continue;
3917 }
3918
3919 /* Validate data offset */
3920 if ((doff < SDPCM_HDRLEN) || (doff > len)) {
3921 DHD_ERROR(("%s (nextlen): bad data offset %d: HW len %d min %d\n",
3922 __func__, doff, len, SDPCM_HDRLEN));
3923 dhd_os_sdlock_rxq(bus->dhd);
3924 PKTFREE2();
3925 dhd_os_sdunlock_rxq(bus->dhd);
3926 ASSERT(0);
3927 dhdsdio_rxfail(bus, false, false);
3928 continue;
3929 }
3930
3931 /* All done with this one -- now deliver the packet */
3932 goto deliver;
3933 }
3934 /* gSPI frames should not be handled in fractions */
3935 if (bus->bus == SPI_BUS)
3936 break;
3937
3938 /* Read frame header (hardware and software) */
3939 sdret =
3940 dhd_bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2,
3941 F2SYNC, bus->rxhdr, firstread, NULL,
3942 NULL, NULL);
3943 bus->f2rxhdrs++;
3944 ASSERT(sdret != BCME_PENDING);
3945
3946 if (sdret < 0) {
3947 DHD_ERROR(("%s: RXHEADER FAILED: %d\n", __func__,
3948 sdret));
3949 bus->rx_hdrfail++;
3950 dhdsdio_rxfail(bus, true, true);
3951 continue;
3952 }
3953 #ifdef DHD_DEBUG
3954 if (DHD_BYTES_ON() || DHD_HDRS_ON())
3955 prhex("RxHdr", bus->rxhdr, SDPCM_HDRLEN);
3956 #endif
3957
3958 /* Extract hardware header fields */
3959 len = get_unaligned_le16(bus->rxhdr);
3960 check = get_unaligned_le16(bus->rxhdr + sizeof(u16));
3961
3962 /* All zeros means no more frames */
3963 if (!(len | check)) {
3964 *finished = true;
3965 break;
3966 }
3967
3968 /* Validate check bytes */
3969 if ((u16) ~(len ^ check)) {
3970 DHD_ERROR(("%s: HW hdr err: len/check 0x%04x/0x%04x\n",
3971 __func__, len, check));
3972 bus->rx_badhdr++;
3973 dhdsdio_rxfail(bus, false, false);
3974 continue;
3975 }
3976
3977 /* Validate frame length */
3978 if (len < SDPCM_HDRLEN) {
3979 DHD_ERROR(("%s: HW hdr length invalid: %d\n",
3980 __func__, len));
3981 continue;
3982 }
3983
3984 /* Extract software header fields */
3985 chan = SDPCM_PACKET_CHANNEL(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3986 seq = SDPCM_PACKET_SEQUENCE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3987 doff = SDPCM_DOFFSET_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3988 txmax = SDPCM_WINDOW_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3989
3990 /* Validate data offset */
3991 if ((doff < SDPCM_HDRLEN) || (doff > len)) {
3992 DHD_ERROR(("%s: Bad data offset %d: HW len %d, min %d "
3993 "seq %d\n",
3994 __func__, doff, len, SDPCM_HDRLEN, seq));
3995 bus->rx_badhdr++;
3996 ASSERT(0);
3997 dhdsdio_rxfail(bus, false, false);
3998 continue;
3999 }
4000
4001 /* Save the readahead length if there is one */
4002 bus->nextlen =
4003 bus->rxhdr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
4004 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
4005 DHD_INFO(("%s (nextlen): got frame w/nextlen too large "
4006 "(%d), seq %d\n",
4007 __func__, bus->nextlen, seq));
4008 bus->nextlen = 0;
4009 }
4010
4011 /* Handle Flow Control */
4012 fcbits = SDPCM_FCMASK_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4013
4014 delta = 0;
4015 if (~bus->flowcontrol & fcbits) {
4016 bus->fc_xoff++;
4017 delta = 1;
4018 }
4019 if (bus->flowcontrol & ~fcbits) {
4020 bus->fc_xon++;
4021 delta = 1;
4022 }
4023
4024 if (delta) {
4025 bus->fc_rcvd++;
4026 bus->flowcontrol = fcbits;
4027 }
4028
4029 /* Check and update sequence number */
4030 if (rxseq != seq) {
4031 DHD_INFO(("%s: rx_seq %d, expected %d\n", __func__,
4032 seq, rxseq));
4033 bus->rx_badseq++;
4034 rxseq = seq;
4035 }
4036
4037 /* Check window for sanity */
4038 if ((u8) (txmax - bus->tx_seq) > 0x40) {
4039 DHD_ERROR(("%s: unlikely tx max %d with tx_seq %d\n",
4040 __func__, txmax, bus->tx_seq));
4041 txmax = bus->tx_seq + 2;
4042 }
4043 bus->tx_max = txmax;
4044
4045 /* Call a separate function for control frames */
4046 if (chan == SDPCM_CONTROL_CHANNEL) {
4047 dhdsdio_read_control(bus, bus->rxhdr, len, doff);
4048 continue;
4049 }
4050
4051 ASSERT((chan == SDPCM_DATA_CHANNEL)
4052 || (chan == SDPCM_EVENT_CHANNEL)
4053 || (chan == SDPCM_TEST_CHANNEL)
4054 || (chan == SDPCM_GLOM_CHANNEL));
4055
4056 /* Length to read */
4057 rdlen = (len > firstread) ? (len - firstread) : 0;
4058
4059 /* May pad read to blocksize for efficiency */
4060 if (bus->roundup && bus->blocksize &&
4061 (rdlen > bus->blocksize)) {
4062 pad = bus->blocksize - (rdlen % bus->blocksize);
4063 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
4064 ((rdlen + pad + firstread) < MAX_RX_DATASZ))
4065 rdlen += pad;
4066 } else if (rdlen % DHD_SDALIGN) {
4067 rdlen += DHD_SDALIGN - (rdlen % DHD_SDALIGN);
4068 }
4069
4070 /* Satisfy length-alignment requirements */
4071 if (forcealign && (rdlen & (ALIGNMENT - 1)))
4072 rdlen = roundup(rdlen, ALIGNMENT);
4073
4074 if ((rdlen + firstread) > MAX_RX_DATASZ) {
4075 /* Too long -- skip this frame */
4076 DHD_ERROR(("%s: too long: len %d rdlen %d\n",
4077 __func__, len, rdlen));
4078 bus->dhd->rx_errors++;
4079 bus->rx_toolong++;
4080 dhdsdio_rxfail(bus, false, false);
4081 continue;
4082 }
4083
4084 dhd_os_sdlock_rxq(bus->dhd);
4085 pkt = pkt_buf_get_skb(rdlen + firstread + DHD_SDALIGN);
4086 if (!pkt) {
4087 /* Give up on data, request rtx of events */
4088 DHD_ERROR(("%s: pkt_buf_get_skb failed: rdlen %d chan %d\n",
4089 __func__, rdlen, chan));
4090 bus->dhd->rx_dropped++;
4091 dhd_os_sdunlock_rxq(bus->dhd);
4092 dhdsdio_rxfail(bus, false, RETRYCHAN(chan));
4093 continue;
4094 }
4095 dhd_os_sdunlock_rxq(bus->dhd);
4096
4097 ASSERT(!(pkt->prev));
4098
4099 /* Leave room for what we already read, and align remainder */
4100 ASSERT(firstread < pkt->len);
4101 skb_pull(pkt, firstread);
4102 PKTALIGN(pkt, rdlen, DHD_SDALIGN);
4103
4104 /* Read the remaining frame data */
4105 sdret =
4106 dhd_bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2,
4107 F2SYNC, ((u8 *) (pkt->data)), rdlen,
4108 pkt, NULL, NULL);
4109 bus->f2rxdata++;
4110 ASSERT(sdret != BCME_PENDING);
4111
4112 if (sdret < 0) {
4113 DHD_ERROR(("%s: read %d %s bytes failed: %d\n",
4114 __func__, rdlen,
4115 ((chan ==
4116 SDPCM_EVENT_CHANNEL) ? "event" : ((chan ==
4117 SDPCM_DATA_CHANNEL)
4118 ? "data" : "test")),
4119 sdret));
4120 dhd_os_sdlock_rxq(bus->dhd);
4121 pkt_buf_free_skb(pkt);
4122 dhd_os_sdunlock_rxq(bus->dhd);
4123 bus->dhd->rx_errors++;
4124 dhdsdio_rxfail(bus, true, RETRYCHAN(chan));
4125 continue;
4126 }
4127
4128 /* Copy the already-read portion */
4129 skb_push(pkt, firstread);
4130 memcpy(pkt->data, bus->rxhdr, firstread);
4131
4132 #ifdef DHD_DEBUG
4133 if (DHD_BYTES_ON() && DHD_DATA_ON())
4134 prhex("Rx Data", pkt->data, len);
4135 #endif
4136
4137 deliver:
4138 /* Save superframe descriptor and allocate packet frame */
4139 if (chan == SDPCM_GLOM_CHANNEL) {
4140 if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_FRAMETAG_LEN])) {
4141 DHD_GLOM(("%s: glom descriptor, %d bytes:\n",
4142 __func__, len));
4143 #ifdef DHD_DEBUG
4144 if (DHD_GLOM_ON()) {
4145 prhex("Glom Data", pkt->data, len);
4146 }
4147 #endif
4148 __skb_trim(pkt, len);
4149 ASSERT(doff == SDPCM_HDRLEN);
4150 skb_pull(pkt, SDPCM_HDRLEN);
4151 bus->glomd = pkt;
4152 } else {
4153 DHD_ERROR(("%s: glom superframe w/o "
4154 "descriptor!\n", __func__));
4155 dhdsdio_rxfail(bus, false, false);
4156 }
4157 continue;
4158 }
4159
4160 /* Fill in packet len and prio, deliver upward */
4161 __skb_trim(pkt, len);
4162 skb_pull(pkt, doff);
4163
4164 #ifdef SDTEST
4165 /* Test channel packets are processed separately */
4166 if (chan == SDPCM_TEST_CHANNEL) {
4167 dhdsdio_testrcv(bus, pkt, seq);
4168 continue;
4169 }
4170 #endif /* SDTEST */
4171
4172 if (pkt->len == 0) {
4173 dhd_os_sdlock_rxq(bus->dhd);
4174 pkt_buf_free_skb(pkt);
4175 dhd_os_sdunlock_rxq(bus->dhd);
4176 continue;
4177 } else if (dhd_prot_hdrpull(bus->dhd, &ifidx, pkt) != 0) {
4178 DHD_ERROR(("%s: rx protocol error\n", __func__));
4179 dhd_os_sdlock_rxq(bus->dhd);
4180 pkt_buf_free_skb(pkt);
4181 dhd_os_sdunlock_rxq(bus->dhd);
4182 bus->dhd->rx_errors++;
4183 continue;
4184 }
4185
4186 /* Unlock during rx call */
4187 dhd_os_sdunlock(bus->dhd);
4188 dhd_rx_frame(bus->dhd, ifidx, pkt, 1);
4189 dhd_os_sdlock(bus->dhd);
4190 }
4191 rxcount = maxframes - rxleft;
4192 #ifdef DHD_DEBUG
4193 /* Message if we hit the limit */
4194 if (!rxleft && !sdtest)
4195 DHD_DATA(("%s: hit rx limit of %d frames\n", __func__,
4196 maxframes));
4197 else
4198 #endif /* DHD_DEBUG */
4199 DHD_DATA(("%s: processed %d frames\n", __func__, rxcount));
4200 /* Back off rxseq if awaiting rtx, update rx_seq */
4201 if (bus->rxskip)
4202 rxseq--;
4203 bus->rx_seq = rxseq;
4204
4205 return rxcount;
4206 }
4207
4208 static u32 dhdsdio_hostmail(dhd_bus_t *bus)
4209 {
4210 sdpcmd_regs_t *regs = bus->regs;
4211 u32 intstatus = 0;
4212 u32 hmb_data;
4213 u8 fcbits;
4214 uint retries = 0;
4215
4216 DHD_TRACE(("%s: Enter\n", __func__));
4217
4218 /* Read mailbox data and ack that we did so */
4219 R_SDREG(hmb_data, &regs->tohostmailboxdata, retries);
4220 if (retries <= retry_limit)
4221 W_SDREG(SMB_INT_ACK, &regs->tosbmailbox, retries);
4222 bus->f1regdata += 2;
4223
4224 /* Dongle recomposed rx frames, accept them again */
4225 if (hmb_data & HMB_DATA_NAKHANDLED) {
4226 DHD_INFO(("Dongle reports NAK handled, expect rtx of %d\n",
4227 bus->rx_seq));
4228 if (!bus->rxskip)
4229 DHD_ERROR(("%s: unexpected NAKHANDLED!\n", __func__));
4230
4231 bus->rxskip = false;
4232 intstatus |= I_HMB_FRAME_IND;
4233 }
4234
4235 /*
4236 * DEVREADY does not occur with gSPI.
4237 */
4238 if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) {
4239 bus->sdpcm_ver =
4240 (hmb_data & HMB_DATA_VERSION_MASK) >>
4241 HMB_DATA_VERSION_SHIFT;
4242 if (bus->sdpcm_ver != SDPCM_PROT_VERSION)
4243 DHD_ERROR(("Version mismatch, dongle reports %d, "
4244 "expecting %d\n",
4245 bus->sdpcm_ver, SDPCM_PROT_VERSION));
4246 else
4247 DHD_INFO(("Dongle ready, protocol version %d\n",
4248 bus->sdpcm_ver));
4249 }
4250
4251 /*
4252 * Flow Control has been moved into the RX headers and this out of band
4253 * method isn't used any more. Leae this here for possibly
4254 * remaining backward
4255 * compatible with older dongles
4256 */
4257 if (hmb_data & HMB_DATA_FC) {
4258 fcbits =
4259 (hmb_data & HMB_DATA_FCDATA_MASK) >> HMB_DATA_FCDATA_SHIFT;
4260
4261 if (fcbits & ~bus->flowcontrol)
4262 bus->fc_xoff++;
4263 if (bus->flowcontrol & ~fcbits)
4264 bus->fc_xon++;
4265
4266 bus->fc_rcvd++;
4267 bus->flowcontrol = fcbits;
4268 }
4269
4270 /* Shouldn't be any others */
4271 if (hmb_data & ~(HMB_DATA_DEVREADY |
4272 HMB_DATA_NAKHANDLED |
4273 HMB_DATA_FC |
4274 HMB_DATA_FWREADY |
4275 HMB_DATA_FCDATA_MASK | HMB_DATA_VERSION_MASK)) {
4276 DHD_ERROR(("Unknown mailbox data content: 0x%02x\n", hmb_data));
4277 }
4278
4279 return intstatus;
4280 }
4281
4282 bool dhdsdio_dpc(dhd_bus_t *bus)
4283 {
4284 bcmsdh_info_t *sdh = bus->sdh;
4285 sdpcmd_regs_t *regs = bus->regs;
4286 u32 intstatus, newstatus = 0;
4287 uint retries = 0;
4288 uint rxlimit = dhd_rxbound; /* Rx frames to read before resched */
4289 uint txlimit = dhd_txbound; /* Tx frames to send before resched */
4290 uint framecnt = 0; /* Temporary counter of tx/rx frames */
4291 bool rxdone = true; /* Flag for no more read data */
4292 bool resched = false; /* Flag indicating resched wanted */
4293
4294 DHD_TRACE(("%s: Enter\n", __func__));
4295
4296 /* Start with leftover status bits */
4297 intstatus = bus->intstatus;
4298
4299 dhd_os_sdlock(bus->dhd);
4300
4301 /* If waiting for HTAVAIL, check status */
4302 if (bus->clkstate == CLK_PENDING) {
4303 int err;
4304 u8 clkctl, devctl = 0;
4305
4306 #ifdef DHD_DEBUG
4307 /* Check for inconsistent device control */
4308 devctl =
4309 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, &err);
4310 if (err) {
4311 DHD_ERROR(("%s: error reading DEVCTL: %d\n",
4312 __func__, err));
4313 bus->dhd->busstate = DHD_BUS_DOWN;
4314 } else {
4315 ASSERT(devctl & SBSDIO_DEVCTL_CA_INT_ONLY);
4316 }
4317 #endif /* DHD_DEBUG */
4318
4319 /* Read CSR, if clock on switch to AVAIL, else ignore */
4320 clkctl =
4321 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
4322 &err);
4323 if (err) {
4324 DHD_ERROR(("%s: error reading CSR: %d\n", __func__,
4325 err));
4326 bus->dhd->busstate = DHD_BUS_DOWN;
4327 }
4328
4329 DHD_INFO(("DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n", devctl,
4330 clkctl));
4331
4332 if (SBSDIO_HTAV(clkctl)) {
4333 devctl =
4334 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
4335 &err);
4336 if (err) {
4337 DHD_ERROR(("%s: error reading DEVCTL: %d\n",
4338 __func__, err));
4339 bus->dhd->busstate = DHD_BUS_DOWN;
4340 }
4341 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
4342 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
4343 devctl, &err);
4344 if (err) {
4345 DHD_ERROR(("%s: error writing DEVCTL: %d\n",
4346 __func__, err));
4347 bus->dhd->busstate = DHD_BUS_DOWN;
4348 }
4349 bus->clkstate = CLK_AVAIL;
4350 } else {
4351 goto clkwait;
4352 }
4353 }
4354
4355 BUS_WAKE(bus);
4356
4357 /* Make sure backplane clock is on */
4358 dhdsdio_clkctl(bus, CLK_AVAIL, true);
4359 if (bus->clkstate == CLK_PENDING)
4360 goto clkwait;
4361
4362 /* Pending interrupt indicates new device status */
4363 if (bus->ipend) {
4364 bus->ipend = false;
4365 R_SDREG(newstatus, &regs->intstatus, retries);
4366 bus->f1regdata++;
4367 if (bcmsdh_regfail(bus->sdh))
4368 newstatus = 0;
4369 newstatus &= bus->hostintmask;
4370 bus->fcstate = !!(newstatus & I_HMB_FC_STATE);
4371 if (newstatus) {
4372 W_SDREG(newstatus, &regs->intstatus, retries);
4373 bus->f1regdata++;
4374 }
4375 }
4376
4377 /* Merge new bits with previous */
4378 intstatus |= newstatus;
4379 bus->intstatus = 0;
4380
4381 /* Handle flow-control change: read new state in case our ack
4382 * crossed another change interrupt. If change still set, assume
4383 * FC ON for safety, let next loop through do the debounce.
4384 */
4385 if (intstatus & I_HMB_FC_CHANGE) {
4386 intstatus &= ~I_HMB_FC_CHANGE;
4387 W_SDREG(I_HMB_FC_CHANGE, &regs->intstatus, retries);
4388 R_SDREG(newstatus, &regs->intstatus, retries);
4389 bus->f1regdata += 2;
4390 bus->fcstate =
4391 !!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE));
4392 intstatus |= (newstatus & bus->hostintmask);
4393 }
4394
4395 /* Handle host mailbox indication */
4396 if (intstatus & I_HMB_HOST_INT) {
4397 intstatus &= ~I_HMB_HOST_INT;
4398 intstatus |= dhdsdio_hostmail(bus);
4399 }
4400
4401 /* Generally don't ask for these, can get CRC errors... */
4402 if (intstatus & I_WR_OOSYNC) {
4403 DHD_ERROR(("Dongle reports WR_OOSYNC\n"));
4404 intstatus &= ~I_WR_OOSYNC;
4405 }
4406
4407 if (intstatus & I_RD_OOSYNC) {
4408 DHD_ERROR(("Dongle reports RD_OOSYNC\n"));
4409 intstatus &= ~I_RD_OOSYNC;
4410 }
4411
4412 if (intstatus & I_SBINT) {
4413 DHD_ERROR(("Dongle reports SBINT\n"));
4414 intstatus &= ~I_SBINT;
4415 }
4416
4417 /* Would be active due to wake-wlan in gSPI */
4418 if (intstatus & I_CHIPACTIVE) {
4419 DHD_INFO(("Dongle reports CHIPACTIVE\n"));
4420 intstatus &= ~I_CHIPACTIVE;
4421 }
4422
4423 /* Ignore frame indications if rxskip is set */
4424 if (bus->rxskip)
4425 intstatus &= ~I_HMB_FRAME_IND;
4426
4427 /* On frame indication, read available frames */
4428 if (PKT_AVAILABLE()) {
4429 framecnt = dhdsdio_readframes(bus, rxlimit, &rxdone);
4430 if (rxdone || bus->rxskip)
4431 intstatus &= ~I_HMB_FRAME_IND;
4432 rxlimit -= min(framecnt, rxlimit);
4433 }
4434
4435 /* Keep still-pending events for next scheduling */
4436 bus->intstatus = intstatus;
4437
4438 clkwait:
4439 #if defined(OOB_INTR_ONLY)
4440 bcmsdh_oob_intr_set(1);
4441 #endif /* (OOB_INTR_ONLY) */
4442 /* Re-enable interrupts to detect new device events (mailbox, rx frame)
4443 * or clock availability. (Allows tx loop to check ipend if desired.)
4444 * (Unless register access seems hosed, as we may not be able to ACK...)
4445 */
4446 if (bus->intr && bus->intdis && !bcmsdh_regfail(sdh)) {
4447 DHD_INTR(("%s: enable SDIO interrupts, rxdone %d framecnt %d\n",
4448 __func__, rxdone, framecnt));
4449 bus->intdis = false;
4450 bcmsdh_intr_enable(sdh);
4451 }
4452
4453 if (DATAOK(bus) && bus->ctrl_frame_stat &&
4454 (bus->clkstate == CLK_AVAIL)) {
4455 int ret, i;
4456
4457 ret =
4458 dhd_bcmsdh_send_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2,
4459 F2SYNC, (u8 *) bus->ctrl_frame_buf,
4460 (u32) bus->ctrl_frame_len, NULL,
4461 NULL, NULL);
4462 ASSERT(ret != BCME_PENDING);
4463
4464 if (ret < 0) {
4465 /* On failure, abort the command and
4466 terminate the frame */
4467 DHD_INFO(("%s: sdio error %d, abort command and "
4468 "terminate frame.\n", __func__, ret));
4469 bus->tx_sderrs++;
4470
4471 bcmsdh_abort(sdh, SDIO_FUNC_2);
4472
4473 bcmsdh_cfg_write(sdh, SDIO_FUNC_1,
4474 SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM,
4475 NULL);
4476 bus->f1regdata++;
4477
4478 for (i = 0; i < 3; i++) {
4479 u8 hi, lo;
4480 hi = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
4481 SBSDIO_FUNC1_WFRAMEBCHI,
4482 NULL);
4483 lo = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
4484 SBSDIO_FUNC1_WFRAMEBCLO,
4485 NULL);
4486 bus->f1regdata += 2;
4487 if ((hi == 0) && (lo == 0))
4488 break;
4489 }
4490
4491 }
4492 if (ret == 0)
4493 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
4494
4495 DHD_INFO(("Return_dpc value is : %d\n", ret));
4496 bus->ctrl_frame_stat = false;
4497 dhd_wait_event_wakeup(bus->dhd);
4498 }
4499 /* Send queued frames (limit 1 if rx may still be pending) */
4500 else if ((bus->clkstate == CLK_AVAIL) && !bus->fcstate &&
4501 pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit
4502 && DATAOK(bus)) {
4503 framecnt = rxdone ? txlimit : min(txlimit, dhd_txminmax);
4504 framecnt = dhdsdio_sendfromq(bus, framecnt);
4505 txlimit -= framecnt;
4506 }
4507
4508 /* Resched if events or tx frames are pending,
4509 else await next interrupt */
4510 /* On failed register access, all bets are off:
4511 no resched or interrupts */
4512 if ((bus->dhd->busstate == DHD_BUS_DOWN) || bcmsdh_regfail(sdh)) {
4513 DHD_ERROR(("%s: failed backplane access over SDIO, halting "
4514 "operation %d\n", __func__, bcmsdh_regfail(sdh)));
4515 bus->dhd->busstate = DHD_BUS_DOWN;
4516 bus->intstatus = 0;
4517 } else if (bus->clkstate == CLK_PENDING) {
4518 DHD_INFO(("%s: rescheduled due to CLK_PENDING awaiting "
4519 "I_CHIPACTIVE interrupt\n", __func__));
4520 resched = true;
4521 } else if (bus->intstatus || bus->ipend ||
4522 (!bus->fcstate && pktq_mlen(&bus->txq, ~bus->flowcontrol) &&
4523 DATAOK(bus)) || PKT_AVAILABLE()) {
4524 resched = true;
4525 }
4526
4527 bus->dpc_sched = resched;
4528
4529 /* If we're done for now, turn off clock request. */
4530 if ((bus->clkstate != CLK_PENDING)
4531 && bus->idletime == DHD_IDLE_IMMEDIATE) {
4532 bus->activity = false;
4533 dhdsdio_clkctl(bus, CLK_NONE, false);
4534 }
4535
4536 dhd_os_sdunlock(bus->dhd);
4537
4538 return resched;
4539 }
4540
4541 bool dhd_bus_dpc(struct dhd_bus *bus)
4542 {
4543 bool resched;
4544
4545 /* Call the DPC directly. */
4546 DHD_TRACE(("Calling dhdsdio_dpc() from %s\n", __func__));
4547 resched = dhdsdio_dpc(bus);
4548
4549 return resched;
4550 }
4551
4552 void dhdsdio_isr(void *arg)
4553 {
4554 dhd_bus_t *bus = (dhd_bus_t *) arg;
4555 bcmsdh_info_t *sdh;
4556
4557 DHD_TRACE(("%s: Enter\n", __func__));
4558
4559 if (!bus) {
4560 DHD_ERROR(("%s : bus is null pointer , exit\n", __func__));
4561 return;
4562 }
4563 sdh = bus->sdh;
4564
4565 if (bus->dhd->busstate == DHD_BUS_DOWN) {
4566 DHD_ERROR(("%s : bus is down. we have nothing to do\n",
4567 __func__));
4568 return;
4569 }
4570 /* Count the interrupt call */
4571 bus->intrcount++;
4572 bus->ipend = true;
4573
4574 /* Shouldn't get this interrupt if we're sleeping? */
4575 if (bus->sleeping) {
4576 DHD_ERROR(("INTERRUPT WHILE SLEEPING??\n"));
4577 return;
4578 }
4579
4580 /* Disable additional interrupts (is this needed now)? */
4581 if (bus->intr)
4582 DHD_INTR(("%s: disable SDIO interrupts\n", __func__));
4583 else
4584 DHD_ERROR(("dhdsdio_isr() w/o interrupt configured!\n"));
4585
4586 bcmsdh_intr_disable(sdh);
4587 bus->intdis = true;
4588
4589 #if defined(SDIO_ISR_THREAD)
4590 DHD_TRACE(("Calling dhdsdio_dpc() from %s\n", __func__));
4591 while (dhdsdio_dpc(bus))
4592 ;
4593 #else
4594 bus->dpc_sched = true;
4595 dhd_sched_dpc(bus->dhd);
4596 #endif
4597
4598 }
4599
4600 #ifdef SDTEST
4601 static void dhdsdio_pktgen_init(dhd_bus_t *bus)
4602 {
4603 /* Default to specified length, or full range */
4604 if (dhd_pktgen_len) {
4605 bus->pktgen_maxlen = min(dhd_pktgen_len, MAX_PKTGEN_LEN);
4606 bus->pktgen_minlen = bus->pktgen_maxlen;
4607 } else {
4608 bus->pktgen_maxlen = MAX_PKTGEN_LEN;
4609 bus->pktgen_minlen = 0;
4610 }
4611 bus->pktgen_len = (u16) bus->pktgen_minlen;
4612
4613 /* Default to per-watchdog burst with 10s print time */
4614 bus->pktgen_freq = 1;
4615 bus->pktgen_print = 10000 / dhd_watchdog_ms;
4616 bus->pktgen_count = (dhd_pktgen * dhd_watchdog_ms + 999) / 1000;
4617
4618 /* Default to echo mode */
4619 bus->pktgen_mode = DHD_PKTGEN_ECHO;
4620 bus->pktgen_stop = 1;
4621 }
4622
4623 static void dhdsdio_pktgen(dhd_bus_t *bus)
4624 {
4625 struct sk_buff *pkt;
4626 u8 *data;
4627 uint pktcount;
4628 uint fillbyte;
4629 u16 len;
4630
4631 /* Display current count if appropriate */
4632 if (bus->pktgen_print && (++bus->pktgen_ptick >= bus->pktgen_print)) {
4633 bus->pktgen_ptick = 0;
4634 printk(KERN_DEBUG "%s: send attempts %d rcvd %d\n",
4635 __func__, bus->pktgen_sent, bus->pktgen_rcvd);
4636 }
4637
4638 /* For recv mode, just make sure dongle has started sending */
4639 if (bus->pktgen_mode == DHD_PKTGEN_RECV) {
4640 if (!bus->pktgen_rcvd)
4641 dhdsdio_sdtest_set(bus, true);
4642 return;
4643 }
4644
4645 /* Otherwise, generate or request the specified number of packets */
4646 for (pktcount = 0; pktcount < bus->pktgen_count; pktcount++) {
4647 /* Stop if total has been reached */
4648 if (bus->pktgen_total
4649 && (bus->pktgen_sent >= bus->pktgen_total)) {
4650 bus->pktgen_count = 0;
4651 break;
4652 }
4653
4654 /* Allocate an appropriate-sized packet */
4655 len = bus->pktgen_len;
4656 pkt = pkt_buf_get_skb(
4657 (len + SDPCM_HDRLEN + SDPCM_TEST_HDRLEN + DHD_SDALIGN),
4658 true);
4659 if (!pkt) {
4660 DHD_ERROR(("%s: pkt_buf_get_skb failed!\n", __func__));
4661 break;
4662 }
4663 PKTALIGN(pkt, (len + SDPCM_HDRLEN + SDPCM_TEST_HDRLEN),
4664 DHD_SDALIGN);
4665 data = (u8 *) (pkt->data) + SDPCM_HDRLEN;
4666
4667 /* Write test header cmd and extra based on mode */
4668 switch (bus->pktgen_mode) {
4669 case DHD_PKTGEN_ECHO:
4670 *data++ = SDPCM_TEST_ECHOREQ;
4671 *data++ = (u8) bus->pktgen_sent;
4672 break;
4673
4674 case DHD_PKTGEN_SEND:
4675 *data++ = SDPCM_TEST_DISCARD;
4676 *data++ = (u8) bus->pktgen_sent;
4677 break;
4678
4679 case DHD_PKTGEN_RXBURST:
4680 *data++ = SDPCM_TEST_BURST;
4681 *data++ = (u8) bus->pktgen_count;
4682 break;
4683
4684 default:
4685 DHD_ERROR(("Unrecognized pktgen mode %d\n",
4686 bus->pktgen_mode));
4687 pkt_buf_free_skb(pkt, true);
4688 bus->pktgen_count = 0;
4689 return;
4690 }
4691
4692 /* Write test header length field */
4693 *data++ = (len >> 0);
4694 *data++ = (len >> 8);
4695
4696 /* Then fill in the remainder -- N/A for burst,
4697 but who cares... */
4698 for (fillbyte = 0; fillbyte < len; fillbyte++)
4699 *data++ =
4700 SDPCM_TEST_FILL(fillbyte, (u8) bus->pktgen_sent);
4701
4702 #ifdef DHD_DEBUG
4703 if (DHD_BYTES_ON() && DHD_DATA_ON()) {
4704 data = (u8 *) (pkt->data) + SDPCM_HDRLEN;
4705 prhex("dhdsdio_pktgen: Tx Data", data,
4706 pkt->len - SDPCM_HDRLEN);
4707 }
4708 #endif
4709
4710 /* Send it */
4711 if (dhdsdio_txpkt(bus, pkt, SDPCM_TEST_CHANNEL, true)) {
4712 bus->pktgen_fail++;
4713 if (bus->pktgen_stop
4714 && bus->pktgen_stop == bus->pktgen_fail)
4715 bus->pktgen_count = 0;
4716 }
4717 bus->pktgen_sent++;
4718
4719 /* Bump length if not fixed, wrap at max */
4720 if (++bus->pktgen_len > bus->pktgen_maxlen)
4721 bus->pktgen_len = (u16) bus->pktgen_minlen;
4722
4723 /* Special case for burst mode: just send one request! */
4724 if (bus->pktgen_mode == DHD_PKTGEN_RXBURST)
4725 break;
4726 }
4727 }
4728
4729 static void dhdsdio_sdtest_set(dhd_bus_t *bus, bool start)
4730 {
4731 struct sk_buff *pkt;
4732 u8 *data;
4733
4734 /* Allocate the packet */
4735 pkt = pkt_buf_get_skb(SDPCM_HDRLEN + SDPCM_TEST_HDRLEN + DHD_SDALIGN,
4736 true);
4737 if (!pkt) {
4738 DHD_ERROR(("%s: pkt_buf_get_skb failed!\n", __func__));
4739 return;
4740 }
4741 PKTALIGN(pkt, (SDPCM_HDRLEN + SDPCM_TEST_HDRLEN), DHD_SDALIGN);
4742 data = (u8 *) (pkt->data) + SDPCM_HDRLEN;
4743
4744 /* Fill in the test header */
4745 *data++ = SDPCM_TEST_SEND;
4746 *data++ = start;
4747 *data++ = (bus->pktgen_maxlen >> 0);
4748 *data++ = (bus->pktgen_maxlen >> 8);
4749
4750 /* Send it */
4751 if (dhdsdio_txpkt(bus, pkt, SDPCM_TEST_CHANNEL, true))
4752 bus->pktgen_fail++;
4753 }
4754
4755 static void dhdsdio_testrcv(dhd_bus_t *bus, struct sk_buff *pkt, uint seq)
4756 {
4757 u8 *data;
4758 uint pktlen;
4759
4760 u8 cmd;
4761 u8 extra;
4762 u16 len;
4763 u16 offset;
4764
4765 /* Check for min length */
4766 pktlen = pkt->len;
4767 if (pktlen < SDPCM_TEST_HDRLEN) {
4768 DHD_ERROR(("dhdsdio_restrcv: toss runt frame, pktlen %d\n",
4769 pktlen));
4770 pkt_buf_free_skb(pkt, false);
4771 return;
4772 }
4773
4774 /* Extract header fields */
4775 data = pkt->data;
4776 cmd = *data++;
4777 extra = *data++;
4778 len = *data++;
4779 len += *data++ << 8;
4780
4781 /* Check length for relevant commands */
4782 if (cmd == SDPCM_TEST_DISCARD || cmd == SDPCM_TEST_ECHOREQ
4783 || cmd == SDPCM_TEST_ECHORSP) {
4784 if (pktlen != len + SDPCM_TEST_HDRLEN) {
4785 DHD_ERROR(("dhdsdio_testrcv: frame length mismatch, "
4786 "pktlen %d seq %d" " cmd %d extra %d len %d\n",
4787 pktlen, seq, cmd, extra, len));
4788 pkt_buf_free_skb(pkt, false);
4789 return;
4790 }
4791 }
4792
4793 /* Process as per command */
4794 switch (cmd) {
4795 case SDPCM_TEST_ECHOREQ:
4796 /* Rx->Tx turnaround ok (even on NDIS w/current
4797 implementation) */
4798 *(u8 *) (pkt->data) = SDPCM_TEST_ECHORSP;
4799 if (dhdsdio_txpkt(bus, pkt, SDPCM_TEST_CHANNEL, true) == 0) {
4800 bus->pktgen_sent++;
4801 } else {
4802 bus->pktgen_fail++;
4803 pkt_buf_free_skb(pkt, false);
4804 }
4805 bus->pktgen_rcvd++;
4806 break;
4807
4808 case SDPCM_TEST_ECHORSP:
4809 if (bus->ext_loop) {
4810 pkt_buf_free_skb(pkt, false);
4811 bus->pktgen_rcvd++;
4812 break;
4813 }
4814
4815 for (offset = 0; offset < len; offset++, data++) {
4816 if (*data != SDPCM_TEST_FILL(offset, extra)) {
4817 DHD_ERROR(("dhdsdio_testrcv: echo data mismatch: " "offset %d (len %d) expect 0x%02x rcvd 0x%02x\n",
4818 offset, len,
4819 SDPCM_TEST_FILL(offset, extra), *data));
4820 break;
4821 }
4822 }
4823 pkt_buf_free_skb(pkt, false);
4824 bus->pktgen_rcvd++;
4825 break;
4826
4827 case SDPCM_TEST_DISCARD:
4828 pkt_buf_free_skb(pkt, false);
4829 bus->pktgen_rcvd++;
4830 break;
4831
4832 case SDPCM_TEST_BURST:
4833 case SDPCM_TEST_SEND:
4834 default:
4835 DHD_INFO(("dhdsdio_testrcv: unsupported or unknown command, "
4836 "pktlen %d seq %d" " cmd %d extra %d len %d\n",
4837 pktlen, seq, cmd, extra, len));
4838 pkt_buf_free_skb(pkt, false);
4839 break;
4840 }
4841
4842 /* For recv mode, stop at limie (and tell dongle to stop sending) */
4843 if (bus->pktgen_mode == DHD_PKTGEN_RECV) {
4844 if (bus->pktgen_total
4845 && (bus->pktgen_rcvd >= bus->pktgen_total)) {
4846 bus->pktgen_count = 0;
4847 dhdsdio_sdtest_set(bus, false);
4848 }
4849 }
4850 }
4851 #endif /* SDTEST */
4852
4853 extern bool dhd_bus_watchdog(dhd_pub_t *dhdp)
4854 {
4855 dhd_bus_t *bus;
4856
4857 DHD_TIMER(("%s: Enter\n", __func__));
4858
4859 bus = dhdp->bus;
4860
4861 if (bus->dhd->dongle_reset)
4862 return false;
4863
4864 /* Ignore the timer if simulating bus down */
4865 if (bus->sleeping)
4866 return false;
4867
4868 dhd_os_sdlock(bus->dhd);
4869
4870 /* Poll period: check device if appropriate. */
4871 if (bus->poll && (++bus->polltick >= bus->pollrate)) {
4872 u32 intstatus = 0;
4873
4874 /* Reset poll tick */
4875 bus->polltick = 0;
4876
4877 /* Check device if no interrupts */
4878 if (!bus->intr || (bus->intrcount == bus->lastintrs)) {
4879
4880 if (!bus->dpc_sched) {
4881 u8 devpend;
4882 devpend = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_0,
4883 SDIOD_CCCR_INTPEND,
4884 NULL);
4885 intstatus =
4886 devpend & (INTR_STATUS_FUNC1 |
4887 INTR_STATUS_FUNC2);
4888 }
4889
4890 /* If there is something, make like the ISR and
4891 schedule the DPC */
4892 if (intstatus) {
4893 bus->pollcnt++;
4894 bus->ipend = true;
4895 if (bus->intr)
4896 bcmsdh_intr_disable(bus->sdh);
4897
4898 bus->dpc_sched = true;
4899 dhd_sched_dpc(bus->dhd);
4900
4901 }
4902 }
4903
4904 /* Update interrupt tracking */
4905 bus->lastintrs = bus->intrcount;
4906 }
4907 #ifdef DHD_DEBUG
4908 /* Poll for console output periodically */
4909 if (dhdp->busstate == DHD_BUS_DATA && dhd_console_ms != 0) {
4910 bus->console.count += dhd_watchdog_ms;
4911 if (bus->console.count >= dhd_console_ms) {
4912 bus->console.count -= dhd_console_ms;
4913 /* Make sure backplane clock is on */
4914 dhdsdio_clkctl(bus, CLK_AVAIL, false);
4915 if (dhdsdio_readconsole(bus) < 0)
4916 dhd_console_ms = 0; /* On error,
4917 stop trying */
4918 }
4919 }
4920 #endif /* DHD_DEBUG */
4921
4922 #ifdef SDTEST
4923 /* Generate packets if configured */
4924 if (bus->pktgen_count && (++bus->pktgen_tick >= bus->pktgen_freq)) {
4925 /* Make sure backplane clock is on */
4926 dhdsdio_clkctl(bus, CLK_AVAIL, false);
4927 bus->pktgen_tick = 0;
4928 dhdsdio_pktgen(bus);
4929 }
4930 #endif
4931
4932 /* On idle timeout clear activity flag and/or turn off clock */
4933 if ((bus->idletime > 0) && (bus->clkstate == CLK_AVAIL)) {
4934 if (++bus->idlecount >= bus->idletime) {
4935 bus->idlecount = 0;
4936 if (bus->activity) {
4937 bus->activity = false;
4938 dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
4939 } else {
4940 dhdsdio_clkctl(bus, CLK_NONE, false);
4941 }
4942 }
4943 }
4944
4945 dhd_os_sdunlock(bus->dhd);
4946
4947 return bus->ipend;
4948 }
4949
4950 #ifdef DHD_DEBUG
4951 extern int dhd_bus_console_in(dhd_pub_t *dhdp, unsigned char *msg, uint msglen)
4952 {
4953 dhd_bus_t *bus = dhdp->bus;
4954 u32 addr, val;
4955 int rv;
4956 struct sk_buff *pkt;
4957
4958 /* Address could be zero if CONSOLE := 0 in dongle Makefile */
4959 if (bus->console_addr == 0)
4960 return BCME_UNSUPPORTED;
4961
4962 /* Exclusive bus access */
4963 dhd_os_sdlock(bus->dhd);
4964
4965 /* Don't allow input if dongle is in reset */
4966 if (bus->dhd->dongle_reset) {
4967 dhd_os_sdunlock(bus->dhd);
4968 return BCME_NOTREADY;
4969 }
4970
4971 /* Request clock to allow SDIO accesses */
4972 BUS_WAKE(bus);
4973 /* No pend allowed since txpkt is called later, ht clk has to be on */
4974 dhdsdio_clkctl(bus, CLK_AVAIL, false);
4975
4976 /* Zero cbuf_index */
4977 addr = bus->console_addr + offsetof(hndrte_cons_t, cbuf_idx);
4978 val = cpu_to_le32(0);
4979 rv = dhdsdio_membytes(bus, true, addr, (u8 *)&val, sizeof(val));
4980 if (rv < 0)
4981 goto done;
4982
4983 /* Write message into cbuf */
4984 addr = bus->console_addr + offsetof(hndrte_cons_t, cbuf);
4985 rv = dhdsdio_membytes(bus, true, addr, (u8 *)msg, msglen);
4986 if (rv < 0)
4987 goto done;
4988
4989 /* Write length into vcons_in */
4990 addr = bus->console_addr + offsetof(hndrte_cons_t, vcons_in);
4991 val = cpu_to_le32(msglen);
4992 rv = dhdsdio_membytes(bus, true, addr, (u8 *)&val, sizeof(val));
4993 if (rv < 0)
4994 goto done;
4995
4996 /* Bump dongle by sending an empty event pkt.
4997 * sdpcm_sendup (RX) checks for virtual console input.
4998 */
4999 pkt = pkt_buf_get_skb(4 + SDPCM_RESERVE);
5000 if ((pkt != NULL) && bus->clkstate == CLK_AVAIL)
5001 dhdsdio_txpkt(bus, pkt, SDPCM_EVENT_CHANNEL, true);
5002
5003 done:
5004 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
5005 bus->activity = false;
5006 dhdsdio_clkctl(bus, CLK_NONE, true);
5007 }
5008
5009 dhd_os_sdunlock(bus->dhd);
5010
5011 return rv;
5012 }
5013 #endif /* DHD_DEBUG */
5014
5015 #ifdef DHD_DEBUG
5016 static void dhd_dump_cis(uint fn, u8 *cis)
5017 {
5018 uint byte, tag, tdata;
5019 DHD_INFO(("Function %d CIS:\n", fn));
5020
5021 for (tdata = byte = 0; byte < SBSDIO_CIS_SIZE_LIMIT; byte++) {
5022 if ((byte % 16) == 0)
5023 DHD_INFO((" "));
5024 DHD_INFO(("%02x ", cis[byte]));
5025 if ((byte % 16) == 15)
5026 DHD_INFO(("\n"));
5027 if (!tdata--) {
5028 tag = cis[byte];
5029 if (tag == 0xff)
5030 break;
5031 else if (!tag)
5032 tdata = 0;
5033 else if ((byte + 1) < SBSDIO_CIS_SIZE_LIMIT)
5034 tdata = cis[byte + 1] + 1;
5035 else
5036 DHD_INFO(("]"));
5037 }
5038 }
5039 if ((byte % 16) != 15)
5040 DHD_INFO(("\n"));
5041 }
5042 #endif /* DHD_DEBUG */
5043
5044 static bool dhdsdio_chipmatch(u16 chipid)
5045 {
5046 if (chipid == BCM4325_CHIP_ID)
5047 return true;
5048 if (chipid == BCM4329_CHIP_ID)
5049 return true;
5050 if (chipid == BCM4319_CHIP_ID)
5051 return true;
5052 return false;
5053 }
5054
5055 static void *dhdsdio_probe(u16 venid, u16 devid, u16 bus_no,
5056 u16 slot, u16 func, uint bustype, void *regsva,
5057 void *sdh)
5058 {
5059 int ret;
5060 dhd_bus_t *bus;
5061
5062 /* Init global variables at run-time, not as part of the declaration.
5063 * This is required to support init/de-init of the driver.
5064 * Initialization
5065 * of globals as part of the declaration results in non-deterministic
5066 * behavior since the value of the globals may be different on the
5067 * first time that the driver is initialized vs subsequent
5068 * initializations.
5069 */
5070 dhd_txbound = DHD_TXBOUND;
5071 dhd_rxbound = DHD_RXBOUND;
5072 dhd_alignctl = true;
5073 sd1idle = true;
5074 dhd_readahead = true;
5075 retrydata = false;
5076 dhd_doflow = false;
5077 dhd_dongle_memsize = 0;
5078 dhd_txminmax = DHD_TXMINMAX;
5079
5080 forcealign = true;
5081
5082 dhd_common_init();
5083
5084 DHD_TRACE(("%s: Enter\n", __func__));
5085 DHD_INFO(("%s: venid 0x%04x devid 0x%04x\n", __func__, venid, devid));
5086
5087 /* We make assumptions about address window mappings */
5088 ASSERT((unsigned long)regsva == SI_ENUM_BASE);
5089
5090 /* BCMSDH passes venid and devid based on CIS parsing -- but
5091 * low-power start
5092 * means early parse could fail, so here we should get either an ID
5093 * we recognize OR (-1) indicating we must request power first.
5094 */
5095 /* Check the Vendor ID */
5096 switch (venid) {
5097 case 0x0000:
5098 case VENDOR_BROADCOM:
5099 break;
5100 default:
5101 DHD_ERROR(("%s: unknown vendor: 0x%04x\n", __func__, venid));
5102 return NULL;
5103 }
5104
5105 /* Check the Device ID and make sure it's one that we support */
5106 switch (devid) {
5107 case BCM4325_D11DUAL_ID: /* 4325 802.11a/g id */
5108 case BCM4325_D11G_ID: /* 4325 802.11g 2.4Ghz band id */
5109 case BCM4325_D11A_ID: /* 4325 802.11a 5Ghz band id */
5110 DHD_INFO(("%s: found 4325 Dongle\n", __func__));
5111 break;
5112 case BCM4329_D11NDUAL_ID: /* 4329 802.11n dualband device */
5113 case BCM4329_D11N2G_ID: /* 4329 802.11n 2.4G device */
5114 case BCM4329_D11N5G_ID: /* 4329 802.11n 5G device */
5115 case 0x4329:
5116 DHD_INFO(("%s: found 4329 Dongle\n", __func__));
5117 break;
5118 case BCM4319_D11N_ID: /* 4319 802.11n id */
5119 case BCM4319_D11N2G_ID: /* 4319 802.11n2g id */
5120 case BCM4319_D11N5G_ID: /* 4319 802.11n5g id */
5121 DHD_INFO(("%s: found 4319 Dongle\n", __func__));
5122 break;
5123 case 0:
5124 DHD_INFO(("%s: allow device id 0, will check chip internals\n",
5125 __func__));
5126 break;
5127
5128 default:
5129 DHD_ERROR(("%s: skipping 0x%04x/0x%04x, not a dongle\n",
5130 __func__, venid, devid));
5131 return NULL;
5132 }
5133
5134 /* Allocate private bus interface state */
5135 bus = kzalloc(sizeof(dhd_bus_t), GFP_ATOMIC);
5136 if (!bus) {
5137 DHD_ERROR(("%s: kmalloc of dhd_bus_t failed\n", __func__));
5138 goto fail;
5139 }
5140 bus->sdh = sdh;
5141 bus->cl_devid = (u16) devid;
5142 bus->bus = DHD_BUS;
5143 bus->tx_seq = SDPCM_SEQUENCE_WRAP - 1;
5144 bus->usebufpool = false; /* Use bufpool if allocated,
5145 else use locally malloced rxbuf */
5146
5147 /* attempt to attach to the dongle */
5148 if (!(dhdsdio_probe_attach(bus, sdh, regsva, devid))) {
5149 DHD_ERROR(("%s: dhdsdio_probe_attach failed\n", __func__));
5150 goto fail;
5151 }
5152
5153 /* Attach to the dhd/OS/network interface */
5154 bus->dhd = dhd_attach(bus, SDPCM_RESERVE);
5155 if (!bus->dhd) {
5156 DHD_ERROR(("%s: dhd_attach failed\n", __func__));
5157 goto fail;
5158 }
5159
5160 /* Allocate buffers */
5161 if (!(dhdsdio_probe_malloc(bus, sdh))) {
5162 DHD_ERROR(("%s: dhdsdio_probe_malloc failed\n", __func__));
5163 goto fail;
5164 }
5165
5166 if (!(dhdsdio_probe_init(bus, sdh))) {
5167 DHD_ERROR(("%s: dhdsdio_probe_init failed\n", __func__));
5168 goto fail;
5169 }
5170
5171 /* Register interrupt callback, but mask it (not operational yet). */
5172 DHD_INTR(("%s: disable SDIO interrupts (not interested yet)\n",
5173 __func__));
5174 bcmsdh_intr_disable(sdh);
5175 ret = bcmsdh_intr_reg(sdh, dhdsdio_isr, bus);
5176 if (ret != 0) {
5177 DHD_ERROR(("%s: FAILED: bcmsdh_intr_reg returned %d\n",
5178 __func__, ret));
5179 goto fail;
5180 }
5181 DHD_INTR(("%s: registered SDIO interrupt function ok\n", __func__));
5182
5183 DHD_INFO(("%s: completed!!\n", __func__));
5184
5185 /* if firmware path present try to download and bring up bus */
5186 ret = dhd_bus_start(bus->dhd);
5187 if (ret != 0) {
5188 if (ret == BCME_NOTUP) {
5189 DHD_ERROR(("%s: dongle is not responding\n", __func__));
5190 goto fail;
5191 }
5192 }
5193 /* Ok, have the per-port tell the stack we're open for business */
5194 if (dhd_net_attach(bus->dhd, 0) != 0) {
5195 DHD_ERROR(("%s: Net attach failed!!\n", __func__));
5196 goto fail;
5197 }
5198
5199 return bus;
5200
5201 fail:
5202 dhdsdio_release(bus);
5203 return NULL;
5204 }
5205
5206 static bool
5207 dhdsdio_probe_attach(struct dhd_bus *bus, void *sdh, void *regsva, u16 devid)
5208 {
5209 u8 clkctl = 0;
5210 int err = 0;
5211
5212 bus->alp_only = true;
5213
5214 /* Return the window to backplane enumeration space for core access */
5215 if (dhdsdio_set_siaddr_window(bus, SI_ENUM_BASE))
5216 DHD_ERROR(("%s: FAILED to return to SI_ENUM_BASE\n", __func__));
5217
5218 #ifdef DHD_DEBUG
5219 printk(KERN_DEBUG "F1 signature read @0x18000000=0x%4x\n",
5220 bcmsdh_reg_read(bus->sdh, SI_ENUM_BASE, 4));
5221
5222 #endif /* DHD_DEBUG */
5223
5224 /* Force PLL off until si_attach() programs PLL control regs */
5225
5226 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
5227 DHD_INIT_CLKCTL1, &err);
5228 if (!err)
5229 clkctl =
5230 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
5231 &err);
5232
5233 if (err || ((clkctl & ~SBSDIO_AVBITS) != DHD_INIT_CLKCTL1)) {
5234 DHD_ERROR(("dhdsdio_probe: ChipClkCSR access: err %d wrote "
5235 "0x%02x read 0x%02x\n",
5236 err, DHD_INIT_CLKCTL1, clkctl));
5237 goto fail;
5238 }
5239 #ifdef DHD_DEBUG
5240 if (DHD_INFO_ON()) {
5241 uint fn, numfn;
5242 u8 *cis[SDIOD_MAX_IOFUNCS];
5243 int err = 0;
5244
5245 numfn = bcmsdh_query_iofnum(sdh);
5246 ASSERT(numfn <= SDIOD_MAX_IOFUNCS);
5247
5248 /* Make sure ALP is available before trying to read CIS */
5249 SPINWAIT(((clkctl = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
5250 SBSDIO_FUNC1_CHIPCLKCSR,
5251 NULL)),
5252 !SBSDIO_ALPAV(clkctl)), PMU_MAX_TRANSITION_DLY);
5253
5254 /* Now request ALP be put on the bus */
5255 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
5256 DHD_INIT_CLKCTL2, &err);
5257 udelay(65);
5258
5259 for (fn = 0; fn <= numfn; fn++) {
5260 cis[fn] = kzalloc(SBSDIO_CIS_SIZE_LIMIT, GFP_ATOMIC);
5261 if (!cis[fn]) {
5262 DHD_INFO(("dhdsdio_probe: fn %d cis malloc "
5263 "failed\n", fn));
5264 break;
5265 }
5266
5267 err = bcmsdh_cis_read(sdh, fn, cis[fn],
5268 SBSDIO_CIS_SIZE_LIMIT);
5269 if (err) {
5270 DHD_INFO(("dhdsdio_probe: fn %d cis read "
5271 "err %d\n", fn, err));
5272 kfree(cis[fn]);
5273 break;
5274 }
5275 dhd_dump_cis(fn, cis[fn]);
5276 }
5277
5278 while (fn-- > 0) {
5279 ASSERT(cis[fn]);
5280 kfree(cis[fn]);
5281 }
5282
5283 if (err) {
5284 DHD_ERROR(("dhdsdio_probe: error read/parsing CIS\n"));
5285 goto fail;
5286 }
5287 }
5288 #endif /* DHD_DEBUG */
5289
5290 /* si_attach() will provide an SI handle and scan the backplane */
5291 bus->sih = si_attach((uint) devid, regsva, DHD_BUS, sdh,
5292 &bus->vars, &bus->varsz);
5293 if (!(bus->sih)) {
5294 DHD_ERROR(("%s: si_attach failed!\n", __func__));
5295 goto fail;
5296 }
5297
5298 bcmsdh_chipinfo(sdh, bus->sih->chip, bus->sih->chiprev);
5299
5300 if (!dhdsdio_chipmatch((u16) bus->sih->chip)) {
5301 DHD_ERROR(("%s: unsupported chip: 0x%04x\n",
5302 __func__, bus->sih->chip));
5303 goto fail;
5304 }
5305
5306 si_sdiod_drive_strength_init(bus->sih, dhd_sdiod_drive_strength);
5307
5308 /* Get info on the ARM and SOCRAM cores... */
5309 if (!DHD_NOPMU(bus)) {
5310 if ((si_setcore(bus->sih, ARM7S_CORE_ID, 0)) ||
5311 (si_setcore(bus->sih, ARMCM3_CORE_ID, 0))) {
5312 bus->armrev = si_corerev(bus->sih);
5313 } else {
5314 DHD_ERROR(("%s: failed to find ARM core!\n", __func__));
5315 goto fail;
5316 }
5317 bus->orig_ramsize = si_socram_size(bus->sih);
5318 if (!(bus->orig_ramsize)) {
5319 DHD_ERROR(("%s: failed to find SOCRAM memory!\n",
5320 __func__));
5321 goto fail;
5322 }
5323 bus->ramsize = bus->orig_ramsize;
5324 if (dhd_dongle_memsize)
5325 dhd_dongle_setmemsize(bus, dhd_dongle_memsize);
5326
5327 DHD_ERROR(("DHD: dongle ram size is set to %d(orig %d)\n",
5328 bus->ramsize, bus->orig_ramsize));
5329 }
5330
5331 /* ...but normally deal with the SDPCMDEV core */
5332 bus->regs = si_setcore(bus->sih, PCMCIA_CORE_ID, 0);
5333 if (!bus->regs) {
5334 bus->regs = si_setcore(bus->sih, SDIOD_CORE_ID, 0);
5335 if (!bus->regs) {
5336 DHD_ERROR(("%s: failed to find SDIODEV core!\n",
5337 __func__));
5338 goto fail;
5339 }
5340 }
5341 bus->sdpcmrev = si_corerev(bus->sih);
5342
5343 /* Set core control so an SDIO reset does a backplane reset */
5344 OR_REG(&bus->regs->corecontrol, CC_BPRESEN);
5345
5346 pktq_init(&bus->txq, (PRIOMASK + 1), TXQLEN);
5347
5348 /* Locate an appropriately-aligned portion of hdrbuf */
5349 bus->rxhdr = (u8 *) roundup((unsigned long)&bus->hdrbuf[0], DHD_SDALIGN);
5350
5351 /* Set the poll and/or interrupt flags */
5352 bus->intr = (bool) dhd_intr;
5353 bus->poll = (bool) dhd_poll;
5354 if (bus->poll)
5355 bus->pollrate = 1;
5356
5357 return true;
5358
5359 fail:
5360 return false;
5361 }
5362
5363 static bool dhdsdio_probe_malloc(dhd_bus_t *bus, void *sdh)
5364 {
5365 DHD_TRACE(("%s: Enter\n", __func__));
5366
5367 if (bus->dhd->maxctl) {
5368 bus->rxblen =
5369 roundup((bus->dhd->maxctl + SDPCM_HDRLEN),
5370 ALIGNMENT) + DHD_SDALIGN;
5371 bus->rxbuf = kmalloc(bus->rxblen, GFP_ATOMIC);
5372 if (!(bus->rxbuf)) {
5373 DHD_ERROR(("%s: kmalloc of %d-byte rxbuf failed\n",
5374 __func__, bus->rxblen));
5375 goto fail;
5376 }
5377 }
5378
5379 /* Allocate buffer to receive glomed packet */
5380 bus->databuf = kmalloc(MAX_DATA_BUF, GFP_ATOMIC);
5381 if (!(bus->databuf)) {
5382 DHD_ERROR(("%s: kmalloc of %d-byte databuf failed\n",
5383 __func__, MAX_DATA_BUF));
5384 /* release rxbuf which was already located as above */
5385 if (!bus->rxblen)
5386 kfree(bus->rxbuf);
5387 goto fail;
5388 }
5389
5390 /* Align the buffer */
5391 if ((unsigned long)bus->databuf % DHD_SDALIGN)
5392 bus->dataptr =
5393 bus->databuf + (DHD_SDALIGN -
5394 ((unsigned long)bus->databuf % DHD_SDALIGN));
5395 else
5396 bus->dataptr = bus->databuf;
5397
5398 return true;
5399
5400 fail:
5401 return false;
5402 }
5403
5404 static bool dhdsdio_probe_init(dhd_bus_t *bus, void *sdh)
5405 {
5406 s32 fnum;
5407
5408 DHD_TRACE(("%s: Enter\n", __func__));
5409
5410 #ifdef SDTEST
5411 dhdsdio_pktgen_init(bus);
5412 #endif /* SDTEST */
5413
5414 /* Disable F2 to clear any intermediate frame state on the dongle */
5415 bcmsdh_cfg_write(sdh, SDIO_FUNC_0, SDIOD_CCCR_IOEN, SDIO_FUNC_ENABLE_1,
5416 NULL);
5417
5418 bus->dhd->busstate = DHD_BUS_DOWN;
5419 bus->sleeping = false;
5420 bus->rxflow = false;
5421 bus->prev_rxlim_hit = 0;
5422
5423 /* Done with backplane-dependent accesses, can drop clock... */
5424 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
5425
5426 /* ...and initialize clock/power states */
5427 bus->clkstate = CLK_SDONLY;
5428 bus->idletime = (s32) dhd_idletime;
5429 bus->idleclock = DHD_IDLE_ACTIVE;
5430
5431 /* Query the SD clock speed */
5432 if (bcmsdh_iovar_op(sdh, "sd_divisor", NULL, 0,
5433 &bus->sd_divisor, sizeof(s32),
5434 false) != BCME_OK) {
5435 DHD_ERROR(("%s: fail on %s get\n", __func__, "sd_divisor"));
5436 bus->sd_divisor = -1;
5437 } else {
5438 DHD_INFO(("%s: Initial value for %s is %d\n",
5439 __func__, "sd_divisor", bus->sd_divisor));
5440 }
5441
5442 /* Query the SD bus mode */
5443 if (bcmsdh_iovar_op(sdh, "sd_mode", NULL, 0,
5444 &bus->sd_mode, sizeof(s32), false) != BCME_OK) {
5445 DHD_ERROR(("%s: fail on %s get\n", __func__, "sd_mode"));
5446 bus->sd_mode = -1;
5447 } else {
5448 DHD_INFO(("%s: Initial value for %s is %d\n",
5449 __func__, "sd_mode", bus->sd_mode));
5450 }
5451
5452 /* Query the F2 block size, set roundup accordingly */
5453 fnum = 2;
5454 if (bcmsdh_iovar_op(sdh, "sd_blocksize", &fnum, sizeof(s32),
5455 &bus->blocksize, sizeof(s32), false) != BCME_OK) {
5456 bus->blocksize = 0;
5457 DHD_ERROR(("%s: fail on %s get\n", __func__, "sd_blocksize"));
5458 } else {
5459 DHD_INFO(("%s: Initial value for %s is %d\n",
5460 __func__, "sd_blocksize", bus->blocksize));
5461 }
5462 bus->roundup = min(max_roundup, bus->blocksize);
5463
5464 /* Query if bus module supports packet chaining,
5465 default to use if supported */
5466 if (bcmsdh_iovar_op(sdh, "sd_rxchain", NULL, 0,
5467 &bus->sd_rxchain, sizeof(s32),
5468 false) != BCME_OK) {
5469 bus->sd_rxchain = false;
5470 } else {
5471 DHD_INFO(("%s: bus module (through bcmsdh API) %s chaining\n",
5472 __func__,
5473 (bus->sd_rxchain ? "supports" : "does not support")));
5474 }
5475 bus->use_rxchain = (bool) bus->sd_rxchain;
5476
5477 return true;
5478 }
5479
5480 bool
5481 dhd_bus_download_firmware(struct dhd_bus *bus, char *fw_path, char *nv_path)
5482 {
5483 bool ret;
5484 bus->fw_path = fw_path;
5485 bus->nv_path = nv_path;
5486
5487 ret = dhdsdio_download_firmware(bus, bus->sdh);
5488
5489 return ret;
5490 }
5491
5492 static bool
5493 dhdsdio_download_firmware(struct dhd_bus *bus, void *sdh)
5494 {
5495 bool ret;
5496
5497 /* Download the firmware */
5498 dhdsdio_clkctl(bus, CLK_AVAIL, false);
5499
5500 ret = _dhdsdio_download_firmware(bus) == 0;
5501
5502 dhdsdio_clkctl(bus, CLK_SDONLY, false);
5503
5504 return ret;
5505 }
5506
5507 /* Detach and free everything */
5508 static void dhdsdio_release(dhd_bus_t *bus)
5509 {
5510 DHD_TRACE(("%s: Enter\n", __func__));
5511
5512 if (bus) {
5513 /* De-register interrupt handler */
5514 bcmsdh_intr_disable(bus->sdh);
5515 bcmsdh_intr_dereg(bus->sdh);
5516
5517 if (bus->dhd) {
5518
5519 dhdsdio_release_dongle(bus);
5520
5521 dhd_detach(bus->dhd);
5522 bus->dhd = NULL;
5523 }
5524
5525 dhdsdio_release_malloc(bus);
5526
5527 kfree(bus);
5528 }
5529
5530 DHD_TRACE(("%s: Disconnected\n", __func__));
5531 }
5532
5533 static void dhdsdio_release_malloc(dhd_bus_t *bus)
5534 {
5535 DHD_TRACE(("%s: Enter\n", __func__));
5536
5537 if (bus->dhd && bus->dhd->dongle_reset)
5538 return;
5539
5540 if (bus->rxbuf) {
5541 kfree(bus->rxbuf);
5542 bus->rxctl = bus->rxbuf = NULL;
5543 bus->rxlen = 0;
5544 }
5545
5546 if (bus->databuf) {
5547 kfree(bus->databuf);
5548 bus->databuf = NULL;
5549 }
5550 }
5551
5552 static void dhdsdio_release_dongle(dhd_bus_t *bus)
5553 {
5554 DHD_TRACE(("%s: Enter\n", __func__));
5555
5556 if (bus->dhd && bus->dhd->dongle_reset)
5557 return;
5558
5559 if (bus->sih) {
5560 dhdsdio_clkctl(bus, CLK_AVAIL, false);
5561 #if !defined(BCMLXSDMMC)
5562 si_watchdog(bus->sih, 4);
5563 #endif /* !defined(BCMLXSDMMC) */
5564 dhdsdio_clkctl(bus, CLK_NONE, false);
5565 si_detach(bus->sih);
5566 if (bus->vars && bus->varsz)
5567 kfree(bus->vars);
5568 bus->vars = NULL;
5569 }
5570
5571 DHD_TRACE(("%s: Disconnected\n", __func__));
5572 }
5573
5574 static void dhdsdio_disconnect(void *ptr)
5575 {
5576 dhd_bus_t *bus = (dhd_bus_t *)ptr;
5577
5578 DHD_TRACE(("%s: Enter\n", __func__));
5579
5580 if (bus) {
5581 ASSERT(bus->dhd);
5582 dhdsdio_release(bus);
5583 }
5584
5585 DHD_TRACE(("%s: Disconnected\n", __func__));
5586 }
5587
5588 /* Register/Unregister functions are called by the main DHD entry
5589 * point (e.g. module insertion) to link with the bus driver, in
5590 * order to look for or await the device.
5591 */
5592
5593 static bcmsdh_driver_t dhd_sdio = {
5594 dhdsdio_probe,
5595 dhdsdio_disconnect
5596 };
5597
5598 int dhd_bus_register(void)
5599 {
5600 DHD_TRACE(("%s: Enter\n", __func__));
5601
5602 return bcmsdh_register(&dhd_sdio);
5603 }
5604
5605 void dhd_bus_unregister(void)
5606 {
5607 DHD_TRACE(("%s: Enter\n", __func__));
5608
5609 bcmsdh_unregister();
5610 }
5611
5612 #ifdef BCMEMBEDIMAGE
5613 static int dhdsdio_download_code_array(struct dhd_bus *bus)
5614 {
5615 int bcmerror = -1;
5616 int offset = 0;
5617
5618 DHD_INFO(("%s: download embedded firmware...\n", __func__));
5619
5620 /* Download image */
5621 while ((offset + MEMBLOCK) < sizeof(dlarray)) {
5622 bcmerror =
5623 dhdsdio_membytes(bus, true, offset, dlarray + offset,
5624 MEMBLOCK);
5625 if (bcmerror) {
5626 DHD_ERROR(("%s: error %d on writing %d membytes at "
5627 "0x%08x\n",
5628 __func__, bcmerror, MEMBLOCK, offset));
5629 goto err;
5630 }
5631
5632 offset += MEMBLOCK;
5633 }
5634
5635 if (offset < sizeof(dlarray)) {
5636 bcmerror = dhdsdio_membytes(bus, true, offset,
5637 dlarray + offset,
5638 sizeof(dlarray) - offset);
5639 if (bcmerror) {
5640 DHD_ERROR(("%s: error %d on writing %d membytes at "
5641 "0x%08x\n", __func__, bcmerror,
5642 sizeof(dlarray) - offset, offset));
5643 goto err;
5644 }
5645 }
5646 #ifdef DHD_DEBUG
5647 /* Upload and compare the downloaded code */
5648 {
5649 unsigned char *ularray;
5650
5651 ularray = kmalloc(bus->ramsize, GFP_ATOMIC);
5652 /* Upload image to verify downloaded contents. */
5653 offset = 0;
5654 memset(ularray, 0xaa, bus->ramsize);
5655 while ((offset + MEMBLOCK) < sizeof(dlarray)) {
5656 bcmerror =
5657 dhdsdio_membytes(bus, false, offset,
5658 ularray + offset, MEMBLOCK);
5659 if (bcmerror) {
5660 DHD_ERROR(("%s: error %d on reading %d membytes"
5661 " at 0x%08x\n",
5662 __func__, bcmerror, MEMBLOCK, offset));
5663 goto err;
5664 }
5665
5666 offset += MEMBLOCK;
5667 }
5668
5669 if (offset < sizeof(dlarray)) {
5670 bcmerror = dhdsdio_membytes(bus, false, offset,
5671 ularray + offset,
5672 sizeof(dlarray) - offset);
5673 if (bcmerror) {
5674 DHD_ERROR(("%s: error %d on reading %d membytes at 0x%08x\n",
5675 __func__, bcmerror,
5676 sizeof(dlarray) - offset, offset));
5677 goto err;
5678 }
5679 }
5680
5681 if (memcmp(dlarray, ularray, sizeof(dlarray))) {
5682 DHD_ERROR(("%s: Downloaded image is corrupted.\n",
5683 __func__));
5684 ASSERT(0);
5685 goto err;
5686 } else
5687 DHD_ERROR(("%s: Download/Upload/Compare succeeded.\n",
5688 __func__));
5689
5690 kfree(ularray);
5691 }
5692 #endif /* DHD_DEBUG */
5693
5694 err:
5695 return bcmerror;
5696 }
5697 #endif /* BCMEMBEDIMAGE */
5698
5699 static int dhdsdio_download_code_file(struct dhd_bus *bus, char *fw_path)
5700 {
5701 int bcmerror = -1;
5702 int offset = 0;
5703 uint len;
5704 void *image = NULL;
5705 u8 *memblock = NULL, *memptr;
5706
5707 DHD_INFO(("%s: download firmware %s\n", __func__, fw_path));
5708
5709 image = dhd_os_open_image(fw_path);
5710 if (image == NULL)
5711 goto err;
5712
5713 memptr = memblock = kmalloc(MEMBLOCK + DHD_SDALIGN, GFP_ATOMIC);
5714 if (memblock == NULL) {
5715 DHD_ERROR(("%s: Failed to allocate memory %d bytes\n",
5716 __func__, MEMBLOCK));
5717 goto err;
5718 }
5719 if ((u32)(unsigned long)memblock % DHD_SDALIGN)
5720 memptr +=
5721 (DHD_SDALIGN - ((u32)(unsigned long)memblock % DHD_SDALIGN));
5722
5723 /* Download image */
5724 while ((len =
5725 dhd_os_get_image_block((char *)memptr, MEMBLOCK, image))) {
5726 bcmerror = dhdsdio_membytes(bus, true, offset, memptr, len);
5727 if (bcmerror) {
5728 DHD_ERROR(("%s: error %d on writing %d membytes at "
5729 "0x%08x\n", __func__, bcmerror, MEMBLOCK, offset));
5730 goto err;
5731 }
5732
5733 offset += MEMBLOCK;
5734 }
5735
5736 err:
5737 if (memblock)
5738 kfree(memblock);
5739
5740 if (image)
5741 dhd_os_close_image(image);
5742
5743 return bcmerror;
5744 }
5745
5746 /*
5747 * ProcessVars:Takes a buffer of "<var>=<value>\n" lines read from a file
5748 * and ending in a NUL.
5749 * Removes carriage returns, empty lines, comment lines, and converts
5750 * newlines to NULs.
5751 * Shortens buffer as needed and pads with NULs. End of buffer is marked
5752 * by two NULs.
5753 */
5754
5755 static uint process_nvram_vars(char *varbuf, uint len)
5756 {
5757 char *dp;
5758 bool findNewline;
5759 int column;
5760 uint buf_len, n;
5761
5762 dp = varbuf;
5763
5764 findNewline = false;
5765 column = 0;
5766
5767 for (n = 0; n < len; n++) {
5768 if (varbuf[n] == 0)
5769 break;
5770 if (varbuf[n] == '\r')
5771 continue;
5772 if (findNewline && varbuf[n] != '\n')
5773 continue;
5774 findNewline = false;
5775 if (varbuf[n] == '#') {
5776 findNewline = true;
5777 continue;
5778 }
5779 if (varbuf[n] == '\n') {
5780 if (column == 0)
5781 continue;
5782 *dp++ = 0;
5783 column = 0;
5784 continue;
5785 }
5786 *dp++ = varbuf[n];
5787 column++;
5788 }
5789 buf_len = dp - varbuf;
5790
5791 while (dp < varbuf + n)
5792 *dp++ = 0;
5793
5794 return buf_len;
5795 }
5796
5797 /*
5798 EXAMPLE: nvram_array
5799 nvram_arry format:
5800 name=value
5801 Use carriage return at the end of each assignment,
5802 and an empty string with
5803 carriage return at the end of array.
5804
5805 For example:
5806 unsigned char nvram_array[] = {"name1=value1\n",
5807 "name2=value2\n", "\n"};
5808 Hex values start with 0x, and mac addr format: xx:xx:xx:xx:xx:xx.
5809
5810 Search "EXAMPLE: nvram_array" to see how the array is activated.
5811 */
5812
5813 void dhd_bus_set_nvram_params(struct dhd_bus *bus, const char *nvram_params)
5814 {
5815 bus->nvram_params = nvram_params;
5816 }
5817
5818 static int dhdsdio_download_nvram(struct dhd_bus *bus)
5819 {
5820 int bcmerror = -1;
5821 uint len;
5822 void *image = NULL;
5823 char *memblock = NULL;
5824 char *bufp;
5825 char *nv_path;
5826 bool nvram_file_exists;
5827
5828 nv_path = bus->nv_path;
5829
5830 nvram_file_exists = ((nv_path != NULL) && (nv_path[0] != '\0'));
5831 if (!nvram_file_exists && (bus->nvram_params == NULL))
5832 return 0;
5833
5834 if (nvram_file_exists) {
5835 image = dhd_os_open_image(nv_path);
5836 if (image == NULL)
5837 goto err;
5838 }
5839
5840 memblock = kmalloc(MEMBLOCK, GFP_ATOMIC);
5841 if (memblock == NULL) {
5842 DHD_ERROR(("%s: Failed to allocate memory %d bytes\n",
5843 __func__, MEMBLOCK));
5844 goto err;
5845 }
5846
5847 /* Download variables */
5848 if (nvram_file_exists) {
5849 len = dhd_os_get_image_block(memblock, MEMBLOCK, image);
5850 } else {
5851 len = strlen(bus->nvram_params);
5852 ASSERT(len <= MEMBLOCK);
5853 if (len > MEMBLOCK)
5854 len = MEMBLOCK;
5855 memcpy(memblock, bus->nvram_params, len);
5856 }
5857
5858 if (len > 0 && len < MEMBLOCK) {
5859 bufp = (char *)memblock;
5860 bufp[len] = 0;
5861 len = process_nvram_vars(bufp, len);
5862 bufp += len;
5863 *bufp++ = 0;
5864 if (len)
5865 bcmerror = dhdsdio_downloadvars(bus, memblock, len + 1);
5866 if (bcmerror) {
5867 DHD_ERROR(("%s: error downloading vars: %d\n",
5868 __func__, bcmerror));
5869 }
5870 } else {
5871 DHD_ERROR(("%s: error reading nvram file: %d\n",
5872 __func__, len));
5873 bcmerror = BCME_SDIO_ERROR;
5874 }
5875
5876 err:
5877 if (memblock)
5878 kfree(memblock);
5879
5880 if (image)
5881 dhd_os_close_image(image);
5882
5883 return bcmerror;
5884 }
5885
5886 static int _dhdsdio_download_firmware(struct dhd_bus *bus)
5887 {
5888 int bcmerror = -1;
5889
5890 bool embed = false; /* download embedded firmware */
5891 bool dlok = false; /* download firmware succeeded */
5892
5893 /* Out immediately if no image to download */
5894 if ((bus->fw_path == NULL) || (bus->fw_path[0] == '\0')) {
5895 #ifdef BCMEMBEDIMAGE
5896 embed = true;
5897 #else
5898 return bcmerror;
5899 #endif
5900 }
5901
5902 /* Keep arm in reset */
5903 if (dhdsdio_download_state(bus, true)) {
5904 DHD_ERROR(("%s: error placing ARM core in reset\n", __func__));
5905 goto err;
5906 }
5907
5908 /* External image takes precedence if specified */
5909 if ((bus->fw_path != NULL) && (bus->fw_path[0] != '\0')) {
5910 if (dhdsdio_download_code_file(bus, bus->fw_path)) {
5911 DHD_ERROR(("%s: dongle image file download failed\n",
5912 __func__));
5913 #ifdef BCMEMBEDIMAGE
5914 embed = true;
5915 #else
5916 goto err;
5917 #endif
5918 } else {
5919 embed = false;
5920 dlok = true;
5921 }
5922 }
5923 #ifdef BCMEMBEDIMAGE
5924 if (embed) {
5925 if (dhdsdio_download_code_array(bus)) {
5926 DHD_ERROR(("%s: dongle image array download failed\n",
5927 __func__));
5928 goto err;
5929 } else {
5930 dlok = true;
5931 }
5932 }
5933 #endif
5934 if (!dlok) {
5935 DHD_ERROR(("%s: dongle image download failed\n", __func__));
5936 goto err;
5937 }
5938
5939 /* EXAMPLE: nvram_array */
5940 /* If a valid nvram_arry is specified as above, it can be passed
5941 down to dongle */
5942 /* dhd_bus_set_nvram_params(bus, (char *)&nvram_array); */
5943
5944 /* External nvram takes precedence if specified */
5945 if (dhdsdio_download_nvram(bus)) {
5946 DHD_ERROR(("%s: dongle nvram file download failed\n",
5947 __func__));
5948 }
5949
5950 /* Take arm out of reset */
5951 if (dhdsdio_download_state(bus, false)) {
5952 DHD_ERROR(("%s: error getting out of ARM core reset\n",
5953 __func__));
5954 goto err;
5955 }
5956
5957 bcmerror = 0;
5958
5959 err:
5960 return bcmerror;
5961 }
5962
5963 static int
5964 dhd_bcmsdh_recv_buf(dhd_bus_t *bus, u32 addr, uint fn, uint flags,
5965 u8 *buf, uint nbytes, struct sk_buff *pkt,
5966 bcmsdh_cmplt_fn_t complete, void *handle)
5967 {
5968 int status;
5969
5970 /* 4329: GSPI check */
5971 status =
5972 bcmsdh_recv_buf(bus->sdh, addr, fn, flags, buf, nbytes, pkt,
5973 complete, handle);
5974 return status;
5975 }
5976
5977 static int
5978 dhd_bcmsdh_send_buf(dhd_bus_t *bus, u32 addr, uint fn, uint flags,
5979 u8 *buf, uint nbytes, struct sk_buff *pkt,
5980 bcmsdh_cmplt_fn_t complete, void *handle)
5981 {
5982 return bcmsdh_send_buf
5983 (bus->sdh, addr, fn, flags, buf, nbytes, pkt, complete,
5984 handle);
5985 }
5986
5987 uint dhd_bus_chip(struct dhd_bus *bus)
5988 {
5989 ASSERT(bus->sih != NULL);
5990 return bus->sih->chip;
5991 }
5992
5993 void *dhd_bus_pub(struct dhd_bus *bus)
5994 {
5995 return bus->dhd;
5996 }
5997
5998 void *dhd_bus_txq(struct dhd_bus *bus)
5999 {
6000 return &bus->txq;
6001 }
6002
6003 uint dhd_bus_hdrlen(struct dhd_bus *bus)
6004 {
6005 return SDPCM_HDRLEN;
6006 }
6007
6008 int dhd_bus_devreset(dhd_pub_t *dhdp, u8 flag)
6009 {
6010 int bcmerror = 0;
6011 dhd_bus_t *bus;
6012
6013 bus = dhdp->bus;
6014
6015 if (flag == true) {
6016 if (!bus->dhd->dongle_reset) {
6017 /* Expect app to have torn down any
6018 connection before calling */
6019 /* Stop the bus, disable F2 */
6020 dhd_bus_stop(bus, false);
6021
6022 /* Clean tx/rx buffer pointers,
6023 detach from the dongle */
6024 dhdsdio_release_dongle(bus);
6025
6026 bus->dhd->dongle_reset = true;
6027 bus->dhd->up = false;
6028
6029 DHD_TRACE(("%s: WLAN OFF DONE\n", __func__));
6030 /* App can now remove power from device */
6031 } else
6032 bcmerror = BCME_SDIO_ERROR;
6033 } else {
6034 /* App must have restored power to device before calling */
6035
6036 DHD_TRACE(("\n\n%s: == WLAN ON ==\n", __func__));
6037
6038 if (bus->dhd->dongle_reset) {
6039 /* Turn on WLAN */
6040 /* Reset SD client */
6041 bcmsdh_reset(bus->sdh);
6042
6043 /* Attempt to re-attach & download */
6044 if (dhdsdio_probe_attach(bus, bus->sdh,
6045 (u32 *) SI_ENUM_BASE,
6046 bus->cl_devid)) {
6047 /* Attempt to download binary to the dongle */
6048 if (dhdsdio_probe_init
6049 (bus, bus->sdh)
6050 && dhdsdio_download_firmware(bus,
6051 bus->sdh)) {
6052
6053 /* Re-init bus, enable F2 transfer */
6054 dhd_bus_init((dhd_pub_t *) bus->dhd,
6055 false);
6056
6057 #if defined(OOB_INTR_ONLY)
6058 dhd_enable_oob_intr(bus, true);
6059 #endif /* defined(OOB_INTR_ONLY) */
6060
6061 bus->dhd->dongle_reset = false;
6062 bus->dhd->up = true;
6063
6064 DHD_TRACE(("%s: WLAN ON DONE\n",
6065 __func__));
6066 } else
6067 bcmerror = BCME_SDIO_ERROR;
6068 } else
6069 bcmerror = BCME_SDIO_ERROR;
6070 } else {
6071 bcmerror = BCME_NOTDOWN;
6072 DHD_ERROR(("%s: Set DEVRESET=false invoked when device "
6073 "is on\n", __func__));
6074 bcmerror = BCME_SDIO_ERROR;
6075 }
6076 }
6077 return bcmerror;
6078 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree