drivers/usb/host/isp1760-hcd.h

   1 #ifndef _ISP1760_HCD_H_
   2 #define _ISP1760_HCD_H_
   3
   4 /* exports for if */
   5 struct usb_hcd *isp1760_register(phys_addr_t res_start, resource_size_t res_len,
   6                                  int irq, unsigned long irqflags,
   7                                  struct device *dev, const char *busname,
   8                                  unsigned int devflags);
   9 int init_kmem_once(void);
  10 void deinit_kmem_cache(void);
  11
  12 /* EHCI capability registers */
  13 #define HC_CAPLENGTH            0x00
  14 #define HC_HCSPARAMS            0x04
  15 #define HC_HCCPARAMS            0x08
  16
  17 /* EHCI operational registers */
  18 #define HC_USBCMD               0x20
  19 #define HC_USBSTS               0x24
  20 #define HC_FRINDEX              0x2c
  21 #define HC_CONFIGFLAG           0x60
  22 #define HC_PORTSC1              0x64
  23 #define HC_ISO_PTD_DONEMAP_REG  0x130
  24 #define HC_ISO_PTD_SKIPMAP_REG  0x134
  25 #define HC_ISO_PTD_LASTPTD_REG  0x138
  26 #define HC_INT_PTD_DONEMAP_REG  0x140
  27 #define HC_INT_PTD_SKIPMAP_REG  0x144
  28 #define HC_INT_PTD_LASTPTD_REG  0x148
  29 #define HC_ATL_PTD_DONEMAP_REG  0x150
  30 #define HC_ATL_PTD_SKIPMAP_REG  0x154
  31 #define HC_ATL_PTD_LASTPTD_REG  0x158
  32
  33 /* Configuration Register */
  34 #define HC_HW_MODE_CTRL         0x300
  35 #define ALL_ATX_RESET           (1 << 31)
  36 #define HW_ANA_DIGI_OC          (1 << 15)
  37 #define HW_DATA_BUS_32BIT       (1 << 8)
  38 #define HW_DACK_POL_HIGH        (1 << 6)
  39 #define HW_DREQ_POL_HIGH        (1 << 5)
  40 #define HW_INTR_HIGH_ACT        (1 << 2)
  41 #define HW_INTR_EDGE_TRIG       (1 << 1)
  42 #define HW_GLOBAL_INTR_EN       (1 << 0)
  43
  44 #define HC_CHIP_ID_REG          0x304
  45 #define HC_SCRATCH_REG          0x308
  46
  47 #define HC_RESET_REG            0x30c
  48 #define SW_RESET_RESET_HC       (1 << 1)
  49 #define SW_RESET_RESET_ALL      (1 << 0)
  50
  51 #define HC_BUFFER_STATUS_REG    0x334
  52 #define ATL_BUFFER              0x1
  53 #define INT_BUFFER              0x2
  54 #define ISO_BUFFER              0x4
  55 #define BUFFER_MAP              0x7
  56
  57 #define HC_MEMORY_REG           0x33c
  58 #define ISP_BANK(x)             ((x) << 16)
  59
  60 #define HC_PORT1_CTRL           0x374
  61 #define PORT1_POWER             (3 << 3)
  62 #define PORT1_INIT1             (1 << 7)
  63 #define PORT1_INIT2             (1 << 23)
  64 #define HW_OTG_CTRL_SET         0x374
  65 #define HW_OTG_CTRL_CLR         0x376
  66
  67 /* Interrupt Register */
  68 #define HC_INTERRUPT_REG        0x310
  69
  70 #define HC_INTERRUPT_ENABLE     0x314
  71 #define INTERRUPT_ENABLE_MASK   (HC_INTL_INT | HC_ATL_INT | HC_EOT_INT)
  72 #define INTERRUPT_ENABLE_SOT_MASK       (HC_INTL_INT | HC_SOT_INT | HC_EOT_INT)
  73
  74 #define HC_ISO_INT              (1 << 9)
  75 #define HC_ATL_INT              (1 << 8)
  76 #define HC_INTL_INT             (1 << 7)
  77 #define HC_EOT_INT              (1 << 3)
  78 #define HC_SOT_INT              (1 << 1)
  79
  80 #define HC_ISO_IRQ_MASK_OR_REG  0x318
  81 #define HC_INT_IRQ_MASK_OR_REG  0x31C
  82 #define HC_ATL_IRQ_MASK_OR_REG  0x320
  83 #define HC_ISO_IRQ_MASK_AND_REG 0x324
  84 #define HC_INT_IRQ_MASK_AND_REG 0x328
  85 #define HC_ATL_IRQ_MASK_AND_REG 0x32C
  86
  87 /* urb state*/
  88 #define DELETE_URB              (0x0008)
  89 #define NO_TRANSFER_ACTIVE      (0xffffffff)
  90
  91 /* Philips Proprietary Transfer Descriptor (PTD) */
  92 typedef __u32 __bitwise __dw;
  93 struct ptd {
  94         __dw dw0;
  95         __dw dw1;
  96         __dw dw2;
  97         __dw dw3;
  98         __dw dw4;
  99         __dw dw5;
 100         __dw dw6;
 101         __dw dw7;
 102 };
 103 #define PTD_OFFSET              0x0400
 104 #define ISO_PTD_OFFSET          0x0400
 105 #define INT_PTD_OFFSET          0x0800
 106 #define ATL_PTD_OFFSET          0x0c00
 107 #define PAYLOAD_OFFSET          0x1000
 108
 109 struct inter_packet_info {
 110         struct isp1760_qh *qh;
 111         struct isp1760_qtd *qtd;
 112 };
 113
 114
 115 typedef void (packet_enqueue)(struct usb_hcd *hcd, struct isp1760_qh *qh,
 116                 struct isp1760_qtd *qtd);
 117
 118 /*
 119  * Device flags that can vary from board to board.  All of these
 120  * indicate the most "atypical" case, so that a devflags of 0 is
 121  * a sane default configuration.
 122  */
 123 #define ISP1760_FLAG_BUS_WIDTH_16       0x00000002 /* 16-bit data bus width */
 124 #define ISP1760_FLAG_OTG_EN             0x00000004 /* Port 1 supports OTG */
 125 #define ISP1760_FLAG_ANALOG_OC          0x00000008 /* Analog overcurrent */
 126 #define ISP1760_FLAG_DACK_POL_HIGH      0x00000010 /* DACK active high */
 127 #define ISP1760_FLAG_DREQ_POL_HIGH      0x00000020 /* DREQ active high */
 128 #define ISP1760_FLAG_ISP1761            0x00000040 /* Chip is ISP1761 */
 129 #define ISP1760_FLAG_INTR_POL_HIGH      0x00000080 /* Interrupt polarity active high */
 130 #define ISP1760_FLAG_INTR_EDGE_TRIG     0x00000100 /* Interrupt edge triggered */
 131
 132 /* chip memory management */
 133 struct memory_chunk {
 134         unsigned int start;
 135         unsigned int size;
 136         unsigned int free;
 137 };
 138
 139 /*
 140  * 60kb divided in:
 141  * - 32 blocks @ 256  bytes
 142  * - 20 blocks @ 1024 bytes
 143  * -  4 blocks @ 8192 bytes
 144  */
 145
 146 #define BLOCK_1_NUM 32
 147 #define BLOCK_2_NUM 20
 148 #define BLOCK_3_NUM 4
 149
 150 #define BLOCK_1_SIZE 256
 151 #define BLOCK_2_SIZE 1024
 152 #define BLOCK_3_SIZE 8192
 153 #define BLOCKS (BLOCK_1_NUM + BLOCK_2_NUM + BLOCK_3_NUM)
 154 #define MAX_PAYLOAD_SIZE BLOCK_3_SIZE
 155 #define PAYLOAD_AREA_SIZE 0xf000
 156
 157 /* ATL */
 158 /* DW0 */
 159 #define PTD_VALID                       1
 160 #define PTD_LENGTH(x)                   (((u32) x) << 3)
 161 #define PTD_MAXPACKET(x)                (((u32) x) << 18)
 162 #define PTD_MULTI(x)                    (((u32) x) << 29)
 163 #define PTD_ENDPOINT(x)                 (((u32) x) << 31)
 164 /* DW1 */
 165 #define PTD_DEVICE_ADDR(x)              (((u32) x) << 3)
 166 #define PTD_PID_TOKEN(x)                (((u32) x) << 10)
 167 #define PTD_TRANS_BULK                  ((u32) 2 << 12)
 168 #define PTD_TRANS_INT                   ((u32) 3 << 12)
 169 #define PTD_TRANS_SPLIT                 ((u32) 1 << 14)
 170 #define PTD_SE_USB_LOSPEED              ((u32) 2 << 16)
 171 #define PTD_PORT_NUM(x)                 (((u32) x) << 18)
 172 #define PTD_HUB_NUM(x)                  (((u32) x) << 25)
 173 #define PTD_PING(x)                     (((u32) x) << 26)
 174 /* DW2 */
 175 #define PTD_RL_CNT(x)                   (((u32) x) << 25)
 176 #define PTD_DATA_START_ADDR(x)          (((u32) x) << 8)
 177 #define BASE_ADDR                       0x1000
 178 /* DW3 */
 179 #define PTD_CERR(x)                     (((u32) x) << 23)
 180 #define PTD_NAC_CNT(x)                  (((u32) x) << 19)
 181 #define PTD_ACTIVE                      ((u32) 1 << 31)
 182 #define PTD_DATA_TOGGLE(x)              (((u32) x) << 25)
 183
 184 #define DW3_HALT_BIT                    (1 << 30)
 185 #define DW3_ERROR_BIT                   (1 << 28)
 186 #define DW3_QTD_ACTIVE                  (1 << 31)
 187
 188 #define INT_UNDERRUN                    (1 << 2)
 189 #define INT_BABBLE                      (1 << 1)
 190 #define INT_EXACT                       (1 << 0)
 191
 192 #define DW1_GET_PID(x)                  (((x) >> 10) & 0x3)
 193 #define PTD_XFERRED_LENGTH(x)           ((x) & 0x7fff)
 194 #define PTD_XFERRED_LENGTH_LO(x)        ((x) & 0x7ff)
 195
 196 #define SETUP_PID       (2)
 197 #define IN_PID          (1)
 198 #define OUT_PID         (0)
 199 #define GET_QTD_TOKEN_TYPE(x)   ((x) & 0x3)
 200
 201 #define DATA_TOGGLE             (1 << 31)
 202 #define GET_DATA_TOGGLE(x)      ((x) >> 31)
 203
 204 /* Errata 1 */
 205 #define RL_COUNTER      (0)
 206 #define NAK_COUNTER     (0)
 207 #define ERR_COUNTER     (2)
 208
 209 #endif