drivers/mtd/nand/ppchameleonevb.c

   1 /*
   2  *  drivers/mtd/nand/ppchameleonevb.c
   3  *
   4  *  Copyright (C) 2003 DAVE Srl (info@wawnet.biz)
   5  *
   6  *  Derived from drivers/mtd/nand/edb7312.c
   7  *
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  *  Overview:
  14  *   This is a device driver for the NAND flash devices found on the
  15  *   PPChameleon/PPChameleonEVB system.
  16  *   PPChameleon options (autodetected):
  17  *   - BA model: no NAND
  18  *   - ME model: 32MB (Samsung K9F5608U0B)
  19  *   - HI model: 128MB (Samsung K9F1G08UOM)
  20  *   PPChameleonEVB options:
  21  *   - 32MB (Samsung K9F5608U0B)
  22  */
  23
  24 #include <linux/init.h>
  25 #include <linux/slab.h>
  26 #include <linux/module.h>
  27 #include <linux/mtd/mtd.h>
  28 #include <linux/mtd/nand.h>
  29 #include <linux/mtd/partitions.h>
  30 #include <asm/io.h>
  31 #include <platforms/PPChameleonEVB.h>
  32
  33 #undef USE_READY_BUSY_PIN
  34 #define USE_READY_BUSY_PIN
  35 /* see datasheets (tR) */
  36 #define NAND_BIG_DELAY_US               25
  37 #define NAND_SMALL_DELAY_US             10
  38
  39 /* handy sizes */
  40 #define SZ_4M                           0x00400000
  41 #define NAND_SMALL_SIZE                 0x02000000
  42 #define NAND_MTD_NAME           "ppchameleon-nand"
  43 #define NAND_EVB_MTD_NAME       "ppchameleonevb-nand"
  44
  45 /* GPIO pins used to drive NAND chip mounted on processor module */
  46 #define NAND_nCE_GPIO_PIN               (0x80000000 >> 1)
  47 #define NAND_CLE_GPIO_PIN               (0x80000000 >> 2)
  48 #define NAND_ALE_GPIO_PIN               (0x80000000 >> 3)
  49 #define NAND_RB_GPIO_PIN                (0x80000000 >> 4)
  50 /* GPIO pins used to drive NAND chip mounted on EVB */
  51 #define NAND_EVB_nCE_GPIO_PIN   (0x80000000 >> 14)
  52 #define NAND_EVB_CLE_GPIO_PIN   (0x80000000 >> 15)
  53 #define NAND_EVB_ALE_GPIO_PIN   (0x80000000 >> 16)
  54 #define NAND_EVB_RB_GPIO_PIN    (0x80000000 >> 31)
  55
  56 /*
  57  * MTD structure for PPChameleonEVB board
  58  */
  59 static struct mtd_info *ppchameleon_mtd = NULL;
  60 static struct mtd_info *ppchameleonevb_mtd = NULL;
  61
  62 /*
  63  * Module stuff
  64  */
  65 static unsigned long ppchameleon_fio_pbase = CFG_NAND0_PADDR;
  66 static unsigned long ppchameleonevb_fio_pbase = CFG_NAND1_PADDR;
  67
  68 #ifdef MODULE
  69 module_param(ppchameleon_fio_pbase, ulong, 0);
  70 module_param(ppchameleonevb_fio_pbase, ulong, 0);
  71 #else
  72 __setup("ppchameleon_fio_pbase=", ppchameleon_fio_pbase);
  73 __setup("ppchameleonevb_fio_pbase=", ppchameleonevb_fio_pbase);
  74 #endif
  75
  76 /*
  77  * Define static partitions for flash devices
  78  */
  79 static struct mtd_partition partition_info_hi[] = {
  80       { .name = "PPChameleon HI Nand Flash",
  81         .offset = 0,
  82         .size = 128 * 1024 * 1024
  83       }
  84 };
  85
  86 static struct mtd_partition partition_info_me[] = {
  87       { .name = "PPChameleon ME Nand Flash",
  88         .offset = 0,
  89         .size = 32 * 1024 * 1024
  90       }
  91 };
  92
  93 static struct mtd_partition partition_info_evb[] = {
  94       { .name = "PPChameleonEVB Nand Flash",
  95         .offset = 0,
  96         .size = 32 * 1024 * 1024
  97       }
  98 };
  99
 100 #define NUM_PARTITIONS 1
 101
 102 extern int parse_cmdline_partitions(struct mtd_info *master, struct mtd_partition **pparts, const char *mtd_id);
 103
 104 /*
 105  *      hardware specific access to control-lines
 106  */
 107 static void ppchameleon_hwcontrol(struct mtd_info *mtdinfo, int cmd,
 108                                   unsigned int ctrl)
 109 {
 110         struct nand_chip *chip = mtd->priv;
 111
 112         if (ctrl & NAND_CTRL_CHANGE) {
 113 #error Missing headerfiles. No way to fix this. -tglx
 114                 switch (cmd) {
 115                 case NAND_CTL_SETCLE:
 116                         MACRO_NAND_CTL_SETCLE((unsigned long)CFG_NAND0_PADDR);
 117                         break;
 118                 case NAND_CTL_CLRCLE:
 119                         MACRO_NAND_CTL_CLRCLE((unsigned long)CFG_NAND0_PADDR);
 120                         break;
 121                 case NAND_CTL_SETALE:
 122                         MACRO_NAND_CTL_SETALE((unsigned long)CFG_NAND0_PADDR);
 123                         break;
 124                 case NAND_CTL_CLRALE:
 125                         MACRO_NAND_CTL_CLRALE((unsigned long)CFG_NAND0_PADDR);
 126                         break;
 127                 case NAND_CTL_SETNCE:
 128                         MACRO_NAND_ENABLE_CE((unsigned long)CFG_NAND0_PADDR);
 129                         break;
 130                 case NAND_CTL_CLRNCE:
 131                         MACRO_NAND_DISABLE_CE((unsigned long)CFG_NAND0_PADDR);
 132                         break;
 133                 }
 134         }
 135         if (cmd != NAND_CMD_NONE)
 136                 writeb(cmd, chip->IO_ADDR_W);
 137 }
 138
 139 static void ppchameleonevb_hwcontrol(struct mtd_info *mtdinfo, int cmd,
 140                                      unsigned int ctrl)
 141 {
 142         struct nand_chip *chip = mtd->priv;
 143
 144         if (ctrl & NAND_CTRL_CHANGE) {
 145 #error Missing headerfiles. No way to fix this. -tglx
 146                 switch (cmd) {
 147                 case NAND_CTL_SETCLE:
 148                         MACRO_NAND_CTL_SETCLE((unsigned long)CFG_NAND1_PADDR);
 149                         break;
 150                 case NAND_CTL_CLRCLE:
 151                         MACRO_NAND_CTL_CLRCLE((unsigned long)CFG_NAND1_PADDR);
 152                         break;
 153                 case NAND_CTL_SETALE:
 154                         MACRO_NAND_CTL_SETALE((unsigned long)CFG_NAND1_PADDR);
 155                         break;
 156                 case NAND_CTL_CLRALE:
 157                         MACRO_NAND_CTL_CLRALE((unsigned long)CFG_NAND1_PADDR);
 158                         break;
 159                 case NAND_CTL_SETNCE:
 160                         MACRO_NAND_ENABLE_CE((unsigned long)CFG_NAND1_PADDR);
 161                         break;
 162                 case NAND_CTL_CLRNCE:
 163                         MACRO_NAND_DISABLE_CE((unsigned long)CFG_NAND1_PADDR);
 164                         break;
 165                 }
 166         }
 167         if (cmd != NAND_CMD_NONE)
 168                 writeb(cmd, chip->IO_ADDR_W);
 169 }
 170
 171 #ifdef USE_READY_BUSY_PIN
 172 /*
 173  *      read device ready pin
 174  */
 175 static int ppchameleon_device_ready(struct mtd_info *minfo)
 176 {
 177         if (in_be32((volatile unsigned *)GPIO0_IR) & NAND_RB_GPIO_PIN)
 178                 return 1;
 179         return 0;
 180 }
 181
 182 static int ppchameleonevb_device_ready(struct mtd_info *minfo)
 183 {
 184         if (in_be32((volatile unsigned *)GPIO0_IR) & NAND_EVB_RB_GPIO_PIN)
 185                 return 1;
 186         return 0;
 187 }
 188 #endif
 189
 190 const char *part_probes[] = { "cmdlinepart", NULL };
 191 const char *part_probes_evb[] = { "cmdlinepart", NULL };
 192
 193 /*
 194  * Main initialization routine
 195  */
 196 static int __init ppchameleonevb_init(void)
 197 {
 198         struct nand_chip *this;
 199         const char *part_type = 0;
 200         int mtd_parts_nb = 0;
 201         struct mtd_partition *mtd_parts = 0;
 202         void __iomem *ppchameleon_fio_base;
 203         void __iomem *ppchameleonevb_fio_base;
 204
 205         /*********************************
 206         * Processor module NAND (if any) *
 207         *********************************/
 208         /* Allocate memory for MTD device structure and private data */
 209         ppchameleon_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL);
 210         if (!ppchameleon_mtd) {
 211                 printk("Unable to allocate PPChameleon NAND MTD device structure.\n");
 212                 return -ENOMEM;
 213         }
 214
 215         /* map physical address */
 216         ppchameleon_fio_base = ioremap(ppchameleon_fio_pbase, SZ_4M);
 217         if (!ppchameleon_fio_base) {
 218                 printk("ioremap PPChameleon NAND flash failed\n");
 219                 kfree(ppchameleon_mtd);
 220                 return -EIO;
 221         }
 222
 223         /* Get pointer to private data */
 224         this = (struct nand_chip *)(&ppchameleon_mtd[1]);
 225
 226         /* Initialize structures */
 227         memset(ppchameleon_mtd, 0, sizeof(struct mtd_info));
 228         memset(this, 0, sizeof(struct nand_chip));
 229
 230         /* Link the private data with the MTD structure */
 231         ppchameleon_mtd->priv = this;
 232         ppchameleon_mtd->owner = THIS_MODULE;
 233
 234         /* Initialize GPIOs */
 235         /* Pin mapping for NAND chip */
 236         /*
 237            CE   GPIO_01
 238            CLE  GPIO_02
 239            ALE  GPIO_03
 240            R/B  GPIO_04
 241          */
 242         /* output select */
 243         out_be32((volatile unsigned *)GPIO0_OSRH, in_be32((volatile unsigned *)GPIO0_OSRH) & 0xC0FFFFFF);
 244         /* three-state select */
 245         out_be32((volatile unsigned *)GPIO0_TSRH, in_be32((volatile unsigned *)GPIO0_TSRH) & 0xC0FFFFFF);
 246         /* enable output driver */
 247         out_be32((volatile unsigned *)GPIO0_TCR,
 248                  in_be32((volatile unsigned *)GPIO0_TCR) | NAND_nCE_GPIO_PIN | NAND_CLE_GPIO_PIN | NAND_ALE_GPIO_PIN);
 249 #ifdef USE_READY_BUSY_PIN
 250         /* three-state select */
 251         out_be32((volatile unsigned *)GPIO0_TSRH, in_be32((volatile unsigned *)GPIO0_TSRH) & 0xFF3FFFFF);
 252         /* high-impedecence */
 253         out_be32((volatile unsigned *)GPIO0_TCR, in_be32((volatile unsigned *)GPIO0_TCR) & (~NAND_RB_GPIO_PIN));
 254         /* input select */
 255         out_be32((volatile unsigned *)GPIO0_ISR1H,
 256                  (in_be32((volatile unsigned *)GPIO0_ISR1H) & 0xFF3FFFFF) | 0x00400000);
 257 #endif
 258
 259         /* insert callbacks */
 260         this->IO_ADDR_R = ppchameleon_fio_base;
 261         this->IO_ADDR_W = ppchameleon_fio_base;
 262         this->cmd_ctrl = ppchameleon_hwcontrol;
 263 #ifdef USE_READY_BUSY_PIN
 264         this->dev_ready = ppchameleon_device_ready;
 265 #endif
 266         this->chip_delay = NAND_BIG_DELAY_US;
 267         /* ECC mode */
 268         this->ecc.mode = NAND_ECC_SOFT;
 269
 270         /* Scan to find existence of the device (it could not be mounted) */
 271         if (nand_scan(ppchameleon_mtd, 1)) {
 272                 iounmap((void *)ppchameleon_fio_base);
 273                 ppchameleon_fio_base = NULL;
 274                 kfree(ppchameleon_mtd);
 275                 goto nand_evb_init;
 276         }
 277 #ifndef USE_READY_BUSY_PIN
 278         /* Adjust delay if necessary */
 279         if (ppchameleon_mtd->size == NAND_SMALL_SIZE)
 280                 this->chip_delay = NAND_SMALL_DELAY_US;
 281 #endif
 282
 283         ppchameleon_mtd->name = "ppchameleon-nand";
 284         mtd_parts_nb = parse_mtd_partitions(ppchameleon_mtd, part_probes, &mtd_parts, 0);
 285         if (mtd_parts_nb > 0)
 286                 part_type = "command line";
 287         else
 288                 mtd_parts_nb = 0;
 289
 290         if (mtd_parts_nb == 0) {
 291                 if (ppchameleon_mtd->size == NAND_SMALL_SIZE)
 292                         mtd_parts = partition_info_me;
 293                 else
 294                         mtd_parts = partition_info_hi;
 295                 mtd_parts_nb = NUM_PARTITIONS;
 296                 part_type = "static";
 297         }
 298
 299         /* Register the partitions */
 300         printk(KERN_NOTICE "Using %s partition definition\n", part_type);
 301         mtd_device_register(ppchameleon_mtd, mtd_parts, mtd_parts_nb);
 302
 303  nand_evb_init:
 304         /****************************
 305         * EVB NAND (always present) *
 306         ****************************/
 307         /* Allocate memory for MTD device structure and private data */
 308         ppchameleonevb_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL);
 309         if (!ppchameleonevb_mtd) {
 310                 printk("Unable to allocate PPChameleonEVB NAND MTD device structure.\n");
 311                 if (ppchameleon_fio_base)
 312                         iounmap(ppchameleon_fio_base);
 313                 return -ENOMEM;
 314         }
 315
 316         /* map physical address */
 317         ppchameleonevb_fio_base = ioremap(ppchameleonevb_fio_pbase, SZ_4M);
 318         if (!ppchameleonevb_fio_base) {
 319                 printk("ioremap PPChameleonEVB NAND flash failed\n");
 320                 kfree(ppchameleonevb_mtd);
 321                 if (ppchameleon_fio_base)
 322                         iounmap(ppchameleon_fio_base);
 323                 return -EIO;
 324         }
 325
 326         /* Get pointer to private data */
 327         this = (struct nand_chip *)(&ppchameleonevb_mtd[1]);
 328
 329         /* Initialize structures */
 330         memset(ppchameleonevb_mtd, 0, sizeof(struct mtd_info));
 331         memset(this, 0, sizeof(struct nand_chip));
 332
 333         /* Link the private data with the MTD structure */
 334         ppchameleonevb_mtd->priv = this;
 335
 336         /* Initialize GPIOs */
 337         /* Pin mapping for NAND chip */
 338         /*
 339            CE   GPIO_14
 340            CLE  GPIO_15
 341            ALE  GPIO_16
 342            R/B  GPIO_31
 343          */
 344         /* output select */
 345         out_be32((volatile unsigned *)GPIO0_OSRH, in_be32((volatile unsigned *)GPIO0_OSRH) & 0xFFFFFFF0);
 346         out_be32((volatile unsigned *)GPIO0_OSRL, in_be32((volatile unsigned *)GPIO0_OSRL) & 0x3FFFFFFF);
 347         /* three-state select */
 348         out_be32((volatile unsigned *)GPIO0_TSRH, in_be32((volatile unsigned *)GPIO0_TSRH) & 0xFFFFFFF0);
 349         out_be32((volatile unsigned *)GPIO0_TSRL, in_be32((volatile unsigned *)GPIO0_TSRL) & 0x3FFFFFFF);
 350         /* enable output driver */
 351         out_be32((volatile unsigned *)GPIO0_TCR, in_be32((volatile unsigned *)GPIO0_TCR) | NAND_EVB_nCE_GPIO_PIN |
 352                  NAND_EVB_CLE_GPIO_PIN | NAND_EVB_ALE_GPIO_PIN);
 353 #ifdef USE_READY_BUSY_PIN
 354         /* three-state select */
 355         out_be32((volatile unsigned *)GPIO0_TSRL, in_be32((volatile unsigned *)GPIO0_TSRL) & 0xFFFFFFFC);
 356         /* high-impedecence */
 357         out_be32((volatile unsigned *)GPIO0_TCR, in_be32((volatile unsigned *)GPIO0_TCR) & (~NAND_EVB_RB_GPIO_PIN));
 358         /* input select */
 359         out_be32((volatile unsigned *)GPIO0_ISR1L,
 360                  (in_be32((volatile unsigned *)GPIO0_ISR1L) & 0xFFFFFFFC) | 0x00000001);
 361 #endif
 362
 363         /* insert callbacks */
 364         this->IO_ADDR_R = ppchameleonevb_fio_base;
 365         this->IO_ADDR_W = ppchameleonevb_fio_base;
 366         this->cmd_ctrl = ppchameleonevb_hwcontrol;
 367 #ifdef USE_READY_BUSY_PIN
 368         this->dev_ready = ppchameleonevb_device_ready;
 369 #endif
 370         this->chip_delay = NAND_SMALL_DELAY_US;
 371
 372         /* ECC mode */
 373         this->ecc.mode = NAND_ECC_SOFT;
 374
 375         /* Scan to find existence of the device */
 376         if (nand_scan(ppchameleonevb_mtd, 1)) {
 377                 iounmap((void *)ppchameleonevb_fio_base);
 378                 kfree(ppchameleonevb_mtd);
 379                 if (ppchameleon_fio_base)
 380                         iounmap(ppchameleon_fio_base);
 381                 return -ENXIO;
 382         }
 383
 384         ppchameleonevb_mtd->name = NAND_EVB_MTD_NAME;
 385         mtd_parts_nb = parse_mtd_partitions(ppchameleonevb_mtd, part_probes_evb, &mtd_parts, 0);
 386         if (mtd_parts_nb > 0)
 387                 part_type = "command line";
 388         else
 389                 mtd_parts_nb = 0;
 390
 391         if (mtd_parts_nb == 0) {
 392                 mtd_parts = partition_info_evb;
 393                 mtd_parts_nb = NUM_PARTITIONS;
 394                 part_type = "static";
 395         }
 396
 397         /* Register the partitions */
 398         printk(KERN_NOTICE "Using %s partition definition\n", part_type);
 399         mtd_device_register(ppchameleonevb_mtd, mtd_parts, mtd_parts_nb);
 400
 401         /* Return happy */
 402         return 0;
 403 }
 404
 405 module_init(ppchameleonevb_init);
 406
 407 /*
 408  * Clean up routine
 409  */
 410 static void __exit ppchameleonevb_cleanup(void)
 411 {
 412         struct nand_chip *this;
 413
 414         /* Release resources, unregister device(s) */
 415         nand_release(ppchameleon_mtd);
 416         nand_release(ppchameleonevb_mtd);
 417
 418         /* Release iomaps */
 419         this = (struct nand_chip *) &ppchameleon_mtd[1];
 420         iounmap((void *) this->IO_ADDR_R);
 421         this = (struct nand_chip *) &ppchameleonevb_mtd[1];
 422         iounmap((void *) this->IO_ADDR_R);
 423
 424         /* Free the MTD device structure */
 425         kfree (ppchameleon_mtd);
 426         kfree (ppchameleonevb_mtd);
 427 }
 428 module_exit(ppchameleonevb_cleanup);
 429
 430 MODULE_LICENSE("GPL");
 431 MODULE_AUTHOR("DAVE Srl <support-ppchameleon@dave-tech.it>");
 432 MODULE_DESCRIPTION("MTD map driver for DAVE Srl PPChameleonEVB board");