2 * QLogic qlge NIC HBA Driver
3 * Copyright (c) 2003-2008 QLogic Corporation
4 * See LICENSE.qlge for copyright and licensing details.
5 * Author: Linux qlge network device driver by
6 * Ron Mercer <ron.mercer@qlogic.com>
8 #include <linux/kernel.h>
9 #include <linux/init.h>
10 #include <linux/types.h>
11 #include <linux/module.h>
12 #include <linux/list.h>
13 #include <linux/pci.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/pagemap.h>
16 #include <linux/sched.h>
17 #include <linux/slab.h>
18 #include <linux/dmapool.h>
19 #include <linux/mempool.h>
20 #include <linux/spinlock.h>
21 #include <linux/kthread.h>
22 #include <linux/interrupt.h>
23 #include <linux/errno.h>
24 #include <linux/ioport.h>
27 #include <linux/ipv6.h>
29 #include <linux/tcp.h>
30 #include <linux/udp.h>
31 #include <linux/if_arp.h>
32 #include <linux/if_ether.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/ethtool.h>
36 #include <linux/skbuff.h>
37 #include <linux/rtnetlink.h>
38 #include <linux/if_vlan.h>
39 #include <linux/delay.h>
41 #include <linux/vmalloc.h>
42 #include <net/ip6_checksum.h>
46 char qlge_driver_name
[] = DRV_NAME
;
47 const char qlge_driver_version
[] = DRV_VERSION
;
49 MODULE_AUTHOR("Ron Mercer <ron.mercer@qlogic.com>");
50 MODULE_DESCRIPTION(DRV_STRING
" ");
51 MODULE_LICENSE("GPL");
52 MODULE_VERSION(DRV_VERSION
);
54 static const u32 default_msg
=
55 NETIF_MSG_DRV
| NETIF_MSG_PROBE
| NETIF_MSG_LINK
|
56 /* NETIF_MSG_TIMER | */
62 NETIF_MSG_INTR
| NETIF_MSG_TX_DONE
| NETIF_MSG_RX_STATUS
|
63 /* NETIF_MSG_PKTDATA | */
64 NETIF_MSG_HW
| NETIF_MSG_WOL
| 0;
66 static int debug
= 0x00007fff; /* defaults above */
67 module_param(debug
, int, 0);
68 MODULE_PARM_DESC(debug
, "Debug level (0=none,...,16=all)");
73 static int irq_type
= MSIX_IRQ
;
74 module_param(irq_type
, int, MSIX_IRQ
);
75 MODULE_PARM_DESC(irq_type
, "0 = MSI-X, 1 = MSI, 2 = Legacy.");
77 static struct pci_device_id qlge_pci_tbl
[] __devinitdata
= {
78 {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC
, QLGE_DEVICE_ID
)},
79 /* required last entry */
83 MODULE_DEVICE_TABLE(pci
, qlge_pci_tbl
);
85 /* This hardware semaphore causes exclusive access to
86 * resources shared between the NIC driver, MPI firmware,
87 * FCOE firmware and the FC driver.
89 static int ql_sem_trylock(struct ql_adapter
*qdev
, u32 sem_mask
)
95 sem_bits
= SEM_SET
<< SEM_XGMAC0_SHIFT
;
98 sem_bits
= SEM_SET
<< SEM_XGMAC1_SHIFT
;
101 sem_bits
= SEM_SET
<< SEM_ICB_SHIFT
;
103 case SEM_MAC_ADDR_MASK
:
104 sem_bits
= SEM_SET
<< SEM_MAC_ADDR_SHIFT
;
107 sem_bits
= SEM_SET
<< SEM_FLASH_SHIFT
;
110 sem_bits
= SEM_SET
<< SEM_PROBE_SHIFT
;
112 case SEM_RT_IDX_MASK
:
113 sem_bits
= SEM_SET
<< SEM_RT_IDX_SHIFT
;
115 case SEM_PROC_REG_MASK
:
116 sem_bits
= SEM_SET
<< SEM_PROC_REG_SHIFT
;
119 QPRINTK(qdev
, PROBE
, ALERT
, "Bad Semaphore mask!.\n");
123 ql_write32(qdev
, SEM
, sem_bits
| sem_mask
);
124 return !(ql_read32(qdev
, SEM
) & sem_bits
);
127 int ql_sem_spinlock(struct ql_adapter
*qdev
, u32 sem_mask
)
129 unsigned int wait_count
= 30;
131 if (!ql_sem_trylock(qdev
, sem_mask
))
134 } while (--wait_count
);
138 void ql_sem_unlock(struct ql_adapter
*qdev
, u32 sem_mask
)
140 ql_write32(qdev
, SEM
, sem_mask
);
141 ql_read32(qdev
, SEM
); /* flush */
144 /* This function waits for a specific bit to come ready
145 * in a given register. It is used mostly by the initialize
146 * process, but is also used in kernel thread API such as
147 * netdev->set_multi, netdev->set_mac_address, netdev->vlan_rx_add_vid.
149 int ql_wait_reg_rdy(struct ql_adapter
*qdev
, u32 reg
, u32 bit
, u32 err_bit
)
152 int count
= UDELAY_COUNT
;
155 temp
= ql_read32(qdev
, reg
);
157 /* check for errors */
158 if (temp
& err_bit
) {
159 QPRINTK(qdev
, PROBE
, ALERT
,
160 "register 0x%.08x access error, value = 0x%.08x!.\n",
163 } else if (temp
& bit
)
165 udelay(UDELAY_DELAY
);
168 QPRINTK(qdev
, PROBE
, ALERT
,
169 "Timed out waiting for reg %x to come ready.\n", reg
);
173 /* The CFG register is used to download TX and RX control blocks
174 * to the chip. This function waits for an operation to complete.
176 static int ql_wait_cfg(struct ql_adapter
*qdev
, u32 bit
)
178 int count
= UDELAY_COUNT
;
182 temp
= ql_read32(qdev
, CFG
);
187 udelay(UDELAY_DELAY
);
194 /* Used to issue init control blocks to hw. Maps control block,
195 * sets address, triggers download, waits for completion.
197 int ql_write_cfg(struct ql_adapter
*qdev
, void *ptr
, int size
, u32 bit
,
207 (bit
& (CFG_LRQ
| CFG_LR
| CFG_LCQ
)) ? PCI_DMA_TODEVICE
:
210 map
= pci_map_single(qdev
->pdev
, ptr
, size
, direction
);
211 if (pci_dma_mapping_error(qdev
->pdev
, map
)) {
212 QPRINTK(qdev
, IFUP
, ERR
, "Couldn't map DMA area.\n");
216 status
= ql_wait_cfg(qdev
, bit
);
218 QPRINTK(qdev
, IFUP
, ERR
,
219 "Timed out waiting for CFG to come ready.\n");
223 status
= ql_sem_spinlock(qdev
, SEM_ICB_MASK
);
226 ql_write32(qdev
, ICB_L
, (u32
) map
);
227 ql_write32(qdev
, ICB_H
, (u32
) (map
>> 32));
228 ql_sem_unlock(qdev
, SEM_ICB_MASK
); /* does flush too */
230 mask
= CFG_Q_MASK
| (bit
<< 16);
231 value
= bit
| (q_id
<< CFG_Q_SHIFT
);
232 ql_write32(qdev
, CFG
, (mask
| value
));
235 * Wait for the bit to clear after signaling hw.
237 status
= ql_wait_cfg(qdev
, bit
);
239 pci_unmap_single(qdev
->pdev
, map
, size
, direction
);
243 /* Get a specific MAC address from the CAM. Used for debug and reg dump. */
244 int ql_get_mac_addr_reg(struct ql_adapter
*qdev
, u32 type
, u16 index
,
250 status
= ql_sem_spinlock(qdev
, SEM_MAC_ADDR_MASK
);
254 case MAC_ADDR_TYPE_MULTI_MAC
:
255 case MAC_ADDR_TYPE_CAM_MAC
:
258 ql_wait_reg_rdy(qdev
,
259 MAC_ADDR_IDX
, MAC_ADDR_MW
, 0);
262 ql_write32(qdev
, MAC_ADDR_IDX
, (offset
++) | /* offset */
263 (index
<< MAC_ADDR_IDX_SHIFT
) | /* index */
264 MAC_ADDR_ADR
| MAC_ADDR_RS
| type
); /* type */
266 ql_wait_reg_rdy(qdev
,
267 MAC_ADDR_IDX
, MAC_ADDR_MR
, 0);
270 *value
++ = ql_read32(qdev
, MAC_ADDR_DATA
);
272 ql_wait_reg_rdy(qdev
,
273 MAC_ADDR_IDX
, MAC_ADDR_MW
, 0);
276 ql_write32(qdev
, MAC_ADDR_IDX
, (offset
++) | /* offset */
277 (index
<< MAC_ADDR_IDX_SHIFT
) | /* index */
278 MAC_ADDR_ADR
| MAC_ADDR_RS
| type
); /* type */
280 ql_wait_reg_rdy(qdev
,
281 MAC_ADDR_IDX
, MAC_ADDR_MR
, 0);
284 *value
++ = ql_read32(qdev
, MAC_ADDR_DATA
);
285 if (type
== MAC_ADDR_TYPE_CAM_MAC
) {
287 ql_wait_reg_rdy(qdev
,
288 MAC_ADDR_IDX
, MAC_ADDR_MW
, 0);
291 ql_write32(qdev
, MAC_ADDR_IDX
, (offset
++) | /* offset */
292 (index
<< MAC_ADDR_IDX_SHIFT
) | /* index */
293 MAC_ADDR_ADR
| MAC_ADDR_RS
| type
); /* type */
295 ql_wait_reg_rdy(qdev
, MAC_ADDR_IDX
,
299 *value
++ = ql_read32(qdev
, MAC_ADDR_DATA
);
303 case MAC_ADDR_TYPE_VLAN
:
304 case MAC_ADDR_TYPE_MULTI_FLTR
:
306 QPRINTK(qdev
, IFUP
, CRIT
,
307 "Address type %d not yet supported.\n", type
);
311 ql_sem_unlock(qdev
, SEM_MAC_ADDR_MASK
);
315 /* Set up a MAC, multicast or VLAN address for the
316 * inbound frame matching.
318 static int ql_set_mac_addr_reg(struct ql_adapter
*qdev
, u8
*addr
, u32 type
,
324 status
= ql_sem_spinlock(qdev
, SEM_MAC_ADDR_MASK
);
328 case MAC_ADDR_TYPE_MULTI_MAC
:
329 case MAC_ADDR_TYPE_CAM_MAC
:
332 u32 upper
= (addr
[0] << 8) | addr
[1];
334 (addr
[2] << 24) | (addr
[3] << 16) | (addr
[4] << 8) |
337 QPRINTK(qdev
, IFUP
, INFO
,
338 "Adding %s address %pM"
339 " at index %d in the CAM.\n",
341 MAC_ADDR_TYPE_MULTI_MAC
) ? "MULTICAST" :
342 "UNICAST"), addr
, index
);
345 ql_wait_reg_rdy(qdev
,
346 MAC_ADDR_IDX
, MAC_ADDR_MW
, 0);
349 ql_write32(qdev
, MAC_ADDR_IDX
, (offset
++) | /* offset */
350 (index
<< MAC_ADDR_IDX_SHIFT
) | /* index */
352 ql_write32(qdev
, MAC_ADDR_DATA
, lower
);
354 ql_wait_reg_rdy(qdev
,
355 MAC_ADDR_IDX
, MAC_ADDR_MW
, 0);
358 ql_write32(qdev
, MAC_ADDR_IDX
, (offset
++) | /* offset */
359 (index
<< MAC_ADDR_IDX_SHIFT
) | /* index */
361 ql_write32(qdev
, MAC_ADDR_DATA
, upper
);
363 ql_wait_reg_rdy(qdev
,
364 MAC_ADDR_IDX
, MAC_ADDR_MW
, 0);
367 ql_write32(qdev
, MAC_ADDR_IDX
, (offset
) | /* offset */
368 (index
<< MAC_ADDR_IDX_SHIFT
) | /* index */
370 /* This field should also include the queue id
371 and possibly the function id. Right now we hardcode
372 the route field to NIC core.
374 if (type
== MAC_ADDR_TYPE_CAM_MAC
) {
375 cam_output
= (CAM_OUT_ROUTE_NIC
|
377 func
<< CAM_OUT_FUNC_SHIFT
) |
379 rss_ring_first_cq_id
<<
380 CAM_OUT_CQ_ID_SHIFT
));
382 cam_output
|= CAM_OUT_RV
;
383 /* route to NIC core */
384 ql_write32(qdev
, MAC_ADDR_DATA
, cam_output
);
388 case MAC_ADDR_TYPE_VLAN
:
390 u32 enable_bit
= *((u32
*) &addr
[0]);
391 /* For VLAN, the addr actually holds a bit that
392 * either enables or disables the vlan id we are
393 * addressing. It's either MAC_ADDR_E on or off.
394 * That's bit-27 we're talking about.
396 QPRINTK(qdev
, IFUP
, INFO
, "%s VLAN ID %d %s the CAM.\n",
397 (enable_bit
? "Adding" : "Removing"),
398 index
, (enable_bit
? "to" : "from"));
401 ql_wait_reg_rdy(qdev
,
402 MAC_ADDR_IDX
, MAC_ADDR_MW
, 0);
405 ql_write32(qdev
, MAC_ADDR_IDX
, offset
| /* offset */
406 (index
<< MAC_ADDR_IDX_SHIFT
) | /* index */
408 enable_bit
); /* enable/disable */
411 case MAC_ADDR_TYPE_MULTI_FLTR
:
413 QPRINTK(qdev
, IFUP
, CRIT
,
414 "Address type %d not yet supported.\n", type
);
418 ql_sem_unlock(qdev
, SEM_MAC_ADDR_MASK
);
422 /* Get a specific frame routing value from the CAM.
423 * Used for debug and reg dump.
425 int ql_get_routing_reg(struct ql_adapter
*qdev
, u32 index
, u32
*value
)
429 status
= ql_sem_spinlock(qdev
, SEM_RT_IDX_MASK
);
433 status
= ql_wait_reg_rdy(qdev
, RT_IDX
, RT_IDX_MW
, 0);
437 ql_write32(qdev
, RT_IDX
,
438 RT_IDX_TYPE_NICQ
| RT_IDX_RS
| (index
<< RT_IDX_IDX_SHIFT
));
439 status
= ql_wait_reg_rdy(qdev
, RT_IDX
, RT_IDX_MR
, 0);
442 *value
= ql_read32(qdev
, RT_DATA
);
444 ql_sem_unlock(qdev
, SEM_RT_IDX_MASK
);
448 /* The NIC function for this chip has 16 routing indexes. Each one can be used
449 * to route different frame types to various inbound queues. We send broadcast/
450 * multicast/error frames to the default queue for slow handling,
451 * and CAM hit/RSS frames to the fast handling queues.
453 static int ql_set_routing_reg(struct ql_adapter
*qdev
, u32 index
, u32 mask
,
459 status
= ql_sem_spinlock(qdev
, SEM_RT_IDX_MASK
);
463 QPRINTK(qdev
, IFUP
, DEBUG
,
464 "%s %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s mask %s the routing reg.\n",
465 (enable
? "Adding" : "Removing"),
466 ((index
== RT_IDX_ALL_ERR_SLOT
) ? "MAC ERROR/ALL ERROR" : ""),
467 ((index
== RT_IDX_IP_CSUM_ERR_SLOT
) ? "IP CSUM ERROR" : ""),
469 RT_IDX_TCP_UDP_CSUM_ERR_SLOT
) ? "TCP/UDP CSUM ERROR" : ""),
470 ((index
== RT_IDX_BCAST_SLOT
) ? "BROADCAST" : ""),
471 ((index
== RT_IDX_MCAST_MATCH_SLOT
) ? "MULTICAST MATCH" : ""),
472 ((index
== RT_IDX_ALLMULTI_SLOT
) ? "ALL MULTICAST MATCH" : ""),
473 ((index
== RT_IDX_UNUSED6_SLOT
) ? "UNUSED6" : ""),
474 ((index
== RT_IDX_UNUSED7_SLOT
) ? "UNUSED7" : ""),
475 ((index
== RT_IDX_RSS_MATCH_SLOT
) ? "RSS ALL/IPV4 MATCH" : ""),
476 ((index
== RT_IDX_RSS_IPV6_SLOT
) ? "RSS IPV6" : ""),
477 ((index
== RT_IDX_RSS_TCP4_SLOT
) ? "RSS TCP4" : ""),
478 ((index
== RT_IDX_RSS_TCP6_SLOT
) ? "RSS TCP6" : ""),
479 ((index
== RT_IDX_CAM_HIT_SLOT
) ? "CAM HIT" : ""),
480 ((index
== RT_IDX_UNUSED013
) ? "UNUSED13" : ""),
481 ((index
== RT_IDX_UNUSED014
) ? "UNUSED14" : ""),
482 ((index
== RT_IDX_PROMISCUOUS_SLOT
) ? "PROMISCUOUS" : ""),
483 (enable
? "to" : "from"));
488 value
= RT_IDX_DST_CAM_Q
| /* dest */
489 RT_IDX_TYPE_NICQ
| /* type */
490 (RT_IDX_CAM_HIT_SLOT
<< RT_IDX_IDX_SHIFT
);/* index */
493 case RT_IDX_VALID
: /* Promiscuous Mode frames. */
495 value
= RT_IDX_DST_DFLT_Q
| /* dest */
496 RT_IDX_TYPE_NICQ
| /* type */
497 (RT_IDX_PROMISCUOUS_SLOT
<< RT_IDX_IDX_SHIFT
);/* index */
500 case RT_IDX_ERR
: /* Pass up MAC,IP,TCP/UDP error frames. */
502 value
= RT_IDX_DST_DFLT_Q
| /* dest */
503 RT_IDX_TYPE_NICQ
| /* type */
504 (RT_IDX_ALL_ERR_SLOT
<< RT_IDX_IDX_SHIFT
);/* index */
507 case RT_IDX_BCAST
: /* Pass up Broadcast frames to default Q. */
509 value
= RT_IDX_DST_DFLT_Q
| /* dest */
510 RT_IDX_TYPE_NICQ
| /* type */
511 (RT_IDX_BCAST_SLOT
<< RT_IDX_IDX_SHIFT
);/* index */
514 case RT_IDX_MCAST
: /* Pass up All Multicast frames. */
516 value
= RT_IDX_DST_CAM_Q
| /* dest */
517 RT_IDX_TYPE_NICQ
| /* type */
518 (RT_IDX_ALLMULTI_SLOT
<< RT_IDX_IDX_SHIFT
);/* index */
521 case RT_IDX_MCAST_MATCH
: /* Pass up matched Multicast frames. */
523 value
= RT_IDX_DST_CAM_Q
| /* dest */
524 RT_IDX_TYPE_NICQ
| /* type */
525 (RT_IDX_MCAST_MATCH_SLOT
<< RT_IDX_IDX_SHIFT
);/* index */
528 case RT_IDX_RSS_MATCH
: /* Pass up matched RSS frames. */
530 value
= RT_IDX_DST_RSS
| /* dest */
531 RT_IDX_TYPE_NICQ
| /* type */
532 (RT_IDX_RSS_MATCH_SLOT
<< RT_IDX_IDX_SHIFT
);/* index */
535 case 0: /* Clear the E-bit on an entry. */
537 value
= RT_IDX_DST_DFLT_Q
| /* dest */
538 RT_IDX_TYPE_NICQ
| /* type */
539 (index
<< RT_IDX_IDX_SHIFT
);/* index */
543 QPRINTK(qdev
, IFUP
, ERR
, "Mask type %d not yet supported.\n",
550 status
= ql_wait_reg_rdy(qdev
, RT_IDX
, RT_IDX_MW
, 0);
553 value
|= (enable
? RT_IDX_E
: 0);
554 ql_write32(qdev
, RT_IDX
, value
);
555 ql_write32(qdev
, RT_DATA
, enable
? mask
: 0);
558 ql_sem_unlock(qdev
, SEM_RT_IDX_MASK
);
562 static void ql_enable_interrupts(struct ql_adapter
*qdev
)
564 ql_write32(qdev
, INTR_EN
, (INTR_EN_EI
<< 16) | INTR_EN_EI
);
567 static void ql_disable_interrupts(struct ql_adapter
*qdev
)
569 ql_write32(qdev
, INTR_EN
, (INTR_EN_EI
<< 16));
572 /* If we're running with multiple MSI-X vectors then we enable on the fly.
573 * Otherwise, we may have multiple outstanding workers and don't want to
574 * enable until the last one finishes. In this case, the irq_cnt gets
575 * incremented everytime we queue a worker and decremented everytime
576 * a worker finishes. Once it hits zero we enable the interrupt.
578 u32
ql_enable_completion_interrupt(struct ql_adapter
*qdev
, u32 intr
)
581 unsigned long hw_flags
= 0;
582 struct intr_context
*ctx
= qdev
->intr_context
+ intr
;
584 if (likely(test_bit(QL_MSIX_ENABLED
, &qdev
->flags
) && intr
)) {
585 /* Always enable if we're MSIX multi interrupts and
586 * it's not the default (zeroeth) interrupt.
588 ql_write32(qdev
, INTR_EN
,
590 var
= ql_read32(qdev
, STS
);
594 spin_lock_irqsave(&qdev
->hw_lock
, hw_flags
);
595 if (atomic_dec_and_test(&ctx
->irq_cnt
)) {
596 ql_write32(qdev
, INTR_EN
,
598 var
= ql_read32(qdev
, STS
);
600 spin_unlock_irqrestore(&qdev
->hw_lock
, hw_flags
);
604 static u32
ql_disable_completion_interrupt(struct ql_adapter
*qdev
, u32 intr
)
607 unsigned long hw_flags
;
608 struct intr_context
*ctx
;
610 /* HW disables for us if we're MSIX multi interrupts and
611 * it's not the default (zeroeth) interrupt.
613 if (likely(test_bit(QL_MSIX_ENABLED
, &qdev
->flags
) && intr
))
616 ctx
= qdev
->intr_context
+ intr
;
617 spin_lock_irqsave(&qdev
->hw_lock
, hw_flags
);
618 if (!atomic_read(&ctx
->irq_cnt
)) {
619 ql_write32(qdev
, INTR_EN
,
621 var
= ql_read32(qdev
, STS
);
623 atomic_inc(&ctx
->irq_cnt
);
624 spin_unlock_irqrestore(&qdev
->hw_lock
, hw_flags
);
628 static void ql_enable_all_completion_interrupts(struct ql_adapter
*qdev
)
631 for (i
= 0; i
< qdev
->intr_count
; i
++) {
632 /* The enable call does a atomic_dec_and_test
633 * and enables only if the result is zero.
634 * So we precharge it here.
636 if (unlikely(!test_bit(QL_MSIX_ENABLED
, &qdev
->flags
) ||
638 atomic_set(&qdev
->intr_context
[i
].irq_cnt
, 1);
639 ql_enable_completion_interrupt(qdev
, i
);
644 static int ql_read_flash_word(struct ql_adapter
*qdev
, int offset
, __le32
*data
)
647 /* wait for reg to come ready */
648 status
= ql_wait_reg_rdy(qdev
,
649 FLASH_ADDR
, FLASH_ADDR_RDY
, FLASH_ADDR_ERR
);
652 /* set up for reg read */
653 ql_write32(qdev
, FLASH_ADDR
, FLASH_ADDR_R
| offset
);
654 /* wait for reg to come ready */
655 status
= ql_wait_reg_rdy(qdev
,
656 FLASH_ADDR
, FLASH_ADDR_RDY
, FLASH_ADDR_ERR
);
659 /* This data is stored on flash as an array of
660 * __le32. Since ql_read32() returns cpu endian
661 * we need to swap it back.
663 *data
= cpu_to_le32(ql_read32(qdev
, FLASH_DATA
));
668 static int ql_get_flash_params(struct ql_adapter
*qdev
)
672 __le32
*p
= (__le32
*)&qdev
->flash
;
674 if (ql_sem_spinlock(qdev
, SEM_FLASH_MASK
))
677 for (i
= 0; i
< sizeof(qdev
->flash
) / sizeof(u32
); i
++, p
++) {
678 status
= ql_read_flash_word(qdev
, i
, p
);
680 QPRINTK(qdev
, IFUP
, ERR
, "Error reading flash.\n");
686 ql_sem_unlock(qdev
, SEM_FLASH_MASK
);
690 /* xgmac register are located behind the xgmac_addr and xgmac_data
691 * register pair. Each read/write requires us to wait for the ready
692 * bit before reading/writing the data.
694 static int ql_write_xgmac_reg(struct ql_adapter
*qdev
, u32 reg
, u32 data
)
697 /* wait for reg to come ready */
698 status
= ql_wait_reg_rdy(qdev
,
699 XGMAC_ADDR
, XGMAC_ADDR_RDY
, XGMAC_ADDR_XME
);
702 /* write the data to the data reg */
703 ql_write32(qdev
, XGMAC_DATA
, data
);
704 /* trigger the write */
705 ql_write32(qdev
, XGMAC_ADDR
, reg
);
709 /* xgmac register are located behind the xgmac_addr and xgmac_data
710 * register pair. Each read/write requires us to wait for the ready
711 * bit before reading/writing the data.
713 int ql_read_xgmac_reg(struct ql_adapter
*qdev
, u32 reg
, u32
*data
)
716 /* wait for reg to come ready */
717 status
= ql_wait_reg_rdy(qdev
,
718 XGMAC_ADDR
, XGMAC_ADDR_RDY
, XGMAC_ADDR_XME
);
721 /* set up for reg read */
722 ql_write32(qdev
, XGMAC_ADDR
, reg
| XGMAC_ADDR_R
);
723 /* wait for reg to come ready */
724 status
= ql_wait_reg_rdy(qdev
,
725 XGMAC_ADDR
, XGMAC_ADDR_RDY
, XGMAC_ADDR_XME
);
729 *data
= ql_read32(qdev
, XGMAC_DATA
);
734 /* This is used for reading the 64-bit statistics regs. */
735 int ql_read_xgmac_reg64(struct ql_adapter
*qdev
, u32 reg
, u64
*data
)
741 status
= ql_read_xgmac_reg(qdev
, reg
, &lo
);
745 status
= ql_read_xgmac_reg(qdev
, reg
+ 4, &hi
);
749 *data
= (u64
) lo
| ((u64
) hi
<< 32);
755 /* Take the MAC Core out of reset.
756 * Enable statistics counting.
757 * Take the transmitter/receiver out of reset.
758 * This functionality may be done in the MPI firmware at a
761 static int ql_port_initialize(struct ql_adapter
*qdev
)
766 if (ql_sem_trylock(qdev
, qdev
->xg_sem_mask
)) {
767 /* Another function has the semaphore, so
768 * wait for the port init bit to come ready.
770 QPRINTK(qdev
, LINK
, INFO
,
771 "Another function has the semaphore, so wait for the port init bit to come ready.\n");
772 status
= ql_wait_reg_rdy(qdev
, STS
, qdev
->port_init
, 0);
774 QPRINTK(qdev
, LINK
, CRIT
,
775 "Port initialize timed out.\n");
780 QPRINTK(qdev
, LINK
, INFO
, "Got xgmac semaphore!.\n");
781 /* Set the core reset. */
782 status
= ql_read_xgmac_reg(qdev
, GLOBAL_CFG
, &data
);
785 data
|= GLOBAL_CFG_RESET
;
786 status
= ql_write_xgmac_reg(qdev
, GLOBAL_CFG
, data
);
790 /* Clear the core reset and turn on jumbo for receiver. */
791 data
&= ~GLOBAL_CFG_RESET
; /* Clear core reset. */
792 data
|= GLOBAL_CFG_JUMBO
; /* Turn on jumbo. */
793 data
|= GLOBAL_CFG_TX_STAT_EN
;
794 data
|= GLOBAL_CFG_RX_STAT_EN
;
795 status
= ql_write_xgmac_reg(qdev
, GLOBAL_CFG
, data
);
799 /* Enable transmitter, and clear it's reset. */
800 status
= ql_read_xgmac_reg(qdev
, TX_CFG
, &data
);
803 data
&= ~TX_CFG_RESET
; /* Clear the TX MAC reset. */
804 data
|= TX_CFG_EN
; /* Enable the transmitter. */
805 status
= ql_write_xgmac_reg(qdev
, TX_CFG
, data
);
809 /* Enable receiver and clear it's reset. */
810 status
= ql_read_xgmac_reg(qdev
, RX_CFG
, &data
);
813 data
&= ~RX_CFG_RESET
; /* Clear the RX MAC reset. */
814 data
|= RX_CFG_EN
; /* Enable the receiver. */
815 status
= ql_write_xgmac_reg(qdev
, RX_CFG
, data
);
821 ql_write_xgmac_reg(qdev
, MAC_TX_PARAMS
, MAC_TX_PARAMS_JUMBO
| (0x2580 << 16));
825 ql_write_xgmac_reg(qdev
, MAC_RX_PARAMS
, 0x2580);
829 /* Signal to the world that the port is enabled. */
830 ql_write32(qdev
, STS
, ((qdev
->port_init
<< 16) | qdev
->port_init
));
832 ql_sem_unlock(qdev
, qdev
->xg_sem_mask
);
836 /* Get the next large buffer. */
837 static struct bq_desc
*ql_get_curr_lbuf(struct rx_ring
*rx_ring
)
839 struct bq_desc
*lbq_desc
= &rx_ring
->lbq
[rx_ring
->lbq_curr_idx
];
840 rx_ring
->lbq_curr_idx
++;
841 if (rx_ring
->lbq_curr_idx
== rx_ring
->lbq_len
)
842 rx_ring
->lbq_curr_idx
= 0;
843 rx_ring
->lbq_free_cnt
++;
847 /* Get the next small buffer. */
848 static struct bq_desc
*ql_get_curr_sbuf(struct rx_ring
*rx_ring
)
850 struct bq_desc
*sbq_desc
= &rx_ring
->sbq
[rx_ring
->sbq_curr_idx
];
851 rx_ring
->sbq_curr_idx
++;
852 if (rx_ring
->sbq_curr_idx
== rx_ring
->sbq_len
)
853 rx_ring
->sbq_curr_idx
= 0;
854 rx_ring
->sbq_free_cnt
++;
858 /* Update an rx ring index. */
859 static void ql_update_cq(struct rx_ring
*rx_ring
)
861 rx_ring
->cnsmr_idx
++;
862 rx_ring
->curr_entry
++;
863 if (unlikely(rx_ring
->cnsmr_idx
== rx_ring
->cq_len
)) {
864 rx_ring
->cnsmr_idx
= 0;
865 rx_ring
->curr_entry
= rx_ring
->cq_base
;
869 static void ql_write_cq_idx(struct rx_ring
*rx_ring
)
871 ql_write_db_reg(rx_ring
->cnsmr_idx
, rx_ring
->cnsmr_idx_db_reg
);
874 /* Process (refill) a large buffer queue. */
875 static void ql_update_lbq(struct ql_adapter
*qdev
, struct rx_ring
*rx_ring
)
877 int clean_idx
= rx_ring
->lbq_clean_idx
;
878 struct bq_desc
*lbq_desc
;
882 while (rx_ring
->lbq_free_cnt
> 16) {
883 for (i
= 0; i
< 16; i
++) {
884 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
885 "lbq: try cleaning clean_idx = %d.\n",
887 lbq_desc
= &rx_ring
->lbq
[clean_idx
];
888 if (lbq_desc
->p
.lbq_page
== NULL
) {
889 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
890 "lbq: getting new page for index %d.\n",
892 lbq_desc
->p
.lbq_page
= alloc_page(GFP_ATOMIC
);
893 if (lbq_desc
->p
.lbq_page
== NULL
) {
894 QPRINTK(qdev
, RX_STATUS
, ERR
,
895 "Couldn't get a page.\n");
898 map
= pci_map_page(qdev
->pdev
,
899 lbq_desc
->p
.lbq_page
,
902 if (pci_dma_mapping_error(qdev
->pdev
, map
)) {
903 QPRINTK(qdev
, RX_STATUS
, ERR
,
904 "PCI mapping failed.\n");
907 pci_unmap_addr_set(lbq_desc
, mapaddr
, map
);
908 pci_unmap_len_set(lbq_desc
, maplen
, PAGE_SIZE
);
909 *lbq_desc
->addr
= cpu_to_le64(map
);
912 if (clean_idx
== rx_ring
->lbq_len
)
916 rx_ring
->lbq_clean_idx
= clean_idx
;
917 rx_ring
->lbq_prod_idx
+= 16;
918 if (rx_ring
->lbq_prod_idx
== rx_ring
->lbq_len
)
919 rx_ring
->lbq_prod_idx
= 0;
920 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
921 "lbq: updating prod idx = %d.\n",
922 rx_ring
->lbq_prod_idx
);
923 ql_write_db_reg(rx_ring
->lbq_prod_idx
,
924 rx_ring
->lbq_prod_idx_db_reg
);
925 rx_ring
->lbq_free_cnt
-= 16;
929 /* Process (refill) a small buffer queue. */
930 static void ql_update_sbq(struct ql_adapter
*qdev
, struct rx_ring
*rx_ring
)
932 int clean_idx
= rx_ring
->sbq_clean_idx
;
933 struct bq_desc
*sbq_desc
;
937 while (rx_ring
->sbq_free_cnt
> 16) {
938 for (i
= 0; i
< 16; i
++) {
939 sbq_desc
= &rx_ring
->sbq
[clean_idx
];
940 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
941 "sbq: try cleaning clean_idx = %d.\n",
943 if (sbq_desc
->p
.skb
== NULL
) {
944 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
945 "sbq: getting new skb for index %d.\n",
948 netdev_alloc_skb(qdev
->ndev
,
949 rx_ring
->sbq_buf_size
);
950 if (sbq_desc
->p
.skb
== NULL
) {
951 QPRINTK(qdev
, PROBE
, ERR
,
952 "Couldn't get an skb.\n");
953 rx_ring
->sbq_clean_idx
= clean_idx
;
956 skb_reserve(sbq_desc
->p
.skb
, QLGE_SB_PAD
);
957 map
= pci_map_single(qdev
->pdev
,
958 sbq_desc
->p
.skb
->data
,
959 rx_ring
->sbq_buf_size
/
960 2, PCI_DMA_FROMDEVICE
);
961 if (pci_dma_mapping_error(qdev
->pdev
, map
)) {
962 QPRINTK(qdev
, IFUP
, ERR
, "PCI mapping failed.\n");
963 rx_ring
->sbq_clean_idx
= clean_idx
;
966 pci_unmap_addr_set(sbq_desc
, mapaddr
, map
);
967 pci_unmap_len_set(sbq_desc
, maplen
,
968 rx_ring
->sbq_buf_size
/ 2);
969 *sbq_desc
->addr
= cpu_to_le64(map
);
973 if (clean_idx
== rx_ring
->sbq_len
)
976 rx_ring
->sbq_clean_idx
= clean_idx
;
977 rx_ring
->sbq_prod_idx
+= 16;
978 if (rx_ring
->sbq_prod_idx
== rx_ring
->sbq_len
)
979 rx_ring
->sbq_prod_idx
= 0;
980 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
981 "sbq: updating prod idx = %d.\n",
982 rx_ring
->sbq_prod_idx
);
983 ql_write_db_reg(rx_ring
->sbq_prod_idx
,
984 rx_ring
->sbq_prod_idx_db_reg
);
986 rx_ring
->sbq_free_cnt
-= 16;
990 static void ql_update_buffer_queues(struct ql_adapter
*qdev
,
991 struct rx_ring
*rx_ring
)
993 ql_update_sbq(qdev
, rx_ring
);
994 ql_update_lbq(qdev
, rx_ring
);
997 /* Unmaps tx buffers. Can be called from send() if a pci mapping
998 * fails at some stage, or from the interrupt when a tx completes.
1000 static void ql_unmap_send(struct ql_adapter
*qdev
,
1001 struct tx_ring_desc
*tx_ring_desc
, int mapped
)
1004 for (i
= 0; i
< mapped
; i
++) {
1005 if (i
== 0 || (i
== 7 && mapped
> 7)) {
1007 * Unmap the skb->data area, or the
1008 * external sglist (AKA the Outbound
1009 * Address List (OAL)).
1010 * If its the zeroeth element, then it's
1011 * the skb->data area. If it's the 7th
1012 * element and there is more than 6 frags,
1016 QPRINTK(qdev
, TX_DONE
, DEBUG
,
1017 "unmapping OAL area.\n");
1019 pci_unmap_single(qdev
->pdev
,
1020 pci_unmap_addr(&tx_ring_desc
->map
[i
],
1022 pci_unmap_len(&tx_ring_desc
->map
[i
],
1026 QPRINTK(qdev
, TX_DONE
, DEBUG
, "unmapping frag %d.\n",
1028 pci_unmap_page(qdev
->pdev
,
1029 pci_unmap_addr(&tx_ring_desc
->map
[i
],
1031 pci_unmap_len(&tx_ring_desc
->map
[i
],
1032 maplen
), PCI_DMA_TODEVICE
);
1038 /* Map the buffers for this transmit. This will return
1039 * NETDEV_TX_BUSY or NETDEV_TX_OK based on success.
1041 static int ql_map_send(struct ql_adapter
*qdev
,
1042 struct ob_mac_iocb_req
*mac_iocb_ptr
,
1043 struct sk_buff
*skb
, struct tx_ring_desc
*tx_ring_desc
)
1045 int len
= skb_headlen(skb
);
1047 int frag_idx
, err
, map_idx
= 0;
1048 struct tx_buf_desc
*tbd
= mac_iocb_ptr
->tbd
;
1049 int frag_cnt
= skb_shinfo(skb
)->nr_frags
;
1052 QPRINTK(qdev
, TX_QUEUED
, DEBUG
, "frag_cnt = %d.\n", frag_cnt
);
1055 * Map the skb buffer first.
1057 map
= pci_map_single(qdev
->pdev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
1059 err
= pci_dma_mapping_error(qdev
->pdev
, map
);
1061 QPRINTK(qdev
, TX_QUEUED
, ERR
,
1062 "PCI mapping failed with error: %d\n", err
);
1064 return NETDEV_TX_BUSY
;
1067 tbd
->len
= cpu_to_le32(len
);
1068 tbd
->addr
= cpu_to_le64(map
);
1069 pci_unmap_addr_set(&tx_ring_desc
->map
[map_idx
], mapaddr
, map
);
1070 pci_unmap_len_set(&tx_ring_desc
->map
[map_idx
], maplen
, len
);
1074 * This loop fills the remainder of the 8 address descriptors
1075 * in the IOCB. If there are more than 7 fragments, then the
1076 * eighth address desc will point to an external list (OAL).
1077 * When this happens, the remainder of the frags will be stored
1080 for (frag_idx
= 0; frag_idx
< frag_cnt
; frag_idx
++, map_idx
++) {
1081 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[frag_idx
];
1083 if (frag_idx
== 6 && frag_cnt
> 7) {
1084 /* Let's tack on an sglist.
1085 * Our control block will now
1087 * iocb->seg[0] = skb->data
1088 * iocb->seg[1] = frag[0]
1089 * iocb->seg[2] = frag[1]
1090 * iocb->seg[3] = frag[2]
1091 * iocb->seg[4] = frag[3]
1092 * iocb->seg[5] = frag[4]
1093 * iocb->seg[6] = frag[5]
1094 * iocb->seg[7] = ptr to OAL (external sglist)
1095 * oal->seg[0] = frag[6]
1096 * oal->seg[1] = frag[7]
1097 * oal->seg[2] = frag[8]
1098 * oal->seg[3] = frag[9]
1099 * oal->seg[4] = frag[10]
1102 /* Tack on the OAL in the eighth segment of IOCB. */
1103 map
= pci_map_single(qdev
->pdev
, &tx_ring_desc
->oal
,
1106 err
= pci_dma_mapping_error(qdev
->pdev
, map
);
1108 QPRINTK(qdev
, TX_QUEUED
, ERR
,
1109 "PCI mapping outbound address list with error: %d\n",
1114 tbd
->addr
= cpu_to_le64(map
);
1116 * The length is the number of fragments
1117 * that remain to be mapped times the length
1118 * of our sglist (OAL).
1121 cpu_to_le32((sizeof(struct tx_buf_desc
) *
1122 (frag_cnt
- frag_idx
)) | TX_DESC_C
);
1123 pci_unmap_addr_set(&tx_ring_desc
->map
[map_idx
], mapaddr
,
1125 pci_unmap_len_set(&tx_ring_desc
->map
[map_idx
], maplen
,
1126 sizeof(struct oal
));
1127 tbd
= (struct tx_buf_desc
*)&tx_ring_desc
->oal
;
1132 pci_map_page(qdev
->pdev
, frag
->page
,
1133 frag
->page_offset
, frag
->size
,
1136 err
= pci_dma_mapping_error(qdev
->pdev
, map
);
1138 QPRINTK(qdev
, TX_QUEUED
, ERR
,
1139 "PCI mapping frags failed with error: %d.\n",
1144 tbd
->addr
= cpu_to_le64(map
);
1145 tbd
->len
= cpu_to_le32(frag
->size
);
1146 pci_unmap_addr_set(&tx_ring_desc
->map
[map_idx
], mapaddr
, map
);
1147 pci_unmap_len_set(&tx_ring_desc
->map
[map_idx
], maplen
,
1151 /* Save the number of segments we've mapped. */
1152 tx_ring_desc
->map_cnt
= map_idx
;
1153 /* Terminate the last segment. */
1154 tbd
->len
= cpu_to_le32(le32_to_cpu(tbd
->len
) | TX_DESC_E
);
1155 return NETDEV_TX_OK
;
1159 * If the first frag mapping failed, then i will be zero.
1160 * This causes the unmap of the skb->data area. Otherwise
1161 * we pass in the number of frags that mapped successfully
1162 * so they can be umapped.
1164 ql_unmap_send(qdev
, tx_ring_desc
, map_idx
);
1165 return NETDEV_TX_BUSY
;
1168 static void ql_realign_skb(struct sk_buff
*skb
, int len
)
1170 void *temp_addr
= skb
->data
;
1172 /* Undo the skb_reserve(skb,32) we did before
1173 * giving to hardware, and realign data on
1174 * a 2-byte boundary.
1176 skb
->data
-= QLGE_SB_PAD
- NET_IP_ALIGN
;
1177 skb
->tail
-= QLGE_SB_PAD
- NET_IP_ALIGN
;
1178 skb_copy_to_linear_data(skb
, temp_addr
,
1183 * This function builds an skb for the given inbound
1184 * completion. It will be rewritten for readability in the near
1185 * future, but for not it works well.
1187 static struct sk_buff
*ql_build_rx_skb(struct ql_adapter
*qdev
,
1188 struct rx_ring
*rx_ring
,
1189 struct ib_mac_iocb_rsp
*ib_mac_rsp
)
1191 struct bq_desc
*lbq_desc
;
1192 struct bq_desc
*sbq_desc
;
1193 struct sk_buff
*skb
= NULL
;
1194 u32 length
= le32_to_cpu(ib_mac_rsp
->data_len
);
1195 u32 hdr_len
= le32_to_cpu(ib_mac_rsp
->hdr_len
);
1198 * Handle the header buffer if present.
1200 if (ib_mac_rsp
->flags4
& IB_MAC_IOCB_RSP_HV
&&
1201 ib_mac_rsp
->flags4
& IB_MAC_IOCB_RSP_HS
) {
1202 QPRINTK(qdev
, RX_STATUS
, DEBUG
, "Header of %d bytes in small buffer.\n", hdr_len
);
1204 * Headers fit nicely into a small buffer.
1206 sbq_desc
= ql_get_curr_sbuf(rx_ring
);
1207 pci_unmap_single(qdev
->pdev
,
1208 pci_unmap_addr(sbq_desc
, mapaddr
),
1209 pci_unmap_len(sbq_desc
, maplen
),
1210 PCI_DMA_FROMDEVICE
);
1211 skb
= sbq_desc
->p
.skb
;
1212 ql_realign_skb(skb
, hdr_len
);
1213 skb_put(skb
, hdr_len
);
1214 sbq_desc
->p
.skb
= NULL
;
1218 * Handle the data buffer(s).
1220 if (unlikely(!length
)) { /* Is there data too? */
1221 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
1222 "No Data buffer in this packet.\n");
1226 if (ib_mac_rsp
->flags3
& IB_MAC_IOCB_RSP_DS
) {
1227 if (ib_mac_rsp
->flags4
& IB_MAC_IOCB_RSP_HS
) {
1228 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
1229 "Headers in small, data of %d bytes in small, combine them.\n", length
);
1231 * Data is less than small buffer size so it's
1232 * stuffed in a small buffer.
1233 * For this case we append the data
1234 * from the "data" small buffer to the "header" small
1237 sbq_desc
= ql_get_curr_sbuf(rx_ring
);
1238 pci_dma_sync_single_for_cpu(qdev
->pdev
,
1240 (sbq_desc
, mapaddr
),
1243 PCI_DMA_FROMDEVICE
);
1244 memcpy(skb_put(skb
, length
),
1245 sbq_desc
->p
.skb
->data
, length
);
1246 pci_dma_sync_single_for_device(qdev
->pdev
,
1253 PCI_DMA_FROMDEVICE
);
1255 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
1256 "%d bytes in a single small buffer.\n", length
);
1257 sbq_desc
= ql_get_curr_sbuf(rx_ring
);
1258 skb
= sbq_desc
->p
.skb
;
1259 ql_realign_skb(skb
, length
);
1260 skb_put(skb
, length
);
1261 pci_unmap_single(qdev
->pdev
,
1262 pci_unmap_addr(sbq_desc
,
1264 pci_unmap_len(sbq_desc
,
1266 PCI_DMA_FROMDEVICE
);
1267 sbq_desc
->p
.skb
= NULL
;
1269 } else if (ib_mac_rsp
->flags3
& IB_MAC_IOCB_RSP_DL
) {
1270 if (ib_mac_rsp
->flags4
& IB_MAC_IOCB_RSP_HS
) {
1271 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
1272 "Header in small, %d bytes in large. Chain large to small!\n", length
);
1274 * The data is in a single large buffer. We
1275 * chain it to the header buffer's skb and let
1278 lbq_desc
= ql_get_curr_lbuf(rx_ring
);
1279 pci_unmap_page(qdev
->pdev
,
1280 pci_unmap_addr(lbq_desc
,
1282 pci_unmap_len(lbq_desc
, maplen
),
1283 PCI_DMA_FROMDEVICE
);
1284 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
1285 "Chaining page to skb.\n");
1286 skb_fill_page_desc(skb
, 0, lbq_desc
->p
.lbq_page
,
1289 skb
->data_len
+= length
;
1290 skb
->truesize
+= length
;
1291 lbq_desc
->p
.lbq_page
= NULL
;
1294 * The headers and data are in a single large buffer. We
1295 * copy it to a new skb and let it go. This can happen with
1296 * jumbo mtu on a non-TCP/UDP frame.
1298 lbq_desc
= ql_get_curr_lbuf(rx_ring
);
1299 skb
= netdev_alloc_skb(qdev
->ndev
, length
);
1301 QPRINTK(qdev
, PROBE
, DEBUG
,
1302 "No skb available, drop the packet.\n");
1305 pci_unmap_page(qdev
->pdev
,
1306 pci_unmap_addr(lbq_desc
,
1308 pci_unmap_len(lbq_desc
, maplen
),
1309 PCI_DMA_FROMDEVICE
);
1310 skb_reserve(skb
, NET_IP_ALIGN
);
1311 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
1312 "%d bytes of headers and data in large. Chain page to new skb and pull tail.\n", length
);
1313 skb_fill_page_desc(skb
, 0, lbq_desc
->p
.lbq_page
,
1316 skb
->data_len
+= length
;
1317 skb
->truesize
+= length
;
1319 lbq_desc
->p
.lbq_page
= NULL
;
1320 __pskb_pull_tail(skb
,
1321 (ib_mac_rsp
->flags2
& IB_MAC_IOCB_RSP_V
) ?
1322 VLAN_ETH_HLEN
: ETH_HLEN
);
1326 * The data is in a chain of large buffers
1327 * pointed to by a small buffer. We loop
1328 * thru and chain them to the our small header
1330 * frags: There are 18 max frags and our small
1331 * buffer will hold 32 of them. The thing is,
1332 * we'll use 3 max for our 9000 byte jumbo
1333 * frames. If the MTU goes up we could
1334 * eventually be in trouble.
1336 int size
, offset
, i
= 0;
1337 __le64
*bq
, bq_array
[8];
1338 sbq_desc
= ql_get_curr_sbuf(rx_ring
);
1339 pci_unmap_single(qdev
->pdev
,
1340 pci_unmap_addr(sbq_desc
, mapaddr
),
1341 pci_unmap_len(sbq_desc
, maplen
),
1342 PCI_DMA_FROMDEVICE
);
1343 if (!(ib_mac_rsp
->flags4
& IB_MAC_IOCB_RSP_HS
)) {
1345 * This is an non TCP/UDP IP frame, so
1346 * the headers aren't split into a small
1347 * buffer. We have to use the small buffer
1348 * that contains our sg list as our skb to
1349 * send upstairs. Copy the sg list here to
1350 * a local buffer and use it to find the
1353 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
1354 "%d bytes of headers & data in chain of large.\n", length
);
1355 skb
= sbq_desc
->p
.skb
;
1357 memcpy(bq
, skb
->data
, sizeof(bq_array
));
1358 sbq_desc
->p
.skb
= NULL
;
1359 skb_reserve(skb
, NET_IP_ALIGN
);
1361 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
1362 "Headers in small, %d bytes of data in chain of large.\n", length
);
1363 bq
= (__le64
*)sbq_desc
->p
.skb
->data
;
1365 while (length
> 0) {
1366 lbq_desc
= ql_get_curr_lbuf(rx_ring
);
1367 pci_unmap_page(qdev
->pdev
,
1368 pci_unmap_addr(lbq_desc
,
1370 pci_unmap_len(lbq_desc
,
1372 PCI_DMA_FROMDEVICE
);
1373 size
= (length
< PAGE_SIZE
) ? length
: PAGE_SIZE
;
1376 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
1377 "Adding page %d to skb for %d bytes.\n",
1379 skb_fill_page_desc(skb
, i
, lbq_desc
->p
.lbq_page
,
1382 skb
->data_len
+= size
;
1383 skb
->truesize
+= size
;
1385 lbq_desc
->p
.lbq_page
= NULL
;
1389 __pskb_pull_tail(skb
, (ib_mac_rsp
->flags2
& IB_MAC_IOCB_RSP_V
) ?
1390 VLAN_ETH_HLEN
: ETH_HLEN
);
1395 /* Process an inbound completion from an rx ring. */
1396 static void ql_process_mac_rx_intr(struct ql_adapter
*qdev
,
1397 struct rx_ring
*rx_ring
,
1398 struct ib_mac_iocb_rsp
*ib_mac_rsp
)
1400 struct net_device
*ndev
= qdev
->ndev
;
1401 struct sk_buff
*skb
= NULL
;
1403 QL_DUMP_IB_MAC_RSP(ib_mac_rsp
);
1405 skb
= ql_build_rx_skb(qdev
, rx_ring
, ib_mac_rsp
);
1406 if (unlikely(!skb
)) {
1407 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
1408 "No skb available, drop packet.\n");
1412 prefetch(skb
->data
);
1414 if (ib_mac_rsp
->flags1
& IB_MAC_IOCB_RSP_M_MASK
) {
1415 QPRINTK(qdev
, RX_STATUS
, DEBUG
, "%s%s%s Multicast.\n",
1416 (ib_mac_rsp
->flags1
& IB_MAC_IOCB_RSP_M_MASK
) ==
1417 IB_MAC_IOCB_RSP_M_HASH
? "Hash" : "",
1418 (ib_mac_rsp
->flags1
& IB_MAC_IOCB_RSP_M_MASK
) ==
1419 IB_MAC_IOCB_RSP_M_REG
? "Registered" : "",
1420 (ib_mac_rsp
->flags1
& IB_MAC_IOCB_RSP_M_MASK
) ==
1421 IB_MAC_IOCB_RSP_M_PROM
? "Promiscuous" : "");
1423 if (ib_mac_rsp
->flags2
& IB_MAC_IOCB_RSP_P
) {
1424 QPRINTK(qdev
, RX_STATUS
, DEBUG
, "Promiscuous Packet.\n");
1426 if (ib_mac_rsp
->flags1
& (IB_MAC_IOCB_RSP_IE
| IB_MAC_IOCB_RSP_TE
)) {
1427 QPRINTK(qdev
, RX_STATUS
, ERR
,
1428 "Bad checksum for this %s packet.\n",
1430 flags2
& IB_MAC_IOCB_RSP_T
) ? "TCP" : "UDP"));
1431 skb
->ip_summed
= CHECKSUM_NONE
;
1432 } else if (qdev
->rx_csum
&&
1433 ((ib_mac_rsp
->flags2
& IB_MAC_IOCB_RSP_T
) ||
1434 ((ib_mac_rsp
->flags2
& IB_MAC_IOCB_RSP_U
) &&
1435 !(ib_mac_rsp
->flags1
& IB_MAC_IOCB_RSP_NU
)))) {
1436 QPRINTK(qdev
, RX_STATUS
, DEBUG
, "RX checksum done!\n");
1437 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1439 qdev
->stats
.rx_packets
++;
1440 qdev
->stats
.rx_bytes
+= skb
->len
;
1441 skb
->protocol
= eth_type_trans(skb
, ndev
);
1442 if (qdev
->vlgrp
&& (ib_mac_rsp
->flags2
& IB_MAC_IOCB_RSP_V
)) {
1443 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
1444 "Passing a VLAN packet upstream.\n");
1445 vlan_hwaccel_rx(skb
, qdev
->vlgrp
,
1446 le16_to_cpu(ib_mac_rsp
->vlan_id
));
1448 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
1449 "Passing a normal packet upstream.\n");
1454 /* Process an outbound completion from an rx ring. */
1455 static void ql_process_mac_tx_intr(struct ql_adapter
*qdev
,
1456 struct ob_mac_iocb_rsp
*mac_rsp
)
1458 struct tx_ring
*tx_ring
;
1459 struct tx_ring_desc
*tx_ring_desc
;
1461 QL_DUMP_OB_MAC_RSP(mac_rsp
);
1462 tx_ring
= &qdev
->tx_ring
[mac_rsp
->txq_idx
];
1463 tx_ring_desc
= &tx_ring
->q
[mac_rsp
->tid
];
1464 ql_unmap_send(qdev
, tx_ring_desc
, tx_ring_desc
->map_cnt
);
1465 qdev
->stats
.tx_bytes
+= tx_ring_desc
->map_cnt
;
1466 qdev
->stats
.tx_packets
++;
1467 dev_kfree_skb(tx_ring_desc
->skb
);
1468 tx_ring_desc
->skb
= NULL
;
1470 if (unlikely(mac_rsp
->flags1
& (OB_MAC_IOCB_RSP_E
|
1473 OB_MAC_IOCB_RSP_P
| OB_MAC_IOCB_RSP_B
))) {
1474 if (mac_rsp
->flags1
& OB_MAC_IOCB_RSP_E
) {
1475 QPRINTK(qdev
, TX_DONE
, WARNING
,
1476 "Total descriptor length did not match transfer length.\n");
1478 if (mac_rsp
->flags1
& OB_MAC_IOCB_RSP_S
) {
1479 QPRINTK(qdev
, TX_DONE
, WARNING
,
1480 "Frame too short to be legal, not sent.\n");
1482 if (mac_rsp
->flags1
& OB_MAC_IOCB_RSP_L
) {
1483 QPRINTK(qdev
, TX_DONE
, WARNING
,
1484 "Frame too long, but sent anyway.\n");
1486 if (mac_rsp
->flags1
& OB_MAC_IOCB_RSP_B
) {
1487 QPRINTK(qdev
, TX_DONE
, WARNING
,
1488 "PCI backplane error. Frame not sent.\n");
1491 atomic_inc(&tx_ring
->tx_count
);
1494 /* Fire up a handler to reset the MPI processor. */
1495 void ql_queue_fw_error(struct ql_adapter
*qdev
)
1497 netif_stop_queue(qdev
->ndev
);
1498 netif_carrier_off(qdev
->ndev
);
1499 queue_delayed_work(qdev
->workqueue
, &qdev
->mpi_reset_work
, 0);
1502 void ql_queue_asic_error(struct ql_adapter
*qdev
)
1504 netif_stop_queue(qdev
->ndev
);
1505 netif_carrier_off(qdev
->ndev
);
1506 ql_disable_interrupts(qdev
);
1507 queue_delayed_work(qdev
->workqueue
, &qdev
->asic_reset_work
, 0);
1510 static void ql_process_chip_ae_intr(struct ql_adapter
*qdev
,
1511 struct ib_ae_iocb_rsp
*ib_ae_rsp
)
1513 switch (ib_ae_rsp
->event
) {
1514 case MGMT_ERR_EVENT
:
1515 QPRINTK(qdev
, RX_ERR
, ERR
,
1516 "Management Processor Fatal Error.\n");
1517 ql_queue_fw_error(qdev
);
1520 case CAM_LOOKUP_ERR_EVENT
:
1521 QPRINTK(qdev
, LINK
, ERR
,
1522 "Multiple CAM hits lookup occurred.\n");
1523 QPRINTK(qdev
, DRV
, ERR
, "This event shouldn't occur.\n");
1524 ql_queue_asic_error(qdev
);
1527 case SOFT_ECC_ERROR_EVENT
:
1528 QPRINTK(qdev
, RX_ERR
, ERR
, "Soft ECC error detected.\n");
1529 ql_queue_asic_error(qdev
);
1532 case PCI_ERR_ANON_BUF_RD
:
1533 QPRINTK(qdev
, RX_ERR
, ERR
,
1534 "PCI error occurred when reading anonymous buffers from rx_ring %d.\n",
1536 ql_queue_asic_error(qdev
);
1540 QPRINTK(qdev
, DRV
, ERR
, "Unexpected event %d.\n",
1542 ql_queue_asic_error(qdev
);
1547 static int ql_clean_outbound_rx_ring(struct rx_ring
*rx_ring
)
1549 struct ql_adapter
*qdev
= rx_ring
->qdev
;
1550 u32 prod
= ql_read_sh_reg(rx_ring
->prod_idx_sh_reg
);
1551 struct ob_mac_iocb_rsp
*net_rsp
= NULL
;
1554 /* While there are entries in the completion queue. */
1555 while (prod
!= rx_ring
->cnsmr_idx
) {
1557 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
1558 "cq_id = %d, prod = %d, cnsmr = %d.\n.", rx_ring
->cq_id
,
1559 prod
, rx_ring
->cnsmr_idx
);
1561 net_rsp
= (struct ob_mac_iocb_rsp
*)rx_ring
->curr_entry
;
1563 switch (net_rsp
->opcode
) {
1565 case OPCODE_OB_MAC_TSO_IOCB
:
1566 case OPCODE_OB_MAC_IOCB
:
1567 ql_process_mac_tx_intr(qdev
, net_rsp
);
1570 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
1571 "Hit default case, not handled! dropping the packet, opcode = %x.\n",
1575 ql_update_cq(rx_ring
);
1576 prod
= ql_read_sh_reg(rx_ring
->prod_idx_sh_reg
);
1578 ql_write_cq_idx(rx_ring
);
1579 if (netif_queue_stopped(qdev
->ndev
) && net_rsp
!= NULL
) {
1580 struct tx_ring
*tx_ring
= &qdev
->tx_ring
[net_rsp
->txq_idx
];
1581 if (atomic_read(&tx_ring
->queue_stopped
) &&
1582 (atomic_read(&tx_ring
->tx_count
) > (tx_ring
->wq_len
/ 4)))
1584 * The queue got stopped because the tx_ring was full.
1585 * Wake it up, because it's now at least 25% empty.
1587 netif_wake_queue(qdev
->ndev
);
1593 static int ql_clean_inbound_rx_ring(struct rx_ring
*rx_ring
, int budget
)
1595 struct ql_adapter
*qdev
= rx_ring
->qdev
;
1596 u32 prod
= ql_read_sh_reg(rx_ring
->prod_idx_sh_reg
);
1597 struct ql_net_rsp_iocb
*net_rsp
;
1600 /* While there are entries in the completion queue. */
1601 while (prod
!= rx_ring
->cnsmr_idx
) {
1603 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
1604 "cq_id = %d, prod = %d, cnsmr = %d.\n.", rx_ring
->cq_id
,
1605 prod
, rx_ring
->cnsmr_idx
);
1607 net_rsp
= rx_ring
->curr_entry
;
1609 switch (net_rsp
->opcode
) {
1610 case OPCODE_IB_MAC_IOCB
:
1611 ql_process_mac_rx_intr(qdev
, rx_ring
,
1612 (struct ib_mac_iocb_rsp
*)
1616 case OPCODE_IB_AE_IOCB
:
1617 ql_process_chip_ae_intr(qdev
, (struct ib_ae_iocb_rsp
*)
1622 QPRINTK(qdev
, RX_STATUS
, DEBUG
,
1623 "Hit default case, not handled! dropping the packet, opcode = %x.\n",
1628 ql_update_cq(rx_ring
);
1629 prod
= ql_read_sh_reg(rx_ring
->prod_idx_sh_reg
);
1630 if (count
== budget
)
1633 ql_update_buffer_queues(qdev
, rx_ring
);
1634 ql_write_cq_idx(rx_ring
);
1638 static int ql_napi_poll_msix(struct napi_struct
*napi
, int budget
)
1640 struct rx_ring
*rx_ring
= container_of(napi
, struct rx_ring
, napi
);
1641 struct ql_adapter
*qdev
= rx_ring
->qdev
;
1642 int work_done
= ql_clean_inbound_rx_ring(rx_ring
, budget
);
1644 QPRINTK(qdev
, RX_STATUS
, DEBUG
, "Enter, NAPI POLL cq_id = %d.\n",
1647 if (work_done
< budget
) {
1648 __netif_rx_complete(napi
);
1649 ql_enable_completion_interrupt(qdev
, rx_ring
->irq
);
1654 static void ql_vlan_rx_register(struct net_device
*ndev
, struct vlan_group
*grp
)
1656 struct ql_adapter
*qdev
= netdev_priv(ndev
);
1660 QPRINTK(qdev
, IFUP
, DEBUG
, "Turning on VLAN in NIC_RCV_CFG.\n");
1661 ql_write32(qdev
, NIC_RCV_CFG
, NIC_RCV_CFG_VLAN_MASK
|
1662 NIC_RCV_CFG_VLAN_MATCH_AND_NON
);
1664 QPRINTK(qdev
, IFUP
, DEBUG
,
1665 "Turning off VLAN in NIC_RCV_CFG.\n");
1666 ql_write32(qdev
, NIC_RCV_CFG
, NIC_RCV_CFG_VLAN_MASK
);
1670 static void ql_vlan_rx_add_vid(struct net_device
*ndev
, u16 vid
)
1672 struct ql_adapter
*qdev
= netdev_priv(ndev
);
1673 u32 enable_bit
= MAC_ADDR_E
;
1675 spin_lock(&qdev
->hw_lock
);
1676 if (ql_set_mac_addr_reg
1677 (qdev
, (u8
*) &enable_bit
, MAC_ADDR_TYPE_VLAN
, vid
)) {
1678 QPRINTK(qdev
, IFUP
, ERR
, "Failed to init vlan address.\n");
1680 spin_unlock(&qdev
->hw_lock
);
1683 static void ql_vlan_rx_kill_vid(struct net_device
*ndev
, u16 vid
)
1685 struct ql_adapter
*qdev
= netdev_priv(ndev
);
1688 spin_lock(&qdev
->hw_lock
);
1689 if (ql_set_mac_addr_reg
1690 (qdev
, (u8
*) &enable_bit
, MAC_ADDR_TYPE_VLAN
, vid
)) {
1691 QPRINTK(qdev
, IFUP
, ERR
, "Failed to clear vlan address.\n");
1693 spin_unlock(&qdev
->hw_lock
);
1697 /* Worker thread to process a given rx_ring that is dedicated
1698 * to outbound completions.
1700 static void ql_tx_clean(struct work_struct
*work
)
1702 struct rx_ring
*rx_ring
=
1703 container_of(work
, struct rx_ring
, rx_work
.work
);
1704 ql_clean_outbound_rx_ring(rx_ring
);
1705 ql_enable_completion_interrupt(rx_ring
->qdev
, rx_ring
->irq
);
1709 /* Worker thread to process a given rx_ring that is dedicated
1710 * to inbound completions.
1712 static void ql_rx_clean(struct work_struct
*work
)
1714 struct rx_ring
*rx_ring
=
1715 container_of(work
, struct rx_ring
, rx_work
.work
);
1716 ql_clean_inbound_rx_ring(rx_ring
, 64);
1717 ql_enable_completion_interrupt(rx_ring
->qdev
, rx_ring
->irq
);
1720 /* MSI-X Multiple Vector Interrupt Handler for outbound completions. */
1721 static irqreturn_t
qlge_msix_tx_isr(int irq
, void *dev_id
)
1723 struct rx_ring
*rx_ring
= dev_id
;
1724 queue_delayed_work_on(rx_ring
->cpu
, rx_ring
->qdev
->q_workqueue
,
1725 &rx_ring
->rx_work
, 0);
1729 /* MSI-X Multiple Vector Interrupt Handler for inbound completions. */
1730 static irqreturn_t
qlge_msix_rx_isr(int irq
, void *dev_id
)
1732 struct rx_ring
*rx_ring
= dev_id
;
1733 netif_rx_schedule(&rx_ring
->napi
);
1737 /* This handles a fatal error, MPI activity, and the default
1738 * rx_ring in an MSI-X multiple vector environment.
1739 * In MSI/Legacy environment it also process the rest of
1742 static irqreturn_t
qlge_isr(int irq
, void *dev_id
)
1744 struct rx_ring
*rx_ring
= dev_id
;
1745 struct ql_adapter
*qdev
= rx_ring
->qdev
;
1746 struct intr_context
*intr_context
= &qdev
->intr_context
[0];
1751 spin_lock(&qdev
->hw_lock
);
1752 if (atomic_read(&qdev
->intr_context
[0].irq_cnt
)) {
1753 QPRINTK(qdev
, INTR
, DEBUG
, "Shared Interrupt, Not ours!\n");
1754 spin_unlock(&qdev
->hw_lock
);
1757 spin_unlock(&qdev
->hw_lock
);
1759 var
= ql_disable_completion_interrupt(qdev
, intr_context
->intr
);
1762 * Check for fatal error.
1765 ql_queue_asic_error(qdev
);
1766 QPRINTK(qdev
, INTR
, ERR
, "Got fatal error, STS = %x.\n", var
);
1767 var
= ql_read32(qdev
, ERR_STS
);
1768 QPRINTK(qdev
, INTR
, ERR
,
1769 "Resetting chip. Error Status Register = 0x%x\n", var
);
1774 * Check MPI processor activity.
1778 * We've got an async event or mailbox completion.
1779 * Handle it and clear the source of the interrupt.
1781 QPRINTK(qdev
, INTR
, ERR
, "Got MPI processor interrupt.\n");
1782 ql_disable_completion_interrupt(qdev
, intr_context
->intr
);
1783 queue_delayed_work_on(smp_processor_id(), qdev
->workqueue
,
1784 &qdev
->mpi_work
, 0);
1789 * Check the default queue and wake handler if active.
1791 rx_ring
= &qdev
->rx_ring
[0];
1792 if (ql_read_sh_reg(rx_ring
->prod_idx_sh_reg
) != rx_ring
->cnsmr_idx
) {
1793 QPRINTK(qdev
, INTR
, INFO
, "Waking handler for rx_ring[0].\n");
1794 ql_disable_completion_interrupt(qdev
, intr_context
->intr
);
1795 queue_delayed_work_on(smp_processor_id(), qdev
->q_workqueue
,
1796 &rx_ring
->rx_work
, 0);
1800 if (!test_bit(QL_MSIX_ENABLED
, &qdev
->flags
)) {
1802 * Start the DPC for each active queue.
1804 for (i
= 1; i
< qdev
->rx_ring_count
; i
++) {
1805 rx_ring
= &qdev
->rx_ring
[i
];
1806 if (ql_read_sh_reg(rx_ring
->prod_idx_sh_reg
) !=
1807 rx_ring
->cnsmr_idx
) {
1808 QPRINTK(qdev
, INTR
, INFO
,
1809 "Waking handler for rx_ring[%d].\n", i
);
1810 ql_disable_completion_interrupt(qdev
,
1813 if (i
< qdev
->rss_ring_first_cq_id
)
1814 queue_delayed_work_on(rx_ring
->cpu
,
1819 netif_rx_schedule(&rx_ring
->napi
);
1824 ql_enable_completion_interrupt(qdev
, intr_context
->intr
);
1825 return work_done
? IRQ_HANDLED
: IRQ_NONE
;
1828 static int ql_tso(struct sk_buff
*skb
, struct ob_mac_tso_iocb_req
*mac_iocb_ptr
)
1831 if (skb_is_gso(skb
)) {
1833 if (skb_header_cloned(skb
)) {
1834 err
= pskb_expand_head(skb
, 0, 0, GFP_ATOMIC
);
1839 mac_iocb_ptr
->opcode
= OPCODE_OB_MAC_TSO_IOCB
;
1840 mac_iocb_ptr
->flags3
|= OB_MAC_TSO_IOCB_IC
;
1841 mac_iocb_ptr
->frame_len
= cpu_to_le32((u32
) skb
->len
);
1842 mac_iocb_ptr
->total_hdrs_len
=
1843 cpu_to_le16(skb_transport_offset(skb
) + tcp_hdrlen(skb
));
1844 mac_iocb_ptr
->net_trans_offset
=
1845 cpu_to_le16(skb_network_offset(skb
) |
1846 skb_transport_offset(skb
)
1847 << OB_MAC_TRANSPORT_HDR_SHIFT
);
1848 mac_iocb_ptr
->mss
= cpu_to_le16(skb_shinfo(skb
)->gso_size
);
1849 mac_iocb_ptr
->flags2
|= OB_MAC_TSO_IOCB_LSO
;
1850 if (likely(skb
->protocol
== htons(ETH_P_IP
))) {
1851 struct iphdr
*iph
= ip_hdr(skb
);
1853 mac_iocb_ptr
->flags1
|= OB_MAC_TSO_IOCB_IP4
;
1854 tcp_hdr(skb
)->check
= ~csum_tcpudp_magic(iph
->saddr
,
1858 } else if (skb
->protocol
== htons(ETH_P_IPV6
)) {
1859 mac_iocb_ptr
->flags1
|= OB_MAC_TSO_IOCB_IP6
;
1860 tcp_hdr(skb
)->check
=
1861 ~csum_ipv6_magic(&ipv6_hdr(skb
)->saddr
,
1862 &ipv6_hdr(skb
)->daddr
,
1870 static void ql_hw_csum_setup(struct sk_buff
*skb
,
1871 struct ob_mac_tso_iocb_req
*mac_iocb_ptr
)
1874 struct iphdr
*iph
= ip_hdr(skb
);
1876 mac_iocb_ptr
->opcode
= OPCODE_OB_MAC_TSO_IOCB
;
1877 mac_iocb_ptr
->frame_len
= cpu_to_le32((u32
) skb
->len
);
1878 mac_iocb_ptr
->net_trans_offset
=
1879 cpu_to_le16(skb_network_offset(skb
) |
1880 skb_transport_offset(skb
) << OB_MAC_TRANSPORT_HDR_SHIFT
);
1882 mac_iocb_ptr
->flags1
|= OB_MAC_TSO_IOCB_IP4
;
1883 len
= (ntohs(iph
->tot_len
) - (iph
->ihl
<< 2));
1884 if (likely(iph
->protocol
== IPPROTO_TCP
)) {
1885 check
= &(tcp_hdr(skb
)->check
);
1886 mac_iocb_ptr
->flags2
|= OB_MAC_TSO_IOCB_TC
;
1887 mac_iocb_ptr
->total_hdrs_len
=
1888 cpu_to_le16(skb_transport_offset(skb
) +
1889 (tcp_hdr(skb
)->doff
<< 2));
1891 check
= &(udp_hdr(skb
)->check
);
1892 mac_iocb_ptr
->flags2
|= OB_MAC_TSO_IOCB_UC
;
1893 mac_iocb_ptr
->total_hdrs_len
=
1894 cpu_to_le16(skb_transport_offset(skb
) +
1895 sizeof(struct udphdr
));
1897 *check
= ~csum_tcpudp_magic(iph
->saddr
,
1898 iph
->daddr
, len
, iph
->protocol
, 0);
1901 static int qlge_send(struct sk_buff
*skb
, struct net_device
*ndev
)
1903 struct tx_ring_desc
*tx_ring_desc
;
1904 struct ob_mac_iocb_req
*mac_iocb_ptr
;
1905 struct ql_adapter
*qdev
= netdev_priv(ndev
);
1907 struct tx_ring
*tx_ring
;
1908 u32 tx_ring_idx
= (u32
) QL_TXQ_IDX(qdev
, skb
);
1910 tx_ring
= &qdev
->tx_ring
[tx_ring_idx
];
1912 if (unlikely(atomic_read(&tx_ring
->tx_count
) < 2)) {
1913 QPRINTK(qdev
, TX_QUEUED
, INFO
,
1914 "%s: shutting down tx queue %d du to lack of resources.\n",
1915 __func__
, tx_ring_idx
);
1916 netif_stop_queue(ndev
);
1917 atomic_inc(&tx_ring
->queue_stopped
);
1918 return NETDEV_TX_BUSY
;
1920 tx_ring_desc
= &tx_ring
->q
[tx_ring
->prod_idx
];
1921 mac_iocb_ptr
= tx_ring_desc
->queue_entry
;
1922 memset((void *)mac_iocb_ptr
, 0, sizeof(mac_iocb_ptr
));
1923 if (ql_map_send(qdev
, mac_iocb_ptr
, skb
, tx_ring_desc
) != NETDEV_TX_OK
) {
1924 QPRINTK(qdev
, TX_QUEUED
, ERR
, "Could not map the segments.\n");
1925 return NETDEV_TX_BUSY
;
1928 mac_iocb_ptr
->opcode
= OPCODE_OB_MAC_IOCB
;
1929 mac_iocb_ptr
->tid
= tx_ring_desc
->index
;
1930 /* We use the upper 32-bits to store the tx queue for this IO.
1931 * When we get the completion we can use it to establish the context.
1933 mac_iocb_ptr
->txq_idx
= tx_ring_idx
;
1934 tx_ring_desc
->skb
= skb
;
1936 mac_iocb_ptr
->frame_len
= cpu_to_le16((u16
) skb
->len
);
1938 if (qdev
->vlgrp
&& vlan_tx_tag_present(skb
)) {
1939 QPRINTK(qdev
, TX_QUEUED
, DEBUG
, "Adding a vlan tag %d.\n",
1940 vlan_tx_tag_get(skb
));
1941 mac_iocb_ptr
->flags3
|= OB_MAC_IOCB_V
;
1942 mac_iocb_ptr
->vlan_tci
= cpu_to_le16(vlan_tx_tag_get(skb
));
1944 tso
= ql_tso(skb
, (struct ob_mac_tso_iocb_req
*)mac_iocb_ptr
);
1946 dev_kfree_skb_any(skb
);
1947 return NETDEV_TX_OK
;
1948 } else if (unlikely(!tso
) && (skb
->ip_summed
== CHECKSUM_PARTIAL
)) {
1949 ql_hw_csum_setup(skb
,
1950 (struct ob_mac_tso_iocb_req
*)mac_iocb_ptr
);
1952 QL_DUMP_OB_MAC_IOCB(mac_iocb_ptr
);
1953 tx_ring
->prod_idx
++;
1954 if (tx_ring
->prod_idx
== tx_ring
->wq_len
)
1955 tx_ring
->prod_idx
= 0;
1958 ql_write_db_reg(tx_ring
->prod_idx
, tx_ring
->prod_idx_db_reg
);
1959 ndev
->trans_start
= jiffies
;
1960 QPRINTK(qdev
, TX_QUEUED
, DEBUG
, "tx queued, slot %d, len %d\n",
1961 tx_ring
->prod_idx
, skb
->len
);
1963 atomic_dec(&tx_ring
->tx_count
);
1964 return NETDEV_TX_OK
;
1967 static void ql_free_shadow_space(struct ql_adapter
*qdev
)
1969 if (qdev
->rx_ring_shadow_reg_area
) {
1970 pci_free_consistent(qdev
->pdev
,
1972 qdev
->rx_ring_shadow_reg_area
,
1973 qdev
->rx_ring_shadow_reg_dma
);
1974 qdev
->rx_ring_shadow_reg_area
= NULL
;
1976 if (qdev
->tx_ring_shadow_reg_area
) {
1977 pci_free_consistent(qdev
->pdev
,
1979 qdev
->tx_ring_shadow_reg_area
,
1980 qdev
->tx_ring_shadow_reg_dma
);
1981 qdev
->tx_ring_shadow_reg_area
= NULL
;
1985 static int ql_alloc_shadow_space(struct ql_adapter
*qdev
)
1987 qdev
->rx_ring_shadow_reg_area
=
1988 pci_alloc_consistent(qdev
->pdev
,
1989 PAGE_SIZE
, &qdev
->rx_ring_shadow_reg_dma
);
1990 if (qdev
->rx_ring_shadow_reg_area
== NULL
) {
1991 QPRINTK(qdev
, IFUP
, ERR
,
1992 "Allocation of RX shadow space failed.\n");
1995 qdev
->tx_ring_shadow_reg_area
=
1996 pci_alloc_consistent(qdev
->pdev
, PAGE_SIZE
,
1997 &qdev
->tx_ring_shadow_reg_dma
);
1998 if (qdev
->tx_ring_shadow_reg_area
== NULL
) {
1999 QPRINTK(qdev
, IFUP
, ERR
,
2000 "Allocation of TX shadow space failed.\n");
2001 goto err_wqp_sh_area
;
2006 pci_free_consistent(qdev
->pdev
,
2008 qdev
->rx_ring_shadow_reg_area
,
2009 qdev
->rx_ring_shadow_reg_dma
);
2013 static void ql_init_tx_ring(struct ql_adapter
*qdev
, struct tx_ring
*tx_ring
)
2015 struct tx_ring_desc
*tx_ring_desc
;
2017 struct ob_mac_iocb_req
*mac_iocb_ptr
;
2019 mac_iocb_ptr
= tx_ring
->wq_base
;
2020 tx_ring_desc
= tx_ring
->q
;
2021 for (i
= 0; i
< tx_ring
->wq_len
; i
++) {
2022 tx_ring_desc
->index
= i
;
2023 tx_ring_desc
->skb
= NULL
;
2024 tx_ring_desc
->queue_entry
= mac_iocb_ptr
;
2028 atomic_set(&tx_ring
->tx_count
, tx_ring
->wq_len
);
2029 atomic_set(&tx_ring
->queue_stopped
, 0);
2032 static void ql_free_tx_resources(struct ql_adapter
*qdev
,
2033 struct tx_ring
*tx_ring
)
2035 if (tx_ring
->wq_base
) {
2036 pci_free_consistent(qdev
->pdev
, tx_ring
->wq_size
,
2037 tx_ring
->wq_base
, tx_ring
->wq_base_dma
);
2038 tx_ring
->wq_base
= NULL
;
2044 static int ql_alloc_tx_resources(struct ql_adapter
*qdev
,
2045 struct tx_ring
*tx_ring
)
2048 pci_alloc_consistent(qdev
->pdev
, tx_ring
->wq_size
,
2049 &tx_ring
->wq_base_dma
);
2051 if ((tx_ring
->wq_base
== NULL
)
2052 || tx_ring
->wq_base_dma
& (tx_ring
->wq_size
- 1)) {
2053 QPRINTK(qdev
, IFUP
, ERR
, "tx_ring alloc failed.\n");
2057 kmalloc(tx_ring
->wq_len
* sizeof(struct tx_ring_desc
), GFP_KERNEL
);
2058 if (tx_ring
->q
== NULL
)
2063 pci_free_consistent(qdev
->pdev
, tx_ring
->wq_size
,
2064 tx_ring
->wq_base
, tx_ring
->wq_base_dma
);
2068 static void ql_free_lbq_buffers(struct ql_adapter
*qdev
, struct rx_ring
*rx_ring
)
2071 struct bq_desc
*lbq_desc
;
2073 for (i
= 0; i
< rx_ring
->lbq_len
; i
++) {
2074 lbq_desc
= &rx_ring
->lbq
[i
];
2075 if (lbq_desc
->p
.lbq_page
) {
2076 pci_unmap_page(qdev
->pdev
,
2077 pci_unmap_addr(lbq_desc
, mapaddr
),
2078 pci_unmap_len(lbq_desc
, maplen
),
2079 PCI_DMA_FROMDEVICE
);
2081 put_page(lbq_desc
->p
.lbq_page
);
2082 lbq_desc
->p
.lbq_page
= NULL
;
2088 * Allocate and map a page for each element of the lbq.
2090 static int ql_alloc_lbq_buffers(struct ql_adapter
*qdev
,
2091 struct rx_ring
*rx_ring
)
2094 struct bq_desc
*lbq_desc
;
2096 __le64
*bq
= rx_ring
->lbq_base
;
2098 for (i
= 0; i
< rx_ring
->lbq_len
; i
++) {
2099 lbq_desc
= &rx_ring
->lbq
[i
];
2100 memset(lbq_desc
, 0, sizeof(lbq_desc
));
2101 lbq_desc
->addr
= bq
;
2102 lbq_desc
->index
= i
;
2103 lbq_desc
->p
.lbq_page
= alloc_page(GFP_ATOMIC
);
2104 if (unlikely(!lbq_desc
->p
.lbq_page
)) {
2105 QPRINTK(qdev
, IFUP
, ERR
, "failed alloc_page().\n");
2108 map
= pci_map_page(qdev
->pdev
,
2109 lbq_desc
->p
.lbq_page
,
2110 0, PAGE_SIZE
, PCI_DMA_FROMDEVICE
);
2111 if (pci_dma_mapping_error(qdev
->pdev
, map
)) {
2112 QPRINTK(qdev
, IFUP
, ERR
,
2113 "PCI mapping failed.\n");
2116 pci_unmap_addr_set(lbq_desc
, mapaddr
, map
);
2117 pci_unmap_len_set(lbq_desc
, maplen
, PAGE_SIZE
);
2118 *lbq_desc
->addr
= cpu_to_le64(map
);
2124 ql_free_lbq_buffers(qdev
, rx_ring
);
2128 static void ql_free_sbq_buffers(struct ql_adapter
*qdev
, struct rx_ring
*rx_ring
)
2131 struct bq_desc
*sbq_desc
;
2133 for (i
= 0; i
< rx_ring
->sbq_len
; i
++) {
2134 sbq_desc
= &rx_ring
->sbq
[i
];
2135 if (sbq_desc
== NULL
) {
2136 QPRINTK(qdev
, IFUP
, ERR
, "sbq_desc %d is NULL.\n", i
);
2139 if (sbq_desc
->p
.skb
) {
2140 pci_unmap_single(qdev
->pdev
,
2141 pci_unmap_addr(sbq_desc
, mapaddr
),
2142 pci_unmap_len(sbq_desc
, maplen
),
2143 PCI_DMA_FROMDEVICE
);
2144 dev_kfree_skb(sbq_desc
->p
.skb
);
2145 sbq_desc
->p
.skb
= NULL
;
2150 /* Allocate and map an skb for each element of the sbq. */
2151 static int ql_alloc_sbq_buffers(struct ql_adapter
*qdev
,
2152 struct rx_ring
*rx_ring
)
2155 struct bq_desc
*sbq_desc
;
2156 struct sk_buff
*skb
;
2158 __le64
*bq
= rx_ring
->sbq_base
;
2160 for (i
= 0; i
< rx_ring
->sbq_len
; i
++) {
2161 sbq_desc
= &rx_ring
->sbq
[i
];
2162 memset(sbq_desc
, 0, sizeof(sbq_desc
));
2163 sbq_desc
->index
= i
;
2164 sbq_desc
->addr
= bq
;
2165 skb
= netdev_alloc_skb(qdev
->ndev
, rx_ring
->sbq_buf_size
);
2166 if (unlikely(!skb
)) {
2167 /* Better luck next round */
2168 QPRINTK(qdev
, IFUP
, ERR
,
2169 "small buff alloc failed for %d bytes at index %d.\n",
2170 rx_ring
->sbq_buf_size
, i
);
2173 skb_reserve(skb
, QLGE_SB_PAD
);
2174 sbq_desc
->p
.skb
= skb
;
2176 * Map only half the buffer. Because the
2177 * other half may get some data copied to it
2178 * when the completion arrives.
2180 map
= pci_map_single(qdev
->pdev
,
2182 rx_ring
->sbq_buf_size
/ 2,
2183 PCI_DMA_FROMDEVICE
);
2184 if (pci_dma_mapping_error(qdev
->pdev
, map
)) {
2185 QPRINTK(qdev
, IFUP
, ERR
, "PCI mapping failed.\n");
2188 pci_unmap_addr_set(sbq_desc
, mapaddr
, map
);
2189 pci_unmap_len_set(sbq_desc
, maplen
, rx_ring
->sbq_buf_size
/ 2);
2190 *sbq_desc
->addr
= cpu_to_le64(map
);
2195 ql_free_sbq_buffers(qdev
, rx_ring
);
2199 static void ql_free_rx_resources(struct ql_adapter
*qdev
,
2200 struct rx_ring
*rx_ring
)
2202 if (rx_ring
->sbq_len
)
2203 ql_free_sbq_buffers(qdev
, rx_ring
);
2204 if (rx_ring
->lbq_len
)
2205 ql_free_lbq_buffers(qdev
, rx_ring
);
2207 /* Free the small buffer queue. */
2208 if (rx_ring
->sbq_base
) {
2209 pci_free_consistent(qdev
->pdev
,
2211 rx_ring
->sbq_base
, rx_ring
->sbq_base_dma
);
2212 rx_ring
->sbq_base
= NULL
;
2215 /* Free the small buffer queue control blocks. */
2216 kfree(rx_ring
->sbq
);
2217 rx_ring
->sbq
= NULL
;
2219 /* Free the large buffer queue. */
2220 if (rx_ring
->lbq_base
) {
2221 pci_free_consistent(qdev
->pdev
,
2223 rx_ring
->lbq_base
, rx_ring
->lbq_base_dma
);
2224 rx_ring
->lbq_base
= NULL
;
2227 /* Free the large buffer queue control blocks. */
2228 kfree(rx_ring
->lbq
);
2229 rx_ring
->lbq
= NULL
;
2231 /* Free the rx queue. */
2232 if (rx_ring
->cq_base
) {
2233 pci_free_consistent(qdev
->pdev
,
2235 rx_ring
->cq_base
, rx_ring
->cq_base_dma
);
2236 rx_ring
->cq_base
= NULL
;
2240 /* Allocate queues and buffers for this completions queue based
2241 * on the values in the parameter structure. */
2242 static int ql_alloc_rx_resources(struct ql_adapter
*qdev
,
2243 struct rx_ring
*rx_ring
)
2247 * Allocate the completion queue for this rx_ring.
2250 pci_alloc_consistent(qdev
->pdev
, rx_ring
->cq_size
,
2251 &rx_ring
->cq_base_dma
);
2253 if (rx_ring
->cq_base
== NULL
) {
2254 QPRINTK(qdev
, IFUP
, ERR
, "rx_ring alloc failed.\n");
2258 if (rx_ring
->sbq_len
) {
2260 * Allocate small buffer queue.
2263 pci_alloc_consistent(qdev
->pdev
, rx_ring
->sbq_size
,
2264 &rx_ring
->sbq_base_dma
);
2266 if (rx_ring
->sbq_base
== NULL
) {
2267 QPRINTK(qdev
, IFUP
, ERR
,
2268 "Small buffer queue allocation failed.\n");
2273 * Allocate small buffer queue control blocks.
2276 kmalloc(rx_ring
->sbq_len
* sizeof(struct bq_desc
),
2278 if (rx_ring
->sbq
== NULL
) {
2279 QPRINTK(qdev
, IFUP
, ERR
,
2280 "Small buffer queue control block allocation failed.\n");
2284 if (ql_alloc_sbq_buffers(qdev
, rx_ring
)) {
2285 QPRINTK(qdev
, IFUP
, ERR
,
2286 "Small buffer allocation failed.\n");
2291 if (rx_ring
->lbq_len
) {
2293 * Allocate large buffer queue.
2296 pci_alloc_consistent(qdev
->pdev
, rx_ring
->lbq_size
,
2297 &rx_ring
->lbq_base_dma
);
2299 if (rx_ring
->lbq_base
== NULL
) {
2300 QPRINTK(qdev
, IFUP
, ERR
,
2301 "Large buffer queue allocation failed.\n");
2305 * Allocate large buffer queue control blocks.
2308 kmalloc(rx_ring
->lbq_len
* sizeof(struct bq_desc
),
2310 if (rx_ring
->lbq
== NULL
) {
2311 QPRINTK(qdev
, IFUP
, ERR
,
2312 "Large buffer queue control block allocation failed.\n");
2317 * Allocate the buffers.
2319 if (ql_alloc_lbq_buffers(qdev
, rx_ring
)) {
2320 QPRINTK(qdev
, IFUP
, ERR
,
2321 "Large buffer allocation failed.\n");
2329 ql_free_rx_resources(qdev
, rx_ring
);
2333 static void ql_tx_ring_clean(struct ql_adapter
*qdev
)
2335 struct tx_ring
*tx_ring
;
2336 struct tx_ring_desc
*tx_ring_desc
;
2340 * Loop through all queues and free
2343 for (j
= 0; j
< qdev
->tx_ring_count
; j
++) {
2344 tx_ring
= &qdev
->tx_ring
[j
];
2345 for (i
= 0; i
< tx_ring
->wq_len
; i
++) {
2346 tx_ring_desc
= &tx_ring
->q
[i
];
2347 if (tx_ring_desc
&& tx_ring_desc
->skb
) {
2348 QPRINTK(qdev
, IFDOWN
, ERR
,
2349 "Freeing lost SKB %p, from queue %d, index %d.\n",
2350 tx_ring_desc
->skb
, j
,
2351 tx_ring_desc
->index
);
2352 ql_unmap_send(qdev
, tx_ring_desc
,
2353 tx_ring_desc
->map_cnt
);
2354 dev_kfree_skb(tx_ring_desc
->skb
);
2355 tx_ring_desc
->skb
= NULL
;
2361 static void ql_free_mem_resources(struct ql_adapter
*qdev
)
2365 for (i
= 0; i
< qdev
->tx_ring_count
; i
++)
2366 ql_free_tx_resources(qdev
, &qdev
->tx_ring
[i
]);
2367 for (i
= 0; i
< qdev
->rx_ring_count
; i
++)
2368 ql_free_rx_resources(qdev
, &qdev
->rx_ring
[i
]);
2369 ql_free_shadow_space(qdev
);
2372 static int ql_alloc_mem_resources(struct ql_adapter
*qdev
)
2376 /* Allocate space for our shadow registers and such. */
2377 if (ql_alloc_shadow_space(qdev
))
2380 for (i
= 0; i
< qdev
->rx_ring_count
; i
++) {
2381 if (ql_alloc_rx_resources(qdev
, &qdev
->rx_ring
[i
]) != 0) {
2382 QPRINTK(qdev
, IFUP
, ERR
,
2383 "RX resource allocation failed.\n");
2387 /* Allocate tx queue resources */
2388 for (i
= 0; i
< qdev
->tx_ring_count
; i
++) {
2389 if (ql_alloc_tx_resources(qdev
, &qdev
->tx_ring
[i
]) != 0) {
2390 QPRINTK(qdev
, IFUP
, ERR
,
2391 "TX resource allocation failed.\n");
2398 ql_free_mem_resources(qdev
);
2402 /* Set up the rx ring control block and pass it to the chip.
2403 * The control block is defined as
2404 * "Completion Queue Initialization Control Block", or cqicb.
2406 static int ql_start_rx_ring(struct ql_adapter
*qdev
, struct rx_ring
*rx_ring
)
2408 struct cqicb
*cqicb
= &rx_ring
->cqicb
;
2409 void *shadow_reg
= qdev
->rx_ring_shadow_reg_area
+
2410 (rx_ring
->cq_id
* sizeof(u64
) * 4);
2411 u64 shadow_reg_dma
= qdev
->rx_ring_shadow_reg_dma
+
2412 (rx_ring
->cq_id
* sizeof(u64
) * 4);
2413 void __iomem
*doorbell_area
=
2414 qdev
->doorbell_area
+ (DB_PAGE_SIZE
* (128 + rx_ring
->cq_id
));
2418 /* Set up the shadow registers for this ring. */
2419 rx_ring
->prod_idx_sh_reg
= shadow_reg
;
2420 rx_ring
->prod_idx_sh_reg_dma
= shadow_reg_dma
;
2421 shadow_reg
+= sizeof(u64
);
2422 shadow_reg_dma
+= sizeof(u64
);
2423 rx_ring
->lbq_base_indirect
= shadow_reg
;
2424 rx_ring
->lbq_base_indirect_dma
= shadow_reg_dma
;
2425 shadow_reg
+= sizeof(u64
);
2426 shadow_reg_dma
+= sizeof(u64
);
2427 rx_ring
->sbq_base_indirect
= shadow_reg
;
2428 rx_ring
->sbq_base_indirect_dma
= shadow_reg_dma
;
2430 /* PCI doorbell mem area + 0x00 for consumer index register */
2431 rx_ring
->cnsmr_idx_db_reg
= (u32 __iomem
*) doorbell_area
;
2432 rx_ring
->cnsmr_idx
= 0;
2433 rx_ring
->curr_entry
= rx_ring
->cq_base
;
2435 /* PCI doorbell mem area + 0x04 for valid register */
2436 rx_ring
->valid_db_reg
= doorbell_area
+ 0x04;
2438 /* PCI doorbell mem area + 0x18 for large buffer consumer */
2439 rx_ring
->lbq_prod_idx_db_reg
= (u32 __iomem
*) (doorbell_area
+ 0x18);
2441 /* PCI doorbell mem area + 0x1c */
2442 rx_ring
->sbq_prod_idx_db_reg
= (u32 __iomem
*) (doorbell_area
+ 0x1c);
2444 memset((void *)cqicb
, 0, sizeof(struct cqicb
));
2445 cqicb
->msix_vect
= rx_ring
->irq
;
2447 bq_len
= (rx_ring
->cq_len
== 65536) ? 0 : (u16
) rx_ring
->cq_len
;
2448 cqicb
->len
= cpu_to_le16(bq_len
| LEN_V
| LEN_CPP_CONT
);
2450 cqicb
->addr
= cpu_to_le64(rx_ring
->cq_base_dma
);
2452 cqicb
->prod_idx_addr
= cpu_to_le64(rx_ring
->prod_idx_sh_reg_dma
);
2455 * Set up the control block load flags.
2457 cqicb
->flags
= FLAGS_LC
| /* Load queue base address */
2458 FLAGS_LV
| /* Load MSI-X vector */
2459 FLAGS_LI
; /* Load irq delay values */
2460 if (rx_ring
->lbq_len
) {
2461 cqicb
->flags
|= FLAGS_LL
; /* Load lbq values */
2462 *((u64
*) rx_ring
->lbq_base_indirect
) = rx_ring
->lbq_base_dma
;
2464 cpu_to_le64(rx_ring
->lbq_base_indirect_dma
);
2465 bq_len
= (rx_ring
->lbq_buf_size
== 65536) ? 0 :
2466 (u16
) rx_ring
->lbq_buf_size
;
2467 cqicb
->lbq_buf_size
= cpu_to_le16(bq_len
);
2468 bq_len
= (rx_ring
->lbq_len
== 65536) ? 0 :
2469 (u16
) rx_ring
->lbq_len
;
2470 cqicb
->lbq_len
= cpu_to_le16(bq_len
);
2471 rx_ring
->lbq_prod_idx
= rx_ring
->lbq_len
- 16;
2472 rx_ring
->lbq_curr_idx
= 0;
2473 rx_ring
->lbq_clean_idx
= rx_ring
->lbq_prod_idx
;
2474 rx_ring
->lbq_free_cnt
= 16;
2476 if (rx_ring
->sbq_len
) {
2477 cqicb
->flags
|= FLAGS_LS
; /* Load sbq values */
2478 *((u64
*) rx_ring
->sbq_base_indirect
) = rx_ring
->sbq_base_dma
;
2480 cpu_to_le64(rx_ring
->sbq_base_indirect_dma
);
2481 cqicb
->sbq_buf_size
=
2482 cpu_to_le16(((rx_ring
->sbq_buf_size
/ 2) + 8) & 0xfffffff8);
2483 bq_len
= (rx_ring
->sbq_len
== 65536) ? 0 :
2484 (u16
) rx_ring
->sbq_len
;
2485 cqicb
->sbq_len
= cpu_to_le16(bq_len
);
2486 rx_ring
->sbq_prod_idx
= rx_ring
->sbq_len
- 16;
2487 rx_ring
->sbq_curr_idx
= 0;
2488 rx_ring
->sbq_clean_idx
= rx_ring
->sbq_prod_idx
;
2489 rx_ring
->sbq_free_cnt
= 16;
2491 switch (rx_ring
->type
) {
2493 /* If there's only one interrupt, then we use
2494 * worker threads to process the outbound
2495 * completion handling rx_rings. We do this so
2496 * they can be run on multiple CPUs. There is
2497 * room to play with this more where we would only
2498 * run in a worker if there are more than x number
2499 * of outbound completions on the queue and more
2500 * than one queue active. Some threshold that
2501 * would indicate a benefit in spite of the cost
2502 * of a context switch.
2503 * If there's more than one interrupt, then the
2504 * outbound completions are processed in the ISR.
2506 if (!test_bit(QL_MSIX_ENABLED
, &qdev
->flags
))
2507 INIT_DELAYED_WORK(&rx_ring
->rx_work
, ql_tx_clean
);
2509 /* With all debug warnings on we see a WARN_ON message
2510 * when we free the skb in the interrupt context.
2512 INIT_DELAYED_WORK(&rx_ring
->rx_work
, ql_tx_clean
);
2514 cqicb
->irq_delay
= cpu_to_le16(qdev
->tx_coalesce_usecs
);
2515 cqicb
->pkt_delay
= cpu_to_le16(qdev
->tx_max_coalesced_frames
);
2518 INIT_DELAYED_WORK(&rx_ring
->rx_work
, ql_rx_clean
);
2519 cqicb
->irq_delay
= 0;
2520 cqicb
->pkt_delay
= 0;
2523 /* Inbound completion handling rx_rings run in
2524 * separate NAPI contexts.
2526 netif_napi_add(qdev
->ndev
, &rx_ring
->napi
, ql_napi_poll_msix
,
2528 cqicb
->irq_delay
= cpu_to_le16(qdev
->rx_coalesce_usecs
);
2529 cqicb
->pkt_delay
= cpu_to_le16(qdev
->rx_max_coalesced_frames
);
2532 QPRINTK(qdev
, IFUP
, DEBUG
, "Invalid rx_ring->type = %d.\n",
2535 QPRINTK(qdev
, IFUP
, INFO
, "Initializing rx work queue.\n");
2536 err
= ql_write_cfg(qdev
, cqicb
, sizeof(struct cqicb
),
2537 CFG_LCQ
, rx_ring
->cq_id
);
2539 QPRINTK(qdev
, IFUP
, ERR
, "Failed to load CQICB.\n");
2542 QPRINTK(qdev
, IFUP
, INFO
, "Successfully loaded CQICB.\n");
2544 * Advance the producer index for the buffer queues.
2547 if (rx_ring
->lbq_len
)
2548 ql_write_db_reg(rx_ring
->lbq_prod_idx
,
2549 rx_ring
->lbq_prod_idx_db_reg
);
2550 if (rx_ring
->sbq_len
)
2551 ql_write_db_reg(rx_ring
->sbq_prod_idx
,
2552 rx_ring
->sbq_prod_idx_db_reg
);
2556 static int ql_start_tx_ring(struct ql_adapter
*qdev
, struct tx_ring
*tx_ring
)
2558 struct wqicb
*wqicb
= (struct wqicb
*)tx_ring
;
2559 void __iomem
*doorbell_area
=
2560 qdev
->doorbell_area
+ (DB_PAGE_SIZE
* tx_ring
->wq_id
);
2561 void *shadow_reg
= qdev
->tx_ring_shadow_reg_area
+
2562 (tx_ring
->wq_id
* sizeof(u64
));
2563 u64 shadow_reg_dma
= qdev
->tx_ring_shadow_reg_dma
+
2564 (tx_ring
->wq_id
* sizeof(u64
));
2568 * Assign doorbell registers for this tx_ring.
2570 /* TX PCI doorbell mem area for tx producer index */
2571 tx_ring
->prod_idx_db_reg
= (u32 __iomem
*) doorbell_area
;
2572 tx_ring
->prod_idx
= 0;
2573 /* TX PCI doorbell mem area + 0x04 */
2574 tx_ring
->valid_db_reg
= doorbell_area
+ 0x04;
2577 * Assign shadow registers for this tx_ring.
2579 tx_ring
->cnsmr_idx_sh_reg
= shadow_reg
;
2580 tx_ring
->cnsmr_idx_sh_reg_dma
= shadow_reg_dma
;
2582 wqicb
->len
= cpu_to_le16(tx_ring
->wq_len
| Q_LEN_V
| Q_LEN_CPP_CONT
);
2583 wqicb
->flags
= cpu_to_le16(Q_FLAGS_LC
|
2584 Q_FLAGS_LB
| Q_FLAGS_LI
| Q_FLAGS_LO
);
2585 wqicb
->cq_id_rss
= cpu_to_le16(tx_ring
->cq_id
);
2587 wqicb
->addr
= cpu_to_le64(tx_ring
->wq_base_dma
);
2589 wqicb
->cnsmr_idx_addr
= cpu_to_le64(tx_ring
->cnsmr_idx_sh_reg_dma
);
2591 ql_init_tx_ring(qdev
, tx_ring
);
2593 err
= ql_write_cfg(qdev
, wqicb
, sizeof(wqicb
), CFG_LRQ
,
2594 (u16
) tx_ring
->wq_id
);
2596 QPRINTK(qdev
, IFUP
, ERR
, "Failed to load tx_ring.\n");
2599 QPRINTK(qdev
, IFUP
, INFO
, "Successfully loaded WQICB.\n");
2603 static void ql_disable_msix(struct ql_adapter
*qdev
)
2605 if (test_bit(QL_MSIX_ENABLED
, &qdev
->flags
)) {
2606 pci_disable_msix(qdev
->pdev
);
2607 clear_bit(QL_MSIX_ENABLED
, &qdev
->flags
);
2608 kfree(qdev
->msi_x_entry
);
2609 qdev
->msi_x_entry
= NULL
;
2610 } else if (test_bit(QL_MSI_ENABLED
, &qdev
->flags
)) {
2611 pci_disable_msi(qdev
->pdev
);
2612 clear_bit(QL_MSI_ENABLED
, &qdev
->flags
);
2616 static void ql_enable_msix(struct ql_adapter
*qdev
)
2620 qdev
->intr_count
= 1;
2621 /* Get the MSIX vectors. */
2622 if (irq_type
== MSIX_IRQ
) {
2623 /* Try to alloc space for the msix struct,
2624 * if it fails then go to MSI/legacy.
2626 qdev
->msi_x_entry
= kcalloc(qdev
->rx_ring_count
,
2627 sizeof(struct msix_entry
),
2629 if (!qdev
->msi_x_entry
) {
2634 for (i
= 0; i
< qdev
->rx_ring_count
; i
++)
2635 qdev
->msi_x_entry
[i
].entry
= i
;
2637 if (!pci_enable_msix
2638 (qdev
->pdev
, qdev
->msi_x_entry
, qdev
->rx_ring_count
)) {
2639 set_bit(QL_MSIX_ENABLED
, &qdev
->flags
);
2640 qdev
->intr_count
= qdev
->rx_ring_count
;
2641 QPRINTK(qdev
, IFUP
, INFO
,
2642 "MSI-X Enabled, got %d vectors.\n",
2646 kfree(qdev
->msi_x_entry
);
2647 qdev
->msi_x_entry
= NULL
;
2648 QPRINTK(qdev
, IFUP
, WARNING
,
2649 "MSI-X Enable failed, trying MSI.\n");
2654 if (irq_type
== MSI_IRQ
) {
2655 if (!pci_enable_msi(qdev
->pdev
)) {
2656 set_bit(QL_MSI_ENABLED
, &qdev
->flags
);
2657 QPRINTK(qdev
, IFUP
, INFO
,
2658 "Running with MSI interrupts.\n");
2663 QPRINTK(qdev
, IFUP
, DEBUG
, "Running with legacy interrupts.\n");
2667 * Here we build the intr_context structures based on
2668 * our rx_ring count and intr vector count.
2669 * The intr_context structure is used to hook each vector
2670 * to possibly different handlers.
2672 static void ql_resolve_queues_to_irqs(struct ql_adapter
*qdev
)
2675 struct intr_context
*intr_context
= &qdev
->intr_context
[0];
2677 ql_enable_msix(qdev
);
2679 if (likely(test_bit(QL_MSIX_ENABLED
, &qdev
->flags
))) {
2680 /* Each rx_ring has it's
2681 * own intr_context since we have separate
2682 * vectors for each queue.
2683 * This only true when MSI-X is enabled.
2685 for (i
= 0; i
< qdev
->intr_count
; i
++, intr_context
++) {
2686 qdev
->rx_ring
[i
].irq
= i
;
2687 intr_context
->intr
= i
;
2688 intr_context
->qdev
= qdev
;
2690 * We set up each vectors enable/disable/read bits so
2691 * there's no bit/mask calculations in the critical path.
2693 intr_context
->intr_en_mask
=
2694 INTR_EN_TYPE_MASK
| INTR_EN_INTR_MASK
|
2695 INTR_EN_TYPE_ENABLE
| INTR_EN_IHD_MASK
| INTR_EN_IHD
2697 intr_context
->intr_dis_mask
=
2698 INTR_EN_TYPE_MASK
| INTR_EN_INTR_MASK
|
2699 INTR_EN_TYPE_DISABLE
| INTR_EN_IHD_MASK
|
2701 intr_context
->intr_read_mask
=
2702 INTR_EN_TYPE_MASK
| INTR_EN_INTR_MASK
|
2703 INTR_EN_TYPE_READ
| INTR_EN_IHD_MASK
| INTR_EN_IHD
|
2708 * Default queue handles bcast/mcast plus
2709 * async events. Needs buffers.
2711 intr_context
->handler
= qlge_isr
;
2712 sprintf(intr_context
->name
, "%s-default-queue",
2714 } else if (i
< qdev
->rss_ring_first_cq_id
) {
2716 * Outbound queue is for outbound completions only.
2718 intr_context
->handler
= qlge_msix_tx_isr
;
2719 sprintf(intr_context
->name
, "%s-tx-%d",
2720 qdev
->ndev
->name
, i
);
2723 * Inbound queues handle unicast frames only.
2725 intr_context
->handler
= qlge_msix_rx_isr
;
2726 sprintf(intr_context
->name
, "%s-rx-%d",
2727 qdev
->ndev
->name
, i
);
2732 * All rx_rings use the same intr_context since
2733 * there is only one vector.
2735 intr_context
->intr
= 0;
2736 intr_context
->qdev
= qdev
;
2738 * We set up each vectors enable/disable/read bits so
2739 * there's no bit/mask calculations in the critical path.
2741 intr_context
->intr_en_mask
=
2742 INTR_EN_TYPE_MASK
| INTR_EN_INTR_MASK
| INTR_EN_TYPE_ENABLE
;
2743 intr_context
->intr_dis_mask
=
2744 INTR_EN_TYPE_MASK
| INTR_EN_INTR_MASK
|
2745 INTR_EN_TYPE_DISABLE
;
2746 intr_context
->intr_read_mask
=
2747 INTR_EN_TYPE_MASK
| INTR_EN_INTR_MASK
| INTR_EN_TYPE_READ
;
2749 * Single interrupt means one handler for all rings.
2751 intr_context
->handler
= qlge_isr
;
2752 sprintf(intr_context
->name
, "%s-single_irq", qdev
->ndev
->name
);
2753 for (i
= 0; i
< qdev
->rx_ring_count
; i
++)
2754 qdev
->rx_ring
[i
].irq
= 0;
2758 static void ql_free_irq(struct ql_adapter
*qdev
)
2761 struct intr_context
*intr_context
= &qdev
->intr_context
[0];
2763 for (i
= 0; i
< qdev
->intr_count
; i
++, intr_context
++) {
2764 if (intr_context
->hooked
) {
2765 if (test_bit(QL_MSIX_ENABLED
, &qdev
->flags
)) {
2766 free_irq(qdev
->msi_x_entry
[i
].vector
,
2768 QPRINTK(qdev
, IFDOWN
, ERR
,
2769 "freeing msix interrupt %d.\n", i
);
2771 free_irq(qdev
->pdev
->irq
, &qdev
->rx_ring
[0]);
2772 QPRINTK(qdev
, IFDOWN
, ERR
,
2773 "freeing msi interrupt %d.\n", i
);
2777 ql_disable_msix(qdev
);
2780 static int ql_request_irq(struct ql_adapter
*qdev
)
2784 struct pci_dev
*pdev
= qdev
->pdev
;
2785 struct intr_context
*intr_context
= &qdev
->intr_context
[0];
2787 ql_resolve_queues_to_irqs(qdev
);
2789 for (i
= 0; i
< qdev
->intr_count
; i
++, intr_context
++) {
2790 atomic_set(&intr_context
->irq_cnt
, 0);
2791 if (test_bit(QL_MSIX_ENABLED
, &qdev
->flags
)) {
2792 status
= request_irq(qdev
->msi_x_entry
[i
].vector
,
2793 intr_context
->handler
,
2798 QPRINTK(qdev
, IFUP
, ERR
,
2799 "Failed request for MSIX interrupt %d.\n",
2803 QPRINTK(qdev
, IFUP
, INFO
,
2804 "Hooked intr %d, queue type %s%s%s, with name %s.\n",
2806 qdev
->rx_ring
[i
].type
==
2807 DEFAULT_Q
? "DEFAULT_Q" : "",
2808 qdev
->rx_ring
[i
].type
==
2810 qdev
->rx_ring
[i
].type
==
2811 RX_Q
? "RX_Q" : "", intr_context
->name
);
2814 QPRINTK(qdev
, IFUP
, DEBUG
,
2815 "trying msi or legacy interrupts.\n");
2816 QPRINTK(qdev
, IFUP
, DEBUG
,
2817 "%s: irq = %d.\n", __func__
, pdev
->irq
);
2818 QPRINTK(qdev
, IFUP
, DEBUG
,
2819 "%s: context->name = %s.\n", __func__
,
2820 intr_context
->name
);
2821 QPRINTK(qdev
, IFUP
, DEBUG
,
2822 "%s: dev_id = 0x%p.\n", __func__
,
2825 request_irq(pdev
->irq
, qlge_isr
,
2826 test_bit(QL_MSI_ENABLED
,
2828 flags
) ? 0 : IRQF_SHARED
,
2829 intr_context
->name
, &qdev
->rx_ring
[0]);
2833 QPRINTK(qdev
, IFUP
, ERR
,
2834 "Hooked intr %d, queue type %s%s%s, with name %s.\n",
2836 qdev
->rx_ring
[0].type
==
2837 DEFAULT_Q
? "DEFAULT_Q" : "",
2838 qdev
->rx_ring
[0].type
== TX_Q
? "TX_Q" : "",
2839 qdev
->rx_ring
[0].type
== RX_Q
? "RX_Q" : "",
2840 intr_context
->name
);
2842 intr_context
->hooked
= 1;
2846 QPRINTK(qdev
, IFUP
, ERR
, "Failed to get the interrupts!!!/n");
2851 static int ql_start_rss(struct ql_adapter
*qdev
)
2853 struct ricb
*ricb
= &qdev
->ricb
;
2856 u8
*hash_id
= (u8
*) ricb
->hash_cq_id
;
2858 memset((void *)ricb
, 0, sizeof(ricb
));
2860 ricb
->base_cq
= qdev
->rss_ring_first_cq_id
| RSS_L4K
;
2862 (RSS_L6K
| RSS_LI
| RSS_LB
| RSS_LM
| RSS_RI4
| RSS_RI6
| RSS_RT4
|
2864 ricb
->mask
= cpu_to_le16(qdev
->rss_ring_count
- 1);
2867 * Fill out the Indirection Table.
2869 for (i
= 0; i
< 32; i
++)
2873 * Random values for the IPv6 and IPv4 Hash Keys.
2875 get_random_bytes((void *)&ricb
->ipv6_hash_key
[0], 40);
2876 get_random_bytes((void *)&ricb
->ipv4_hash_key
[0], 16);
2878 QPRINTK(qdev
, IFUP
, INFO
, "Initializing RSS.\n");
2880 status
= ql_write_cfg(qdev
, ricb
, sizeof(ricb
), CFG_LR
, 0);
2882 QPRINTK(qdev
, IFUP
, ERR
, "Failed to load RICB.\n");
2885 QPRINTK(qdev
, IFUP
, INFO
, "Successfully loaded RICB.\n");
2889 /* Initialize the frame-to-queue routing. */
2890 static int ql_route_initialize(struct ql_adapter
*qdev
)
2895 /* Clear all the entries in the routing table. */
2896 for (i
= 0; i
< 16; i
++) {
2897 status
= ql_set_routing_reg(qdev
, i
, 0, 0);
2899 QPRINTK(qdev
, IFUP
, ERR
,
2900 "Failed to init routing register for CAM packets.\n");
2905 status
= ql_set_routing_reg(qdev
, RT_IDX_ALL_ERR_SLOT
, RT_IDX_ERR
, 1);
2907 QPRINTK(qdev
, IFUP
, ERR
,
2908 "Failed to init routing register for error packets.\n");
2911 status
= ql_set_routing_reg(qdev
, RT_IDX_BCAST_SLOT
, RT_IDX_BCAST
, 1);
2913 QPRINTK(qdev
, IFUP
, ERR
,
2914 "Failed to init routing register for broadcast packets.\n");
2917 /* If we have more than one inbound queue, then turn on RSS in the
2920 if (qdev
->rss_ring_count
> 1) {
2921 status
= ql_set_routing_reg(qdev
, RT_IDX_RSS_MATCH_SLOT
,
2922 RT_IDX_RSS_MATCH
, 1);
2924 QPRINTK(qdev
, IFUP
, ERR
,
2925 "Failed to init routing register for MATCH RSS packets.\n");
2930 status
= ql_set_routing_reg(qdev
, RT_IDX_CAM_HIT_SLOT
,
2933 QPRINTK(qdev
, IFUP
, ERR
,
2934 "Failed to init routing register for CAM packets.\n");
2940 static int ql_adapter_initialize(struct ql_adapter
*qdev
)
2947 * Set up the System register to halt on errors.
2949 value
= SYS_EFE
| SYS_FAE
;
2951 ql_write32(qdev
, SYS
, mask
| value
);
2953 /* Set the default queue. */
2954 value
= NIC_RCV_CFG_DFQ
;
2955 mask
= NIC_RCV_CFG_DFQ_MASK
;
2956 ql_write32(qdev
, NIC_RCV_CFG
, (mask
| value
));
2958 /* Set the MPI interrupt to enabled. */
2959 ql_write32(qdev
, INTR_MASK
, (INTR_MASK_PI
<< 16) | INTR_MASK_PI
);
2961 /* Enable the function, set pagesize, enable error checking. */
2962 value
= FSC_FE
| FSC_EPC_INBOUND
| FSC_EPC_OUTBOUND
|
2963 FSC_EC
| FSC_VM_PAGE_4K
| FSC_SH
;
2965 /* Set/clear header splitting. */
2966 mask
= FSC_VM_PAGESIZE_MASK
|
2967 FSC_DBL_MASK
| FSC_DBRST_MASK
| (value
<< 16);
2968 ql_write32(qdev
, FSC
, mask
| value
);
2970 ql_write32(qdev
, SPLT_HDR
, SPLT_HDR_EP
|
2971 min(SMALL_BUFFER_SIZE
, MAX_SPLIT_SIZE
));
2973 /* Start up the rx queues. */
2974 for (i
= 0; i
< qdev
->rx_ring_count
; i
++) {
2975 status
= ql_start_rx_ring(qdev
, &qdev
->rx_ring
[i
]);
2977 QPRINTK(qdev
, IFUP
, ERR
,
2978 "Failed to start rx ring[%d].\n", i
);
2983 /* If there is more than one inbound completion queue
2984 * then download a RICB to configure RSS.
2986 if (qdev
->rss_ring_count
> 1) {
2987 status
= ql_start_rss(qdev
);
2989 QPRINTK(qdev
, IFUP
, ERR
, "Failed to start RSS.\n");
2994 /* Start up the tx queues. */
2995 for (i
= 0; i
< qdev
->tx_ring_count
; i
++) {
2996 status
= ql_start_tx_ring(qdev
, &qdev
->tx_ring
[i
]);
2998 QPRINTK(qdev
, IFUP
, ERR
,
2999 "Failed to start tx ring[%d].\n", i
);
3004 status
= ql_port_initialize(qdev
);
3006 QPRINTK(qdev
, IFUP
, ERR
, "Failed to start port.\n");
3010 status
= ql_set_mac_addr_reg(qdev
, (u8
*) qdev
->ndev
->perm_addr
,
3011 MAC_ADDR_TYPE_CAM_MAC
, qdev
->func
);
3013 QPRINTK(qdev
, IFUP
, ERR
, "Failed to init mac address.\n");
3017 status
= ql_route_initialize(qdev
);
3019 QPRINTK(qdev
, IFUP
, ERR
, "Failed to init routing table.\n");
3023 /* Start NAPI for the RSS queues. */
3024 for (i
= qdev
->rss_ring_first_cq_id
; i
< qdev
->rx_ring_count
; i
++) {
3025 QPRINTK(qdev
, IFUP
, INFO
, "Enabling NAPI for rx_ring[%d].\n",
3027 napi_enable(&qdev
->rx_ring
[i
].napi
);
3033 /* Issue soft reset to chip. */
3034 static int ql_adapter_reset(struct ql_adapter
*qdev
)
3041 #define MAX_RESET_CNT 1
3044 QPRINTK(qdev
, IFDOWN
, DEBUG
, "Issue soft reset to chip.\n");
3045 ql_write32(qdev
, RST_FO
, (RST_FO_FR
<< 16) | RST_FO_FR
);
3046 /* Wait for reset to complete. */
3048 QPRINTK(qdev
, IFDOWN
, DEBUG
, "Wait %d seconds for reset to complete.\n",
3051 value
= ql_read32(qdev
, RST_FO
);
3052 if ((value
& RST_FO_FR
) == 0)
3056 } while ((--max_wait_time
));
3057 if (value
& RST_FO_FR
) {
3058 QPRINTK(qdev
, IFDOWN
, ERR
,
3059 "Stuck in SoftReset: FSC_SR:0x%08x\n", value
);
3060 if (resetCnt
< MAX_RESET_CNT
)
3063 if (max_wait_time
== 0) {
3064 status
= -ETIMEDOUT
;
3065 QPRINTK(qdev
, IFDOWN
, ERR
,
3066 "ETIMEOUT!!! errored out of resetting the chip!\n");
3072 static void ql_display_dev_info(struct net_device
*ndev
)
3074 struct ql_adapter
*qdev
= (struct ql_adapter
*)netdev_priv(ndev
);
3076 QPRINTK(qdev
, PROBE
, INFO
,
3077 "Function #%d, NIC Roll %d, NIC Rev = %d, "
3078 "XG Roll = %d, XG Rev = %d.\n",
3080 qdev
->chip_rev_id
& 0x0000000f,
3081 qdev
->chip_rev_id
>> 4 & 0x0000000f,
3082 qdev
->chip_rev_id
>> 8 & 0x0000000f,
3083 qdev
->chip_rev_id
>> 12 & 0x0000000f);
3084 QPRINTK(qdev
, PROBE
, INFO
, "MAC address %pM\n", ndev
->dev_addr
);
3087 static int ql_adapter_down(struct ql_adapter
*qdev
)
3089 struct net_device
*ndev
= qdev
->ndev
;
3091 struct rx_ring
*rx_ring
;
3093 netif_stop_queue(ndev
);
3094 netif_carrier_off(ndev
);
3096 cancel_delayed_work_sync(&qdev
->asic_reset_work
);
3097 cancel_delayed_work_sync(&qdev
->mpi_reset_work
);
3098 cancel_delayed_work_sync(&qdev
->mpi_work
);
3100 /* The default queue at index 0 is always processed in
3103 cancel_delayed_work_sync(&qdev
->rx_ring
[0].rx_work
);
3105 /* The rest of the rx_rings are processed in
3106 * a workqueue only if it's a single interrupt
3107 * environment (MSI/Legacy).
3109 for (i
= 1; i
< qdev
->rx_ring_count
; i
++) {
3110 rx_ring
= &qdev
->rx_ring
[i
];
3111 /* Only the RSS rings use NAPI on multi irq
3112 * environment. Outbound completion processing
3113 * is done in interrupt context.
3115 if (i
>= qdev
->rss_ring_first_cq_id
) {
3116 napi_disable(&rx_ring
->napi
);
3118 cancel_delayed_work_sync(&rx_ring
->rx_work
);
3122 clear_bit(QL_ADAPTER_UP
, &qdev
->flags
);
3124 ql_disable_interrupts(qdev
);
3126 ql_tx_ring_clean(qdev
);
3128 spin_lock(&qdev
->hw_lock
);
3129 status
= ql_adapter_reset(qdev
);
3131 QPRINTK(qdev
, IFDOWN
, ERR
, "reset(func #%d) FAILED!\n",
3133 spin_unlock(&qdev
->hw_lock
);
3137 static int ql_adapter_up(struct ql_adapter
*qdev
)
3141 spin_lock(&qdev
->hw_lock
);
3142 err
= ql_adapter_initialize(qdev
);
3144 QPRINTK(qdev
, IFUP
, INFO
, "Unable to initialize adapter.\n");
3145 spin_unlock(&qdev
->hw_lock
);
3148 spin_unlock(&qdev
->hw_lock
);
3149 set_bit(QL_ADAPTER_UP
, &qdev
->flags
);
3150 ql_enable_interrupts(qdev
);
3151 ql_enable_all_completion_interrupts(qdev
);
3152 if ((ql_read32(qdev
, STS
) & qdev
->port_init
)) {
3153 netif_carrier_on(qdev
->ndev
);
3154 netif_start_queue(qdev
->ndev
);
3159 ql_adapter_reset(qdev
);
3163 static int ql_cycle_adapter(struct ql_adapter
*qdev
)
3167 status
= ql_adapter_down(qdev
);
3171 status
= ql_adapter_up(qdev
);
3177 QPRINTK(qdev
, IFUP
, ALERT
,
3178 "Driver up/down cycle failed, closing device\n");
3180 dev_close(qdev
->ndev
);
3185 static void ql_release_adapter_resources(struct ql_adapter
*qdev
)
3187 ql_free_mem_resources(qdev
);
3191 static int ql_get_adapter_resources(struct ql_adapter
*qdev
)
3195 if (ql_alloc_mem_resources(qdev
)) {
3196 QPRINTK(qdev
, IFUP
, ERR
, "Unable to allocate memory.\n");
3199 status
= ql_request_irq(qdev
);
3204 ql_free_mem_resources(qdev
);
3208 static int qlge_close(struct net_device
*ndev
)
3210 struct ql_adapter
*qdev
= netdev_priv(ndev
);
3213 * Wait for device to recover from a reset.
3214 * (Rarely happens, but possible.)
3216 while (!test_bit(QL_ADAPTER_UP
, &qdev
->flags
))
3218 ql_adapter_down(qdev
);
3219 ql_release_adapter_resources(qdev
);
3223 static int ql_configure_rings(struct ql_adapter
*qdev
)
3226 struct rx_ring
*rx_ring
;
3227 struct tx_ring
*tx_ring
;
3228 int cpu_cnt
= num_online_cpus();
3231 * For each processor present we allocate one
3232 * rx_ring for outbound completions, and one
3233 * rx_ring for inbound completions. Plus there is
3234 * always the one default queue. For the CPU
3235 * counts we end up with the following rx_rings:
3237 * one default queue +
3238 * (CPU count * outbound completion rx_ring) +
3239 * (CPU count * inbound (RSS) completion rx_ring)
3240 * To keep it simple we limit the total number of
3241 * queues to < 32, so we truncate CPU to 8.
3242 * This limitation can be removed when requested.
3245 if (cpu_cnt
> MAX_CPUS
)
3249 * rx_ring[0] is always the default queue.
3251 /* Allocate outbound completion ring for each CPU. */
3252 qdev
->tx_ring_count
= cpu_cnt
;
3253 /* Allocate inbound completion (RSS) ring for each CPU. */
3254 qdev
->rss_ring_count
= cpu_cnt
;
3255 /* cq_id for the first inbound ring handler. */
3256 qdev
->rss_ring_first_cq_id
= cpu_cnt
+ 1;
3258 * qdev->rx_ring_count:
3259 * Total number of rx_rings. This includes the one
3260 * default queue, a number of outbound completion
3261 * handler rx_rings, and the number of inbound
3262 * completion handler rx_rings.
3264 qdev
->rx_ring_count
= qdev
->tx_ring_count
+ qdev
->rss_ring_count
+ 1;
3266 for (i
= 0; i
< qdev
->tx_ring_count
; i
++) {
3267 tx_ring
= &qdev
->tx_ring
[i
];
3268 memset((void *)tx_ring
, 0, sizeof(tx_ring
));
3269 tx_ring
->qdev
= qdev
;
3271 tx_ring
->wq_len
= qdev
->tx_ring_size
;
3273 tx_ring
->wq_len
* sizeof(struct ob_mac_iocb_req
);
3276 * The completion queue ID for the tx rings start
3277 * immediately after the default Q ID, which is zero.
3279 tx_ring
->cq_id
= i
+ 1;
3282 for (i
= 0; i
< qdev
->rx_ring_count
; i
++) {
3283 rx_ring
= &qdev
->rx_ring
[i
];
3284 memset((void *)rx_ring
, 0, sizeof(rx_ring
));
3285 rx_ring
->qdev
= qdev
;
3287 rx_ring
->cpu
= i
% cpu_cnt
; /* CPU to run handler on. */
3288 if (i
== 0) { /* Default queue at index 0. */
3290 * Default queue handles bcast/mcast plus
3291 * async events. Needs buffers.
3293 rx_ring
->cq_len
= qdev
->rx_ring_size
;
3295 rx_ring
->cq_len
* sizeof(struct ql_net_rsp_iocb
);
3296 rx_ring
->lbq_len
= NUM_LARGE_BUFFERS
;
3298 rx_ring
->lbq_len
* sizeof(__le64
);
3299 rx_ring
->lbq_buf_size
= LARGE_BUFFER_SIZE
;
3300 rx_ring
->sbq_len
= NUM_SMALL_BUFFERS
;
3302 rx_ring
->sbq_len
* sizeof(__le64
);
3303 rx_ring
->sbq_buf_size
= SMALL_BUFFER_SIZE
* 2;
3304 rx_ring
->type
= DEFAULT_Q
;
3305 } else if (i
< qdev
->rss_ring_first_cq_id
) {
3307 * Outbound queue handles outbound completions only.
3309 /* outbound cq is same size as tx_ring it services. */
3310 rx_ring
->cq_len
= qdev
->tx_ring_size
;
3312 rx_ring
->cq_len
* sizeof(struct ql_net_rsp_iocb
);
3313 rx_ring
->lbq_len
= 0;
3314 rx_ring
->lbq_size
= 0;
3315 rx_ring
->lbq_buf_size
= 0;
3316 rx_ring
->sbq_len
= 0;
3317 rx_ring
->sbq_size
= 0;
3318 rx_ring
->sbq_buf_size
= 0;
3319 rx_ring
->type
= TX_Q
;
3320 } else { /* Inbound completions (RSS) queues */
3322 * Inbound queues handle unicast frames only.
3324 rx_ring
->cq_len
= qdev
->rx_ring_size
;
3326 rx_ring
->cq_len
* sizeof(struct ql_net_rsp_iocb
);
3327 rx_ring
->lbq_len
= NUM_LARGE_BUFFERS
;
3329 rx_ring
->lbq_len
* sizeof(__le64
);
3330 rx_ring
->lbq_buf_size
= LARGE_BUFFER_SIZE
;
3331 rx_ring
->sbq_len
= NUM_SMALL_BUFFERS
;
3333 rx_ring
->sbq_len
* sizeof(__le64
);
3334 rx_ring
->sbq_buf_size
= SMALL_BUFFER_SIZE
* 2;
3335 rx_ring
->type
= RX_Q
;
3341 static int qlge_open(struct net_device
*ndev
)
3344 struct ql_adapter
*qdev
= netdev_priv(ndev
);
3346 err
= ql_configure_rings(qdev
);
3350 err
= ql_get_adapter_resources(qdev
);
3354 err
= ql_adapter_up(qdev
);
3361 ql_release_adapter_resources(qdev
);
3365 static int qlge_change_mtu(struct net_device
*ndev
, int new_mtu
)
3367 struct ql_adapter
*qdev
= netdev_priv(ndev
);
3369 if (ndev
->mtu
== 1500 && new_mtu
== 9000) {
3370 QPRINTK(qdev
, IFUP
, ERR
, "Changing to jumbo MTU.\n");
3371 } else if (ndev
->mtu
== 9000 && new_mtu
== 1500) {
3372 QPRINTK(qdev
, IFUP
, ERR
, "Changing to normal MTU.\n");
3373 } else if ((ndev
->mtu
== 1500 && new_mtu
== 1500) ||
3374 (ndev
->mtu
== 9000 && new_mtu
== 9000)) {
3378 ndev
->mtu
= new_mtu
;
3382 static struct net_device_stats
*qlge_get_stats(struct net_device
3385 struct ql_adapter
*qdev
= netdev_priv(ndev
);
3386 return &qdev
->stats
;
3389 static void qlge_set_multicast_list(struct net_device
*ndev
)
3391 struct ql_adapter
*qdev
= (struct ql_adapter
*)netdev_priv(ndev
);
3392 struct dev_mc_list
*mc_ptr
;
3395 spin_lock(&qdev
->hw_lock
);
3397 * Set or clear promiscuous mode if a
3398 * transition is taking place.
3400 if (ndev
->flags
& IFF_PROMISC
) {
3401 if (!test_bit(QL_PROMISCUOUS
, &qdev
->flags
)) {
3402 if (ql_set_routing_reg
3403 (qdev
, RT_IDX_PROMISCUOUS_SLOT
, RT_IDX_VALID
, 1)) {
3404 QPRINTK(qdev
, HW
, ERR
,
3405 "Failed to set promiscous mode.\n");
3407 set_bit(QL_PROMISCUOUS
, &qdev
->flags
);
3411 if (test_bit(QL_PROMISCUOUS
, &qdev
->flags
)) {
3412 if (ql_set_routing_reg
3413 (qdev
, RT_IDX_PROMISCUOUS_SLOT
, RT_IDX_VALID
, 0)) {
3414 QPRINTK(qdev
, HW
, ERR
,
3415 "Failed to clear promiscous mode.\n");
3417 clear_bit(QL_PROMISCUOUS
, &qdev
->flags
);
3423 * Set or clear all multicast mode if a
3424 * transition is taking place.
3426 if ((ndev
->flags
& IFF_ALLMULTI
) ||
3427 (ndev
->mc_count
> MAX_MULTICAST_ENTRIES
)) {
3428 if (!test_bit(QL_ALLMULTI
, &qdev
->flags
)) {
3429 if (ql_set_routing_reg
3430 (qdev
, RT_IDX_ALLMULTI_SLOT
, RT_IDX_MCAST
, 1)) {
3431 QPRINTK(qdev
, HW
, ERR
,
3432 "Failed to set all-multi mode.\n");
3434 set_bit(QL_ALLMULTI
, &qdev
->flags
);
3438 if (test_bit(QL_ALLMULTI
, &qdev
->flags
)) {
3439 if (ql_set_routing_reg
3440 (qdev
, RT_IDX_ALLMULTI_SLOT
, RT_IDX_MCAST
, 0)) {
3441 QPRINTK(qdev
, HW
, ERR
,
3442 "Failed to clear all-multi mode.\n");
3444 clear_bit(QL_ALLMULTI
, &qdev
->flags
);
3449 if (ndev
->mc_count
) {
3450 for (i
= 0, mc_ptr
= ndev
->mc_list
; mc_ptr
;
3451 i
++, mc_ptr
= mc_ptr
->next
)
3452 if (ql_set_mac_addr_reg(qdev
, (u8
*) mc_ptr
->dmi_addr
,
3453 MAC_ADDR_TYPE_MULTI_MAC
, i
)) {
3454 QPRINTK(qdev
, HW
, ERR
,
3455 "Failed to loadmulticast address.\n");
3458 if (ql_set_routing_reg
3459 (qdev
, RT_IDX_MCAST_MATCH_SLOT
, RT_IDX_MCAST_MATCH
, 1)) {
3460 QPRINTK(qdev
, HW
, ERR
,
3461 "Failed to set multicast match mode.\n");
3463 set_bit(QL_ALLMULTI
, &qdev
->flags
);
3467 spin_unlock(&qdev
->hw_lock
);
3470 static int qlge_set_mac_address(struct net_device
*ndev
, void *p
)
3472 struct ql_adapter
*qdev
= (struct ql_adapter
*)netdev_priv(ndev
);
3473 struct sockaddr
*addr
= p
;
3476 if (netif_running(ndev
))
3479 if (!is_valid_ether_addr(addr
->sa_data
))
3480 return -EADDRNOTAVAIL
;
3481 memcpy(ndev
->dev_addr
, addr
->sa_data
, ndev
->addr_len
);
3483 spin_lock(&qdev
->hw_lock
);
3484 if (ql_set_mac_addr_reg(qdev
, (u8
*) ndev
->dev_addr
,
3485 MAC_ADDR_TYPE_CAM_MAC
, qdev
->func
)) {/* Unicast */
3486 QPRINTK(qdev
, HW
, ERR
, "Failed to load MAC address.\n");
3489 spin_unlock(&qdev
->hw_lock
);
3494 static void qlge_tx_timeout(struct net_device
*ndev
)
3496 struct ql_adapter
*qdev
= (struct ql_adapter
*)netdev_priv(ndev
);
3497 queue_delayed_work(qdev
->workqueue
, &qdev
->asic_reset_work
, 0);
3500 static void ql_asic_reset_work(struct work_struct
*work
)
3502 struct ql_adapter
*qdev
=
3503 container_of(work
, struct ql_adapter
, asic_reset_work
.work
);
3504 ql_cycle_adapter(qdev
);
3507 static void ql_get_board_info(struct ql_adapter
*qdev
)
3510 (ql_read32(qdev
, STS
) & STS_FUNC_ID_MASK
) >> STS_FUNC_ID_SHIFT
;
3512 qdev
->xg_sem_mask
= SEM_XGMAC1_MASK
;
3513 qdev
->port_link_up
= STS_PL1
;
3514 qdev
->port_init
= STS_PI1
;
3515 qdev
->mailbox_in
= PROC_ADDR_MPI_RISC
| PROC_ADDR_FUNC2_MBI
;
3516 qdev
->mailbox_out
= PROC_ADDR_MPI_RISC
| PROC_ADDR_FUNC2_MBO
;
3518 qdev
->xg_sem_mask
= SEM_XGMAC0_MASK
;
3519 qdev
->port_link_up
= STS_PL0
;
3520 qdev
->port_init
= STS_PI0
;
3521 qdev
->mailbox_in
= PROC_ADDR_MPI_RISC
| PROC_ADDR_FUNC0_MBI
;
3522 qdev
->mailbox_out
= PROC_ADDR_MPI_RISC
| PROC_ADDR_FUNC0_MBO
;
3524 qdev
->chip_rev_id
= ql_read32(qdev
, REV_ID
);
3527 static void ql_release_all(struct pci_dev
*pdev
)
3529 struct net_device
*ndev
= pci_get_drvdata(pdev
);
3530 struct ql_adapter
*qdev
= netdev_priv(ndev
);
3532 if (qdev
->workqueue
) {
3533 destroy_workqueue(qdev
->workqueue
);
3534 qdev
->workqueue
= NULL
;
3536 if (qdev
->q_workqueue
) {
3537 destroy_workqueue(qdev
->q_workqueue
);
3538 qdev
->q_workqueue
= NULL
;
3541 iounmap(qdev
->reg_base
);
3542 if (qdev
->doorbell_area
)
3543 iounmap(qdev
->doorbell_area
);
3544 pci_release_regions(pdev
);
3545 pci_set_drvdata(pdev
, NULL
);
3548 static int __devinit
ql_init_device(struct pci_dev
*pdev
,
3549 struct net_device
*ndev
, int cards_found
)
3551 struct ql_adapter
*qdev
= netdev_priv(ndev
);
3555 memset((void *)qdev
, 0, sizeof(qdev
));
3556 err
= pci_enable_device(pdev
);
3558 dev_err(&pdev
->dev
, "PCI device enable failed.\n");
3562 pos
= pci_find_capability(pdev
, PCI_CAP_ID_EXP
);
3564 dev_err(&pdev
->dev
, PFX
"Cannot find PCI Express capability, "
3568 pci_read_config_word(pdev
, pos
+ PCI_EXP_DEVCTL
, &val16
);
3569 val16
&= ~PCI_EXP_DEVCTL_NOSNOOP_EN
;
3570 val16
|= (PCI_EXP_DEVCTL_CERE
|
3571 PCI_EXP_DEVCTL_NFERE
|
3572 PCI_EXP_DEVCTL_FERE
| PCI_EXP_DEVCTL_URRE
);
3573 pci_write_config_word(pdev
, pos
+ PCI_EXP_DEVCTL
, val16
);
3576 err
= pci_request_regions(pdev
, DRV_NAME
);
3578 dev_err(&pdev
->dev
, "PCI region request failed.\n");
3582 pci_set_master(pdev
);
3583 if (!pci_set_dma_mask(pdev
, DMA_64BIT_MASK
)) {
3584 set_bit(QL_DMA64
, &qdev
->flags
);
3585 err
= pci_set_consistent_dma_mask(pdev
, DMA_64BIT_MASK
);
3587 err
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
3589 err
= pci_set_consistent_dma_mask(pdev
, DMA_32BIT_MASK
);
3593 dev_err(&pdev
->dev
, "No usable DMA configuration.\n");
3597 pci_set_drvdata(pdev
, ndev
);
3599 ioremap_nocache(pci_resource_start(pdev
, 1),
3600 pci_resource_len(pdev
, 1));
3601 if (!qdev
->reg_base
) {
3602 dev_err(&pdev
->dev
, "Register mapping failed.\n");
3607 qdev
->doorbell_area_size
= pci_resource_len(pdev
, 3);
3608 qdev
->doorbell_area
=
3609 ioremap_nocache(pci_resource_start(pdev
, 3),
3610 pci_resource_len(pdev
, 3));
3611 if (!qdev
->doorbell_area
) {
3612 dev_err(&pdev
->dev
, "Doorbell register mapping failed.\n");
3617 ql_get_board_info(qdev
);
3620 qdev
->msg_enable
= netif_msg_init(debug
, default_msg
);
3621 spin_lock_init(&qdev
->hw_lock
);
3622 spin_lock_init(&qdev
->stats_lock
);
3624 /* make sure the EEPROM is good */
3625 err
= ql_get_flash_params(qdev
);
3627 dev_err(&pdev
->dev
, "Invalid FLASH.\n");
3631 if (!is_valid_ether_addr(qdev
->flash
.mac_addr
))
3634 memcpy(ndev
->dev_addr
, qdev
->flash
.mac_addr
, ndev
->addr_len
);
3635 memcpy(ndev
->perm_addr
, ndev
->dev_addr
, ndev
->addr_len
);
3637 /* Set up the default ring sizes. */
3638 qdev
->tx_ring_size
= NUM_TX_RING_ENTRIES
;
3639 qdev
->rx_ring_size
= NUM_RX_RING_ENTRIES
;
3641 /* Set up the coalescing parameters. */
3642 qdev
->rx_coalesce_usecs
= DFLT_COALESCE_WAIT
;
3643 qdev
->tx_coalesce_usecs
= DFLT_COALESCE_WAIT
;
3644 qdev
->rx_max_coalesced_frames
= DFLT_INTER_FRAME_WAIT
;
3645 qdev
->tx_max_coalesced_frames
= DFLT_INTER_FRAME_WAIT
;
3648 * Set up the operating parameters.
3652 qdev
->q_workqueue
= create_workqueue(ndev
->name
);
3653 qdev
->workqueue
= create_singlethread_workqueue(ndev
->name
);
3654 INIT_DELAYED_WORK(&qdev
->asic_reset_work
, ql_asic_reset_work
);
3655 INIT_DELAYED_WORK(&qdev
->mpi_reset_work
, ql_mpi_reset_work
);
3656 INIT_DELAYED_WORK(&qdev
->mpi_work
, ql_mpi_work
);
3659 dev_info(&pdev
->dev
, "%s\n", DRV_STRING
);
3660 dev_info(&pdev
->dev
, "Driver name: %s, Version: %s.\n",
3661 DRV_NAME
, DRV_VERSION
);
3665 ql_release_all(pdev
);
3666 pci_disable_device(pdev
);
3671 static const struct net_device_ops qlge_netdev_ops
= {
3672 .ndo_open
= qlge_open
,
3673 .ndo_stop
= qlge_close
,
3674 .ndo_start_xmit
= qlge_send
,
3675 .ndo_change_mtu
= qlge_change_mtu
,
3676 .ndo_get_stats
= qlge_get_stats
,
3677 .ndo_set_multicast_list
= qlge_set_multicast_list
,
3678 .ndo_set_mac_address
= qlge_set_mac_address
,
3679 .ndo_validate_addr
= eth_validate_addr
,
3680 .ndo_tx_timeout
= qlge_tx_timeout
,
3681 .ndo_vlan_rx_register
= ql_vlan_rx_register
,
3682 .ndo_vlan_rx_add_vid
= ql_vlan_rx_add_vid
,
3683 .ndo_vlan_rx_kill_vid
= ql_vlan_rx_kill_vid
,
3686 static int __devinit
qlge_probe(struct pci_dev
*pdev
,
3687 const struct pci_device_id
*pci_entry
)
3689 struct net_device
*ndev
= NULL
;
3690 struct ql_adapter
*qdev
= NULL
;
3691 static int cards_found
= 0;
3694 ndev
= alloc_etherdev(sizeof(struct ql_adapter
));
3698 err
= ql_init_device(pdev
, ndev
, cards_found
);
3704 qdev
= netdev_priv(ndev
);
3705 SET_NETDEV_DEV(ndev
, &pdev
->dev
);
3712 | NETIF_F_HW_VLAN_TX
3713 | NETIF_F_HW_VLAN_RX
| NETIF_F_HW_VLAN_FILTER
);
3715 if (test_bit(QL_DMA64
, &qdev
->flags
))
3716 ndev
->features
|= NETIF_F_HIGHDMA
;
3719 * Set up net_device structure.
3721 ndev
->tx_queue_len
= qdev
->tx_ring_size
;
3722 ndev
->irq
= pdev
->irq
;
3724 ndev
->netdev_ops
= &qlge_netdev_ops
;
3725 SET_ETHTOOL_OPS(ndev
, &qlge_ethtool_ops
);
3726 ndev
->watchdog_timeo
= 10 * HZ
;
3728 err
= register_netdev(ndev
);
3730 dev_err(&pdev
->dev
, "net device registration failed.\n");
3731 ql_release_all(pdev
);
3732 pci_disable_device(pdev
);
3735 netif_carrier_off(ndev
);
3736 netif_stop_queue(ndev
);
3737 ql_display_dev_info(ndev
);
3742 static void __devexit
qlge_remove(struct pci_dev
*pdev
)
3744 struct net_device
*ndev
= pci_get_drvdata(pdev
);
3745 unregister_netdev(ndev
);
3746 ql_release_all(pdev
);
3747 pci_disable_device(pdev
);
3752 * This callback is called by the PCI subsystem whenever
3753 * a PCI bus error is detected.
3755 static pci_ers_result_t
qlge_io_error_detected(struct pci_dev
*pdev
,
3756 enum pci_channel_state state
)
3758 struct net_device
*ndev
= pci_get_drvdata(pdev
);
3759 struct ql_adapter
*qdev
= netdev_priv(ndev
);
3761 if (netif_running(ndev
))
3762 ql_adapter_down(qdev
);
3764 pci_disable_device(pdev
);
3766 /* Request a slot reset. */
3767 return PCI_ERS_RESULT_NEED_RESET
;
3771 * This callback is called after the PCI buss has been reset.
3772 * Basically, this tries to restart the card from scratch.
3773 * This is a shortened version of the device probe/discovery code,
3774 * it resembles the first-half of the () routine.
3776 static pci_ers_result_t
qlge_io_slot_reset(struct pci_dev
*pdev
)
3778 struct net_device
*ndev
= pci_get_drvdata(pdev
);
3779 struct ql_adapter
*qdev
= netdev_priv(ndev
);
3781 if (pci_enable_device(pdev
)) {
3782 QPRINTK(qdev
, IFUP
, ERR
,
3783 "Cannot re-enable PCI device after reset.\n");
3784 return PCI_ERS_RESULT_DISCONNECT
;
3787 pci_set_master(pdev
);
3789 netif_carrier_off(ndev
);
3790 netif_stop_queue(ndev
);
3791 ql_adapter_reset(qdev
);
3793 /* Make sure the EEPROM is good */
3794 memcpy(ndev
->perm_addr
, ndev
->dev_addr
, ndev
->addr_len
);
3796 if (!is_valid_ether_addr(ndev
->perm_addr
)) {
3797 QPRINTK(qdev
, IFUP
, ERR
, "After reset, invalid MAC address.\n");
3798 return PCI_ERS_RESULT_DISCONNECT
;
3801 return PCI_ERS_RESULT_RECOVERED
;
3804 static void qlge_io_resume(struct pci_dev
*pdev
)
3806 struct net_device
*ndev
= pci_get_drvdata(pdev
);
3807 struct ql_adapter
*qdev
= netdev_priv(ndev
);
3809 pci_set_master(pdev
);
3811 if (netif_running(ndev
)) {
3812 if (ql_adapter_up(qdev
)) {
3813 QPRINTK(qdev
, IFUP
, ERR
,
3814 "Device initialization failed after reset.\n");
3819 netif_device_attach(ndev
);
3822 static struct pci_error_handlers qlge_err_handler
= {
3823 .error_detected
= qlge_io_error_detected
,
3824 .slot_reset
= qlge_io_slot_reset
,
3825 .resume
= qlge_io_resume
,
3828 static int qlge_suspend(struct pci_dev
*pdev
, pm_message_t state
)
3830 struct net_device
*ndev
= pci_get_drvdata(pdev
);
3831 struct ql_adapter
*qdev
= netdev_priv(ndev
);
3834 netif_device_detach(ndev
);
3836 if (netif_running(ndev
)) {
3837 err
= ql_adapter_down(qdev
);
3842 err
= pci_save_state(pdev
);
3846 pci_disable_device(pdev
);
3848 pci_set_power_state(pdev
, pci_choose_state(pdev
, state
));
3854 static int qlge_resume(struct pci_dev
*pdev
)
3856 struct net_device
*ndev
= pci_get_drvdata(pdev
);
3857 struct ql_adapter
*qdev
= netdev_priv(ndev
);
3860 pci_set_power_state(pdev
, PCI_D0
);
3861 pci_restore_state(pdev
);
3862 err
= pci_enable_device(pdev
);
3864 QPRINTK(qdev
, IFUP
, ERR
, "Cannot enable PCI device from suspend\n");
3867 pci_set_master(pdev
);
3869 pci_enable_wake(pdev
, PCI_D3hot
, 0);
3870 pci_enable_wake(pdev
, PCI_D3cold
, 0);
3872 if (netif_running(ndev
)) {
3873 err
= ql_adapter_up(qdev
);
3878 netif_device_attach(ndev
);
3882 #endif /* CONFIG_PM */
3884 static void qlge_shutdown(struct pci_dev
*pdev
)
3886 qlge_suspend(pdev
, PMSG_SUSPEND
);
3889 static struct pci_driver qlge_driver
= {
3891 .id_table
= qlge_pci_tbl
,
3892 .probe
= qlge_probe
,
3893 .remove
= __devexit_p(qlge_remove
),
3895 .suspend
= qlge_suspend
,
3896 .resume
= qlge_resume
,
3898 .shutdown
= qlge_shutdown
,
3899 .err_handler
= &qlge_err_handler
3902 static int __init
qlge_init_module(void)
3904 return pci_register_driver(&qlge_driver
);
3907 static void __exit
qlge_exit(void)
3909 pci_unregister_driver(&qlge_driver
);
3912 module_init(qlge_init_module
);
3913 module_exit(qlge_exit
);