include/asm-s390/smp.h

   1 /*
   2  *  include/asm-s390/smp.h
   3  *
   4  *  S390 version
   5  *    Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
   6  *    Author(s): Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com),
   7  *               Martin Schwidefsky (schwidefsky@de.ibm.com)
   8  *               Heiko Carstens (heiko.carstens@de.ibm.com)
   9  */
  10 #ifndef __ASM_SMP_H
  11 #define __ASM_SMP_H
  12
  13 #include <linux/threads.h>
  14 #include <linux/cpumask.h>
  15 #include <linux/bitops.h>
  16
  17 #if defined(__KERNEL__) && defined(CONFIG_SMP) && !defined(__ASSEMBLY__)
  18
  19 #include <asm/lowcore.h>
  20 #include <asm/sigp.h>
  21 #include <asm/ptrace.h>
  22
  23 /*
  24   s390 specific smp.c headers
  25  */
  26 typedef struct
  27 {
  28         int        intresting;
  29         sigp_ccode ccode;
  30         __u32      status;
  31         __u16      cpu;
  32 } sigp_info;
  33
  34 extern void machine_restart_smp(char *);
  35 extern void machine_halt_smp(void);
  36 extern void machine_power_off_smp(void);
  37
  38 extern void smp_setup_cpu_possible_map(void);
  39
  40 #define NO_PROC_ID              0xFF            /* No processor magic marker */
  41
  42 /*
  43  *      This magic constant controls our willingness to transfer
  44  *      a process across CPUs. Such a transfer incurs misses on the L1
  45  *      cache, and on a P6 or P5 with multiple L2 caches L2 hits. My
  46  *      gut feeling is this will vary by board in value. For a board
  47  *      with separate L2 cache it probably depends also on the RSS, and
  48  *      for a board with shared L2 cache it ought to decay fast as other
  49  *      processes are run.
  50  */
  51
  52 #define PROC_CHANGE_PENALTY     20              /* Schedule penalty */
  53
  54 #define raw_smp_processor_id()  (S390_lowcore.cpu_data.cpu_nr)
  55
  56 static inline __u16 hard_smp_processor_id(void)
  57 {
  58         __u16 cpu_address;
  59
  60         asm volatile("stap %0" : "=m" (cpu_address));
  61         return cpu_address;
  62 }
  63
  64 /*
  65  * returns 1 if cpu is in stopped/check stopped state or not operational
  66  * returns 0 otherwise
  67  */
  68 static inline int
  69 smp_cpu_not_running(int cpu)
  70 {
  71         __u32 status;
  72
  73         switch (signal_processor_ps(&status, 0, cpu, sigp_sense)) {
  74         case sigp_order_code_accepted:
  75         case sigp_status_stored:
  76                 /* Check for stopped and check stop state */
  77                 if (status & 0x50)
  78                         return 1;
  79                 break;
  80         case sigp_not_operational:
  81                 return 1;
  82         default:
  83                 break;
  84         }
  85         return 0;
  86 }
  87
  88 #define cpu_logical_map(cpu) (cpu)
  89
  90 extern int __cpu_disable (void);
  91 extern void __cpu_die (unsigned int cpu);
  92 extern void cpu_die (void) __attribute__ ((noreturn));
  93 extern int __cpu_up (unsigned int cpu);
  94
  95 #endif
  96
  97 #ifndef CONFIG_SMP
  98 static inline void smp_send_stop(void)
  99 {
 100         /* Disable all interrupts/machine checks */
 101         __load_psw_mask(psw_kernel_bits & ~PSW_MASK_MCHECK);
 102 }
 103
 104 #define hard_smp_processor_id()         0
 105 #define smp_cpu_not_running(cpu)        1
 106 #define smp_setup_cpu_possible_map()    do { } while (0)
 107 #endif
 108
 109 extern union save_area *zfcpdump_save_areas[NR_CPUS + 1];
 110 #endif