2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/slab.h>
35 #include <linux/swap.h>
36 #include <linux/pci.h>
37 #include <linux/intel-gtt.h>
39 static uint32_t i915_gem_get_gtt_alignment(struct drm_gem_object
*obj
);
41 static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object
*obj
,
43 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object
*obj
);
44 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object
*obj
);
45 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object
*obj
,
47 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object
*obj
,
50 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object
*obj
);
51 static int i915_gem_object_wait_rendering(struct drm_gem_object
*obj
,
53 static int i915_gem_object_bind_to_gtt(struct drm_gem_object
*obj
,
55 static void i915_gem_clear_fence_reg(struct drm_gem_object
*obj
);
56 static int i915_gem_phys_pwrite(struct drm_device
*dev
, struct drm_gem_object
*obj
,
57 struct drm_i915_gem_pwrite
*args
,
58 struct drm_file
*file_priv
);
59 static void i915_gem_free_object_tail(struct drm_gem_object
*obj
);
62 i915_gem_object_get_pages(struct drm_gem_object
*obj
,
66 i915_gem_object_put_pages(struct drm_gem_object
*obj
);
68 static LIST_HEAD(shrink_list
);
69 static DEFINE_SPINLOCK(shrink_list_lock
);
71 /* some bookkeeping */
72 static void i915_gem_info_add_obj(struct drm_i915_private
*dev_priv
,
75 dev_priv
->mm
.object_count
++;
76 dev_priv
->mm
.object_memory
+= size
;
79 static void i915_gem_info_remove_obj(struct drm_i915_private
*dev_priv
,
82 dev_priv
->mm
.object_count
--;
83 dev_priv
->mm
.object_memory
-= size
;
86 static void i915_gem_info_add_gtt(struct drm_i915_private
*dev_priv
,
89 dev_priv
->mm
.gtt_count
++;
90 dev_priv
->mm
.gtt_memory
+= size
;
93 static void i915_gem_info_remove_gtt(struct drm_i915_private
*dev_priv
,
96 dev_priv
->mm
.gtt_count
--;
97 dev_priv
->mm
.gtt_memory
-= size
;
100 static void i915_gem_info_add_pin(struct drm_i915_private
*dev_priv
,
103 dev_priv
->mm
.pin_count
++;
104 dev_priv
->mm
.pin_memory
+= size
;
107 static void i915_gem_info_remove_pin(struct drm_i915_private
*dev_priv
,
110 dev_priv
->mm
.pin_count
--;
111 dev_priv
->mm
.pin_memory
-= size
;
115 i915_gem_check_is_wedged(struct drm_device
*dev
)
117 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
118 struct completion
*x
= &dev_priv
->error_completion
;
122 if (!atomic_read(&dev_priv
->mm
.wedged
))
125 ret
= wait_for_completion_interruptible(x
);
129 /* Success, we reset the GPU! */
130 if (!atomic_read(&dev_priv
->mm
.wedged
))
133 /* GPU is hung, bump the completion count to account for
134 * the token we just consumed so that we never hit zero and
135 * end up waiting upon a subsequent completion event that
138 spin_lock_irqsave(&x
->wait
.lock
, flags
);
140 spin_unlock_irqrestore(&x
->wait
.lock
, flags
);
144 static int i915_mutex_lock_interruptible(struct drm_device
*dev
)
146 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
149 ret
= i915_gem_check_is_wedged(dev
);
153 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
157 if (atomic_read(&dev_priv
->mm
.wedged
)) {
158 mutex_unlock(&dev
->struct_mutex
);
162 WARN_ON(i915_verify_lists(dev
));
167 i915_gem_object_is_inactive(struct drm_i915_gem_object
*obj_priv
)
169 return obj_priv
->gtt_space
&&
171 obj_priv
->pin_count
== 0;
174 int i915_gem_do_init(struct drm_device
*dev
,
178 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
181 (start
& (PAGE_SIZE
- 1)) != 0 ||
182 (end
& (PAGE_SIZE
- 1)) != 0) {
186 drm_mm_init(&dev_priv
->mm
.gtt_space
, start
,
189 dev_priv
->mm
.gtt_total
= end
- start
;
195 i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
196 struct drm_file
*file_priv
)
198 struct drm_i915_gem_init
*args
= data
;
201 mutex_lock(&dev
->struct_mutex
);
202 ret
= i915_gem_do_init(dev
, args
->gtt_start
, args
->gtt_end
);
203 mutex_unlock(&dev
->struct_mutex
);
209 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
210 struct drm_file
*file_priv
)
212 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
213 struct drm_i915_gem_get_aperture
*args
= data
;
215 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
218 mutex_lock(&dev
->struct_mutex
);
219 args
->aper_size
= dev_priv
->mm
.gtt_total
;
220 args
->aper_available_size
= args
->aper_size
- dev_priv
->mm
.pin_memory
;
221 mutex_unlock(&dev
->struct_mutex
);
228 * Creates a new mm object and returns a handle to it.
231 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
232 struct drm_file
*file_priv
)
234 struct drm_i915_gem_create
*args
= data
;
235 struct drm_gem_object
*obj
;
239 args
->size
= roundup(args
->size
, PAGE_SIZE
);
241 /* Allocate the new object */
242 obj
= i915_gem_alloc_object(dev
, args
->size
);
246 ret
= drm_gem_handle_create(file_priv
, obj
, &handle
);
247 /* drop reference from allocate - handle holds it now */
248 drm_gem_object_unreference_unlocked(obj
);
253 args
->handle
= handle
;
258 fast_shmem_read(struct page
**pages
,
259 loff_t page_base
, int page_offset
,
266 vaddr
= kmap_atomic(pages
[page_base
>> PAGE_SHIFT
], KM_USER0
);
269 unwritten
= __copy_to_user_inatomic(data
, vaddr
+ page_offset
, length
);
270 kunmap_atomic(vaddr
, KM_USER0
);
278 static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object
*obj
)
280 drm_i915_private_t
*dev_priv
= obj
->dev
->dev_private
;
281 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
283 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
284 obj_priv
->tiling_mode
!= I915_TILING_NONE
;
288 slow_shmem_copy(struct page
*dst_page
,
290 struct page
*src_page
,
294 char *dst_vaddr
, *src_vaddr
;
296 dst_vaddr
= kmap(dst_page
);
297 src_vaddr
= kmap(src_page
);
299 memcpy(dst_vaddr
+ dst_offset
, src_vaddr
+ src_offset
, length
);
306 slow_shmem_bit17_copy(struct page
*gpu_page
,
308 struct page
*cpu_page
,
313 char *gpu_vaddr
, *cpu_vaddr
;
315 /* Use the unswizzled path if this page isn't affected. */
316 if ((page_to_phys(gpu_page
) & (1 << 17)) == 0) {
318 return slow_shmem_copy(cpu_page
, cpu_offset
,
319 gpu_page
, gpu_offset
, length
);
321 return slow_shmem_copy(gpu_page
, gpu_offset
,
322 cpu_page
, cpu_offset
, length
);
325 gpu_vaddr
= kmap(gpu_page
);
326 cpu_vaddr
= kmap(cpu_page
);
328 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
329 * XORing with the other bits (A9 for Y, A9 and A10 for X)
332 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
333 int this_length
= min(cacheline_end
- gpu_offset
, length
);
334 int swizzled_gpu_offset
= gpu_offset
^ 64;
337 memcpy(cpu_vaddr
+ cpu_offset
,
338 gpu_vaddr
+ swizzled_gpu_offset
,
341 memcpy(gpu_vaddr
+ swizzled_gpu_offset
,
342 cpu_vaddr
+ cpu_offset
,
345 cpu_offset
+= this_length
;
346 gpu_offset
+= this_length
;
347 length
-= this_length
;
355 * This is the fast shmem pread path, which attempts to copy_from_user directly
356 * from the backing pages of the object to the user's address space. On a
357 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
360 i915_gem_shmem_pread_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
361 struct drm_i915_gem_pread
*args
,
362 struct drm_file
*file_priv
)
364 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
366 loff_t offset
, page_base
;
367 char __user
*user_data
;
368 int page_offset
, page_length
;
371 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
374 ret
= i915_mutex_lock_interruptible(dev
);
378 ret
= i915_gem_object_get_pages(obj
, 0);
382 ret
= i915_gem_object_set_cpu_read_domain_range(obj
, args
->offset
,
387 obj_priv
= to_intel_bo(obj
);
388 offset
= args
->offset
;
391 /* Operation in this page
393 * page_base = page offset within aperture
394 * page_offset = offset within page
395 * page_length = bytes to copy for this page
397 page_base
= (offset
& ~(PAGE_SIZE
-1));
398 page_offset
= offset
& (PAGE_SIZE
-1);
399 page_length
= remain
;
400 if ((page_offset
+ remain
) > PAGE_SIZE
)
401 page_length
= PAGE_SIZE
- page_offset
;
403 ret
= fast_shmem_read(obj_priv
->pages
,
404 page_base
, page_offset
,
405 user_data
, page_length
);
409 remain
-= page_length
;
410 user_data
+= page_length
;
411 offset
+= page_length
;
415 i915_gem_object_put_pages(obj
);
417 mutex_unlock(&dev
->struct_mutex
);
423 i915_gem_object_get_pages_or_evict(struct drm_gem_object
*obj
)
427 ret
= i915_gem_object_get_pages(obj
, __GFP_NORETRY
| __GFP_NOWARN
);
429 /* If we've insufficient memory to map in the pages, attempt
430 * to make some space by throwing out some old buffers.
432 if (ret
== -ENOMEM
) {
433 struct drm_device
*dev
= obj
->dev
;
435 ret
= i915_gem_evict_something(dev
, obj
->size
,
436 i915_gem_get_gtt_alignment(obj
));
440 ret
= i915_gem_object_get_pages(obj
, 0);
447 * This is the fallback shmem pread path, which allocates temporary storage
448 * in kernel space to copy_to_user into outside of the struct_mutex, so we
449 * can copy out of the object's backing pages while holding the struct mutex
450 * and not take page faults.
453 i915_gem_shmem_pread_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
454 struct drm_i915_gem_pread
*args
,
455 struct drm_file
*file_priv
)
457 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
458 struct mm_struct
*mm
= current
->mm
;
459 struct page
**user_pages
;
461 loff_t offset
, pinned_pages
, i
;
462 loff_t first_data_page
, last_data_page
, num_pages
;
463 int shmem_page_index
, shmem_page_offset
;
464 int data_page_index
, data_page_offset
;
467 uint64_t data_ptr
= args
->data_ptr
;
468 int do_bit17_swizzling
;
472 /* Pin the user pages containing the data. We can't fault while
473 * holding the struct mutex, yet we want to hold it while
474 * dereferencing the user data.
476 first_data_page
= data_ptr
/ PAGE_SIZE
;
477 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
478 num_pages
= last_data_page
- first_data_page
+ 1;
480 user_pages
= drm_calloc_large(num_pages
, sizeof(struct page
*));
481 if (user_pages
== NULL
)
484 down_read(&mm
->mmap_sem
);
485 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
486 num_pages
, 1, 0, user_pages
, NULL
);
487 up_read(&mm
->mmap_sem
);
488 if (pinned_pages
< num_pages
) {
490 goto fail_put_user_pages
;
493 do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
495 ret
= i915_mutex_lock_interruptible(dev
);
497 goto fail_put_user_pages
;
499 ret
= i915_gem_object_get_pages_or_evict(obj
);
503 ret
= i915_gem_object_set_cpu_read_domain_range(obj
, args
->offset
,
508 obj_priv
= to_intel_bo(obj
);
509 offset
= args
->offset
;
512 /* Operation in this page
514 * shmem_page_index = page number within shmem file
515 * shmem_page_offset = offset within page in shmem file
516 * data_page_index = page number in get_user_pages return
517 * data_page_offset = offset with data_page_index page.
518 * page_length = bytes to copy for this page
520 shmem_page_index
= offset
/ PAGE_SIZE
;
521 shmem_page_offset
= offset
& ~PAGE_MASK
;
522 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
523 data_page_offset
= data_ptr
& ~PAGE_MASK
;
525 page_length
= remain
;
526 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
527 page_length
= PAGE_SIZE
- shmem_page_offset
;
528 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
529 page_length
= PAGE_SIZE
- data_page_offset
;
531 if (do_bit17_swizzling
) {
532 slow_shmem_bit17_copy(obj_priv
->pages
[shmem_page_index
],
534 user_pages
[data_page_index
],
539 slow_shmem_copy(user_pages
[data_page_index
],
541 obj_priv
->pages
[shmem_page_index
],
546 remain
-= page_length
;
547 data_ptr
+= page_length
;
548 offset
+= page_length
;
552 i915_gem_object_put_pages(obj
);
554 mutex_unlock(&dev
->struct_mutex
);
556 for (i
= 0; i
< pinned_pages
; i
++) {
557 SetPageDirty(user_pages
[i
]);
558 page_cache_release(user_pages
[i
]);
560 drm_free_large(user_pages
);
566 * Reads data from the object referenced by handle.
568 * On error, the contents of *data are undefined.
571 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
572 struct drm_file
*file_priv
)
574 struct drm_i915_gem_pread
*args
= data
;
575 struct drm_gem_object
*obj
;
576 struct drm_i915_gem_object
*obj_priv
;
579 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
582 obj_priv
= to_intel_bo(obj
);
584 /* Bounds check source. */
585 if (args
->offset
> obj
->size
|| args
->size
> obj
->size
- args
->offset
) {
593 if (!access_ok(VERIFY_WRITE
,
594 (char __user
*)(uintptr_t)args
->data_ptr
,
600 if (i915_gem_object_needs_bit17_swizzle(obj
)) {
601 ret
= i915_gem_shmem_pread_slow(dev
, obj
, args
, file_priv
);
603 ret
= i915_gem_shmem_pread_fast(dev
, obj
, args
, file_priv
);
605 ret
= i915_gem_shmem_pread_slow(dev
, obj
, args
,
610 drm_gem_object_unreference_unlocked(obj
);
614 /* This is the fast write path which cannot handle
615 * page faults in the source data
619 fast_user_write(struct io_mapping
*mapping
,
620 loff_t page_base
, int page_offset
,
621 char __user
*user_data
,
625 unsigned long unwritten
;
627 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
, KM_USER0
);
628 unwritten
= __copy_from_user_inatomic_nocache(vaddr_atomic
+ page_offset
,
630 io_mapping_unmap_atomic(vaddr_atomic
, KM_USER0
);
636 /* Here's the write path which can sleep for
641 slow_kernel_write(struct io_mapping
*mapping
,
642 loff_t gtt_base
, int gtt_offset
,
643 struct page
*user_page
, int user_offset
,
646 char __iomem
*dst_vaddr
;
649 dst_vaddr
= io_mapping_map_wc(mapping
, gtt_base
);
650 src_vaddr
= kmap(user_page
);
652 memcpy_toio(dst_vaddr
+ gtt_offset
,
653 src_vaddr
+ user_offset
,
657 io_mapping_unmap(dst_vaddr
);
661 fast_shmem_write(struct page
**pages
,
662 loff_t page_base
, int page_offset
,
667 unsigned long unwritten
;
669 vaddr
= kmap_atomic(pages
[page_base
>> PAGE_SHIFT
], KM_USER0
);
672 unwritten
= __copy_from_user_inatomic(vaddr
+ page_offset
, data
, length
);
673 kunmap_atomic(vaddr
, KM_USER0
);
681 * This is the fast pwrite path, where we copy the data directly from the
682 * user into the GTT, uncached.
685 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
686 struct drm_i915_gem_pwrite
*args
,
687 struct drm_file
*file_priv
)
689 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
690 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
692 loff_t offset
, page_base
;
693 char __user
*user_data
;
694 int page_offset
, page_length
;
697 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
700 ret
= i915_mutex_lock_interruptible(dev
);
704 ret
= i915_gem_object_pin(obj
, 0);
706 mutex_unlock(&dev
->struct_mutex
);
709 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
713 obj_priv
= to_intel_bo(obj
);
714 offset
= obj_priv
->gtt_offset
+ args
->offset
;
717 /* Operation in this page
719 * page_base = page offset within aperture
720 * page_offset = offset within page
721 * page_length = bytes to copy for this page
723 page_base
= (offset
& ~(PAGE_SIZE
-1));
724 page_offset
= offset
& (PAGE_SIZE
-1);
725 page_length
= remain
;
726 if ((page_offset
+ remain
) > PAGE_SIZE
)
727 page_length
= PAGE_SIZE
- page_offset
;
729 ret
= fast_user_write (dev_priv
->mm
.gtt_mapping
, page_base
,
730 page_offset
, user_data
, page_length
);
732 /* If we get a fault while copying data, then (presumably) our
733 * source page isn't available. Return the error and we'll
734 * retry in the slow path.
739 remain
-= page_length
;
740 user_data
+= page_length
;
741 offset
+= page_length
;
745 i915_gem_object_unpin(obj
);
746 mutex_unlock(&dev
->struct_mutex
);
752 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
753 * the memory and maps it using kmap_atomic for copying.
755 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
756 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
759 i915_gem_gtt_pwrite_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
760 struct drm_i915_gem_pwrite
*args
,
761 struct drm_file
*file_priv
)
763 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
764 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
766 loff_t gtt_page_base
, offset
;
767 loff_t first_data_page
, last_data_page
, num_pages
;
768 loff_t pinned_pages
, i
;
769 struct page
**user_pages
;
770 struct mm_struct
*mm
= current
->mm
;
771 int gtt_page_offset
, data_page_offset
, data_page_index
, page_length
;
773 uint64_t data_ptr
= args
->data_ptr
;
777 /* Pin the user pages containing the data. We can't fault while
778 * holding the struct mutex, and all of the pwrite implementations
779 * want to hold it while dereferencing the user data.
781 first_data_page
= data_ptr
/ PAGE_SIZE
;
782 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
783 num_pages
= last_data_page
- first_data_page
+ 1;
785 user_pages
= drm_calloc_large(num_pages
, sizeof(struct page
*));
786 if (user_pages
== NULL
)
789 down_read(&mm
->mmap_sem
);
790 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
791 num_pages
, 0, 0, user_pages
, NULL
);
792 up_read(&mm
->mmap_sem
);
793 if (pinned_pages
< num_pages
) {
795 goto out_unpin_pages
;
798 ret
= i915_mutex_lock_interruptible(dev
);
800 goto out_unpin_pages
;
802 ret
= i915_gem_object_pin(obj
, 0);
806 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
808 goto out_unpin_object
;
810 obj_priv
= to_intel_bo(obj
);
811 offset
= obj_priv
->gtt_offset
+ args
->offset
;
814 /* Operation in this page
816 * gtt_page_base = page offset within aperture
817 * gtt_page_offset = offset within page in aperture
818 * data_page_index = page number in get_user_pages return
819 * data_page_offset = offset with data_page_index page.
820 * page_length = bytes to copy for this page
822 gtt_page_base
= offset
& PAGE_MASK
;
823 gtt_page_offset
= offset
& ~PAGE_MASK
;
824 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
825 data_page_offset
= data_ptr
& ~PAGE_MASK
;
827 page_length
= remain
;
828 if ((gtt_page_offset
+ page_length
) > PAGE_SIZE
)
829 page_length
= PAGE_SIZE
- gtt_page_offset
;
830 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
831 page_length
= PAGE_SIZE
- data_page_offset
;
833 slow_kernel_write(dev_priv
->mm
.gtt_mapping
,
834 gtt_page_base
, gtt_page_offset
,
835 user_pages
[data_page_index
],
839 remain
-= page_length
;
840 offset
+= page_length
;
841 data_ptr
+= page_length
;
845 i915_gem_object_unpin(obj
);
847 mutex_unlock(&dev
->struct_mutex
);
849 for (i
= 0; i
< pinned_pages
; i
++)
850 page_cache_release(user_pages
[i
]);
851 drm_free_large(user_pages
);
857 * This is the fast shmem pwrite path, which attempts to directly
858 * copy_from_user into the kmapped pages backing the object.
861 i915_gem_shmem_pwrite_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
862 struct drm_i915_gem_pwrite
*args
,
863 struct drm_file
*file_priv
)
865 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
867 loff_t offset
, page_base
;
868 char __user
*user_data
;
869 int page_offset
, page_length
;
872 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
875 ret
= i915_mutex_lock_interruptible(dev
);
879 ret
= i915_gem_object_get_pages(obj
, 0);
883 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
887 obj_priv
= to_intel_bo(obj
);
888 offset
= args
->offset
;
892 /* Operation in this page
894 * page_base = page offset within aperture
895 * page_offset = offset within page
896 * page_length = bytes to copy for this page
898 page_base
= (offset
& ~(PAGE_SIZE
-1));
899 page_offset
= offset
& (PAGE_SIZE
-1);
900 page_length
= remain
;
901 if ((page_offset
+ remain
) > PAGE_SIZE
)
902 page_length
= PAGE_SIZE
- page_offset
;
904 ret
= fast_shmem_write(obj_priv
->pages
,
905 page_base
, page_offset
,
906 user_data
, page_length
);
910 remain
-= page_length
;
911 user_data
+= page_length
;
912 offset
+= page_length
;
916 i915_gem_object_put_pages(obj
);
918 mutex_unlock(&dev
->struct_mutex
);
924 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
925 * the memory and maps it using kmap_atomic for copying.
927 * This avoids taking mmap_sem for faulting on the user's address while the
928 * struct_mutex is held.
931 i915_gem_shmem_pwrite_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
932 struct drm_i915_gem_pwrite
*args
,
933 struct drm_file
*file_priv
)
935 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
936 struct mm_struct
*mm
= current
->mm
;
937 struct page
**user_pages
;
939 loff_t offset
, pinned_pages
, i
;
940 loff_t first_data_page
, last_data_page
, num_pages
;
941 int shmem_page_index
, shmem_page_offset
;
942 int data_page_index
, data_page_offset
;
945 uint64_t data_ptr
= args
->data_ptr
;
946 int do_bit17_swizzling
;
950 /* Pin the user pages containing the data. We can't fault while
951 * holding the struct mutex, and all of the pwrite implementations
952 * want to hold it while dereferencing the user data.
954 first_data_page
= data_ptr
/ PAGE_SIZE
;
955 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
956 num_pages
= last_data_page
- first_data_page
+ 1;
958 user_pages
= drm_calloc_large(num_pages
, sizeof(struct page
*));
959 if (user_pages
== NULL
)
962 down_read(&mm
->mmap_sem
);
963 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
964 num_pages
, 0, 0, user_pages
, NULL
);
965 up_read(&mm
->mmap_sem
);
966 if (pinned_pages
< num_pages
) {
968 goto fail_put_user_pages
;
971 do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
973 ret
= i915_mutex_lock_interruptible(dev
);
975 goto fail_put_user_pages
;
977 ret
= i915_gem_object_get_pages_or_evict(obj
);
981 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
985 obj_priv
= to_intel_bo(obj
);
986 offset
= args
->offset
;
990 /* Operation in this page
992 * shmem_page_index = page number within shmem file
993 * shmem_page_offset = offset within page in shmem file
994 * data_page_index = page number in get_user_pages return
995 * data_page_offset = offset with data_page_index page.
996 * page_length = bytes to copy for this page
998 shmem_page_index
= offset
/ PAGE_SIZE
;
999 shmem_page_offset
= offset
& ~PAGE_MASK
;
1000 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
1001 data_page_offset
= data_ptr
& ~PAGE_MASK
;
1003 page_length
= remain
;
1004 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
1005 page_length
= PAGE_SIZE
- shmem_page_offset
;
1006 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
1007 page_length
= PAGE_SIZE
- data_page_offset
;
1009 if (do_bit17_swizzling
) {
1010 slow_shmem_bit17_copy(obj_priv
->pages
[shmem_page_index
],
1012 user_pages
[data_page_index
],
1017 slow_shmem_copy(obj_priv
->pages
[shmem_page_index
],
1019 user_pages
[data_page_index
],
1024 remain
-= page_length
;
1025 data_ptr
+= page_length
;
1026 offset
+= page_length
;
1030 i915_gem_object_put_pages(obj
);
1032 mutex_unlock(&dev
->struct_mutex
);
1033 fail_put_user_pages
:
1034 for (i
= 0; i
< pinned_pages
; i
++)
1035 page_cache_release(user_pages
[i
]);
1036 drm_free_large(user_pages
);
1042 * Writes data to the object referenced by handle.
1044 * On error, the contents of the buffer that were to be modified are undefined.
1047 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
1048 struct drm_file
*file_priv
)
1050 struct drm_i915_gem_pwrite
*args
= data
;
1051 struct drm_gem_object
*obj
;
1052 struct drm_i915_gem_object
*obj_priv
;
1055 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1058 obj_priv
= to_intel_bo(obj
);
1060 /* Bounds check destination. */
1061 if (args
->offset
> obj
->size
|| args
->size
> obj
->size
- args
->offset
) {
1066 if (args
->size
== 0)
1069 if (!access_ok(VERIFY_READ
,
1070 (char __user
*)(uintptr_t)args
->data_ptr
,
1076 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1077 * it would end up going through the fenced access, and we'll get
1078 * different detiling behavior between reading and writing.
1079 * pread/pwrite currently are reading and writing from the CPU
1080 * perspective, requiring manual detiling by the client.
1082 if (obj_priv
->phys_obj
)
1083 ret
= i915_gem_phys_pwrite(dev
, obj
, args
, file_priv
);
1084 else if (obj_priv
->tiling_mode
== I915_TILING_NONE
&&
1085 obj_priv
->gtt_space
&&
1086 obj
->write_domain
!= I915_GEM_DOMAIN_CPU
) {
1087 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file_priv
);
1088 if (ret
== -EFAULT
) {
1089 ret
= i915_gem_gtt_pwrite_slow(dev
, obj
, args
,
1092 } else if (i915_gem_object_needs_bit17_swizzle(obj
)) {
1093 ret
= i915_gem_shmem_pwrite_slow(dev
, obj
, args
, file_priv
);
1095 ret
= i915_gem_shmem_pwrite_fast(dev
, obj
, args
, file_priv
);
1096 if (ret
== -EFAULT
) {
1097 ret
= i915_gem_shmem_pwrite_slow(dev
, obj
, args
,
1104 DRM_INFO("pwrite failed %d\n", ret
);
1108 drm_gem_object_unreference_unlocked(obj
);
1113 * Called when user space prepares to use an object with the CPU, either
1114 * through the mmap ioctl's mapping or a GTT mapping.
1117 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1118 struct drm_file
*file_priv
)
1120 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1121 struct drm_i915_gem_set_domain
*args
= data
;
1122 struct drm_gem_object
*obj
;
1123 struct drm_i915_gem_object
*obj_priv
;
1124 uint32_t read_domains
= args
->read_domains
;
1125 uint32_t write_domain
= args
->write_domain
;
1128 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1131 /* Only handle setting domains to types used by the CPU. */
1132 if (write_domain
& I915_GEM_GPU_DOMAINS
)
1135 if (read_domains
& I915_GEM_GPU_DOMAINS
)
1138 /* Having something in the write domain implies it's in the read
1139 * domain, and only that read domain. Enforce that in the request.
1141 if (write_domain
!= 0 && read_domains
!= write_domain
)
1144 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1147 obj_priv
= to_intel_bo(obj
);
1149 ret
= i915_mutex_lock_interruptible(dev
);
1151 drm_gem_object_unreference_unlocked(obj
);
1155 intel_mark_busy(dev
, obj
);
1157 if (read_domains
& I915_GEM_DOMAIN_GTT
) {
1158 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1160 /* Update the LRU on the fence for the CPU access that's
1163 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
1164 struct drm_i915_fence_reg
*reg
=
1165 &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
1166 list_move_tail(®
->lru_list
,
1167 &dev_priv
->mm
.fence_list
);
1170 /* Silently promote "you're not bound, there was nothing to do"
1171 * to success, since the client was just asking us to
1172 * make sure everything was done.
1177 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1180 /* Maintain LRU order of "inactive" objects */
1181 if (ret
== 0 && i915_gem_object_is_inactive(obj_priv
))
1182 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
1184 drm_gem_object_unreference(obj
);
1185 mutex_unlock(&dev
->struct_mutex
);
1190 * Called when user space has done writes to this buffer
1193 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1194 struct drm_file
*file_priv
)
1196 struct drm_i915_gem_sw_finish
*args
= data
;
1197 struct drm_gem_object
*obj
;
1200 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1203 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1207 ret
= i915_mutex_lock_interruptible(dev
);
1209 drm_gem_object_unreference_unlocked(obj
);
1213 /* Pinned buffers may be scanout, so flush the cache */
1214 if (to_intel_bo(obj
)->pin_count
)
1215 i915_gem_object_flush_cpu_write_domain(obj
);
1217 drm_gem_object_unreference(obj
);
1218 mutex_unlock(&dev
->struct_mutex
);
1223 * Maps the contents of an object, returning the address it is mapped
1226 * While the mapping holds a reference on the contents of the object, it doesn't
1227 * imply a ref on the object itself.
1230 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1231 struct drm_file
*file_priv
)
1233 struct drm_i915_gem_mmap
*args
= data
;
1234 struct drm_gem_object
*obj
;
1238 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1241 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1245 offset
= args
->offset
;
1247 down_write(¤t
->mm
->mmap_sem
);
1248 addr
= do_mmap(obj
->filp
, 0, args
->size
,
1249 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1251 up_write(¤t
->mm
->mmap_sem
);
1252 drm_gem_object_unreference_unlocked(obj
);
1253 if (IS_ERR((void *)addr
))
1256 args
->addr_ptr
= (uint64_t) addr
;
1262 * i915_gem_fault - fault a page into the GTT
1263 * vma: VMA in question
1266 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1267 * from userspace. The fault handler takes care of binding the object to
1268 * the GTT (if needed), allocating and programming a fence register (again,
1269 * only if needed based on whether the old reg is still valid or the object
1270 * is tiled) and inserting a new PTE into the faulting process.
1272 * Note that the faulting process may involve evicting existing objects
1273 * from the GTT and/or fence registers to make room. So performance may
1274 * suffer if the GTT working set is large or there are few fence registers
1277 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1279 struct drm_gem_object
*obj
= vma
->vm_private_data
;
1280 struct drm_device
*dev
= obj
->dev
;
1281 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1282 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1283 pgoff_t page_offset
;
1286 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1288 /* We don't use vmf->pgoff since that has the fake offset */
1289 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1292 /* Now bind it into the GTT if needed */
1293 mutex_lock(&dev
->struct_mutex
);
1294 if (!obj_priv
->gtt_space
) {
1295 ret
= i915_gem_object_bind_to_gtt(obj
, 0);
1299 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1304 /* Need a new fence register? */
1305 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
) {
1306 ret
= i915_gem_object_get_fence_reg(obj
, true);
1311 if (i915_gem_object_is_inactive(obj_priv
))
1312 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
1314 pfn
= ((dev
->agp
->base
+ obj_priv
->gtt_offset
) >> PAGE_SHIFT
) +
1317 /* Finally, remap it using the new GTT offset */
1318 ret
= vm_insert_pfn(vma
, (unsigned long)vmf
->virtual_address
, pfn
);
1320 mutex_unlock(&dev
->struct_mutex
);
1325 return VM_FAULT_NOPAGE
;
1328 return VM_FAULT_OOM
;
1330 return VM_FAULT_SIGBUS
;
1335 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1336 * @obj: obj in question
1338 * GEM memory mapping works by handing back to userspace a fake mmap offset
1339 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1340 * up the object based on the offset and sets up the various memory mapping
1343 * This routine allocates and attaches a fake offset for @obj.
1346 i915_gem_create_mmap_offset(struct drm_gem_object
*obj
)
1348 struct drm_device
*dev
= obj
->dev
;
1349 struct drm_gem_mm
*mm
= dev
->mm_private
;
1350 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1351 struct drm_map_list
*list
;
1352 struct drm_local_map
*map
;
1355 /* Set the object up for mmap'ing */
1356 list
= &obj
->map_list
;
1357 list
->map
= kzalloc(sizeof(struct drm_map_list
), GFP_KERNEL
);
1362 map
->type
= _DRM_GEM
;
1363 map
->size
= obj
->size
;
1366 /* Get a DRM GEM mmap offset allocated... */
1367 list
->file_offset_node
= drm_mm_search_free(&mm
->offset_manager
,
1368 obj
->size
/ PAGE_SIZE
, 0, 0);
1369 if (!list
->file_offset_node
) {
1370 DRM_ERROR("failed to allocate offset for bo %d\n", obj
->name
);
1375 list
->file_offset_node
= drm_mm_get_block(list
->file_offset_node
,
1376 obj
->size
/ PAGE_SIZE
, 0);
1377 if (!list
->file_offset_node
) {
1382 list
->hash
.key
= list
->file_offset_node
->start
;
1383 ret
= drm_ht_insert_item(&mm
->offset_hash
, &list
->hash
);
1385 DRM_ERROR("failed to add to map hash\n");
1389 /* By now we should be all set, any drm_mmap request on the offset
1390 * below will get to our mmap & fault handler */
1391 obj_priv
->mmap_offset
= ((uint64_t) list
->hash
.key
) << PAGE_SHIFT
;
1396 drm_mm_put_block(list
->file_offset_node
);
1404 * i915_gem_release_mmap - remove physical page mappings
1405 * @obj: obj in question
1407 * Preserve the reservation of the mmapping with the DRM core code, but
1408 * relinquish ownership of the pages back to the system.
1410 * It is vital that we remove the page mapping if we have mapped a tiled
1411 * object through the GTT and then lose the fence register due to
1412 * resource pressure. Similarly if the object has been moved out of the
1413 * aperture, than pages mapped into userspace must be revoked. Removing the
1414 * mapping will then trigger a page fault on the next user access, allowing
1415 * fixup by i915_gem_fault().
1418 i915_gem_release_mmap(struct drm_gem_object
*obj
)
1420 struct drm_device
*dev
= obj
->dev
;
1421 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1423 if (dev
->dev_mapping
)
1424 unmap_mapping_range(dev
->dev_mapping
,
1425 obj_priv
->mmap_offset
, obj
->size
, 1);
1429 i915_gem_free_mmap_offset(struct drm_gem_object
*obj
)
1431 struct drm_device
*dev
= obj
->dev
;
1432 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1433 struct drm_gem_mm
*mm
= dev
->mm_private
;
1434 struct drm_map_list
*list
;
1436 list
= &obj
->map_list
;
1437 drm_ht_remove_item(&mm
->offset_hash
, &list
->hash
);
1439 if (list
->file_offset_node
) {
1440 drm_mm_put_block(list
->file_offset_node
);
1441 list
->file_offset_node
= NULL
;
1449 obj_priv
->mmap_offset
= 0;
1453 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1454 * @obj: object to check
1456 * Return the required GTT alignment for an object, taking into account
1457 * potential fence register mapping if needed.
1460 i915_gem_get_gtt_alignment(struct drm_gem_object
*obj
)
1462 struct drm_device
*dev
= obj
->dev
;
1463 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1467 * Minimum alignment is 4k (GTT page size), but might be greater
1468 * if a fence register is needed for the object.
1470 if (INTEL_INFO(dev
)->gen
>= 4 || obj_priv
->tiling_mode
== I915_TILING_NONE
)
1474 * Previous chips need to be aligned to the size of the smallest
1475 * fence register that can contain the object.
1477 if (INTEL_INFO(dev
)->gen
== 3)
1482 for (i
= start
; i
< obj
->size
; i
<<= 1)
1489 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1491 * @data: GTT mapping ioctl data
1492 * @file_priv: GEM object info
1494 * Simply returns the fake offset to userspace so it can mmap it.
1495 * The mmap call will end up in drm_gem_mmap(), which will set things
1496 * up so we can get faults in the handler above.
1498 * The fault handler will take care of binding the object into the GTT
1499 * (since it may have been evicted to make room for something), allocating
1500 * a fence register, and mapping the appropriate aperture address into
1504 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1505 struct drm_file
*file_priv
)
1507 struct drm_i915_gem_mmap_gtt
*args
= data
;
1508 struct drm_gem_object
*obj
;
1509 struct drm_i915_gem_object
*obj_priv
;
1512 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1515 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1519 ret
= i915_mutex_lock_interruptible(dev
);
1521 drm_gem_object_unreference_unlocked(obj
);
1525 obj_priv
= to_intel_bo(obj
);
1527 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
1528 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1529 drm_gem_object_unreference(obj
);
1530 mutex_unlock(&dev
->struct_mutex
);
1535 if (!obj_priv
->mmap_offset
) {
1536 ret
= i915_gem_create_mmap_offset(obj
);
1538 drm_gem_object_unreference(obj
);
1539 mutex_unlock(&dev
->struct_mutex
);
1544 args
->offset
= obj_priv
->mmap_offset
;
1547 * Pull it into the GTT so that we have a page list (makes the
1548 * initial fault faster and any subsequent flushing possible).
1550 if (!obj_priv
->agp_mem
) {
1551 ret
= i915_gem_object_bind_to_gtt(obj
, 0);
1553 drm_gem_object_unreference(obj
);
1554 mutex_unlock(&dev
->struct_mutex
);
1559 drm_gem_object_unreference(obj
);
1560 mutex_unlock(&dev
->struct_mutex
);
1566 i915_gem_object_put_pages(struct drm_gem_object
*obj
)
1568 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1569 int page_count
= obj
->size
/ PAGE_SIZE
;
1572 BUG_ON(obj_priv
->pages_refcount
== 0);
1573 BUG_ON(obj_priv
->madv
== __I915_MADV_PURGED
);
1575 if (--obj_priv
->pages_refcount
!= 0)
1578 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
1579 i915_gem_object_save_bit_17_swizzle(obj
);
1581 if (obj_priv
->madv
== I915_MADV_DONTNEED
)
1582 obj_priv
->dirty
= 0;
1584 for (i
= 0; i
< page_count
; i
++) {
1585 if (obj_priv
->dirty
)
1586 set_page_dirty(obj_priv
->pages
[i
]);
1588 if (obj_priv
->madv
== I915_MADV_WILLNEED
)
1589 mark_page_accessed(obj_priv
->pages
[i
]);
1591 page_cache_release(obj_priv
->pages
[i
]);
1593 obj_priv
->dirty
= 0;
1595 drm_free_large(obj_priv
->pages
);
1596 obj_priv
->pages
= NULL
;
1600 i915_gem_next_request_seqno(struct drm_device
*dev
,
1601 struct intel_ring_buffer
*ring
)
1603 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1605 ring
->outstanding_lazy_request
= true;
1606 return dev_priv
->next_seqno
;
1610 i915_gem_object_move_to_active(struct drm_gem_object
*obj
,
1611 struct intel_ring_buffer
*ring
)
1613 struct drm_device
*dev
= obj
->dev
;
1614 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1615 uint32_t seqno
= i915_gem_next_request_seqno(dev
, ring
);
1617 BUG_ON(ring
== NULL
);
1618 obj_priv
->ring
= ring
;
1620 /* Add a reference if we're newly entering the active list. */
1621 if (!obj_priv
->active
) {
1622 drm_gem_object_reference(obj
);
1623 obj_priv
->active
= 1;
1626 /* Move from whatever list we were on to the tail of execution. */
1627 list_move_tail(&obj_priv
->list
, &ring
->active_list
);
1628 obj_priv
->last_rendering_seqno
= seqno
;
1632 i915_gem_object_move_to_flushing(struct drm_gem_object
*obj
)
1634 struct drm_device
*dev
= obj
->dev
;
1635 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1636 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1638 BUG_ON(!obj_priv
->active
);
1639 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.flushing_list
);
1640 obj_priv
->last_rendering_seqno
= 0;
1643 /* Immediately discard the backing storage */
1645 i915_gem_object_truncate(struct drm_gem_object
*obj
)
1647 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1648 struct inode
*inode
;
1650 /* Our goal here is to return as much of the memory as
1651 * is possible back to the system as we are called from OOM.
1652 * To do this we must instruct the shmfs to drop all of its
1653 * backing pages, *now*. Here we mirror the actions taken
1654 * when by shmem_delete_inode() to release the backing store.
1656 inode
= obj
->filp
->f_path
.dentry
->d_inode
;
1657 truncate_inode_pages(inode
->i_mapping
, 0);
1658 if (inode
->i_op
->truncate_range
)
1659 inode
->i_op
->truncate_range(inode
, 0, (loff_t
)-1);
1661 obj_priv
->madv
= __I915_MADV_PURGED
;
1665 i915_gem_object_is_purgeable(struct drm_i915_gem_object
*obj_priv
)
1667 return obj_priv
->madv
== I915_MADV_DONTNEED
;
1671 i915_gem_object_move_to_inactive(struct drm_gem_object
*obj
)
1673 struct drm_device
*dev
= obj
->dev
;
1674 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1675 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1677 if (obj_priv
->pin_count
!= 0)
1678 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.pinned_list
);
1680 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
1682 BUG_ON(!list_empty(&obj_priv
->gpu_write_list
));
1684 obj_priv
->last_rendering_seqno
= 0;
1685 obj_priv
->ring
= NULL
;
1686 if (obj_priv
->active
) {
1687 obj_priv
->active
= 0;
1688 drm_gem_object_unreference(obj
);
1690 WARN_ON(i915_verify_lists(dev
));
1694 i915_gem_process_flushing_list(struct drm_device
*dev
,
1695 uint32_t flush_domains
,
1696 struct intel_ring_buffer
*ring
)
1698 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1699 struct drm_i915_gem_object
*obj_priv
, *next
;
1701 list_for_each_entry_safe(obj_priv
, next
,
1702 &dev_priv
->mm
.gpu_write_list
,
1704 struct drm_gem_object
*obj
= &obj_priv
->base
;
1706 if (obj
->write_domain
& flush_domains
&&
1707 obj_priv
->ring
== ring
) {
1708 uint32_t old_write_domain
= obj
->write_domain
;
1710 obj
->write_domain
= 0;
1711 list_del_init(&obj_priv
->gpu_write_list
);
1712 i915_gem_object_move_to_active(obj
, ring
);
1714 /* update the fence lru list */
1715 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
1716 struct drm_i915_fence_reg
*reg
=
1717 &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
1718 list_move_tail(®
->lru_list
,
1719 &dev_priv
->mm
.fence_list
);
1722 trace_i915_gem_object_change_domain(obj
,
1730 i915_add_request(struct drm_device
*dev
,
1731 struct drm_file
*file
,
1732 struct drm_i915_gem_request
*request
,
1733 struct intel_ring_buffer
*ring
)
1735 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1736 struct drm_i915_file_private
*file_priv
= NULL
;
1741 file_priv
= file
->driver_priv
;
1743 if (request
== NULL
) {
1744 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
1745 if (request
== NULL
)
1749 seqno
= ring
->add_request(dev
, ring
, 0);
1750 ring
->outstanding_lazy_request
= false;
1752 request
->seqno
= seqno
;
1753 request
->ring
= ring
;
1754 request
->emitted_jiffies
= jiffies
;
1755 was_empty
= list_empty(&ring
->request_list
);
1756 list_add_tail(&request
->list
, &ring
->request_list
);
1759 spin_lock(&file_priv
->mm
.lock
);
1760 request
->file_priv
= file_priv
;
1761 list_add_tail(&request
->client_list
,
1762 &file_priv
->mm
.request_list
);
1763 spin_unlock(&file_priv
->mm
.lock
);
1766 if (!dev_priv
->mm
.suspended
) {
1767 mod_timer(&dev_priv
->hangcheck_timer
,
1768 jiffies
+ msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD
));
1770 queue_delayed_work(dev_priv
->wq
,
1771 &dev_priv
->mm
.retire_work
, HZ
);
1777 * Command execution barrier
1779 * Ensures that all commands in the ring are finished
1780 * before signalling the CPU
1783 i915_retire_commands(struct drm_device
*dev
, struct intel_ring_buffer
*ring
)
1785 uint32_t flush_domains
= 0;
1787 /* The sampler always gets flushed on i965 (sigh) */
1788 if (INTEL_INFO(dev
)->gen
>= 4)
1789 flush_domains
|= I915_GEM_DOMAIN_SAMPLER
;
1791 ring
->flush(dev
, ring
,
1792 I915_GEM_DOMAIN_COMMAND
, flush_domains
);
1796 i915_gem_request_remove_from_client(struct drm_i915_gem_request
*request
)
1798 struct drm_i915_file_private
*file_priv
= request
->file_priv
;
1803 spin_lock(&file_priv
->mm
.lock
);
1804 list_del(&request
->client_list
);
1805 request
->file_priv
= NULL
;
1806 spin_unlock(&file_priv
->mm
.lock
);
1809 static void i915_gem_reset_ring_lists(struct drm_i915_private
*dev_priv
,
1810 struct intel_ring_buffer
*ring
)
1812 while (!list_empty(&ring
->request_list
)) {
1813 struct drm_i915_gem_request
*request
;
1815 request
= list_first_entry(&ring
->request_list
,
1816 struct drm_i915_gem_request
,
1819 list_del(&request
->list
);
1820 i915_gem_request_remove_from_client(request
);
1824 while (!list_empty(&ring
->active_list
)) {
1825 struct drm_i915_gem_object
*obj_priv
;
1827 obj_priv
= list_first_entry(&ring
->active_list
,
1828 struct drm_i915_gem_object
,
1831 obj_priv
->base
.write_domain
= 0;
1832 list_del_init(&obj_priv
->gpu_write_list
);
1833 i915_gem_object_move_to_inactive(&obj_priv
->base
);
1837 void i915_gem_reset(struct drm_device
*dev
)
1839 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1840 struct drm_i915_gem_object
*obj_priv
;
1843 i915_gem_reset_ring_lists(dev_priv
, &dev_priv
->render_ring
);
1845 i915_gem_reset_ring_lists(dev_priv
, &dev_priv
->bsd_ring
);
1847 /* Remove anything from the flushing lists. The GPU cache is likely
1848 * to be lost on reset along with the data, so simply move the
1849 * lost bo to the inactive list.
1851 while (!list_empty(&dev_priv
->mm
.flushing_list
)) {
1852 obj_priv
= list_first_entry(&dev_priv
->mm
.flushing_list
,
1853 struct drm_i915_gem_object
,
1856 obj_priv
->base
.write_domain
= 0;
1857 list_del_init(&obj_priv
->gpu_write_list
);
1858 i915_gem_object_move_to_inactive(&obj_priv
->base
);
1861 /* Move everything out of the GPU domains to ensure we do any
1862 * necessary invalidation upon reuse.
1864 list_for_each_entry(obj_priv
,
1865 &dev_priv
->mm
.inactive_list
,
1868 obj_priv
->base
.read_domains
&= ~I915_GEM_GPU_DOMAINS
;
1871 /* The fence registers are invalidated so clear them out */
1872 for (i
= 0; i
< 16; i
++) {
1873 struct drm_i915_fence_reg
*reg
;
1875 reg
= &dev_priv
->fence_regs
[i
];
1879 i915_gem_clear_fence_reg(reg
->obj
);
1884 * This function clears the request list as sequence numbers are passed.
1887 i915_gem_retire_requests_ring(struct drm_device
*dev
,
1888 struct intel_ring_buffer
*ring
)
1890 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1893 if (!ring
->status_page
.page_addr
||
1894 list_empty(&ring
->request_list
))
1897 WARN_ON(i915_verify_lists(dev
));
1899 seqno
= ring
->get_seqno(dev
, ring
);
1900 while (!list_empty(&ring
->request_list
)) {
1901 struct drm_i915_gem_request
*request
;
1903 request
= list_first_entry(&ring
->request_list
,
1904 struct drm_i915_gem_request
,
1907 if (!i915_seqno_passed(seqno
, request
->seqno
))
1910 trace_i915_gem_request_retire(dev
, request
->seqno
);
1912 list_del(&request
->list
);
1913 i915_gem_request_remove_from_client(request
);
1917 /* Move any buffers on the active list that are no longer referenced
1918 * by the ringbuffer to the flushing/inactive lists as appropriate.
1920 while (!list_empty(&ring
->active_list
)) {
1921 struct drm_gem_object
*obj
;
1922 struct drm_i915_gem_object
*obj_priv
;
1924 obj_priv
= list_first_entry(&ring
->active_list
,
1925 struct drm_i915_gem_object
,
1928 if (!i915_seqno_passed(seqno
, obj_priv
->last_rendering_seqno
))
1931 obj
= &obj_priv
->base
;
1932 if (obj
->write_domain
!= 0)
1933 i915_gem_object_move_to_flushing(obj
);
1935 i915_gem_object_move_to_inactive(obj
);
1938 if (unlikely (dev_priv
->trace_irq_seqno
&&
1939 i915_seqno_passed(dev_priv
->trace_irq_seqno
, seqno
))) {
1940 ring
->user_irq_put(dev
, ring
);
1941 dev_priv
->trace_irq_seqno
= 0;
1944 WARN_ON(i915_verify_lists(dev
));
1948 i915_gem_retire_requests(struct drm_device
*dev
)
1950 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1952 if (!list_empty(&dev_priv
->mm
.deferred_free_list
)) {
1953 struct drm_i915_gem_object
*obj_priv
, *tmp
;
1955 /* We must be careful that during unbind() we do not
1956 * accidentally infinitely recurse into retire requests.
1958 * retire -> free -> unbind -> wait -> retire_ring
1960 list_for_each_entry_safe(obj_priv
, tmp
,
1961 &dev_priv
->mm
.deferred_free_list
,
1963 i915_gem_free_object_tail(&obj_priv
->base
);
1966 i915_gem_retire_requests_ring(dev
, &dev_priv
->render_ring
);
1968 i915_gem_retire_requests_ring(dev
, &dev_priv
->bsd_ring
);
1972 i915_gem_retire_work_handler(struct work_struct
*work
)
1974 drm_i915_private_t
*dev_priv
;
1975 struct drm_device
*dev
;
1977 dev_priv
= container_of(work
, drm_i915_private_t
,
1978 mm
.retire_work
.work
);
1979 dev
= dev_priv
->dev
;
1981 /* Come back later if the device is busy... */
1982 if (!mutex_trylock(&dev
->struct_mutex
)) {
1983 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
1987 i915_gem_retire_requests(dev
);
1989 if (!dev_priv
->mm
.suspended
&&
1990 (!list_empty(&dev_priv
->render_ring
.request_list
) ||
1992 !list_empty(&dev_priv
->bsd_ring
.request_list
))))
1993 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
1994 mutex_unlock(&dev
->struct_mutex
);
1998 i915_do_wait_request(struct drm_device
*dev
, uint32_t seqno
,
1999 bool interruptible
, struct intel_ring_buffer
*ring
)
2001 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2007 if (atomic_read(&dev_priv
->mm
.wedged
))
2010 if (ring
->outstanding_lazy_request
) {
2011 seqno
= i915_add_request(dev
, NULL
, NULL
, ring
);
2015 BUG_ON(seqno
== dev_priv
->next_seqno
);
2017 if (!i915_seqno_passed(ring
->get_seqno(dev
, ring
), seqno
)) {
2018 if (HAS_PCH_SPLIT(dev
))
2019 ier
= I915_READ(DEIER
) | I915_READ(GTIER
);
2021 ier
= I915_READ(IER
);
2023 DRM_ERROR("something (likely vbetool) disabled "
2024 "interrupts, re-enabling\n");
2025 i915_driver_irq_preinstall(dev
);
2026 i915_driver_irq_postinstall(dev
);
2029 trace_i915_gem_request_wait_begin(dev
, seqno
);
2031 ring
->waiting_gem_seqno
= seqno
;
2032 ring
->user_irq_get(dev
, ring
);
2034 ret
= wait_event_interruptible(ring
->irq_queue
,
2036 ring
->get_seqno(dev
, ring
), seqno
)
2037 || atomic_read(&dev_priv
->mm
.wedged
));
2039 wait_event(ring
->irq_queue
,
2041 ring
->get_seqno(dev
, ring
), seqno
)
2042 || atomic_read(&dev_priv
->mm
.wedged
));
2044 ring
->user_irq_put(dev
, ring
);
2045 ring
->waiting_gem_seqno
= 0;
2047 trace_i915_gem_request_wait_end(dev
, seqno
);
2049 if (atomic_read(&dev_priv
->mm
.wedged
))
2052 if (ret
&& ret
!= -ERESTARTSYS
)
2053 DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n",
2054 __func__
, ret
, seqno
, ring
->get_seqno(dev
, ring
),
2055 dev_priv
->next_seqno
);
2057 /* Directly dispatch request retiring. While we have the work queue
2058 * to handle this, the waiter on a request often wants an associated
2059 * buffer to have made it to the inactive list, and we would need
2060 * a separate wait queue to handle that.
2063 i915_gem_retire_requests_ring(dev
, ring
);
2069 * Waits for a sequence number to be signaled, and cleans up the
2070 * request and object lists appropriately for that event.
2073 i915_wait_request(struct drm_device
*dev
, uint32_t seqno
,
2074 struct intel_ring_buffer
*ring
)
2076 return i915_do_wait_request(dev
, seqno
, 1, ring
);
2080 i915_gem_flush_ring(struct drm_device
*dev
,
2081 struct drm_file
*file_priv
,
2082 struct intel_ring_buffer
*ring
,
2083 uint32_t invalidate_domains
,
2084 uint32_t flush_domains
)
2086 ring
->flush(dev
, ring
, invalidate_domains
, flush_domains
);
2087 i915_gem_process_flushing_list(dev
, flush_domains
, ring
);
2091 i915_gem_flush(struct drm_device
*dev
,
2092 struct drm_file
*file_priv
,
2093 uint32_t invalidate_domains
,
2094 uint32_t flush_domains
,
2095 uint32_t flush_rings
)
2097 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2099 if (flush_domains
& I915_GEM_DOMAIN_CPU
)
2100 drm_agp_chipset_flush(dev
);
2102 if ((flush_domains
| invalidate_domains
) & I915_GEM_GPU_DOMAINS
) {
2103 if (flush_rings
& RING_RENDER
)
2104 i915_gem_flush_ring(dev
, file_priv
,
2105 &dev_priv
->render_ring
,
2106 invalidate_domains
, flush_domains
);
2107 if (flush_rings
& RING_BSD
)
2108 i915_gem_flush_ring(dev
, file_priv
,
2109 &dev_priv
->bsd_ring
,
2110 invalidate_domains
, flush_domains
);
2115 * Ensures that all rendering to the object has completed and the object is
2116 * safe to unbind from the GTT or access from the CPU.
2119 i915_gem_object_wait_rendering(struct drm_gem_object
*obj
,
2122 struct drm_device
*dev
= obj
->dev
;
2123 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2126 /* This function only exists to support waiting for existing rendering,
2127 * not for emitting required flushes.
2129 BUG_ON((obj
->write_domain
& I915_GEM_GPU_DOMAINS
) != 0);
2131 /* If there is rendering queued on the buffer being evicted, wait for
2134 if (obj_priv
->active
) {
2135 ret
= i915_do_wait_request(dev
,
2136 obj_priv
->last_rendering_seqno
,
2147 * Unbinds an object from the GTT aperture.
2150 i915_gem_object_unbind(struct drm_gem_object
*obj
)
2152 struct drm_device
*dev
= obj
->dev
;
2153 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2154 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2157 if (obj_priv
->gtt_space
== NULL
)
2160 if (obj_priv
->pin_count
!= 0) {
2161 DRM_ERROR("Attempting to unbind pinned buffer\n");
2165 /* blow away mappings if mapped through GTT */
2166 i915_gem_release_mmap(obj
);
2168 /* Move the object to the CPU domain to ensure that
2169 * any possible CPU writes while it's not in the GTT
2170 * are flushed when we go to remap it. This will
2171 * also ensure that all pending GPU writes are finished
2174 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
2175 if (ret
== -ERESTARTSYS
)
2177 /* Continue on if we fail due to EIO, the GPU is hung so we
2178 * should be safe and we need to cleanup or else we might
2179 * cause memory corruption through use-after-free.
2182 i915_gem_clflush_object(obj
);
2183 obj
->read_domains
= obj
->write_domain
= I915_GEM_DOMAIN_CPU
;
2186 /* release the fence reg _after_ flushing */
2187 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
)
2188 i915_gem_clear_fence_reg(obj
);
2190 drm_unbind_agp(obj_priv
->agp_mem
);
2191 drm_free_agp(obj_priv
->agp_mem
, obj
->size
/ PAGE_SIZE
);
2193 i915_gem_object_put_pages(obj
);
2194 BUG_ON(obj_priv
->pages_refcount
);
2196 i915_gem_info_remove_gtt(dev_priv
, obj
->size
);
2197 list_del_init(&obj_priv
->list
);
2199 drm_mm_put_block(obj_priv
->gtt_space
);
2200 obj_priv
->gtt_space
= NULL
;
2202 if (i915_gem_object_is_purgeable(obj_priv
))
2203 i915_gem_object_truncate(obj
);
2205 trace_i915_gem_object_unbind(obj
);
2210 static int i915_ring_idle(struct drm_device
*dev
,
2211 struct intel_ring_buffer
*ring
)
2213 i915_gem_flush_ring(dev
, NULL
, ring
,
2214 I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
2215 return i915_wait_request(dev
,
2216 i915_gem_next_request_seqno(dev
, ring
),
2221 i915_gpu_idle(struct drm_device
*dev
)
2223 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2227 lists_empty
= (list_empty(&dev_priv
->mm
.flushing_list
) &&
2228 list_empty(&dev_priv
->render_ring
.active_list
) &&
2230 list_empty(&dev_priv
->bsd_ring
.active_list
)));
2234 /* Flush everything onto the inactive list. */
2235 ret
= i915_ring_idle(dev
, &dev_priv
->render_ring
);
2240 ret
= i915_ring_idle(dev
, &dev_priv
->bsd_ring
);
2249 i915_gem_object_get_pages(struct drm_gem_object
*obj
,
2252 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2254 struct address_space
*mapping
;
2255 struct inode
*inode
;
2258 BUG_ON(obj_priv
->pages_refcount
2259 == DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT
);
2261 if (obj_priv
->pages_refcount
++ != 0)
2264 /* Get the list of pages out of our struct file. They'll be pinned
2265 * at this point until we release them.
2267 page_count
= obj
->size
/ PAGE_SIZE
;
2268 BUG_ON(obj_priv
->pages
!= NULL
);
2269 obj_priv
->pages
= drm_calloc_large(page_count
, sizeof(struct page
*));
2270 if (obj_priv
->pages
== NULL
) {
2271 obj_priv
->pages_refcount
--;
2275 inode
= obj
->filp
->f_path
.dentry
->d_inode
;
2276 mapping
= inode
->i_mapping
;
2277 for (i
= 0; i
< page_count
; i
++) {
2278 page
= read_cache_page_gfp(mapping
, i
,
2286 obj_priv
->pages
[i
] = page
;
2289 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
2290 i915_gem_object_do_bit_17_swizzle(obj
);
2296 page_cache_release(obj_priv
->pages
[i
]);
2298 drm_free_large(obj_priv
->pages
);
2299 obj_priv
->pages
= NULL
;
2300 obj_priv
->pages_refcount
--;
2301 return PTR_ERR(page
);
2304 static void sandybridge_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2306 struct drm_gem_object
*obj
= reg
->obj
;
2307 struct drm_device
*dev
= obj
->dev
;
2308 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2309 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2310 int regnum
= obj_priv
->fence_reg
;
2313 val
= (uint64_t)((obj_priv
->gtt_offset
+ obj
->size
- 4096) &
2315 val
|= obj_priv
->gtt_offset
& 0xfffff000;
2316 val
|= (uint64_t)((obj_priv
->stride
/ 128) - 1) <<
2317 SANDYBRIDGE_FENCE_PITCH_SHIFT
;
2319 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2320 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2321 val
|= I965_FENCE_REG_VALID
;
2323 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+ (regnum
* 8), val
);
2326 static void i965_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2328 struct drm_gem_object
*obj
= reg
->obj
;
2329 struct drm_device
*dev
= obj
->dev
;
2330 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2331 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2332 int regnum
= obj_priv
->fence_reg
;
2335 val
= (uint64_t)((obj_priv
->gtt_offset
+ obj
->size
- 4096) &
2337 val
|= obj_priv
->gtt_offset
& 0xfffff000;
2338 val
|= ((obj_priv
->stride
/ 128) - 1) << I965_FENCE_PITCH_SHIFT
;
2339 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2340 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2341 val
|= I965_FENCE_REG_VALID
;
2343 I915_WRITE64(FENCE_REG_965_0
+ (regnum
* 8), val
);
2346 static void i915_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2348 struct drm_gem_object
*obj
= reg
->obj
;
2349 struct drm_device
*dev
= obj
->dev
;
2350 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2351 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2352 int regnum
= obj_priv
->fence_reg
;
2354 uint32_t fence_reg
, val
;
2357 if ((obj_priv
->gtt_offset
& ~I915_FENCE_START_MASK
) ||
2358 (obj_priv
->gtt_offset
& (obj
->size
- 1))) {
2359 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
2360 __func__
, obj_priv
->gtt_offset
, obj
->size
);
2364 if (obj_priv
->tiling_mode
== I915_TILING_Y
&&
2365 HAS_128_BYTE_Y_TILING(dev
))
2370 /* Note: pitch better be a power of two tile widths */
2371 pitch_val
= obj_priv
->stride
/ tile_width
;
2372 pitch_val
= ffs(pitch_val
) - 1;
2374 if (obj_priv
->tiling_mode
== I915_TILING_Y
&&
2375 HAS_128_BYTE_Y_TILING(dev
))
2376 WARN_ON(pitch_val
> I830_FENCE_MAX_PITCH_VAL
);
2378 WARN_ON(pitch_val
> I915_FENCE_MAX_PITCH_VAL
);
2380 val
= obj_priv
->gtt_offset
;
2381 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2382 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2383 val
|= I915_FENCE_SIZE_BITS(obj
->size
);
2384 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2385 val
|= I830_FENCE_REG_VALID
;
2388 fence_reg
= FENCE_REG_830_0
+ (regnum
* 4);
2390 fence_reg
= FENCE_REG_945_8
+ ((regnum
- 8) * 4);
2391 I915_WRITE(fence_reg
, val
);
2394 static void i830_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2396 struct drm_gem_object
*obj
= reg
->obj
;
2397 struct drm_device
*dev
= obj
->dev
;
2398 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2399 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2400 int regnum
= obj_priv
->fence_reg
;
2403 uint32_t fence_size_bits
;
2405 if ((obj_priv
->gtt_offset
& ~I830_FENCE_START_MASK
) ||
2406 (obj_priv
->gtt_offset
& (obj
->size
- 1))) {
2407 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2408 __func__
, obj_priv
->gtt_offset
);
2412 pitch_val
= obj_priv
->stride
/ 128;
2413 pitch_val
= ffs(pitch_val
) - 1;
2414 WARN_ON(pitch_val
> I830_FENCE_MAX_PITCH_VAL
);
2416 val
= obj_priv
->gtt_offset
;
2417 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2418 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2419 fence_size_bits
= I830_FENCE_SIZE_BITS(obj
->size
);
2420 WARN_ON(fence_size_bits
& ~0x00000f00);
2421 val
|= fence_size_bits
;
2422 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2423 val
|= I830_FENCE_REG_VALID
;
2425 I915_WRITE(FENCE_REG_830_0
+ (regnum
* 4), val
);
2428 static int i915_find_fence_reg(struct drm_device
*dev
,
2431 struct drm_i915_fence_reg
*reg
= NULL
;
2432 struct drm_i915_gem_object
*obj_priv
= NULL
;
2433 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2434 struct drm_gem_object
*obj
= NULL
;
2437 /* First try to find a free reg */
2439 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
2440 reg
= &dev_priv
->fence_regs
[i
];
2444 obj_priv
= to_intel_bo(reg
->obj
);
2445 if (!obj_priv
->pin_count
)
2452 /* None available, try to steal one or wait for a user to finish */
2453 i
= I915_FENCE_REG_NONE
;
2454 list_for_each_entry(reg
, &dev_priv
->mm
.fence_list
,
2457 obj_priv
= to_intel_bo(obj
);
2459 if (obj_priv
->pin_count
)
2463 i
= obj_priv
->fence_reg
;
2467 BUG_ON(i
== I915_FENCE_REG_NONE
);
2469 /* We only have a reference on obj from the active list. put_fence_reg
2470 * might drop that one, causing a use-after-free in it. So hold a
2471 * private reference to obj like the other callers of put_fence_reg
2472 * (set_tiling ioctl) do. */
2473 drm_gem_object_reference(obj
);
2474 ret
= i915_gem_object_put_fence_reg(obj
, interruptible
);
2475 drm_gem_object_unreference(obj
);
2483 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2484 * @obj: object to map through a fence reg
2486 * When mapping objects through the GTT, userspace wants to be able to write
2487 * to them without having to worry about swizzling if the object is tiled.
2489 * This function walks the fence regs looking for a free one for @obj,
2490 * stealing one if it can't find any.
2492 * It then sets up the reg based on the object's properties: address, pitch
2493 * and tiling format.
2496 i915_gem_object_get_fence_reg(struct drm_gem_object
*obj
,
2499 struct drm_device
*dev
= obj
->dev
;
2500 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2501 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2502 struct drm_i915_fence_reg
*reg
= NULL
;
2505 /* Just update our place in the LRU if our fence is getting used. */
2506 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
2507 reg
= &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
2508 list_move_tail(®
->lru_list
, &dev_priv
->mm
.fence_list
);
2512 switch (obj_priv
->tiling_mode
) {
2513 case I915_TILING_NONE
:
2514 WARN(1, "allocating a fence for non-tiled object?\n");
2517 if (!obj_priv
->stride
)
2519 WARN((obj_priv
->stride
& (512 - 1)),
2520 "object 0x%08x is X tiled but has non-512B pitch\n",
2521 obj_priv
->gtt_offset
);
2524 if (!obj_priv
->stride
)
2526 WARN((obj_priv
->stride
& (128 - 1)),
2527 "object 0x%08x is Y tiled but has non-128B pitch\n",
2528 obj_priv
->gtt_offset
);
2532 ret
= i915_find_fence_reg(dev
, interruptible
);
2536 obj_priv
->fence_reg
= ret
;
2537 reg
= &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
2538 list_add_tail(®
->lru_list
, &dev_priv
->mm
.fence_list
);
2542 switch (INTEL_INFO(dev
)->gen
) {
2544 sandybridge_write_fence_reg(reg
);
2548 i965_write_fence_reg(reg
);
2551 i915_write_fence_reg(reg
);
2554 i830_write_fence_reg(reg
);
2558 trace_i915_gem_object_get_fence(obj
, obj_priv
->fence_reg
,
2559 obj_priv
->tiling_mode
);
2565 * i915_gem_clear_fence_reg - clear out fence register info
2566 * @obj: object to clear
2568 * Zeroes out the fence register itself and clears out the associated
2569 * data structures in dev_priv and obj_priv.
2572 i915_gem_clear_fence_reg(struct drm_gem_object
*obj
)
2574 struct drm_device
*dev
= obj
->dev
;
2575 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2576 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2577 struct drm_i915_fence_reg
*reg
=
2578 &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
2581 switch (INTEL_INFO(dev
)->gen
) {
2583 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+
2584 (obj_priv
->fence_reg
* 8), 0);
2588 I915_WRITE64(FENCE_REG_965_0
+ (obj_priv
->fence_reg
* 8), 0);
2591 if (obj_priv
->fence_reg
>= 8)
2592 fence_reg
= FENCE_REG_945_8
+ (obj_priv
->fence_reg
- 8) * 4;
2595 fence_reg
= FENCE_REG_830_0
+ obj_priv
->fence_reg
* 4;
2597 I915_WRITE(fence_reg
, 0);
2602 obj_priv
->fence_reg
= I915_FENCE_REG_NONE
;
2603 list_del_init(®
->lru_list
);
2607 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2608 * to the buffer to finish, and then resets the fence register.
2609 * @obj: tiled object holding a fence register.
2610 * @bool: whether the wait upon the fence is interruptible
2612 * Zeroes out the fence register itself and clears out the associated
2613 * data structures in dev_priv and obj_priv.
2616 i915_gem_object_put_fence_reg(struct drm_gem_object
*obj
,
2619 struct drm_device
*dev
= obj
->dev
;
2620 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2621 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2622 struct drm_i915_fence_reg
*reg
;
2624 if (obj_priv
->fence_reg
== I915_FENCE_REG_NONE
)
2627 /* If we've changed tiling, GTT-mappings of the object
2628 * need to re-fault to ensure that the correct fence register
2629 * setup is in place.
2631 i915_gem_release_mmap(obj
);
2633 /* On the i915, GPU access to tiled buffers is via a fence,
2634 * therefore we must wait for any outstanding access to complete
2635 * before clearing the fence.
2637 reg
= &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
2641 ret
= i915_gem_object_flush_gpu_write_domain(obj
, true);
2645 ret
= i915_gem_object_wait_rendering(obj
, interruptible
);
2652 i915_gem_object_flush_gtt_write_domain(obj
);
2653 i915_gem_clear_fence_reg(obj
);
2659 * Finds free space in the GTT aperture and binds the object there.
2662 i915_gem_object_bind_to_gtt(struct drm_gem_object
*obj
, unsigned alignment
)
2664 struct drm_device
*dev
= obj
->dev
;
2665 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2666 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2667 struct drm_mm_node
*free_space
;
2668 gfp_t gfpmask
= __GFP_NORETRY
| __GFP_NOWARN
;
2671 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
2672 DRM_ERROR("Attempting to bind a purgeable object\n");
2677 alignment
= i915_gem_get_gtt_alignment(obj
);
2678 if (alignment
& (i915_gem_get_gtt_alignment(obj
) - 1)) {
2679 DRM_ERROR("Invalid object alignment requested %u\n", alignment
);
2683 /* If the object is bigger than the entire aperture, reject it early
2684 * before evicting everything in a vain attempt to find space.
2686 if (obj
->size
> dev_priv
->mm
.gtt_total
) {
2687 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2692 free_space
= drm_mm_search_free(&dev_priv
->mm
.gtt_space
,
2693 obj
->size
, alignment
, 0);
2694 if (free_space
!= NULL
) {
2695 obj_priv
->gtt_space
= drm_mm_get_block(free_space
, obj
->size
,
2697 if (obj_priv
->gtt_space
!= NULL
)
2698 obj_priv
->gtt_offset
= obj_priv
->gtt_space
->start
;
2700 if (obj_priv
->gtt_space
== NULL
) {
2701 /* If the gtt is empty and we're still having trouble
2702 * fitting our object in, we're out of memory.
2704 ret
= i915_gem_evict_something(dev
, obj
->size
, alignment
);
2711 ret
= i915_gem_object_get_pages(obj
, gfpmask
);
2713 drm_mm_put_block(obj_priv
->gtt_space
);
2714 obj_priv
->gtt_space
= NULL
;
2716 if (ret
== -ENOMEM
) {
2717 /* first try to clear up some space from the GTT */
2718 ret
= i915_gem_evict_something(dev
, obj
->size
,
2721 /* now try to shrink everyone else */
2736 /* Create an AGP memory structure pointing at our pages, and bind it
2739 obj_priv
->agp_mem
= drm_agp_bind_pages(dev
,
2741 obj
->size
>> PAGE_SHIFT
,
2742 obj_priv
->gtt_offset
,
2743 obj_priv
->agp_type
);
2744 if (obj_priv
->agp_mem
== NULL
) {
2745 i915_gem_object_put_pages(obj
);
2746 drm_mm_put_block(obj_priv
->gtt_space
);
2747 obj_priv
->gtt_space
= NULL
;
2749 ret
= i915_gem_evict_something(dev
, obj
->size
, alignment
);
2756 /* keep track of bounds object by adding it to the inactive list */
2757 list_add_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
2758 i915_gem_info_add_gtt(dev_priv
, obj
->size
);
2760 /* Assert that the object is not currently in any GPU domain. As it
2761 * wasn't in the GTT, there shouldn't be any way it could have been in
2764 BUG_ON(obj
->read_domains
& I915_GEM_GPU_DOMAINS
);
2765 BUG_ON(obj
->write_domain
& I915_GEM_GPU_DOMAINS
);
2767 trace_i915_gem_object_bind(obj
, obj_priv
->gtt_offset
);
2773 i915_gem_clflush_object(struct drm_gem_object
*obj
)
2775 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2777 /* If we don't have a page list set up, then we're not pinned
2778 * to GPU, and we can ignore the cache flush because it'll happen
2779 * again at bind time.
2781 if (obj_priv
->pages
== NULL
)
2784 trace_i915_gem_object_clflush(obj
);
2786 drm_clflush_pages(obj_priv
->pages
, obj
->size
/ PAGE_SIZE
);
2789 /** Flushes any GPU write domain for the object if it's dirty. */
2791 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object
*obj
,
2794 struct drm_device
*dev
= obj
->dev
;
2795 uint32_t old_write_domain
;
2797 if ((obj
->write_domain
& I915_GEM_GPU_DOMAINS
) == 0)
2800 /* Queue the GPU write cache flushing we need. */
2801 old_write_domain
= obj
->write_domain
;
2802 i915_gem_flush_ring(dev
, NULL
,
2803 to_intel_bo(obj
)->ring
,
2804 0, obj
->write_domain
);
2805 BUG_ON(obj
->write_domain
);
2807 trace_i915_gem_object_change_domain(obj
,
2814 return i915_gem_object_wait_rendering(obj
, true);
2817 /** Flushes the GTT write domain for the object if it's dirty. */
2819 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object
*obj
)
2821 uint32_t old_write_domain
;
2823 if (obj
->write_domain
!= I915_GEM_DOMAIN_GTT
)
2826 /* No actual flushing is required for the GTT write domain. Writes
2827 * to it immediately go to main memory as far as we know, so there's
2828 * no chipset flush. It also doesn't land in render cache.
2830 old_write_domain
= obj
->write_domain
;
2831 obj
->write_domain
= 0;
2833 trace_i915_gem_object_change_domain(obj
,
2838 /** Flushes the CPU write domain for the object if it's dirty. */
2840 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object
*obj
)
2842 struct drm_device
*dev
= obj
->dev
;
2843 uint32_t old_write_domain
;
2845 if (obj
->write_domain
!= I915_GEM_DOMAIN_CPU
)
2848 i915_gem_clflush_object(obj
);
2849 drm_agp_chipset_flush(dev
);
2850 old_write_domain
= obj
->write_domain
;
2851 obj
->write_domain
= 0;
2853 trace_i915_gem_object_change_domain(obj
,
2859 * Moves a single object to the GTT read, and possibly write domain.
2861 * This function returns when the move is complete, including waiting on
2865 i915_gem_object_set_to_gtt_domain(struct drm_gem_object
*obj
, int write
)
2867 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2868 uint32_t old_write_domain
, old_read_domains
;
2871 /* Not valid to be called on unbound objects. */
2872 if (obj_priv
->gtt_space
== NULL
)
2875 ret
= i915_gem_object_flush_gpu_write_domain(obj
, false);
2879 i915_gem_object_flush_cpu_write_domain(obj
);
2882 ret
= i915_gem_object_wait_rendering(obj
, true);
2887 old_write_domain
= obj
->write_domain
;
2888 old_read_domains
= obj
->read_domains
;
2890 /* It should now be out of any other write domains, and we can update
2891 * the domain values for our changes.
2893 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
2894 obj
->read_domains
|= I915_GEM_DOMAIN_GTT
;
2896 obj
->read_domains
= I915_GEM_DOMAIN_GTT
;
2897 obj
->write_domain
= I915_GEM_DOMAIN_GTT
;
2898 obj_priv
->dirty
= 1;
2901 trace_i915_gem_object_change_domain(obj
,
2909 * Prepare buffer for display plane. Use uninterruptible for possible flush
2910 * wait, as in modesetting process we're not supposed to be interrupted.
2913 i915_gem_object_set_to_display_plane(struct drm_gem_object
*obj
,
2916 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2917 uint32_t old_read_domains
;
2920 /* Not valid to be called on unbound objects. */
2921 if (obj_priv
->gtt_space
== NULL
)
2924 ret
= i915_gem_object_flush_gpu_write_domain(obj
, true);
2928 /* Currently, we are always called from an non-interruptible context. */
2930 ret
= i915_gem_object_wait_rendering(obj
, false);
2935 i915_gem_object_flush_cpu_write_domain(obj
);
2937 old_read_domains
= obj
->read_domains
;
2938 obj
->read_domains
|= I915_GEM_DOMAIN_GTT
;
2940 trace_i915_gem_object_change_domain(obj
,
2948 * Moves a single object to the CPU read, and possibly write domain.
2950 * This function returns when the move is complete, including waiting on
2954 i915_gem_object_set_to_cpu_domain(struct drm_gem_object
*obj
, int write
)
2956 uint32_t old_write_domain
, old_read_domains
;
2959 ret
= i915_gem_object_flush_gpu_write_domain(obj
, false);
2963 i915_gem_object_flush_gtt_write_domain(obj
);
2965 /* If we have a partially-valid cache of the object in the CPU,
2966 * finish invalidating it and free the per-page flags.
2968 i915_gem_object_set_to_full_cpu_read_domain(obj
);
2971 ret
= i915_gem_object_wait_rendering(obj
, true);
2976 old_write_domain
= obj
->write_domain
;
2977 old_read_domains
= obj
->read_domains
;
2979 /* Flush the CPU cache if it's still invalid. */
2980 if ((obj
->read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
2981 i915_gem_clflush_object(obj
);
2983 obj
->read_domains
|= I915_GEM_DOMAIN_CPU
;
2986 /* It should now be out of any other write domains, and we can update
2987 * the domain values for our changes.
2989 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
2991 /* If we're writing through the CPU, then the GPU read domains will
2992 * need to be invalidated at next use.
2995 obj
->read_domains
= I915_GEM_DOMAIN_CPU
;
2996 obj
->write_domain
= I915_GEM_DOMAIN_CPU
;
2999 trace_i915_gem_object_change_domain(obj
,
3007 * Set the next domain for the specified object. This
3008 * may not actually perform the necessary flushing/invaliding though,
3009 * as that may want to be batched with other set_domain operations
3011 * This is (we hope) the only really tricky part of gem. The goal
3012 * is fairly simple -- track which caches hold bits of the object
3013 * and make sure they remain coherent. A few concrete examples may
3014 * help to explain how it works. For shorthand, we use the notation
3015 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
3016 * a pair of read and write domain masks.
3018 * Case 1: the batch buffer
3024 * 5. Unmapped from GTT
3027 * Let's take these a step at a time
3030 * Pages allocated from the kernel may still have
3031 * cache contents, so we set them to (CPU, CPU) always.
3032 * 2. Written by CPU (using pwrite)
3033 * The pwrite function calls set_domain (CPU, CPU) and
3034 * this function does nothing (as nothing changes)
3036 * This function asserts that the object is not
3037 * currently in any GPU-based read or write domains
3039 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
3040 * As write_domain is zero, this function adds in the
3041 * current read domains (CPU+COMMAND, 0).
3042 * flush_domains is set to CPU.
3043 * invalidate_domains is set to COMMAND
3044 * clflush is run to get data out of the CPU caches
3045 * then i915_dev_set_domain calls i915_gem_flush to
3046 * emit an MI_FLUSH and drm_agp_chipset_flush
3047 * 5. Unmapped from GTT
3048 * i915_gem_object_unbind calls set_domain (CPU, CPU)
3049 * flush_domains and invalidate_domains end up both zero
3050 * so no flushing/invalidating happens
3054 * Case 2: The shared render buffer
3058 * 3. Read/written by GPU
3059 * 4. set_domain to (CPU,CPU)
3060 * 5. Read/written by CPU
3061 * 6. Read/written by GPU
3064 * Same as last example, (CPU, CPU)
3066 * Nothing changes (assertions find that it is not in the GPU)
3067 * 3. Read/written by GPU
3068 * execbuffer calls set_domain (RENDER, RENDER)
3069 * flush_domains gets CPU
3070 * invalidate_domains gets GPU
3072 * MI_FLUSH and drm_agp_chipset_flush
3073 * 4. set_domain (CPU, CPU)
3074 * flush_domains gets GPU
3075 * invalidate_domains gets CPU
3076 * wait_rendering (obj) to make sure all drawing is complete.
3077 * This will include an MI_FLUSH to get the data from GPU
3079 * clflush (obj) to invalidate the CPU cache
3080 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
3081 * 5. Read/written by CPU
3082 * cache lines are loaded and dirtied
3083 * 6. Read written by GPU
3084 * Same as last GPU access
3086 * Case 3: The constant buffer
3091 * 4. Updated (written) by CPU again
3100 * flush_domains = CPU
3101 * invalidate_domains = RENDER
3104 * drm_agp_chipset_flush
3105 * 4. Updated (written) by CPU again
3107 * flush_domains = 0 (no previous write domain)
3108 * invalidate_domains = 0 (no new read domains)
3111 * flush_domains = CPU
3112 * invalidate_domains = RENDER
3115 * drm_agp_chipset_flush
3118 i915_gem_object_set_to_gpu_domain(struct drm_gem_object
*obj
)
3120 struct drm_device
*dev
= obj
->dev
;
3121 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3122 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3123 uint32_t invalidate_domains
= 0;
3124 uint32_t flush_domains
= 0;
3125 uint32_t old_read_domains
;
3127 BUG_ON(obj
->pending_read_domains
& I915_GEM_DOMAIN_CPU
);
3128 BUG_ON(obj
->pending_write_domain
== I915_GEM_DOMAIN_CPU
);
3130 intel_mark_busy(dev
, obj
);
3133 * If the object isn't moving to a new write domain,
3134 * let the object stay in multiple read domains
3136 if (obj
->pending_write_domain
== 0)
3137 obj
->pending_read_domains
|= obj
->read_domains
;
3139 obj_priv
->dirty
= 1;
3142 * Flush the current write domain if
3143 * the new read domains don't match. Invalidate
3144 * any read domains which differ from the old
3147 if (obj
->write_domain
&&
3148 obj
->write_domain
!= obj
->pending_read_domains
) {
3149 flush_domains
|= obj
->write_domain
;
3150 invalidate_domains
|=
3151 obj
->pending_read_domains
& ~obj
->write_domain
;
3154 * Invalidate any read caches which may have
3155 * stale data. That is, any new read domains.
3157 invalidate_domains
|= obj
->pending_read_domains
& ~obj
->read_domains
;
3158 if ((flush_domains
| invalidate_domains
) & I915_GEM_DOMAIN_CPU
)
3159 i915_gem_clflush_object(obj
);
3161 old_read_domains
= obj
->read_domains
;
3163 /* The actual obj->write_domain will be updated with
3164 * pending_write_domain after we emit the accumulated flush for all
3165 * of our domain changes in execbuffers (which clears objects'
3166 * write_domains). So if we have a current write domain that we
3167 * aren't changing, set pending_write_domain to that.
3169 if (flush_domains
== 0 && obj
->pending_write_domain
== 0)
3170 obj
->pending_write_domain
= obj
->write_domain
;
3171 obj
->read_domains
= obj
->pending_read_domains
;
3173 dev
->invalidate_domains
|= invalidate_domains
;
3174 dev
->flush_domains
|= flush_domains
;
3176 dev_priv
->mm
.flush_rings
|= obj_priv
->ring
->id
;
3178 trace_i915_gem_object_change_domain(obj
,
3184 * Moves the object from a partially CPU read to a full one.
3186 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3187 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3190 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object
*obj
)
3192 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3194 if (!obj_priv
->page_cpu_valid
)
3197 /* If we're partially in the CPU read domain, finish moving it in.
3199 if (obj
->read_domains
& I915_GEM_DOMAIN_CPU
) {
3202 for (i
= 0; i
<= (obj
->size
- 1) / PAGE_SIZE
; i
++) {
3203 if (obj_priv
->page_cpu_valid
[i
])
3205 drm_clflush_pages(obj_priv
->pages
+ i
, 1);
3209 /* Free the page_cpu_valid mappings which are now stale, whether
3210 * or not we've got I915_GEM_DOMAIN_CPU.
3212 kfree(obj_priv
->page_cpu_valid
);
3213 obj_priv
->page_cpu_valid
= NULL
;
3217 * Set the CPU read domain on a range of the object.
3219 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3220 * not entirely valid. The page_cpu_valid member of the object flags which
3221 * pages have been flushed, and will be respected by
3222 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3223 * of the whole object.
3225 * This function returns when the move is complete, including waiting on
3229 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object
*obj
,
3230 uint64_t offset
, uint64_t size
)
3232 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3233 uint32_t old_read_domains
;
3236 if (offset
== 0 && size
== obj
->size
)
3237 return i915_gem_object_set_to_cpu_domain(obj
, 0);
3239 ret
= i915_gem_object_flush_gpu_write_domain(obj
, false);
3242 i915_gem_object_flush_gtt_write_domain(obj
);
3244 /* If we're already fully in the CPU read domain, we're done. */
3245 if (obj_priv
->page_cpu_valid
== NULL
&&
3246 (obj
->read_domains
& I915_GEM_DOMAIN_CPU
) != 0)
3249 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3250 * newly adding I915_GEM_DOMAIN_CPU
3252 if (obj_priv
->page_cpu_valid
== NULL
) {
3253 obj_priv
->page_cpu_valid
= kzalloc(obj
->size
/ PAGE_SIZE
,
3255 if (obj_priv
->page_cpu_valid
== NULL
)
3257 } else if ((obj
->read_domains
& I915_GEM_DOMAIN_CPU
) == 0)
3258 memset(obj_priv
->page_cpu_valid
, 0, obj
->size
/ PAGE_SIZE
);
3260 /* Flush the cache on any pages that are still invalid from the CPU's
3263 for (i
= offset
/ PAGE_SIZE
; i
<= (offset
+ size
- 1) / PAGE_SIZE
;
3265 if (obj_priv
->page_cpu_valid
[i
])
3268 drm_clflush_pages(obj_priv
->pages
+ i
, 1);
3270 obj_priv
->page_cpu_valid
[i
] = 1;
3273 /* It should now be out of any other write domains, and we can update
3274 * the domain values for our changes.
3276 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
3278 old_read_domains
= obj
->read_domains
;
3279 obj
->read_domains
|= I915_GEM_DOMAIN_CPU
;
3281 trace_i915_gem_object_change_domain(obj
,
3289 * Pin an object to the GTT and evaluate the relocations landing in it.
3292 i915_gem_object_pin_and_relocate(struct drm_gem_object
*obj
,
3293 struct drm_file
*file_priv
,
3294 struct drm_i915_gem_exec_object2
*entry
)
3296 struct drm_device
*dev
= obj
->dev
;
3297 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3298 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3299 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
3301 void __iomem
*reloc_page
;
3304 need_fence
= entry
->flags
& EXEC_OBJECT_NEEDS_FENCE
&&
3305 obj_priv
->tiling_mode
!= I915_TILING_NONE
;
3307 /* Check fence reg constraints and rebind if necessary */
3309 !i915_gem_object_fence_offset_ok(obj
,
3310 obj_priv
->tiling_mode
)) {
3311 ret
= i915_gem_object_unbind(obj
);
3316 /* Choose the GTT offset for our buffer and put it there. */
3317 ret
= i915_gem_object_pin(obj
, (uint32_t) entry
->alignment
);
3322 * Pre-965 chips need a fence register set up in order to
3323 * properly handle blits to/from tiled surfaces.
3326 ret
= i915_gem_object_get_fence_reg(obj
, true);
3328 i915_gem_object_unpin(obj
);
3332 dev_priv
->fence_regs
[obj_priv
->fence_reg
].gpu
= true;
3335 entry
->offset
= obj_priv
->gtt_offset
;
3337 /* Apply the relocations, using the GTT aperture to avoid cache
3338 * flushing requirements.
3340 user_relocs
= (void __user
*)(uintptr_t)entry
->relocs_ptr
;
3341 for (i
= 0; i
< entry
->relocation_count
; i
++) {
3342 struct drm_i915_gem_relocation_entry reloc
;
3343 struct drm_gem_object
*target_obj
;
3344 struct drm_i915_gem_object
*target_obj_priv
;
3345 uint32_t reloc_val
, reloc_offset
;
3346 uint32_t __iomem
*reloc_entry
;
3348 ret
= __copy_from_user_inatomic(&reloc
,
3352 i915_gem_object_unpin(obj
);
3356 target_obj
= drm_gem_object_lookup(obj
->dev
, file_priv
,
3357 reloc
.target_handle
);
3358 if (target_obj
== NULL
) {
3359 i915_gem_object_unpin(obj
);
3362 target_obj_priv
= to_intel_bo(target_obj
);
3365 DRM_INFO("%s: obj %p offset %08x target %d "
3366 "read %08x write %08x gtt %08x "
3367 "presumed %08x delta %08x\n",
3371 (int) reloc
.target_handle
,
3372 (int) reloc
.read_domains
,
3373 (int) reloc
.write_domain
,
3374 (int) target_obj_priv
->gtt_offset
,
3375 (int) reloc
.presumed_offset
,
3379 /* The target buffer should have appeared before us in the
3380 * exec_object list, so it should have a GTT space bound by now.
3382 if (target_obj_priv
->gtt_space
== NULL
) {
3383 DRM_ERROR("No GTT space found for object %d\n",
3384 reloc
.target_handle
);
3385 drm_gem_object_unreference(target_obj
);
3386 i915_gem_object_unpin(obj
);
3390 /* Validate that the target is in a valid r/w GPU domain */
3391 if (reloc
.write_domain
& (reloc
.write_domain
- 1)) {
3392 DRM_ERROR("reloc with multiple write domains: "
3393 "obj %p target %d offset %d "
3394 "read %08x write %08x",
3395 obj
, reloc
.target_handle
,
3398 reloc
.write_domain
);
3399 drm_gem_object_unreference(target_obj
);
3400 i915_gem_object_unpin(obj
);
3403 if (reloc
.write_domain
& I915_GEM_DOMAIN_CPU
||
3404 reloc
.read_domains
& I915_GEM_DOMAIN_CPU
) {
3405 DRM_ERROR("reloc with read/write CPU domains: "
3406 "obj %p target %d offset %d "
3407 "read %08x write %08x",
3408 obj
, reloc
.target_handle
,
3411 reloc
.write_domain
);
3412 drm_gem_object_unreference(target_obj
);
3413 i915_gem_object_unpin(obj
);
3416 if (reloc
.write_domain
&& target_obj
->pending_write_domain
&&
3417 reloc
.write_domain
!= target_obj
->pending_write_domain
) {
3418 DRM_ERROR("Write domain conflict: "
3419 "obj %p target %d offset %d "
3420 "new %08x old %08x\n",
3421 obj
, reloc
.target_handle
,
3424 target_obj
->pending_write_domain
);
3425 drm_gem_object_unreference(target_obj
);
3426 i915_gem_object_unpin(obj
);
3430 target_obj
->pending_read_domains
|= reloc
.read_domains
;
3431 target_obj
->pending_write_domain
|= reloc
.write_domain
;
3433 /* If the relocation already has the right value in it, no
3434 * more work needs to be done.
3436 if (target_obj_priv
->gtt_offset
== reloc
.presumed_offset
) {
3437 drm_gem_object_unreference(target_obj
);
3441 /* Check that the relocation address is valid... */
3442 if (reloc
.offset
> obj
->size
- 4) {
3443 DRM_ERROR("Relocation beyond object bounds: "
3444 "obj %p target %d offset %d size %d.\n",
3445 obj
, reloc
.target_handle
,
3446 (int) reloc
.offset
, (int) obj
->size
);
3447 drm_gem_object_unreference(target_obj
);
3448 i915_gem_object_unpin(obj
);
3451 if (reloc
.offset
& 3) {
3452 DRM_ERROR("Relocation not 4-byte aligned: "
3453 "obj %p target %d offset %d.\n",
3454 obj
, reloc
.target_handle
,
3455 (int) reloc
.offset
);
3456 drm_gem_object_unreference(target_obj
);
3457 i915_gem_object_unpin(obj
);
3461 /* and points to somewhere within the target object. */
3462 if (reloc
.delta
>= target_obj
->size
) {
3463 DRM_ERROR("Relocation beyond target object bounds: "
3464 "obj %p target %d delta %d size %d.\n",
3465 obj
, reloc
.target_handle
,
3466 (int) reloc
.delta
, (int) target_obj
->size
);
3467 drm_gem_object_unreference(target_obj
);
3468 i915_gem_object_unpin(obj
);
3472 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
3474 drm_gem_object_unreference(target_obj
);
3475 i915_gem_object_unpin(obj
);
3479 /* Map the page containing the relocation we're going to
3482 reloc_offset
= obj_priv
->gtt_offset
+ reloc
.offset
;
3483 reloc_page
= io_mapping_map_atomic_wc(dev_priv
->mm
.gtt_mapping
,
3487 reloc_entry
= (uint32_t __iomem
*)(reloc_page
+
3488 (reloc_offset
& (PAGE_SIZE
- 1)));
3489 reloc_val
= target_obj_priv
->gtt_offset
+ reloc
.delta
;
3491 writel(reloc_val
, reloc_entry
);
3492 io_mapping_unmap_atomic(reloc_page
, KM_USER0
);
3494 drm_gem_object_unreference(target_obj
);
3500 /* Throttle our rendering by waiting until the ring has completed our requests
3501 * emitted over 20 msec ago.
3503 * Note that if we were to use the current jiffies each time around the loop,
3504 * we wouldn't escape the function with any frames outstanding if the time to
3505 * render a frame was over 20ms.
3507 * This should get us reasonable parallelism between CPU and GPU but also
3508 * relatively low latency when blocking on a particular request to finish.
3511 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file
)
3513 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3514 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
3515 unsigned long recent_enough
= jiffies
- msecs_to_jiffies(20);
3516 struct drm_i915_gem_request
*request
;
3517 struct intel_ring_buffer
*ring
= NULL
;
3521 spin_lock(&file_priv
->mm
.lock
);
3522 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_list
) {
3523 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
3526 ring
= request
->ring
;
3527 seqno
= request
->seqno
;
3529 spin_unlock(&file_priv
->mm
.lock
);
3535 if (!i915_seqno_passed(ring
->get_seqno(dev
, ring
), seqno
)) {
3536 /* And wait for the seqno passing without holding any locks and
3537 * causing extra latency for others. This is safe as the irq
3538 * generation is designed to be run atomically and so is
3541 ring
->user_irq_get(dev
, ring
);
3542 ret
= wait_event_interruptible(ring
->irq_queue
,
3543 i915_seqno_passed(ring
->get_seqno(dev
, ring
), seqno
)
3544 || atomic_read(&dev_priv
->mm
.wedged
));
3545 ring
->user_irq_put(dev
, ring
);
3547 if (ret
== 0 && atomic_read(&dev_priv
->mm
.wedged
))
3552 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, 0);
3558 i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2
*exec
,
3559 uint64_t exec_offset
)
3561 uint32_t exec_start
, exec_len
;
3563 exec_start
= (uint32_t) exec_offset
+ exec
->batch_start_offset
;
3564 exec_len
= (uint32_t) exec
->batch_len
;
3566 if ((exec_start
| exec_len
) & 0x7)
3576 validate_exec_list(struct drm_i915_gem_exec_object2
*exec
,
3581 for (i
= 0; i
< count
; i
++) {
3582 char __user
*ptr
= (char __user
*)(uintptr_t)exec
[i
].relocs_ptr
;
3583 size_t length
= exec
[i
].relocation_count
* sizeof(struct drm_i915_gem_relocation_entry
);
3585 if (!access_ok(VERIFY_READ
, ptr
, length
))
3588 if (fault_in_pages_readable(ptr
, length
))
3596 i915_gem_do_execbuffer(struct drm_device
*dev
, void *data
,
3597 struct drm_file
*file_priv
,
3598 struct drm_i915_gem_execbuffer2
*args
,
3599 struct drm_i915_gem_exec_object2
*exec_list
)
3601 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3602 struct drm_gem_object
**object_list
= NULL
;
3603 struct drm_gem_object
*batch_obj
;
3604 struct drm_i915_gem_object
*obj_priv
;
3605 struct drm_clip_rect
*cliprects
= NULL
;
3606 struct drm_i915_gem_request
*request
= NULL
;
3607 int ret
, i
, pinned
= 0;
3608 uint64_t exec_offset
;
3609 int pin_tries
, flips
;
3611 struct intel_ring_buffer
*ring
= NULL
;
3613 ret
= i915_gem_check_is_wedged(dev
);
3617 ret
= validate_exec_list(exec_list
, args
->buffer_count
);
3622 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3623 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
3625 if (args
->flags
& I915_EXEC_BSD
) {
3626 if (!HAS_BSD(dev
)) {
3627 DRM_ERROR("execbuf with wrong flag\n");
3630 ring
= &dev_priv
->bsd_ring
;
3632 ring
= &dev_priv
->render_ring
;
3635 if (args
->buffer_count
< 1) {
3636 DRM_ERROR("execbuf with %d buffers\n", args
->buffer_count
);
3639 object_list
= drm_malloc_ab(sizeof(*object_list
), args
->buffer_count
);
3640 if (object_list
== NULL
) {
3641 DRM_ERROR("Failed to allocate object list for %d buffers\n",
3642 args
->buffer_count
);
3647 if (args
->num_cliprects
!= 0) {
3648 cliprects
= kcalloc(args
->num_cliprects
, sizeof(*cliprects
),
3650 if (cliprects
== NULL
) {
3655 ret
= copy_from_user(cliprects
,
3656 (struct drm_clip_rect __user
*)
3657 (uintptr_t) args
->cliprects_ptr
,
3658 sizeof(*cliprects
) * args
->num_cliprects
);
3660 DRM_ERROR("copy %d cliprects failed: %d\n",
3661 args
->num_cliprects
, ret
);
3667 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
3668 if (request
== NULL
) {
3673 ret
= i915_mutex_lock_interruptible(dev
);
3677 if (dev_priv
->mm
.suspended
) {
3678 mutex_unlock(&dev
->struct_mutex
);
3683 /* Look up object handles */
3684 for (i
= 0; i
< args
->buffer_count
; i
++) {
3685 object_list
[i
] = drm_gem_object_lookup(dev
, file_priv
,
3686 exec_list
[i
].handle
);
3687 if (object_list
[i
] == NULL
) {
3688 DRM_ERROR("Invalid object handle %d at index %d\n",
3689 exec_list
[i
].handle
, i
);
3690 /* prevent error path from reading uninitialized data */
3691 args
->buffer_count
= i
+ 1;
3696 obj_priv
= to_intel_bo(object_list
[i
]);
3697 if (obj_priv
->in_execbuffer
) {
3698 DRM_ERROR("Object %p appears more than once in object list\n",
3700 /* prevent error path from reading uninitialized data */
3701 args
->buffer_count
= i
+ 1;
3705 obj_priv
->in_execbuffer
= true;
3708 /* Pin and relocate */
3709 for (pin_tries
= 0; ; pin_tries
++) {
3712 for (i
= 0; i
< args
->buffer_count
; i
++) {
3713 object_list
[i
]->pending_read_domains
= 0;
3714 object_list
[i
]->pending_write_domain
= 0;
3715 ret
= i915_gem_object_pin_and_relocate(object_list
[i
],
3726 /* error other than GTT full, or we've already tried again */
3727 if (ret
!= -ENOSPC
|| pin_tries
>= 1) {
3728 if (ret
!= -ERESTARTSYS
) {
3729 unsigned long long total_size
= 0;
3731 for (i
= 0; i
< args
->buffer_count
; i
++) {
3732 obj_priv
= to_intel_bo(object_list
[i
]);
3734 total_size
+= object_list
[i
]->size
;
3736 exec_list
[i
].flags
& EXEC_OBJECT_NEEDS_FENCE
&&
3737 obj_priv
->tiling_mode
!= I915_TILING_NONE
;
3739 DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes, %d fences: %d\n",
3740 pinned
+1, args
->buffer_count
,
3741 total_size
, num_fences
,
3743 DRM_ERROR("%u objects [%u pinned, %u GTT], "
3744 "%zu object bytes [%zu pinned], "
3745 "%zu /%zu gtt bytes\n",
3746 dev_priv
->mm
.object_count
,
3747 dev_priv
->mm
.pin_count
,
3748 dev_priv
->mm
.gtt_count
,
3749 dev_priv
->mm
.object_memory
,
3750 dev_priv
->mm
.pin_memory
,
3751 dev_priv
->mm
.gtt_memory
,
3752 dev_priv
->mm
.gtt_total
);
3757 /* unpin all of our buffers */
3758 for (i
= 0; i
< pinned
; i
++)
3759 i915_gem_object_unpin(object_list
[i
]);
3762 /* evict everyone we can from the aperture */
3763 ret
= i915_gem_evict_everything(dev
);
3764 if (ret
&& ret
!= -ENOSPC
)
3768 /* Set the pending read domains for the batch buffer to COMMAND */
3769 batch_obj
= object_list
[args
->buffer_count
-1];
3770 if (batch_obj
->pending_write_domain
) {
3771 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3775 batch_obj
->pending_read_domains
|= I915_GEM_DOMAIN_COMMAND
;
3777 /* Sanity check the batch buffer, prior to moving objects */
3778 exec_offset
= exec_list
[args
->buffer_count
- 1].offset
;
3779 ret
= i915_gem_check_execbuffer (args
, exec_offset
);
3781 DRM_ERROR("execbuf with invalid offset/length\n");
3785 /* Zero the global flush/invalidate flags. These
3786 * will be modified as new domains are computed
3789 dev
->invalidate_domains
= 0;
3790 dev
->flush_domains
= 0;
3791 dev_priv
->mm
.flush_rings
= 0;
3793 for (i
= 0; i
< args
->buffer_count
; i
++) {
3794 struct drm_gem_object
*obj
= object_list
[i
];
3796 /* Compute new gpu domains and update invalidate/flush */
3797 i915_gem_object_set_to_gpu_domain(obj
);
3800 if (dev
->invalidate_domains
| dev
->flush_domains
) {
3802 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3804 dev
->invalidate_domains
,
3805 dev
->flush_domains
);
3807 i915_gem_flush(dev
, file_priv
,
3808 dev
->invalidate_domains
,
3810 dev_priv
->mm
.flush_rings
);
3813 for (i
= 0; i
< args
->buffer_count
; i
++) {
3814 struct drm_gem_object
*obj
= object_list
[i
];
3815 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3816 uint32_t old_write_domain
= obj
->write_domain
;
3818 obj
->write_domain
= obj
->pending_write_domain
;
3819 if (obj
->write_domain
)
3820 list_move_tail(&obj_priv
->gpu_write_list
,
3821 &dev_priv
->mm
.gpu_write_list
);
3823 trace_i915_gem_object_change_domain(obj
,
3829 for (i
= 0; i
< args
->buffer_count
; i
++) {
3830 i915_gem_object_check_coherency(object_list
[i
],
3831 exec_list
[i
].handle
);
3836 i915_gem_dump_object(batch_obj
,
3842 /* Check for any pending flips. As we only maintain a flip queue depth
3843 * of 1, we can simply insert a WAIT for the next display flip prior
3844 * to executing the batch and avoid stalling the CPU.
3847 for (i
= 0; i
< args
->buffer_count
; i
++) {
3848 if (object_list
[i
]->write_domain
)
3849 flips
|= atomic_read(&to_intel_bo(object_list
[i
])->pending_flip
);
3852 int plane
, flip_mask
;
3854 for (plane
= 0; flips
>> plane
; plane
++) {
3855 if (((flips
>> plane
) & 1) == 0)
3859 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
3861 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
3863 intel_ring_begin(dev
, ring
, 2);
3864 intel_ring_emit(dev
, ring
,
3865 MI_WAIT_FOR_EVENT
| flip_mask
);
3866 intel_ring_emit(dev
, ring
, MI_NOOP
);
3867 intel_ring_advance(dev
, ring
);
3871 /* Exec the batchbuffer */
3872 ret
= ring
->dispatch_gem_execbuffer(dev
, ring
, args
,
3873 cliprects
, exec_offset
);
3875 DRM_ERROR("dispatch failed %d\n", ret
);
3880 * Ensure that the commands in the batch buffer are
3881 * finished before the interrupt fires
3883 i915_retire_commands(dev
, ring
);
3885 for (i
= 0; i
< args
->buffer_count
; i
++) {
3886 struct drm_gem_object
*obj
= object_list
[i
];
3887 obj_priv
= to_intel_bo(obj
);
3889 i915_gem_object_move_to_active(obj
, ring
);
3892 i915_add_request(dev
, file_priv
, request
, ring
);
3896 for (i
= 0; i
< pinned
; i
++)
3897 i915_gem_object_unpin(object_list
[i
]);
3899 for (i
= 0; i
< args
->buffer_count
; i
++) {
3900 if (object_list
[i
]) {
3901 obj_priv
= to_intel_bo(object_list
[i
]);
3902 obj_priv
->in_execbuffer
= false;
3904 drm_gem_object_unreference(object_list
[i
]);
3907 mutex_unlock(&dev
->struct_mutex
);
3910 drm_free_large(object_list
);
3918 * Legacy execbuffer just creates an exec2 list from the original exec object
3919 * list array and passes it to the real function.
3922 i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
3923 struct drm_file
*file_priv
)
3925 struct drm_i915_gem_execbuffer
*args
= data
;
3926 struct drm_i915_gem_execbuffer2 exec2
;
3927 struct drm_i915_gem_exec_object
*exec_list
= NULL
;
3928 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
3932 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3933 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
3936 if (args
->buffer_count
< 1) {
3937 DRM_ERROR("execbuf with %d buffers\n", args
->buffer_count
);
3941 /* Copy in the exec list from userland */
3942 exec_list
= drm_malloc_ab(sizeof(*exec_list
), args
->buffer_count
);
3943 exec2_list
= drm_malloc_ab(sizeof(*exec2_list
), args
->buffer_count
);
3944 if (exec_list
== NULL
|| exec2_list
== NULL
) {
3945 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
3946 args
->buffer_count
);
3947 drm_free_large(exec_list
);
3948 drm_free_large(exec2_list
);
3951 ret
= copy_from_user(exec_list
,
3952 (struct drm_i915_relocation_entry __user
*)
3953 (uintptr_t) args
->buffers_ptr
,
3954 sizeof(*exec_list
) * args
->buffer_count
);
3956 DRM_ERROR("copy %d exec entries failed %d\n",
3957 args
->buffer_count
, ret
);
3958 drm_free_large(exec_list
);
3959 drm_free_large(exec2_list
);
3963 for (i
= 0; i
< args
->buffer_count
; i
++) {
3964 exec2_list
[i
].handle
= exec_list
[i
].handle
;
3965 exec2_list
[i
].relocation_count
= exec_list
[i
].relocation_count
;
3966 exec2_list
[i
].relocs_ptr
= exec_list
[i
].relocs_ptr
;
3967 exec2_list
[i
].alignment
= exec_list
[i
].alignment
;
3968 exec2_list
[i
].offset
= exec_list
[i
].offset
;
3969 if (INTEL_INFO(dev
)->gen
< 4)
3970 exec2_list
[i
].flags
= EXEC_OBJECT_NEEDS_FENCE
;
3972 exec2_list
[i
].flags
= 0;
3975 exec2
.buffers_ptr
= args
->buffers_ptr
;
3976 exec2
.buffer_count
= args
->buffer_count
;
3977 exec2
.batch_start_offset
= args
->batch_start_offset
;
3978 exec2
.batch_len
= args
->batch_len
;
3979 exec2
.DR1
= args
->DR1
;
3980 exec2
.DR4
= args
->DR4
;
3981 exec2
.num_cliprects
= args
->num_cliprects
;
3982 exec2
.cliprects_ptr
= args
->cliprects_ptr
;
3983 exec2
.flags
= I915_EXEC_RENDER
;
3985 ret
= i915_gem_do_execbuffer(dev
, data
, file_priv
, &exec2
, exec2_list
);
3987 /* Copy the new buffer offsets back to the user's exec list. */
3988 for (i
= 0; i
< args
->buffer_count
; i
++)
3989 exec_list
[i
].offset
= exec2_list
[i
].offset
;
3990 /* ... and back out to userspace */
3991 ret
= copy_to_user((struct drm_i915_relocation_entry __user
*)
3992 (uintptr_t) args
->buffers_ptr
,
3994 sizeof(*exec_list
) * args
->buffer_count
);
3997 DRM_ERROR("failed to copy %d exec entries "
3998 "back to user (%d)\n",
3999 args
->buffer_count
, ret
);
4003 drm_free_large(exec_list
);
4004 drm_free_large(exec2_list
);
4009 i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
4010 struct drm_file
*file_priv
)
4012 struct drm_i915_gem_execbuffer2
*args
= data
;
4013 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
4017 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
4018 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
4021 if (args
->buffer_count
< 1) {
4022 DRM_ERROR("execbuf2 with %d buffers\n", args
->buffer_count
);
4026 exec2_list
= drm_malloc_ab(sizeof(*exec2_list
), args
->buffer_count
);
4027 if (exec2_list
== NULL
) {
4028 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4029 args
->buffer_count
);
4032 ret
= copy_from_user(exec2_list
,
4033 (struct drm_i915_relocation_entry __user
*)
4034 (uintptr_t) args
->buffers_ptr
,
4035 sizeof(*exec2_list
) * args
->buffer_count
);
4037 DRM_ERROR("copy %d exec entries failed %d\n",
4038 args
->buffer_count
, ret
);
4039 drm_free_large(exec2_list
);
4043 ret
= i915_gem_do_execbuffer(dev
, data
, file_priv
, args
, exec2_list
);
4045 /* Copy the new buffer offsets back to the user's exec list. */
4046 ret
= copy_to_user((struct drm_i915_relocation_entry __user
*)
4047 (uintptr_t) args
->buffers_ptr
,
4049 sizeof(*exec2_list
) * args
->buffer_count
);
4052 DRM_ERROR("failed to copy %d exec entries "
4053 "back to user (%d)\n",
4054 args
->buffer_count
, ret
);
4058 drm_free_large(exec2_list
);
4063 i915_gem_object_pin(struct drm_gem_object
*obj
, uint32_t alignment
)
4065 struct drm_device
*dev
= obj
->dev
;
4066 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4067 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4070 BUG_ON(obj_priv
->pin_count
== DRM_I915_GEM_OBJECT_MAX_PIN_COUNT
);
4071 WARN_ON(i915_verify_lists(dev
));
4073 if (obj_priv
->gtt_space
!= NULL
) {
4075 alignment
= i915_gem_get_gtt_alignment(obj
);
4076 if (obj_priv
->gtt_offset
& (alignment
- 1)) {
4077 WARN(obj_priv
->pin_count
,
4078 "bo is already pinned with incorrect alignment:"
4079 " offset=%x, req.alignment=%x\n",
4080 obj_priv
->gtt_offset
, alignment
);
4081 ret
= i915_gem_object_unbind(obj
);
4087 if (obj_priv
->gtt_space
== NULL
) {
4088 ret
= i915_gem_object_bind_to_gtt(obj
, alignment
);
4093 obj_priv
->pin_count
++;
4095 /* If the object is not active and not pending a flush,
4096 * remove it from the inactive list
4098 if (obj_priv
->pin_count
== 1) {
4099 i915_gem_info_add_pin(dev_priv
, obj
->size
);
4100 if (!obj_priv
->active
)
4101 list_move_tail(&obj_priv
->list
,
4102 &dev_priv
->mm
.pinned_list
);
4105 WARN_ON(i915_verify_lists(dev
));
4110 i915_gem_object_unpin(struct drm_gem_object
*obj
)
4112 struct drm_device
*dev
= obj
->dev
;
4113 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4114 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4116 WARN_ON(i915_verify_lists(dev
));
4117 obj_priv
->pin_count
--;
4118 BUG_ON(obj_priv
->pin_count
< 0);
4119 BUG_ON(obj_priv
->gtt_space
== NULL
);
4121 /* If the object is no longer pinned, and is
4122 * neither active nor being flushed, then stick it on
4125 if (obj_priv
->pin_count
== 0) {
4126 if (!obj_priv
->active
)
4127 list_move_tail(&obj_priv
->list
,
4128 &dev_priv
->mm
.inactive_list
);
4129 i915_gem_info_remove_pin(dev_priv
, obj
->size
);
4131 WARN_ON(i915_verify_lists(dev
));
4135 i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
4136 struct drm_file
*file_priv
)
4138 struct drm_i915_gem_pin
*args
= data
;
4139 struct drm_gem_object
*obj
;
4140 struct drm_i915_gem_object
*obj_priv
;
4143 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4145 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
4149 obj_priv
= to_intel_bo(obj
);
4151 ret
= i915_mutex_lock_interruptible(dev
);
4153 drm_gem_object_unreference_unlocked(obj
);
4157 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
4158 DRM_ERROR("Attempting to pin a purgeable buffer\n");
4159 drm_gem_object_unreference(obj
);
4160 mutex_unlock(&dev
->struct_mutex
);
4164 if (obj_priv
->pin_filp
!= NULL
&& obj_priv
->pin_filp
!= file_priv
) {
4165 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
4167 drm_gem_object_unreference(obj
);
4168 mutex_unlock(&dev
->struct_mutex
);
4172 obj_priv
->user_pin_count
++;
4173 obj_priv
->pin_filp
= file_priv
;
4174 if (obj_priv
->user_pin_count
== 1) {
4175 ret
= i915_gem_object_pin(obj
, args
->alignment
);
4177 drm_gem_object_unreference(obj
);
4178 mutex_unlock(&dev
->struct_mutex
);
4183 /* XXX - flush the CPU caches for pinned objects
4184 * as the X server doesn't manage domains yet
4186 i915_gem_object_flush_cpu_write_domain(obj
);
4187 args
->offset
= obj_priv
->gtt_offset
;
4188 drm_gem_object_unreference(obj
);
4189 mutex_unlock(&dev
->struct_mutex
);
4195 i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
4196 struct drm_file
*file_priv
)
4198 struct drm_i915_gem_pin
*args
= data
;
4199 struct drm_gem_object
*obj
;
4200 struct drm_i915_gem_object
*obj_priv
;
4203 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4205 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
4210 obj_priv
= to_intel_bo(obj
);
4212 ret
= i915_mutex_lock_interruptible(dev
);
4214 drm_gem_object_unreference_unlocked(obj
);
4218 if (obj_priv
->pin_filp
!= file_priv
) {
4219 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4221 drm_gem_object_unreference(obj
);
4222 mutex_unlock(&dev
->struct_mutex
);
4225 obj_priv
->user_pin_count
--;
4226 if (obj_priv
->user_pin_count
== 0) {
4227 obj_priv
->pin_filp
= NULL
;
4228 i915_gem_object_unpin(obj
);
4231 drm_gem_object_unreference(obj
);
4232 mutex_unlock(&dev
->struct_mutex
);
4237 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
4238 struct drm_file
*file_priv
)
4240 struct drm_i915_gem_busy
*args
= data
;
4241 struct drm_gem_object
*obj
;
4242 struct drm_i915_gem_object
*obj_priv
;
4245 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4247 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
4252 ret
= i915_mutex_lock_interruptible(dev
);
4254 drm_gem_object_unreference_unlocked(obj
);
4258 /* Count all active objects as busy, even if they are currently not used
4259 * by the gpu. Users of this interface expect objects to eventually
4260 * become non-busy without any further actions, therefore emit any
4261 * necessary flushes here.
4263 obj_priv
= to_intel_bo(obj
);
4264 args
->busy
= obj_priv
->active
;
4266 /* Unconditionally flush objects, even when the gpu still uses this
4267 * object. Userspace calling this function indicates that it wants to
4268 * use this buffer rather sooner than later, so issuing the required
4269 * flush earlier is beneficial.
4271 if (obj
->write_domain
& I915_GEM_GPU_DOMAINS
)
4272 i915_gem_flush_ring(dev
, file_priv
,
4274 0, obj
->write_domain
);
4276 /* Update the active list for the hardware's current position.
4277 * Otherwise this only updates on a delayed timer or when irqs
4278 * are actually unmasked, and our working set ends up being
4279 * larger than required.
4281 i915_gem_retire_requests_ring(dev
, obj_priv
->ring
);
4283 args
->busy
= obj_priv
->active
;
4286 drm_gem_object_unreference(obj
);
4287 mutex_unlock(&dev
->struct_mutex
);
4292 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
4293 struct drm_file
*file_priv
)
4295 return i915_gem_ring_throttle(dev
, file_priv
);
4299 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
4300 struct drm_file
*file_priv
)
4302 struct drm_i915_gem_madvise
*args
= data
;
4303 struct drm_gem_object
*obj
;
4304 struct drm_i915_gem_object
*obj_priv
;
4307 switch (args
->madv
) {
4308 case I915_MADV_DONTNEED
:
4309 case I915_MADV_WILLNEED
:
4315 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4317 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n",
4321 obj_priv
= to_intel_bo(obj
);
4323 ret
= i915_mutex_lock_interruptible(dev
);
4325 drm_gem_object_unreference_unlocked(obj
);
4329 if (obj_priv
->pin_count
) {
4330 drm_gem_object_unreference(obj
);
4331 mutex_unlock(&dev
->struct_mutex
);
4333 DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n");
4337 if (obj_priv
->madv
!= __I915_MADV_PURGED
)
4338 obj_priv
->madv
= args
->madv
;
4340 /* if the object is no longer bound, discard its backing storage */
4341 if (i915_gem_object_is_purgeable(obj_priv
) &&
4342 obj_priv
->gtt_space
== NULL
)
4343 i915_gem_object_truncate(obj
);
4345 args
->retained
= obj_priv
->madv
!= __I915_MADV_PURGED
;
4347 drm_gem_object_unreference(obj
);
4348 mutex_unlock(&dev
->struct_mutex
);
4353 struct drm_gem_object
* i915_gem_alloc_object(struct drm_device
*dev
,
4356 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4357 struct drm_i915_gem_object
*obj
;
4359 obj
= kzalloc(sizeof(*obj
), GFP_KERNEL
);
4363 if (drm_gem_object_init(dev
, &obj
->base
, size
) != 0) {
4368 i915_gem_info_add_obj(dev_priv
, size
);
4370 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4371 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4373 obj
->agp_type
= AGP_USER_MEMORY
;
4374 obj
->base
.driver_private
= NULL
;
4375 obj
->fence_reg
= I915_FENCE_REG_NONE
;
4376 INIT_LIST_HEAD(&obj
->list
);
4377 INIT_LIST_HEAD(&obj
->gpu_write_list
);
4378 obj
->madv
= I915_MADV_WILLNEED
;
4380 trace_i915_gem_object_create(&obj
->base
);
4385 int i915_gem_init_object(struct drm_gem_object
*obj
)
4392 static void i915_gem_free_object_tail(struct drm_gem_object
*obj
)
4394 struct drm_device
*dev
= obj
->dev
;
4395 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4396 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4399 ret
= i915_gem_object_unbind(obj
);
4400 if (ret
== -ERESTARTSYS
) {
4401 list_move(&obj_priv
->list
,
4402 &dev_priv
->mm
.deferred_free_list
);
4406 if (obj_priv
->mmap_offset
)
4407 i915_gem_free_mmap_offset(obj
);
4409 drm_gem_object_release(obj
);
4410 i915_gem_info_remove_obj(dev_priv
, obj
->size
);
4412 kfree(obj_priv
->page_cpu_valid
);
4413 kfree(obj_priv
->bit_17
);
4417 void i915_gem_free_object(struct drm_gem_object
*obj
)
4419 struct drm_device
*dev
= obj
->dev
;
4420 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4422 trace_i915_gem_object_destroy(obj
);
4424 while (obj_priv
->pin_count
> 0)
4425 i915_gem_object_unpin(obj
);
4427 if (obj_priv
->phys_obj
)
4428 i915_gem_detach_phys_object(dev
, obj
);
4430 i915_gem_free_object_tail(obj
);
4434 i915_gem_idle(struct drm_device
*dev
)
4436 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4439 mutex_lock(&dev
->struct_mutex
);
4441 if (dev_priv
->mm
.suspended
||
4442 (dev_priv
->render_ring
.gem_object
== NULL
) ||
4444 dev_priv
->bsd_ring
.gem_object
== NULL
)) {
4445 mutex_unlock(&dev
->struct_mutex
);
4449 ret
= i915_gpu_idle(dev
);
4451 mutex_unlock(&dev
->struct_mutex
);
4455 /* Under UMS, be paranoid and evict. */
4456 if (!drm_core_check_feature(dev
, DRIVER_MODESET
)) {
4457 ret
= i915_gem_evict_inactive(dev
);
4459 mutex_unlock(&dev
->struct_mutex
);
4464 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4465 * We need to replace this with a semaphore, or something.
4466 * And not confound mm.suspended!
4468 dev_priv
->mm
.suspended
= 1;
4469 del_timer_sync(&dev_priv
->hangcheck_timer
);
4471 i915_kernel_lost_context(dev
);
4472 i915_gem_cleanup_ringbuffer(dev
);
4474 mutex_unlock(&dev
->struct_mutex
);
4476 /* Cancel the retire work handler, which should be idle now. */
4477 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
4483 * 965+ support PIPE_CONTROL commands, which provide finer grained control
4484 * over cache flushing.
4487 i915_gem_init_pipe_control(struct drm_device
*dev
)
4489 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4490 struct drm_gem_object
*obj
;
4491 struct drm_i915_gem_object
*obj_priv
;
4494 obj
= i915_gem_alloc_object(dev
, 4096);
4496 DRM_ERROR("Failed to allocate seqno page\n");
4500 obj_priv
= to_intel_bo(obj
);
4501 obj_priv
->agp_type
= AGP_USER_CACHED_MEMORY
;
4503 ret
= i915_gem_object_pin(obj
, 4096);
4507 dev_priv
->seqno_gfx_addr
= obj_priv
->gtt_offset
;
4508 dev_priv
->seqno_page
= kmap(obj_priv
->pages
[0]);
4509 if (dev_priv
->seqno_page
== NULL
)
4512 dev_priv
->seqno_obj
= obj
;
4513 memset(dev_priv
->seqno_page
, 0, PAGE_SIZE
);
4518 i915_gem_object_unpin(obj
);
4520 drm_gem_object_unreference(obj
);
4527 i915_gem_cleanup_pipe_control(struct drm_device
*dev
)
4529 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4530 struct drm_gem_object
*obj
;
4531 struct drm_i915_gem_object
*obj_priv
;
4533 obj
= dev_priv
->seqno_obj
;
4534 obj_priv
= to_intel_bo(obj
);
4535 kunmap(obj_priv
->pages
[0]);
4536 i915_gem_object_unpin(obj
);
4537 drm_gem_object_unreference(obj
);
4538 dev_priv
->seqno_obj
= NULL
;
4540 dev_priv
->seqno_page
= NULL
;
4544 i915_gem_init_ringbuffer(struct drm_device
*dev
)
4546 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4549 if (HAS_PIPE_CONTROL(dev
)) {
4550 ret
= i915_gem_init_pipe_control(dev
);
4555 ret
= intel_init_render_ring_buffer(dev
);
4557 goto cleanup_pipe_control
;
4560 ret
= intel_init_bsd_ring_buffer(dev
);
4562 goto cleanup_render_ring
;
4565 dev_priv
->next_seqno
= 1;
4569 cleanup_render_ring
:
4570 intel_cleanup_ring_buffer(dev
, &dev_priv
->render_ring
);
4571 cleanup_pipe_control
:
4572 if (HAS_PIPE_CONTROL(dev
))
4573 i915_gem_cleanup_pipe_control(dev
);
4578 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
4580 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4582 intel_cleanup_ring_buffer(dev
, &dev_priv
->render_ring
);
4584 intel_cleanup_ring_buffer(dev
, &dev_priv
->bsd_ring
);
4585 if (HAS_PIPE_CONTROL(dev
))
4586 i915_gem_cleanup_pipe_control(dev
);
4590 i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
4591 struct drm_file
*file_priv
)
4593 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4596 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4599 if (atomic_read(&dev_priv
->mm
.wedged
)) {
4600 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4601 atomic_set(&dev_priv
->mm
.wedged
, 0);
4604 mutex_lock(&dev
->struct_mutex
);
4605 dev_priv
->mm
.suspended
= 0;
4607 ret
= i915_gem_init_ringbuffer(dev
);
4609 mutex_unlock(&dev
->struct_mutex
);
4613 BUG_ON(!list_empty(&dev_priv
->render_ring
.active_list
));
4614 BUG_ON(HAS_BSD(dev
) && !list_empty(&dev_priv
->bsd_ring
.active_list
));
4615 BUG_ON(!list_empty(&dev_priv
->mm
.flushing_list
));
4616 BUG_ON(!list_empty(&dev_priv
->mm
.inactive_list
));
4617 BUG_ON(!list_empty(&dev_priv
->render_ring
.request_list
));
4618 BUG_ON(HAS_BSD(dev
) && !list_empty(&dev_priv
->bsd_ring
.request_list
));
4619 mutex_unlock(&dev
->struct_mutex
);
4621 ret
= drm_irq_install(dev
);
4623 goto cleanup_ringbuffer
;
4628 mutex_lock(&dev
->struct_mutex
);
4629 i915_gem_cleanup_ringbuffer(dev
);
4630 dev_priv
->mm
.suspended
= 1;
4631 mutex_unlock(&dev
->struct_mutex
);
4637 i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
4638 struct drm_file
*file_priv
)
4640 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4643 drm_irq_uninstall(dev
);
4644 return i915_gem_idle(dev
);
4648 i915_gem_lastclose(struct drm_device
*dev
)
4652 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4655 ret
= i915_gem_idle(dev
);
4657 DRM_ERROR("failed to idle hardware: %d\n", ret
);
4661 i915_gem_load(struct drm_device
*dev
)
4664 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4666 INIT_LIST_HEAD(&dev_priv
->mm
.flushing_list
);
4667 INIT_LIST_HEAD(&dev_priv
->mm
.gpu_write_list
);
4668 INIT_LIST_HEAD(&dev_priv
->mm
.inactive_list
);
4669 INIT_LIST_HEAD(&dev_priv
->mm
.pinned_list
);
4670 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
4671 INIT_LIST_HEAD(&dev_priv
->mm
.deferred_free_list
);
4672 INIT_LIST_HEAD(&dev_priv
->render_ring
.active_list
);
4673 INIT_LIST_HEAD(&dev_priv
->render_ring
.request_list
);
4675 INIT_LIST_HEAD(&dev_priv
->bsd_ring
.active_list
);
4676 INIT_LIST_HEAD(&dev_priv
->bsd_ring
.request_list
);
4678 for (i
= 0; i
< 16; i
++)
4679 INIT_LIST_HEAD(&dev_priv
->fence_regs
[i
].lru_list
);
4680 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
4681 i915_gem_retire_work_handler
);
4682 init_completion(&dev_priv
->error_completion
);
4683 spin_lock(&shrink_list_lock
);
4684 list_add(&dev_priv
->mm
.shrink_list
, &shrink_list
);
4685 spin_unlock(&shrink_list_lock
);
4687 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4689 u32 tmp
= I915_READ(MI_ARB_STATE
);
4690 if (!(tmp
& MI_ARB_C3_LP_WRITE_ENABLE
)) {
4691 /* arb state is a masked write, so set bit + bit in mask */
4692 tmp
= MI_ARB_C3_LP_WRITE_ENABLE
| (MI_ARB_C3_LP_WRITE_ENABLE
<< MI_ARB_MASK_SHIFT
);
4693 I915_WRITE(MI_ARB_STATE
, tmp
);
4697 /* Old X drivers will take 0-2 for front, back, depth buffers */
4698 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4699 dev_priv
->fence_reg_start
= 3;
4701 if (INTEL_INFO(dev
)->gen
>= 4 || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4702 dev_priv
->num_fence_regs
= 16;
4704 dev_priv
->num_fence_regs
= 8;
4706 /* Initialize fence registers to zero */
4707 switch (INTEL_INFO(dev
)->gen
) {
4709 for (i
= 0; i
< 16; i
++)
4710 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+ (i
* 8), 0);
4714 for (i
= 0; i
< 16; i
++)
4715 I915_WRITE64(FENCE_REG_965_0
+ (i
* 8), 0);
4718 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4719 for (i
= 0; i
< 8; i
++)
4720 I915_WRITE(FENCE_REG_945_8
+ (i
* 4), 0);
4722 for (i
= 0; i
< 8; i
++)
4723 I915_WRITE(FENCE_REG_830_0
+ (i
* 4), 0);
4726 i915_gem_detect_bit_6_swizzle(dev
);
4727 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
4731 * Create a physically contiguous memory object for this object
4732 * e.g. for cursor + overlay regs
4734 static int i915_gem_init_phys_object(struct drm_device
*dev
,
4735 int id
, int size
, int align
)
4737 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4738 struct drm_i915_gem_phys_object
*phys_obj
;
4741 if (dev_priv
->mm
.phys_objs
[id
- 1] || !size
)
4744 phys_obj
= kzalloc(sizeof(struct drm_i915_gem_phys_object
), GFP_KERNEL
);
4750 phys_obj
->handle
= drm_pci_alloc(dev
, size
, align
);
4751 if (!phys_obj
->handle
) {
4756 set_memory_wc((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4759 dev_priv
->mm
.phys_objs
[id
- 1] = phys_obj
;
4767 static void i915_gem_free_phys_object(struct drm_device
*dev
, int id
)
4769 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4770 struct drm_i915_gem_phys_object
*phys_obj
;
4772 if (!dev_priv
->mm
.phys_objs
[id
- 1])
4775 phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4776 if (phys_obj
->cur_obj
) {
4777 i915_gem_detach_phys_object(dev
, phys_obj
->cur_obj
);
4781 set_memory_wb((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4783 drm_pci_free(dev
, phys_obj
->handle
);
4785 dev_priv
->mm
.phys_objs
[id
- 1] = NULL
;
4788 void i915_gem_free_all_phys_object(struct drm_device
*dev
)
4792 for (i
= I915_GEM_PHYS_CURSOR_0
; i
<= I915_MAX_PHYS_OBJECT
; i
++)
4793 i915_gem_free_phys_object(dev
, i
);
4796 void i915_gem_detach_phys_object(struct drm_device
*dev
,
4797 struct drm_gem_object
*obj
)
4799 struct drm_i915_gem_object
*obj_priv
;
4804 obj_priv
= to_intel_bo(obj
);
4805 if (!obj_priv
->phys_obj
)
4808 ret
= i915_gem_object_get_pages(obj
, 0);
4812 page_count
= obj
->size
/ PAGE_SIZE
;
4814 for (i
= 0; i
< page_count
; i
++) {
4815 char *dst
= kmap_atomic(obj_priv
->pages
[i
], KM_USER0
);
4816 char *src
= obj_priv
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
4818 memcpy(dst
, src
, PAGE_SIZE
);
4819 kunmap_atomic(dst
, KM_USER0
);
4821 drm_clflush_pages(obj_priv
->pages
, page_count
);
4822 drm_agp_chipset_flush(dev
);
4824 i915_gem_object_put_pages(obj
);
4826 obj_priv
->phys_obj
->cur_obj
= NULL
;
4827 obj_priv
->phys_obj
= NULL
;
4831 i915_gem_attach_phys_object(struct drm_device
*dev
,
4832 struct drm_gem_object
*obj
,
4836 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4837 struct drm_i915_gem_object
*obj_priv
;
4842 if (id
> I915_MAX_PHYS_OBJECT
)
4845 obj_priv
= to_intel_bo(obj
);
4847 if (obj_priv
->phys_obj
) {
4848 if (obj_priv
->phys_obj
->id
== id
)
4850 i915_gem_detach_phys_object(dev
, obj
);
4853 /* create a new object */
4854 if (!dev_priv
->mm
.phys_objs
[id
- 1]) {
4855 ret
= i915_gem_init_phys_object(dev
, id
,
4858 DRM_ERROR("failed to init phys object %d size: %zu\n", id
, obj
->size
);
4863 /* bind to the object */
4864 obj_priv
->phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4865 obj_priv
->phys_obj
->cur_obj
= obj
;
4867 ret
= i915_gem_object_get_pages(obj
, 0);
4869 DRM_ERROR("failed to get page list\n");
4873 page_count
= obj
->size
/ PAGE_SIZE
;
4875 for (i
= 0; i
< page_count
; i
++) {
4876 char *src
= kmap_atomic(obj_priv
->pages
[i
], KM_USER0
);
4877 char *dst
= obj_priv
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
4879 memcpy(dst
, src
, PAGE_SIZE
);
4880 kunmap_atomic(src
, KM_USER0
);
4883 i915_gem_object_put_pages(obj
);
4891 i915_gem_phys_pwrite(struct drm_device
*dev
, struct drm_gem_object
*obj
,
4892 struct drm_i915_gem_pwrite
*args
,
4893 struct drm_file
*file_priv
)
4895 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4898 char __user
*user_data
;
4900 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
4901 obj_addr
= obj_priv
->phys_obj
->handle
->vaddr
+ args
->offset
;
4903 DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr
, args
->size
);
4904 ret
= copy_from_user(obj_addr
, user_data
, args
->size
);
4908 drm_agp_chipset_flush(dev
);
4912 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
)
4914 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
4916 /* Clean up our request list when the client is going away, so that
4917 * later retire_requests won't dereference our soon-to-be-gone
4920 spin_lock(&file_priv
->mm
.lock
);
4921 while (!list_empty(&file_priv
->mm
.request_list
)) {
4922 struct drm_i915_gem_request
*request
;
4924 request
= list_first_entry(&file_priv
->mm
.request_list
,
4925 struct drm_i915_gem_request
,
4927 list_del(&request
->client_list
);
4928 request
->file_priv
= NULL
;
4930 spin_unlock(&file_priv
->mm
.lock
);
4934 i915_gpu_is_active(struct drm_device
*dev
)
4936 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4939 lists_empty
= list_empty(&dev_priv
->mm
.flushing_list
) &&
4940 list_empty(&dev_priv
->render_ring
.active_list
);
4942 lists_empty
&= list_empty(&dev_priv
->bsd_ring
.active_list
);
4944 return !lists_empty
;
4948 i915_gem_shrink(struct shrinker
*shrink
, int nr_to_scan
, gfp_t gfp_mask
)
4950 drm_i915_private_t
*dev_priv
, *next_dev
;
4951 struct drm_i915_gem_object
*obj_priv
, *next_obj
;
4953 int would_deadlock
= 1;
4955 /* "fast-path" to count number of available objects */
4956 if (nr_to_scan
== 0) {
4957 spin_lock(&shrink_list_lock
);
4958 list_for_each_entry(dev_priv
, &shrink_list
, mm
.shrink_list
) {
4959 struct drm_device
*dev
= dev_priv
->dev
;
4961 if (mutex_trylock(&dev
->struct_mutex
)) {
4962 list_for_each_entry(obj_priv
,
4963 &dev_priv
->mm
.inactive_list
,
4966 mutex_unlock(&dev
->struct_mutex
);
4969 spin_unlock(&shrink_list_lock
);
4971 return (cnt
/ 100) * sysctl_vfs_cache_pressure
;
4974 spin_lock(&shrink_list_lock
);
4977 /* first scan for clean buffers */
4978 list_for_each_entry_safe(dev_priv
, next_dev
,
4979 &shrink_list
, mm
.shrink_list
) {
4980 struct drm_device
*dev
= dev_priv
->dev
;
4982 if (! mutex_trylock(&dev
->struct_mutex
))
4985 spin_unlock(&shrink_list_lock
);
4986 i915_gem_retire_requests(dev
);
4988 list_for_each_entry_safe(obj_priv
, next_obj
,
4989 &dev_priv
->mm
.inactive_list
,
4991 if (i915_gem_object_is_purgeable(obj_priv
)) {
4992 i915_gem_object_unbind(&obj_priv
->base
);
4993 if (--nr_to_scan
<= 0)
4998 spin_lock(&shrink_list_lock
);
4999 mutex_unlock(&dev
->struct_mutex
);
5003 if (nr_to_scan
<= 0)
5007 /* second pass, evict/count anything still on the inactive list */
5008 list_for_each_entry_safe(dev_priv
, next_dev
,
5009 &shrink_list
, mm
.shrink_list
) {
5010 struct drm_device
*dev
= dev_priv
->dev
;
5012 if (! mutex_trylock(&dev
->struct_mutex
))
5015 spin_unlock(&shrink_list_lock
);
5017 list_for_each_entry_safe(obj_priv
, next_obj
,
5018 &dev_priv
->mm
.inactive_list
,
5020 if (nr_to_scan
> 0) {
5021 i915_gem_object_unbind(&obj_priv
->base
);
5027 spin_lock(&shrink_list_lock
);
5028 mutex_unlock(&dev
->struct_mutex
);
5037 * We are desperate for pages, so as a last resort, wait
5038 * for the GPU to finish and discard whatever we can.
5039 * This has a dramatic impact to reduce the number of
5040 * OOM-killer events whilst running the GPU aggressively.
5042 list_for_each_entry(dev_priv
, &shrink_list
, mm
.shrink_list
) {
5043 struct drm_device
*dev
= dev_priv
->dev
;
5045 if (!mutex_trylock(&dev
->struct_mutex
))
5048 spin_unlock(&shrink_list_lock
);
5050 if (i915_gpu_is_active(dev
)) {
5055 spin_lock(&shrink_list_lock
);
5056 mutex_unlock(&dev
->struct_mutex
);
5063 spin_unlock(&shrink_list_lock
);
5068 return (cnt
/ 100) * sysctl_vfs_cache_pressure
;
5073 static struct shrinker shrinker
= {
5074 .shrink
= i915_gem_shrink
,
5075 .seeks
= DEFAULT_SEEKS
,
5079 i915_gem_shrinker_init(void)
5081 register_shrinker(&shrinker
);
5085 i915_gem_shrinker_exit(void)
5087 unregister_shrinker(&shrinker
);