drivers/staging/et131x/et1310_address_map.h

   1 /*
   2  * Agere Systems Inc.
   3  * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
   4  *
   5  * Copyright © 2005 Agere Systems Inc.
   6  * All rights reserved.
   7  *   http://www.agere.com
   8  *
   9  *------------------------------------------------------------------------------
  10  *
  11  * et1310_address_map.h - Contains the register mapping for the ET1310
  12  *
  13  *------------------------------------------------------------------------------
  14  *
  15  * SOFTWARE LICENSE
  16  *
  17  * This software is provided subject to the following terms and conditions,
  18  * which you should read carefully before using the software.  Using this
  19  * software indicates your acceptance of these terms and conditions.  If you do
  20  * not agree with these terms and conditions, do not use the software.
  21  *
  22  * Copyright © 2005 Agere Systems Inc.
  23  * All rights reserved.
  24  *
  25  * Redistribution and use in source or binary forms, with or without
  26  * modifications, are permitted provided that the following conditions are met:
  27  *
  28  * . Redistributions of source code must retain the above copyright notice, this
  29  *    list of conditions and the following Disclaimer as comments in the code as
  30  *    well as in the documentation and/or other materials provided with the
  31  *    distribution.
  32  *
  33  * . Redistributions in binary form must reproduce the above copyright notice,
  34  *    this list of conditions and the following Disclaimer in the documentation
  35  *    and/or other materials provided with the distribution.
  36  *
  37  * . Neither the name of Agere Systems Inc. nor the names of the contributors
  38  *    may be used to endorse or promote products derived from this software
  39  *    without specific prior written permission.
  40  *
  41  * Disclaimer
  42  *
  43  * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
  44  * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
  45  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  ANY
  46  * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
  47  * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
  48  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  49  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  50  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  51  * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
  52  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  53  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
  54  * DAMAGE.
  55  *
  56  */
  57
  58 #ifndef _ET1310_ADDRESS_MAP_H_
  59 #define _ET1310_ADDRESS_MAP_H_
  60
  61
  62 /* START OF GLOBAL REGISTER ADDRESS MAP */
  63
  64 /*
  65  * 10bit registers
  66  *
  67  * Tx queue start address reg in global address map at address 0x0000
  68  * tx queue end address reg in global address map at address 0x0004
  69  * rx queue start address reg in global address map at address 0x0008
  70  * rx queue end address reg in global address map at address 0x000C
  71  */
  72
  73 /*
  74  * structure for power management control status reg in global address map
  75  * located at address 0x0010
  76  *      jagcore_rx_rdy  bit 9
  77  *      jagcore_tx_rdy  bit 8
  78  *      phy_lped_en     bit 7
  79  *      phy_sw_coma     bit 6
  80  *      rxclk_gate      bit 5
  81  *      txclk_gate      bit 4
  82  *      sysclk_gate     bit 3
  83  *      jagcore_rx_en   bit 2
  84  *      jagcore_tx_en   bit 1
  85  *      gigephy_en      bit 0
  86  */
  87
  88 #define ET_PM_PHY_SW_COMA               0x40
  89 #define ET_PMCSR_INIT                   0x38
  90
  91 /*
  92  * Interrupt status reg at address 0x0018
  93  */
  94
  95 #define ET_INTR_TXDMA_ISR       0x00000008
  96 #define ET_INTR_TXDMA_ERR       0x00000010
  97 #define ET_INTR_RXDMA_XFR_DONE  0x00000020
  98 #define ET_INTR_RXDMA_FB_R0_LOW 0x00000040
  99 #define ET_INTR_RXDMA_FB_R1_LOW 0x00000080
 100 #define ET_INTR_RXDMA_STAT_LOW  0x00000100
 101 #define ET_INTR_RXDMA_ERR       0x00000200
 102 #define ET_INTR_WATCHDOG        0x00004000
 103 #define ET_INTR_WOL             0x00008000
 104 #define ET_INTR_PHY             0x00010000
 105 #define ET_INTR_TXMAC           0x00020000
 106 #define ET_INTR_RXMAC           0x00040000
 107 #define ET_INTR_MAC_STAT        0x00080000
 108 #define ET_INTR_SLV_TIMEOUT     0x00100000
 109
 110 /*
 111  * Interrupt mask register at address 0x001C
 112  * Interrupt alias clear mask reg at address 0x0020
 113  * Interrupt status alias reg at address 0x0024
 114  *
 115  * Same masks as above
 116  */
 117
 118 /*
 119  * Software reset reg at address 0x0028
 120  * 0:   txdma_sw_reset
 121  * 1:   rxdma_sw_reset
 122  * 2:   txmac_sw_reset
 123  * 3:   rxmac_sw_reset
 124  * 4:   mac_sw_reset
 125  * 5:   mac_stat_sw_reset
 126  * 6:   mmc_sw_reset
 127  *31:   selfclr_disable
 128  */
 129
 130 /*
 131  * SLV Timer reg at address 0x002C (low 24 bits)
 132  */
 133
 134 /*
 135  * MSI Configuration reg at address 0x0030
 136  */
 137
 138 #define ET_MSI_VECTOR   0x0000001F
 139 #define ET_MSI_TC       0x00070000
 140
 141 /*
 142  * Loopback reg located at address 0x0034
 143  */
 144
 145 #define ET_LOOP_MAC     0x00000001
 146 #define ET_LOOP_DMA     0x00000002
 147
 148 /*
 149  * GLOBAL Module of JAGCore Address Mapping
 150  * Located at address 0x0000
 151  */
 152 typedef struct _GLOBAL_t {                      /* Location: */
 153         u32 txq_start_addr;                     /*  0x0000 */
 154         u32 txq_end_addr;                       /*  0x0004 */
 155         u32 rxq_start_addr;                     /*  0x0008 */
 156         u32 rxq_end_addr;                       /*  0x000C */
 157         u32 pm_csr;                             /*  0x0010 */
 158         u32 unused;                             /*  0x0014 */
 159         u32 int_status;                         /*  0x0018 */
 160         u32 int_mask;                           /*  0x001C */
 161         u32 int_alias_clr_en;                   /*  0x0020 */
 162         u32 int_status_alias;                   /*  0x0024 */
 163         u32 sw_reset;                           /*  0x0028 */
 164         u32 slv_timer;                          /*  0x002C */
 165         u32 msi_config;                         /*  0x0030 */
 166         u32 loopback;                   /*  0x0034 */
 167         u32 watchdog_timer;                     /*  0x0038 */
 168 } GLOBAL_t, *PGLOBAL_t;
 169
 170 /* END OF GLOBAL REGISTER ADDRESS MAP */
 171
 172
 173 /* START OF TXDMA REGISTER ADDRESS MAP */
 174
 175 /*
 176  * txdma control status reg at address 0x1000
 177  */
 178
 179 #define ET_TXDMA_CSR_HALT       0x00000001
 180 #define ET_TXDMA_DROP_TLP       0x00000002
 181 #define ET_TXDMA_CACHE_THRS     0x000000F0
 182 #define ET_TXDMA_CACHE_SHIFT    4
 183 #define ET_TXDMA_SNGL_EPKT      0x00000100
 184 #define ET_TXDMA_CLASS          0x00001E00
 185
 186 /*
 187  * structure for txdma packet ring base address hi reg in txdma address map
 188  * located at address 0x1004
 189  * Defined earlier (u32)
 190  */
 191
 192 /*
 193  * structure for txdma packet ring base address low reg in txdma address map
 194  * located at address 0x1008
 195  * Defined earlier (u32)
 196  */
 197
 198 /*
 199  * structure for txdma packet ring number of descriptor reg in txdma address
 200  * map.  Located at address 0x100C
 201  *
 202  * 31-10: unused
 203  * 9-0: pr ndes
 204  */
 205
 206 #define ET_DMA12_MASK           0x0FFF  /* 12 bit mask for DMA12W types */
 207 #define ET_DMA12_WRAP           0x1000
 208 #define ET_DMA10_MASK           0x03FF  /* 10 bit mask for DMA10W types */
 209 #define ET_DMA10_WRAP           0x0400
 210 #define ET_DMA4_MASK            0x000F  /* 4 bit mask for DMA4W types */
 211 #define ET_DMA4_WRAP            0x0010
 212
 213 #define INDEX12(x)      ((x) & ET_DMA12_MASK)
 214 #define INDEX10(x)      ((x) & ET_DMA10_MASK)
 215 #define INDEX4(x)       ((x) & ET_DMA4_MASK)
 216
 217 extern inline void add_10bit(u32 *v, int n)
 218 {
 219         *v = INDEX10(*v + n) | (*v & ET_DMA10_WRAP);
 220 }
 221
 222 extern inline void add_12bit(u32 *v, int n)
 223 {
 224         *v = INDEX12(*v + n) | (*v & ET_DMA12_WRAP);
 225 }
 226
 227 /*
 228  * 10bit DMA with wrap
 229  * txdma tx queue write address reg in txdma address map at 0x1010
 230  * txdma tx queue write address external reg in txdma address map at 0x1014
 231  * txdma tx queue read address reg in txdma address map at 0x1018
 232  *
 233  * u32
 234  * txdma status writeback address hi reg in txdma address map at0x101C
 235  * txdma status writeback address lo reg in txdma address map at 0x1020
 236  *
 237  * 10bit DMA with wrap
 238  * txdma service request reg in txdma address map at 0x1024
 239  * structure for txdma service complete reg in txdma address map at 0x1028
 240  *
 241  * 4bit DMA with wrap
 242  * txdma tx descriptor cache read index reg in txdma address map at 0x102C
 243  * txdma tx descriptor cache write index reg in txdma address map at 0x1030
 244  *
 245  * txdma error reg in txdma address map at address 0x1034
 246  * 0: PyldResend
 247  * 1: PyldRewind
 248  * 4: DescrResend
 249  * 5: DescrRewind
 250  * 8: WrbkResend
 251  * 9: WrbkRewind
 252  */
 253
 254 /*
 255  * Tx DMA Module of JAGCore Address Mapping
 256  * Located at address 0x1000
 257  */
 258 typedef struct _TXDMA_t {               /* Location: */
 259         u32 csr;                        /*  0x1000 */
 260         u32 pr_base_hi;                 /*  0x1004 */
 261         u32 pr_base_lo;                 /*  0x1008 */
 262         u32 pr_num_des;                 /*  0x100C */
 263         u32 txq_wr_addr;                /*  0x1010 */
 264         u32 txq_wr_addr_ext;            /*  0x1014 */
 265         u32 txq_rd_addr;                /*  0x1018 */
 266         u32 dma_wb_base_hi;             /*  0x101C */
 267         u32 dma_wb_base_lo;             /*  0x1020 */
 268         u32 service_request;            /*  0x1024 */
 269         u32 service_complete;           /*  0x1028 */
 270         u32 cache_rd_index;             /*  0x102C */
 271         u32 cache_wr_index;             /*  0x1030 */
 272         u32 TxDmaError;                 /*  0x1034 */
 273         u32 DescAbortCount;             /*  0x1038 */
 274         u32 PayloadAbortCnt;            /*  0x103c */
 275         u32 WriteBackAbortCnt;          /*  0x1040 */
 276         u32 DescTimeoutCnt;             /*  0x1044 */
 277         u32 PayloadTimeoutCnt;          /*  0x1048 */
 278         u32 WriteBackTimeoutCnt;        /*  0x104c */
 279         u32 DescErrorCount;             /*  0x1050 */
 280         u32 PayloadErrorCnt;            /*  0x1054 */
 281         u32 WriteBackErrorCnt;          /*  0x1058 */
 282         u32 DroppedTLPCount;            /*  0x105c */
 283         u32 NewServiceComplete;         /*  0x1060 */
 284         u32 EthernetPacketCount;        /*  0x1064 */
 285 } TXDMA_t, *PTXDMA_t;
 286
 287 /* END OF TXDMA REGISTER ADDRESS MAP */
 288
 289
 290 /* START OF RXDMA REGISTER ADDRESS MAP */
 291
 292 /*
 293  * structure for control status reg in rxdma address map
 294  * Located at address 0x2000
 295  *
 296  * CSR
 297  * 0: halt
 298  * 1-3: tc
 299  * 4: fbr_big_endian
 300  * 5: psr_big_endian
 301  * 6: pkt_big_endian
 302  * 7: dma_big_endian
 303  * 8-9: fbr0_size
 304  * 10: fbr0_enable
 305  * 11-12: fbr1_size
 306  * 13: fbr1_enable
 307  * 14: unused
 308  * 15: pkt_drop_disable
 309  * 16: pkt_done_flush
 310  * 17: halt_status
 311  * 18-31: unused
 312  */
 313
 314
 315 /*
 316  * structure for dma writeback lo reg in rxdma address map
 317  * located at address 0x2004
 318  * Defined earlier (u32)
 319  */
 320
 321 /*
 322  * structure for dma writeback hi reg in rxdma address map
 323  * located at address 0x2008
 324  * Defined earlier (u32)
 325  */
 326
 327 /*
 328  * structure for number of packets done reg in rxdma address map
 329  * located at address 0x200C
 330  *
 331  * 31-8: unused
 332  * 7-0: num done
 333  */
 334
 335 /*
 336  * structure for max packet time reg in rxdma address map
 337  * located at address 0x2010
 338  *
 339  * 31-18: unused
 340  * 17-0: time done
 341  */
 342
 343 /*
 344  * structure for rx queue read address reg in rxdma address map
 345  * located at address 0x2014
 346  * Defined earlier (u32)
 347  */
 348
 349 /*
 350  * structure for rx queue read address external reg in rxdma address map
 351  * located at address 0x2018
 352  * Defined earlier (u32)
 353  */
 354
 355 /*
 356  * structure for rx queue write address reg in rxdma address map
 357  * located at address 0x201C
 358  * Defined earlier (u32)
 359  */
 360
 361 /*
 362  * structure for packet status ring base address lo reg in rxdma address map
 363  * located at address 0x2020
 364  * Defined earlier (u32)
 365  */
 366
 367 /*
 368  * structure for packet status ring base address hi reg in rxdma address map
 369  * located at address 0x2024
 370  * Defined earlier (u32)
 371  */
 372
 373 /*
 374  * structure for packet status ring number of descriptors reg in rxdma address
 375  * map.  Located at address 0x2028
 376  *
 377  * 31-12: unused
 378  * 11-0: psr ndes
 379  */
 380
 381 /*
 382  * structure for packet status ring available offset reg in rxdma address map
 383  * located at address 0x202C
 384  *
 385  * 31-13: unused
 386  * 12: psr avail wrap
 387  * 11-0: psr avail
 388  */
 389
 390 /*
 391  * structure for packet status ring full offset reg in rxdma address map
 392  * located at address 0x2030
 393  *
 394  * 31-13: unused
 395  * 12: psr full wrap
 396  * 11-0: psr full
 397  */
 398
 399 /*
 400  * structure for packet status ring access index reg in rxdma address map
 401  * located at address 0x2034
 402  *
 403  * 31-5: unused
 404  * 4-0: psr_ai
 405  */
 406
 407 /*
 408  * structure for packet status ring minimum descriptors reg in rxdma address
 409  * map.  Located at address 0x2038
 410  *
 411  * 31-12: unused
 412  * 11-0: psr_min
 413  */
 414
 415 /*
 416  * structure for free buffer ring base lo address reg in rxdma address map
 417  * located at address 0x203C
 418  * Defined earlier (u32)
 419  */
 420
 421 /*
 422  * structure for free buffer ring base hi address reg in rxdma address map
 423  * located at address 0x2040
 424  * Defined earlier (u32)
 425  */
 426
 427 /*
 428  * structure for free buffer ring number of descriptors reg in rxdma address
 429  * map.  Located at address 0x2044
 430  *
 431  * 31-10: unused
 432  * 9-0: fbr ndesc
 433  */
 434
 435 /*
 436  * structure for free buffer ring 0 available offset reg in rxdma address map
 437  * located at address 0x2048
 438  * Defined earlier (u32)
 439  */
 440
 441 /*
 442  * structure for free buffer ring 0 full offset reg in rxdma address map
 443  * located at address 0x204C
 444  * Defined earlier (u32)
 445  */
 446
 447 /*
 448  * structure for free buffer cache 0 full offset reg in rxdma address map
 449  * located at address 0x2050
 450  *
 451  * 31-5: unused
 452  * 4-0: fbc rdi
 453  */
 454
 455 /*
 456  * structure for free buffer ring 0 minimum descriptor reg in rxdma address map
 457  * located at address 0x2054
 458  *
 459  * 31-10: unused
 460  * 9-0: fbr min
 461  */
 462
 463 /*
 464  * structure for free buffer ring 1 base address lo reg in rxdma address map
 465  * located at address 0x2058 - 0x205C
 466  * Defined earlier (RXDMA_FBR_BASE_LO_t and RXDMA_FBR_BASE_HI_t)
 467  */
 468
 469 /*
 470  * structure for free buffer ring 1 number of descriptors reg in rxdma address
 471  * map.  Located at address 0x2060
 472  * Defined earlier (RXDMA_FBR_NUM_DES_t)
 473  */
 474
 475 /*
 476  * structure for free buffer ring 1 available offset reg in rxdma address map
 477  * located at address 0x2064
 478  * Defined Earlier (RXDMA_FBR_AVAIL_OFFSET_t)
 479  */
 480
 481 /*
 482  * structure for free buffer ring 1 full offset reg in rxdma address map
 483  * located at address 0x2068
 484  * Defined Earlier (RXDMA_FBR_FULL_OFFSET_t)
 485  */
 486
 487 /*
 488  * structure for free buffer cache 1 read index reg in rxdma address map
 489  * located at address 0x206C
 490  * Defined Earlier (RXDMA_FBC_RD_INDEX_t)
 491  */
 492
 493 /*
 494  * structure for free buffer ring 1 minimum descriptor reg in rxdma address map
 495  * located at address 0x2070
 496  * Defined Earlier (RXDMA_FBR_MIN_DES_t)
 497  */
 498
 499 /*
 500  * Rx DMA Module of JAGCore Address Mapping
 501  * Located at address 0x2000
 502  */
 503 struct rxdma_regs {                                     /* Location: */
 504         u32 csr;                                        /*  0x2000 */
 505         u32 dma_wb_base_lo;                             /*  0x2004 */
 506         u32 dma_wb_base_hi;                             /*  0x2008 */
 507         u32 num_pkt_done;                               /*  0x200C */
 508         u32 max_pkt_time;                               /*  0x2010 */
 509         u32 rxq_rd_addr;                                /*  0x2014 */
 510         u32 rxq_rd_addr_ext;                            /*  0x2018 */
 511         u32 rxq_wr_addr;                                /*  0x201C */
 512         u32 psr_base_lo;                                /*  0x2020 */
 513         u32 psr_base_hi;                                /*  0x2024 */
 514         u32 psr_num_des;                                /*  0x2028 */
 515         u32 psr_avail_offset;                           /*  0x202C */
 516         u32 psr_full_offset;                            /*  0x2030 */
 517         u32 psr_access_index;                           /*  0x2034 */
 518         u32 psr_min_des;                                /*  0x2038 */
 519         u32 fbr0_base_lo;                               /*  0x203C */
 520         u32 fbr0_base_hi;                               /*  0x2040 */
 521         u32 fbr0_num_des;                               /*  0x2044 */
 522         u32 fbr0_avail_offset;                          /*  0x2048 */
 523         u32 fbr0_full_offset;                           /*  0x204C */
 524         u32 fbr0_rd_index;                              /*  0x2050 */
 525         u32 fbr0_min_des;                               /*  0x2054 */
 526         u32 fbr1_base_lo;                               /*  0x2058 */
 527         u32 fbr1_base_hi;                               /*  0x205C */
 528         u32 fbr1_num_des;                               /*  0x2060 */
 529         u32 fbr1_avail_offset;                          /*  0x2064 */
 530         u32 fbr1_full_offset;                           /*  0x2068 */
 531         u32 fbr1_rd_index;                              /*  0x206C */
 532         u32 fbr1_min_des;                               /*  0x2070 */
 533 };
 534
 535 /* END OF RXDMA REGISTER ADDRESS MAP */
 536
 537
 538 /* START OF TXMAC REGISTER ADDRESS MAP */
 539
 540 /*
 541  * structure for control reg in txmac address map
 542  * located at address 0x3000
 543  */
 544 typedef union _TXMAC_CTL_t {
 545         u32 value;
 546         struct {
 547 #ifdef _BIT_FIELDS_HTOL
 548                 u32 unused:24;          /* bits 8-31 */
 549                 u32 cklseg_diable:1;    /* bit 7 */
 550                 u32 ckbcnt_disable:1;   /* bit 6 */
 551                 u32 cksegnum:1;         /* bit 5 */
 552                 u32 async_disable:1;    /* bit 4 */
 553                 u32 fc_disable:1;       /* bit 3 */
 554                 u32 mcif_disable:1;     /* bit 2 */
 555                 u32 mif_disable:1;      /* bit 1 */
 556                 u32 txmac_en:1;         /* bit 0 */
 557 #else
 558                 u32 txmac_en:1;         /* bit 0 */
 559                 u32 mif_disable:1;      /* bit 1 mac interface */
 560                 u32 mcif_disable:1;     /* bit 2 mem. contr. interface */
 561                 u32 fc_disable:1;       /* bit 3 */
 562                 u32 async_disable:1;    /* bit 4 */
 563                 u32 cksegnum:1;         /* bit 5 */
 564                 u32 ckbcnt_disable:1;   /* bit 6 */
 565                 u32 cklseg_diable:1;    /* bit 7 */
 566                 u32 unused:24;          /* bits 8-31 */
 567 #endif
 568         } bits;
 569 } TXMAC_CTL_t, *PTXMAC_CTL_t;
 570
 571 /*
 572  * structure for shadow pointer reg in txmac address map
 573  * located at address 0x3004
 574  * 31-27: reserved
 575  * 26-16: txq rd ptr
 576  * 15-11: reserved
 577  * 10-0: txq wr ptr
 578  */
 579
 580 /*
 581  * structure for error count reg in txmac address map
 582  * located at address 0x3008
 583  */
 584 typedef union _TXMAC_ERR_CNT_t {
 585         u32 value;
 586         struct {
 587 #ifdef _BIT_FIELDS_HTOL
 588                 u32 unused:20;          /* bits 12-31 */
 589                 u32 reserved:4;         /* bits 8-11 */
 590                 u32 txq_underrun:4;     /* bits 4-7 */
 591                 u32 fifo_underrun:4;    /* bits 0-3 */
 592 #else
 593                 u32 fifo_underrun:4;    /* bits 0-3 */
 594                 u32 txq_underrun:4;     /* bits 4-7 */
 595                 u32 reserved:4;         /* bits 8-11 */
 596                 u32 unused:20;          /* bits 12-31 */
 597 #endif
 598         } bits;
 599 } TXMAC_ERR_CNT_t, *PTXMAC_ERR_CNT_t;
 600
 601 /*
 602  * structure for max fill reg in txmac address map
 603  * located at address 0x300C
 604  * 31-12: unused
 605  * 11-0: max fill
 606  */
 607
 608 /*
 609  * structure for cf parameter reg in txmac address map
 610  * located at address 0x3010
 611  * 31-16: cfep
 612  * 15-0: cfpt
 613  */
 614
 615 /*
 616  * structure for tx test reg in txmac address map
 617  * located at address 0x3014
 618  * 31-17: unused
 619  * 16: reserved1
 620  * 15: txtest_en
 621  * 14-11: unused
 622  * 10-0: txq test pointer
 623  */
 624
 625 /*
 626  * structure for error reg in txmac address map
 627  * located at address 0x3018
 628  */
 629 typedef union _TXMAC_ERR_t {
 630         u32 value;
 631         struct {
 632 #ifdef _BIT_FIELDS_HTOL
 633                 u32 unused2:23;         /* bits 9-31 */
 634                 u32 fifo_underrun:1;    /* bit 8 */
 635                 u32 unused1:2;          /* bits 6-7 */
 636                 u32 ctrl2_err:1;        /* bit 5 */
 637                 u32 txq_underrun:1;     /* bit 4 */
 638                 u32 bcnt_err:1;         /* bit 3 */
 639                 u32 lseg_err:1;         /* bit 2 */
 640                 u32 segnum_err:1;       /* bit 1 */
 641                 u32 seg0_err:1;         /* bit 0 */
 642 #else
 643                 u32 seg0_err:1;         /* bit 0 */
 644                 u32 segnum_err:1;       /* bit 1 */
 645                 u32 lseg_err:1;         /* bit 2 */
 646                 u32 bcnt_err:1;         /* bit 3 */
 647                 u32 txq_underrun:1;     /* bit 4 */
 648                 u32 ctrl2_err:1;        /* bit 5 */
 649                 u32 unused1:2;          /* bits 6-7 */
 650                 u32 fifo_underrun:1;    /* bit 8 */
 651                 u32 unused2:23;         /* bits 9-31 */
 652 #endif
 653         } bits;
 654 } TXMAC_ERR_t, *PTXMAC_ERR_t;
 655
 656 /*
 657  * structure for error interrupt reg in txmac address map
 658  * located at address 0x301C
 659  */
 660 typedef union _TXMAC_ERR_INT_t {
 661         u32 value;
 662         struct {
 663 #ifdef _BIT_FIELDS_HTOL
 664                 u32 unused2:23;         /* bits 9-31 */
 665                 u32 fifo_underrun:1;    /* bit 8 */
 666                 u32 unused1:2;          /* bits 6-7 */
 667                 u32 ctrl2_err:1;        /* bit 5 */
 668                 u32 txq_underrun:1;     /* bit 4 */
 669                 u32 bcnt_err:1;         /* bit 3 */
 670                 u32 lseg_err:1;         /* bit 2 */
 671                 u32 segnum_err:1;       /* bit 1 */
 672                 u32 seg0_err:1;         /* bit 0 */
 673 #else
 674                 u32 seg0_err:1;         /* bit 0 */
 675                 u32 segnum_err:1;       /* bit 1 */
 676                 u32 lseg_err:1;         /* bit 2 */
 677                 u32 bcnt_err:1;         /* bit 3 */
 678                 u32 txq_underrun:1;     /* bit 4 */
 679                 u32 ctrl2_err:1;        /* bit 5 */
 680                 u32 unused1:2;          /* bits 6-7 */
 681                 u32 fifo_underrun:1;    /* bit 8 */
 682                 u32 unused2:23;         /* bits 9-31 */
 683 #endif
 684         } bits;
 685 } TXMAC_ERR_INT_t, *PTXMAC_ERR_INT_t;
 686
 687 /*
 688  * structure for error interrupt reg in txmac address map
 689  * located at address 0x3020
 690  *
 691  * 31-2: unused
 692  * 1: bp_req
 693  * 0: bp_xonxoff
 694  */
 695
 696 /*
 697  * Tx MAC Module of JAGCore Address Mapping
 698  */
 699 typedef struct _TXMAC_t {               /* Location: */
 700         TXMAC_CTL_t ctl;                /*  0x3000 */
 701         u32 shadow_ptr;                 /*  0x3004 */
 702         TXMAC_ERR_CNT_t err_cnt;        /*  0x3008 */
 703         u32 max_fill;                   /*  0x300C */
 704         u32 cf_param;                   /*  0x3010 */
 705         u32 tx_test;                    /*  0x3014 */
 706         TXMAC_ERR_t err;                /*  0x3018 */
 707         TXMAC_ERR_INT_t err_int;        /*  0x301C */
 708         u32 bp_ctrl;                    /*  0x3020 */
 709 } TXMAC_t, *PTXMAC_t;
 710
 711 /* END OF TXMAC REGISTER ADDRESS MAP */
 712
 713 /* START OF RXMAC REGISTER ADDRESS MAP */
 714
 715 /*
 716  * structure for rxmac control reg in rxmac address map
 717  * located at address 0x4000
 718  */
 719 typedef union _RXMAC_CTRL_t {
 720         u32 value;
 721         struct {
 722 #ifdef _BIT_FIELDS_HTOL
 723                 u32 reserved:25;                /* bits 7-31 */
 724                 u32 rxmac_int_disable:1;        /* bit 6 */
 725                 u32 async_disable:1;            /* bit 5 */
 726                 u32 mif_disable:1;              /* bit 4 */
 727                 u32 wol_disable:1;              /* bit 3 */
 728                 u32 pkt_filter_disable:1;       /* bit 2 */
 729                 u32 mcif_disable:1;             /* bit 1 */
 730                 u32 rxmac_en:1;                 /* bit 0 */
 731 #else
 732                 u32 rxmac_en:1;                 /* bit 0 */
 733                 u32 mcif_disable:1;             /* bit 1 */
 734                 u32 pkt_filter_disable:1;       /* bit 2 */
 735                 u32 wol_disable:1;              /* bit 3 */
 736                 u32 mif_disable:1;              /* bit 4 */
 737                 u32 async_disable:1;            /* bit 5 */
 738                 u32 rxmac_int_disable:1;        /* bit 6 */
 739                 u32 reserved:25;                /* bits 7-31 */
 740 #endif
 741         } bits;
 742 } RXMAC_CTRL_t, *PRXMAC_CTRL_t;
 743
 744 /*
 745  * structure for Wake On Lan Control and CRC 0 reg in rxmac address map
 746  * located at address 0x4004
 747  */
 748 typedef union _RXMAC_WOL_CTL_CRC0_t {
 749         u32 value;
 750         struct {
 751 #ifdef _BIT_FIELDS_HTOL
 752                 u32 crc0:16;            /* bits 16-31 */
 753                 u32 reserve:4;          /* bits 12-15 */
 754                 u32 ignore_pp:1;        /* bit 11 */
 755                 u32 ignore_mp:1;        /* bit 10 */
 756                 u32 clr_intr:1;         /* bit 9 */
 757                 u32 ignore_link_chg:1;  /* bit 8 */
 758                 u32 ignore_uni:1;       /* bit 7 */
 759                 u32 ignore_multi:1;     /* bit 6 */
 760                 u32 ignore_broad:1;     /* bit 5 */
 761                 u32 valid_crc4:1;       /* bit 4 */
 762                 u32 valid_crc3:1;       /* bit 3 */
 763                 u32 valid_crc2:1;       /* bit 2 */
 764                 u32 valid_crc1:1;       /* bit 1 */
 765                 u32 valid_crc0:1;       /* bit 0 */
 766 #else
 767                 u32 valid_crc0:1;       /* bit 0 */
 768                 u32 valid_crc1:1;       /* bit 1 */
 769                 u32 valid_crc2:1;       /* bit 2 */
 770                 u32 valid_crc3:1;       /* bit 3 */
 771                 u32 valid_crc4:1;       /* bit 4 */
 772                 u32 ignore_broad:1;     /* bit 5 */
 773                 u32 ignore_multi:1;     /* bit 6 */
 774                 u32 ignore_uni:1;       /* bit 7 */
 775                 u32 ignore_link_chg:1;  /* bit 8 */
 776                 u32 clr_intr:1;         /* bit 9 */
 777                 u32 ignore_mp:1;        /* bit 10 */
 778                 u32 ignore_pp:1;        /* bit 11 */
 779                 u32 reserve:4;          /* bits 12-15 */
 780                 u32 crc0:16;            /* bits 16-31 */
 781 #endif
 782         } bits;
 783 } RXMAC_WOL_CTL_CRC0_t, *PRXMAC_WOL_CTL_CRC0_t;
 784
 785 /*
 786  * structure for CRC 1 and CRC 2 reg in rxmac address map
 787  * located at address 0x4008
 788  */
 789 typedef union _RXMAC_WOL_CRC12_t {
 790         u32 value;
 791         struct {
 792 #ifdef _BIT_FIELDS_HTOL
 793                 u32 crc2:16;    /* bits 16-31 */
 794                 u32 crc1:16;    /* bits 0-15 */
 795 #else
 796                 u32 crc1:16;    /* bits 0-15 */
 797                 u32 crc2:16;    /* bits 16-31 */
 798 #endif
 799         } bits;
 800 } RXMAC_WOL_CRC12_t, *PRXMAC_WOL_CRC12_t;
 801
 802 /*
 803  * structure for CRC 3 and CRC 4 reg in rxmac address map
 804  * located at address 0x400C
 805  */
 806 typedef union _RXMAC_WOL_CRC34_t {
 807         u32 value;
 808         struct {
 809 #ifdef _BIT_FIELDS_HTOL
 810                 u32 crc4:16;    /* bits 16-31 */
 811                 u32 crc3:16;    /* bits 0-15 */
 812 #else
 813                 u32 crc3:16;    /* bits 0-15 */
 814                 u32 crc4:16;    /* bits 16-31 */
 815 #endif
 816         } bits;
 817 } RXMAC_WOL_CRC34_t, *PRXMAC_WOL_CRC34_t;
 818
 819 /*
 820  * structure for Wake On Lan Source Address Lo reg in rxmac address map
 821  * located at address 0x4010
 822  */
 823 typedef union _RXMAC_WOL_SA_LO_t {
 824         u32 value;
 825         struct {
 826 #ifdef _BIT_FIELDS_HTOL
 827                 u32 sa3:8;      /* bits 24-31 */
 828                 u32 sa4:8;      /* bits 16-23 */
 829                 u32 sa5:8;      /* bits 8-15 */
 830                 u32 sa6:8;      /* bits 0-7 */
 831 #else
 832                 u32 sa6:8;      /* bits 0-7 */
 833                 u32 sa5:8;      /* bits 8-15 */
 834                 u32 sa4:8;      /* bits 16-23 */
 835                 u32 sa3:8;      /* bits 24-31 */
 836 #endif
 837         } bits;
 838 } RXMAC_WOL_SA_LO_t, *PRXMAC_WOL_SA_LO_t;
 839
 840 /*
 841  * structure for Wake On Lan Source Address Hi reg in rxmac address map
 842  * located at address 0x4014
 843  */
 844 typedef union _RXMAC_WOL_SA_HI_t {
 845         u32 value;
 846         struct {
 847 #ifdef _BIT_FIELDS_HTOL
 848                 u32 reserved:16;        /* bits 16-31 */
 849                 u32 sa1:8;              /* bits 8-15 */
 850                 u32 sa2:8;              /* bits 0-7 */
 851 #else
 852                 u32 sa2:8;              /* bits 0-7 */
 853                 u32 sa1:8;              /* bits 8-15 */
 854                 u32 reserved:16;        /* bits 16-31 */
 855 #endif
 856         } bits;
 857 } RXMAC_WOL_SA_HI_t, *PRXMAC_WOL_SA_HI_t;
 858
 859 /*
 860  * structure for Wake On Lan mask reg in rxmac address map
 861  * located at address 0x4018 - 0x4064
 862  * Defined earlier (u32)
 863  */
 864
 865 /*
 866  * structure for Unicast Paket Filter Address 1 reg in rxmac address map
 867  * located at address 0x4068
 868  */
 869 typedef union _RXMAC_UNI_PF_ADDR1_t {
 870         u32 value;
 871         struct {
 872 #ifdef _BIT_FIELDS_HTOL
 873                 u32 addr1_3:8;  /* bits 24-31 */
 874                 u32 addr1_4:8;  /* bits 16-23 */
 875                 u32 addr1_5:8;  /* bits 8-15 */
 876                 u32 addr1_6:8;  /* bits 0-7 */
 877 #else
 878                 u32 addr1_6:8;  /* bits 0-7 */
 879                 u32 addr1_5:8;  /* bits 8-15 */
 880                 u32 addr1_4:8;  /* bits 16-23 */
 881                 u32 addr1_3:8;  /* bits 24-31 */
 882 #endif
 883         } bits;
 884 } RXMAC_UNI_PF_ADDR1_t, *PRXMAC_UNI_PF_ADDR1_t;
 885
 886 /*
 887  * structure for Unicast Paket Filter Address 2 reg in rxmac address map
 888  * located at address 0x406C
 889  */
 890 typedef union _RXMAC_UNI_PF_ADDR2_t {
 891         u32 value;
 892         struct {
 893 #ifdef _BIT_FIELDS_HTOL
 894                 u32 addr2_3:8;  /* bits 24-31 */
 895                 u32 addr2_4:8;  /* bits 16-23 */
 896                 u32 addr2_5:8;  /* bits 8-15 */
 897                 u32 addr2_6:8;  /* bits 0-7 */
 898 #else
 899                 u32 addr2_6:8;  /* bits 0-7 */
 900                 u32 addr2_5:8;  /* bits 8-15 */
 901                 u32 addr2_4:8;  /* bits 16-23 */
 902                 u32 addr2_3:8;  /* bits 24-31 */
 903 #endif
 904         } bits;
 905 } RXMAC_UNI_PF_ADDR2_t, *PRXMAC_UNI_PF_ADDR2_t;
 906
 907 /*
 908  * structure for Unicast Paket Filter Address 1 & 2 reg in rxmac address map
 909  * located at address 0x4070
 910  */
 911 typedef union _RXMAC_UNI_PF_ADDR3_t {
 912         u32 value;
 913         struct {
 914 #ifdef _BIT_FIELDS_HTOL
 915                 u32 addr2_1:8;  /* bits 24-31 */
 916                 u32 addr2_2:8;  /* bits 16-23 */
 917                 u32 addr1_1:8;  /* bits 8-15 */
 918                 u32 addr1_2:8;  /* bits 0-7 */
 919 #else
 920                 u32 addr1_2:8;  /* bits 0-7 */
 921                 u32 addr1_1:8;  /* bits 8-15 */
 922                 u32 addr2_2:8;  /* bits 16-23 */
 923                 u32 addr2_1:8;  /* bits 24-31 */
 924 #endif
 925         } bits;
 926 } RXMAC_UNI_PF_ADDR3_t, *PRXMAC_UNI_PF_ADDR3_t;
 927
 928 /*
 929  * structure for Multicast Hash reg in rxmac address map
 930  * located at address 0x4074 - 0x4080
 931  * Defined earlier (u32)
 932  */
 933
 934 /*
 935  * structure for Packet Filter Control reg in rxmac address map
 936  * located at address 0x4084
 937  */
 938 typedef union _RXMAC_PF_CTRL_t {
 939         u32 value;
 940         struct {
 941 #ifdef _BIT_FIELDS_HTOL
 942                 u32 unused2:9;          /* bits 23-31 */
 943                 u32 min_pkt_size:7;     /* bits 16-22 */
 944                 u32 unused1:12;         /* bits 4-15 */
 945                 u32 filter_frag_en:1;   /* bit 3 */
 946                 u32 filter_uni_en:1;    /* bit 2 */
 947                 u32 filter_multi_en:1;  /* bit 1 */
 948                 u32 filter_broad_en:1;  /* bit 0 */
 949 #else
 950                 u32 filter_broad_en:1;  /* bit 0 */
 951                 u32 filter_multi_en:1;  /* bit 1 */
 952                 u32 filter_uni_en:1;    /* bit 2 */
 953                 u32 filter_frag_en:1;   /* bit 3 */
 954                 u32 unused1:12;         /* bits 4-15 */
 955                 u32 min_pkt_size:7;     /* bits 16-22 */
 956                 u32 unused2:9;          /* bits 23-31 */
 957 #endif
 958         } bits;
 959 } RXMAC_PF_CTRL_t, *PRXMAC_PF_CTRL_t;
 960
 961 /*
 962  * structure for Memory Controller Interface Control Max Segment reg in rxmac
 963  * address map.  Located at address 0x4088
 964  */
 965 typedef union _RXMAC_MCIF_CTRL_MAX_SEG_t {
 966         u32 value;
 967         struct {
 968 #ifdef _BIT_FIELDS_HTOL
 969                 u32 reserved:22;        /* bits 10-31 */
 970                 u32 max_size:8; /* bits 2-9 */
 971                 u32 fc_en:1;    /* bit 1 */
 972                 u32 seg_en:1;   /* bit 0 */
 973 #else
 974                 u32 seg_en:1;   /* bit 0 */
 975                 u32 fc_en:1;    /* bit 1 */
 976                 u32 max_size:8; /* bits 2-9 */
 977                 u32 reserved:22;        /* bits 10-31 */
 978 #endif
 979         } bits;
 980 } RXMAC_MCIF_CTRL_MAX_SEG_t, *PRXMAC_MCIF_CTRL_MAX_SEG_t;
 981
 982 /*
 983  * structure for Memory Controller Interface Water Mark reg in rxmac address
 984  * map.  Located at address 0x408C
 985  */
 986 typedef union _RXMAC_MCIF_WATER_MARK_t {
 987         u32 value;
 988         struct {
 989 #ifdef _BIT_FIELDS_HTOL
 990                 u32 reserved2:6;        /* bits 26-31 */
 991                 u32 mark_hi:10; /* bits 16-25 */
 992                 u32 reserved1:6;        /* bits 10-15 */
 993                 u32 mark_lo:10; /* bits 0-9 */
 994 #else
 995                 u32 mark_lo:10; /* bits 0-9 */
 996                 u32 reserved1:6;        /* bits 10-15 */
 997                 u32 mark_hi:10; /* bits 16-25 */
 998                 u32 reserved2:6;        /* bits 26-31 */
 999 #endif
1000         } bits;
1001 } RXMAC_MCIF_WATER_MARK_t, *PRXMAC_MCIF_WATER_MARK_t;
1002
1003 /*
1004  * structure for Rx Queue Dialog reg in rxmac address map.
1005  * located at address 0x4090
1006  */
1007 typedef union _RXMAC_RXQ_DIAG_t {
1008         u32 value;
1009         struct {
1010 #ifdef _BIT_FIELDS_HTOL
1011                 u32 reserved2:6;        /* bits 26-31 */
1012                 u32 rd_ptr:10;  /* bits 16-25 */
1013                 u32 reserved1:6;        /* bits 10-15 */
1014                 u32 wr_ptr:10;  /* bits 0-9 */
1015 #else
1016                 u32 wr_ptr:10;  /* bits 0-9 */
1017                 u32 reserved1:6;        /* bits 10-15 */
1018                 u32 rd_ptr:10;  /* bits 16-25 */
1019                 u32 reserved2:6;        /* bits 26-31 */
1020 #endif
1021         } bits;
1022 } RXMAC_RXQ_DIAG_t, *PRXMAC_RXQ_DIAG_t;
1023
1024 /*
1025  * structure for space availiable reg in rxmac address map.
1026  * located at address 0x4094
1027  */
1028 typedef union _RXMAC_SPACE_AVAIL_t {
1029         u32 value;
1030         struct {
1031 #ifdef _BIT_FIELDS_HTOL
1032                 u32 reserved2:15;               /* bits 17-31 */
1033                 u32 space_avail_en:1;   /* bit 16 */
1034                 u32 reserved1:6;                /* bits 10-15 */
1035                 u32 space_avail:10;     /* bits 0-9 */
1036 #else
1037                 u32 space_avail:10;     /* bits 0-9 */
1038                 u32 reserved1:6;                /* bits 10-15 */
1039                 u32 space_avail_en:1;   /* bit 16 */
1040                 u32 reserved2:15;               /* bits 17-31 */
1041 #endif
1042         } bits;
1043 } RXMAC_SPACE_AVAIL_t, *PRXMAC_SPACE_AVAIL_t;
1044
1045 /*
1046  * structure for management interface reg in rxmac address map.
1047  * located at address 0x4098
1048  */
1049 typedef union _RXMAC_MIF_CTL_t {
1050         u32 value;
1051         struct {
1052 #ifdef _BIT_FIELDS_HTOL
1053                 u32 reserve:14;         /* bits 18-31 */
1054                 u32 drop_pkt_en:1;              /* bit 17 */
1055                 u32 drop_pkt_mask:17;   /* bits 0-16 */
1056 #else
1057                 u32 drop_pkt_mask:17;   /* bits 0-16 */
1058                 u32 drop_pkt_en:1;              /* bit 17 */
1059                 u32 reserve:14;         /* bits 18-31 */
1060 #endif
1061         } bits;
1062 } RXMAC_MIF_CTL_t, *PRXMAC_MIF_CTL_t;
1063
1064 /*
1065  * structure for Error reg in rxmac address map.
1066  * located at address 0x409C
1067  */
1068 typedef union _RXMAC_ERROR_REG_t {
1069         u32 value;
1070         struct {
1071 #ifdef _BIT_FIELDS_HTOL
1072                 u32 reserve:28; /* bits 4-31 */
1073                 u32 mif:1;              /* bit 3 */
1074                 u32 async:1;    /* bit 2 */
1075                 u32 pkt_filter:1;       /* bit 1 */
1076                 u32 mcif:1;     /* bit 0 */
1077 #else
1078                 u32 mcif:1;     /* bit 0 */
1079                 u32 pkt_filter:1;       /* bit 1 */
1080                 u32 async:1;    /* bit 2 */
1081                 u32 mif:1;              /* bit 3 */
1082                 u32 reserve:28; /* bits 4-31 */
1083 #endif
1084         } bits;
1085 } RXMAC_ERROR_REG_t, *PRXMAC_ERROR_REG_t;
1086
1087 /*
1088  * Rx MAC Module of JAGCore Address Mapping
1089  */
1090 typedef struct _RXMAC_t {                               /* Location: */
1091         RXMAC_CTRL_t ctrl;                              /*  0x4000 */
1092         RXMAC_WOL_CTL_CRC0_t crc0;                      /*  0x4004 */
1093         RXMAC_WOL_CRC12_t crc12;                        /*  0x4008 */
1094         RXMAC_WOL_CRC34_t crc34;                        /*  0x400C */
1095         RXMAC_WOL_SA_LO_t sa_lo;                        /*  0x4010 */
1096         RXMAC_WOL_SA_HI_t sa_hi;                        /*  0x4014 */
1097         u32 mask0_word0;                                /*  0x4018 */
1098         u32 mask0_word1;                                /*  0x401C */
1099         u32 mask0_word2;                                /*  0x4020 */
1100         u32 mask0_word3;                                /*  0x4024 */
1101         u32 mask1_word0;                                /*  0x4028 */
1102         u32 mask1_word1;                                /*  0x402C */
1103         u32 mask1_word2;                                /*  0x4030 */
1104         u32 mask1_word3;                                /*  0x4034 */
1105         u32 mask2_word0;                                /*  0x4038 */
1106         u32 mask2_word1;                                /*  0x403C */
1107         u32 mask2_word2;                                /*  0x4040 */
1108         u32 mask2_word3;                                /*  0x4044 */
1109         u32 mask3_word0;                                /*  0x4048 */
1110         u32 mask3_word1;                                /*  0x404C */
1111         u32 mask3_word2;                                /*  0x4050 */
1112         u32 mask3_word3;                                /*  0x4054 */
1113         u32 mask4_word0;                                /*  0x4058 */
1114         u32 mask4_word1;                                /*  0x405C */
1115         u32 mask4_word2;                                /*  0x4060 */
1116         u32 mask4_word3;                                /*  0x4064 */
1117         RXMAC_UNI_PF_ADDR1_t uni_pf_addr1;              /*  0x4068 */
1118         RXMAC_UNI_PF_ADDR2_t uni_pf_addr2;              /*  0x406C */
1119         RXMAC_UNI_PF_ADDR3_t uni_pf_addr3;              /*  0x4070 */
1120         u32 multi_hash1;                                /*  0x4074 */
1121         u32 multi_hash2;                                /*  0x4078 */
1122         u32 multi_hash3;                                /*  0x407C */
1123         u32 multi_hash4;                                /*  0x4080 */
1124         RXMAC_PF_CTRL_t pf_ctrl;                        /*  0x4084 */
1125         RXMAC_MCIF_CTRL_MAX_SEG_t mcif_ctrl_max_seg;    /*  0x4088 */
1126         RXMAC_MCIF_WATER_MARK_t mcif_water_mark;        /*  0x408C */
1127         RXMAC_RXQ_DIAG_t rxq_diag;                      /*  0x4090 */
1128         RXMAC_SPACE_AVAIL_t space_avail;                /*  0x4094 */
1129
1130         RXMAC_MIF_CTL_t mif_ctrl;                       /*  0x4098 */
1131         RXMAC_ERROR_REG_t err_reg;                      /*  0x409C */
1132 } RXMAC_t, *PRXMAC_t;
1133
1134 /* END OF TXMAC REGISTER ADDRESS MAP */
1135
1136
1137 /* START OF MAC REGISTER ADDRESS MAP */
1138
1139 /*
1140  * structure for configuration #1 reg in mac address map.
1141  * located at address 0x5000
1142  *
1143  * 31: soft reset
1144  * 30: sim reset
1145  * 29-20: reserved
1146  * 19: reset rx mc
1147  * 18: reset tx mc
1148  * 17: reset rx func
1149  * 16: reset tx fnc
1150  * 15-9: reserved
1151  * 8: loopback
1152  * 7-6: reserved
1153  * 5: rx flow
1154  * 4: tx flow
1155  * 3: syncd rx en
1156  * 2: rx enable
1157  * 1: syncd tx en
1158  * 0: tx enable
1159  */
1160
1161 #define CFG1_LOOPBACK   0x00000100
1162 #define CFG1_RX_FLOW    0x00000020
1163 #define CFG1_TX_FLOW    0x00000010
1164 #define CFG1_RX_ENABLE  0x00000004
1165 #define CFG1_TX_ENABLE  0x00000001
1166 #define CFG1_WAIT       0x0000000A      /* RX & TX syncd */
1167
1168 /*
1169  * structure for configuration #2 reg in mac address map.
1170  * located at address 0x5004
1171  * 31-16: reserved
1172  * 15-12: preamble
1173  * 11-10: reserved
1174  * 9-8: if mode
1175  * 7-6: reserved
1176  * 5: huge frame
1177  * 4: length check
1178  * 3: undefined
1179  * 2: pad crc
1180  * 1: crc enable
1181  * 0: full duplex
1182  */
1183
1184
1185 /*
1186  * structure for Interpacket gap reg in mac address map.
1187  * located at address 0x5008
1188  *
1189  * 31: reserved
1190  * 30-24: non B2B ipg 1
1191  * 23: undefined
1192  * 22-16: non B2B ipg 2
1193  * 15-8: Min ifg enforce
1194  * 7-0: B2B ipg
1195  *
1196  * structure for half duplex reg in mac address map.
1197  * located at address 0x500C
1198  * 31-24: reserved
1199  * 23-20: Alt BEB trunc
1200  * 19: Alt BEB enable
1201  * 18: BP no backoff
1202  * 17: no backoff
1203  * 16: excess defer
1204  * 15-12: re-xmit max
1205  * 11-10: reserved
1206  * 9-0: collision window
1207  */
1208
1209 /*
1210  * structure for Maximum Frame Length reg in mac address map.
1211  * located at address 0x5010: bits 0-15 hold the length.
1212  */
1213
1214 /*
1215  * structure for Reserve 1 reg in mac address map.
1216  * located at address 0x5014 - 0x5018
1217  * Defined earlier (u32)
1218  */
1219
1220 /*
1221  * structure for Test reg in mac address map.
1222  * located at address 0x501C
1223  * test: bits 0-2, rest unused
1224  */
1225
1226 /*
1227  * structure for MII Management Configuration reg in mac address map.
1228  * located at address 0x5020
1229  *
1230  * 31: reset MII mgmt
1231  * 30-6: unused
1232  * 5: scan auto increment
1233  * 4: preamble supress
1234  * 3: undefined
1235  * 2-0: mgmt clock reset
1236  */
1237
1238 /*
1239  * structure for MII Management Command reg in mac address map.
1240  * located at address 0x5024
1241  * bit 1: scan cycle
1242  * bit 0: read cycle
1243  */
1244
1245 /*
1246  * structure for MII Management Address reg in mac address map.
1247  * located at address 0x5028
1248  * 31-13: reserved
1249  * 12-8: phy addr
1250  * 7-5: reserved
1251  * 4-0: register
1252  */
1253
1254 #define MII_ADDR(phy,reg)       ((phy) << 8 | (reg))
1255
1256 /*
1257  * structure for MII Management Control reg in mac address map.
1258  * located at address 0x502C
1259  * 31-16: reserved
1260  * 15-0: phy control
1261  */
1262
1263 /*
1264  * structure for MII Management Status reg in mac address map.
1265  * located at address 0x5030
1266  * 31-16: reserved
1267  * 15-0: phy control
1268  */
1269
1270 /*
1271  * structure for MII Management Indicators reg in mac address map.
1272  * located at address 0x5034
1273  * 31-3: reserved
1274  * 2: not valid
1275  * 1: scanning
1276  * 0: busy
1277  */
1278
1279 #define MGMT_BUSY       0x00000001      /* busy */
1280 #define MGMT_WAIT       0x00000005      /* busy | not valid */
1281
1282 /*
1283  * structure for Interface Control reg in mac address map.
1284  * located at address 0x5038
1285  *
1286  * 31: reset if module
1287  * 30-28: reserved
1288  * 27: tbi mode
1289  * 26: ghd mode
1290  * 25: lhd mode
1291  * 24: phy mode
1292  * 23: reset per mii
1293  * 22-17: reserved
1294  * 16: speed
1295  * 15: reset pe100x
1296  * 14-11: reserved
1297  * 10: force quiet
1298  * 9: no cipher
1299  * 8: disable link fail
1300  * 7: reset gpsi
1301  * 6-1: reserved
1302  * 0: enable jabber protection
1303  */
1304
1305 /*
1306  * structure for Interface Status reg in mac address map.
1307  * located at address 0x503C
1308  */
1309 typedef union _MAC_IF_STAT_t {
1310         u32 value;
1311         struct {
1312 #ifdef _BIT_FIELDS_HTOL
1313                 u32 reserved:22;                /* bits 10-31 */
1314                 u32 excess_defer:1;     /* bit 9 */
1315                 u32 clash:1;            /* bit 8 */
1316                 u32 phy_jabber:1;               /* bit 7 */
1317                 u32 phy_link_ok:1;              /* bit 6 */
1318                 u32 phy_full_duplex:1;  /* bit 5 */
1319                 u32 phy_speed:1;                /* bit 4 */
1320                 u32 pe100x_link_fail:1; /* bit 3 */
1321                 u32 pe10t_loss_carrie:1;        /* bit 2 */
1322                 u32 pe10t_sqe_error:1;  /* bit 1 */
1323                 u32 pe10t_jabber:1;     /* bit 0 */
1324 #else
1325                 u32 pe10t_jabber:1;     /* bit 0 */
1326                 u32 pe10t_sqe_error:1;  /* bit 1 */
1327                 u32 pe10t_loss_carrie:1;        /* bit 2 */
1328                 u32 pe100x_link_fail:1; /* bit 3 */
1329                 u32 phy_speed:1;                /* bit 4 */
1330                 u32 phy_full_duplex:1;  /* bit 5 */
1331                 u32 phy_link_ok:1;              /* bit 6 */
1332                 u32 phy_jabber:1;               /* bit 7 */
1333                 u32 clash:1;            /* bit 8 */
1334                 u32 excess_defer:1;     /* bit 9 */
1335                 u32 reserved:22;                /* bits 10-31 */
1336 #endif
1337         } bits;
1338 } MAC_IF_STAT_t, *PMAC_IF_STAT_t;
1339
1340 /*
1341  * structure for Mac Station Address, Part 1 reg in mac address map.
1342  * located at address 0x5040
1343  */
1344 typedef union _MAC_STATION_ADDR1_t {
1345         u32 value;
1346         struct {
1347 #ifdef _BIT_FIELDS_HTOL
1348                 u32 Octet6:8;   /* bits 24-31 */
1349                 u32 Octet5:8;   /* bits 16-23 */
1350                 u32 Octet4:8;   /* bits 8-15 */
1351                 u32 Octet3:8;   /* bits 0-7 */
1352 #else
1353                 u32 Octet3:8;   /* bits 0-7 */
1354                 u32 Octet4:8;   /* bits 8-15 */
1355                 u32 Octet5:8;   /* bits 16-23 */
1356                 u32 Octet6:8;   /* bits 24-31 */
1357 #endif
1358         } bits;
1359 } MAC_STATION_ADDR1_t, *PMAC_STATION_ADDR1_t;
1360
1361 /*
1362  * structure for Mac Station Address, Part 2 reg in mac address map.
1363  * located at address 0x5044
1364  */
1365 typedef union _MAC_STATION_ADDR2_t {
1366         u32 value;
1367         struct {
1368 #ifdef _BIT_FIELDS_HTOL
1369                 u32 Octet2:8;   /* bits 24-31 */
1370                 u32 Octet1:8;   /* bits 16-23 */
1371                 u32 reserved:16;        /* bits 0-15 */
1372 #else
1373                 u32 reserved:16;        /* bit 0-15 */
1374                 u32 Octet1:8;   /* bits 16-23 */
1375                 u32 Octet2:8;   /* bits 24-31 */
1376 #endif
1377         } bits;
1378 } MAC_STATION_ADDR2_t, *PMAC_STATION_ADDR2_t;
1379
1380 /*
1381  * MAC Module of JAGCore Address Mapping
1382  */
1383 typedef struct _MAC_t {                                 /* Location: */
1384         u32 cfg1;                                       /*  0x5000 */
1385         u32 cfg2;                                       /*  0x5004 */
1386         u32 ipg;                                        /*  0x5008 */
1387         u32 hfdp;                                       /*  0x500C */
1388         u32 max_fm_len;                                 /*  0x5010 */
1389         u32 rsv1;                                       /*  0x5014 */
1390         u32 rsv2;                                       /*  0x5018 */
1391         u32 mac_test;                                   /*  0x501C */
1392         u32 mii_mgmt_cfg;                               /*  0x5020 */
1393         u32 mii_mgmt_cmd;                               /*  0x5024 */
1394         u32 mii_mgmt_addr;                              /*  0x5028 */
1395         u32 mii_mgmt_ctrl;                              /*  0x502C */
1396         u32 mii_mgmt_stat;                              /*  0x5030 */
1397         u32 mii_mgmt_indicator;                         /*  0x5034 */
1398         u32 if_ctrl;                                    /*  0x5038 */
1399         MAC_IF_STAT_t if_stat;                          /*  0x503C */
1400         MAC_STATION_ADDR1_t station_addr_1;             /*  0x5040 */
1401         MAC_STATION_ADDR2_t station_addr_2;             /*  0x5044 */
1402 } MAC_t, *PMAC_t;
1403
1404 /* END OF MAC REGISTER ADDRESS MAP */
1405
1406 /* START OF MAC STAT REGISTER ADDRESS MAP */
1407
1408 /*
1409  * structure for Carry Register One and it's Mask Register reg located in mac
1410  * stat address map address 0x6130 and 0x6138.
1411  *
1412  * 31: tr64
1413  * 30: tr127
1414  * 29: tr255
1415  * 28: tr511
1416  * 27: tr1k
1417  * 26: trmax
1418  * 25: trmgv
1419  * 24-17: unused
1420  * 16: rbyt
1421  * 15: rpkt
1422  * 14: rfcs
1423  * 13: rmca
1424  * 12: rbca
1425  * 11: rxcf
1426  * 10: rxpf
1427  * 9: rxuo
1428  * 8: raln
1429  * 7: rflr
1430  * 6: rcde
1431  * 5: rcse
1432  * 4: rund
1433  * 3: rovr
1434  * 2: rfrg
1435  * 1: rjbr
1436  * 0: rdrp
1437  */
1438
1439 /*
1440  * structure for Carry Register Two Mask Register reg in mac stat address map.
1441  * located at address 0x613C
1442  *
1443  * 31-20: unused
1444  * 19: tjbr
1445  * 18: tfcs
1446  * 17: txcf
1447  * 16: tovr
1448  * 15: tund
1449  * 14: trfg
1450  * 13: tbyt
1451  * 12: tpkt
1452  * 11: tmca
1453  * 10: tbca
1454  * 9: txpf
1455  * 8: tdfr
1456  * 7: tedf
1457  * 6: tscl
1458  * 5: tmcl
1459  * 4: tlcl
1460  * 3: txcl
1461  * 2: tncl
1462  * 1: tpfh
1463  * 0: tdrp
1464  */
1465
1466 /*
1467  * MAC STATS Module of JAGCore Address Mapping
1468  */
1469 typedef struct _MAC_STAT_t {            /* Location: */
1470         u32 pad[32];            /*  0x6000 - 607C */
1471
1472         /* Tx/Rx 0-64 Byte Frame Counter */
1473         u32 TR64;                       /*  0x6080 */
1474
1475         /* Tx/Rx 65-127 Byte Frame Counter */
1476         u32 TR127;                      /*  0x6084 */
1477
1478         /* Tx/Rx 128-255 Byte Frame Counter */
1479         u32 TR255;                      /*  0x6088 */
1480
1481         /* Tx/Rx 256-511 Byte Frame Counter */
1482         u32 TR511;                      /*  0x608C */
1483
1484         /* Tx/Rx 512-1023 Byte Frame Counter */
1485         u32 TR1K;                       /*  0x6090 */
1486
1487         /* Tx/Rx 1024-1518 Byte Frame Counter */
1488         u32 TRMax;                      /*  0x6094 */
1489
1490         /* Tx/Rx 1519-1522 Byte Good VLAN Frame Count */
1491         u32 TRMgv;                      /*  0x6098 */
1492
1493         /* Rx Byte Counter */
1494         u32 RByt;                       /*  0x609C */
1495
1496         /* Rx Packet Counter */
1497         u32 RPkt;                       /*  0x60A0 */
1498
1499         /* Rx FCS Error Counter */
1500         u32 RFcs;                       /*  0x60A4 */
1501
1502         /* Rx Multicast Packet Counter */
1503         u32 RMca;                       /*  0x60A8 */
1504
1505         /* Rx Broadcast Packet Counter */
1506         u32 RBca;                       /*  0x60AC */
1507
1508         /* Rx Control Frame Packet Counter */
1509         u32 RxCf;                       /*  0x60B0 */
1510
1511         /* Rx Pause Frame Packet Counter */
1512         u32 RxPf;                       /*  0x60B4 */
1513
1514         /* Rx Unknown OP Code Counter */
1515         u32 RxUo;                       /*  0x60B8 */
1516
1517         /* Rx Alignment Error Counter */
1518         u32 RAln;                       /*  0x60BC */
1519
1520         /* Rx Frame Length Error Counter */
1521         u32 RFlr;                       /*  0x60C0 */
1522
1523         /* Rx Code Error Counter */
1524         u32 RCde;                       /*  0x60C4 */
1525
1526         /* Rx Carrier Sense Error Counter */
1527         u32 RCse;                       /*  0x60C8 */
1528
1529         /* Rx Undersize Packet Counter */
1530         u32 RUnd;                       /*  0x60CC */
1531
1532         /* Rx Oversize Packet Counter */
1533         u32 ROvr;                       /*  0x60D0 */
1534
1535         /* Rx Fragment Counter */
1536         u32 RFrg;                       /*  0x60D4 */
1537
1538         /* Rx Jabber Counter */
1539         u32 RJbr;                       /*  0x60D8 */
1540
1541         /* Rx Drop */
1542         u32 RDrp;                       /*  0x60DC */
1543
1544         /* Tx Byte Counter */
1545         u32 TByt;                       /*  0x60E0 */
1546
1547         /* Tx Packet Counter */
1548         u32 TPkt;                       /*  0x60E4 */
1549
1550         /* Tx Multicast Packet Counter */
1551         u32 TMca;                       /*  0x60E8 */
1552
1553         /* Tx Broadcast Packet Counter */
1554         u32 TBca;                       /*  0x60EC */
1555
1556         /* Tx Pause Control Frame Counter */
1557         u32 TxPf;                       /*  0x60F0 */
1558
1559         /* Tx Deferral Packet Counter */
1560         u32 TDfr;                       /*  0x60F4 */
1561
1562         /* Tx Excessive Deferral Packet Counter */
1563         u32 TEdf;                       /*  0x60F8 */
1564
1565         /* Tx Single Collision Packet Counter */
1566         u32 TScl;                       /*  0x60FC */
1567
1568         /* Tx Multiple Collision Packet Counter */
1569         u32 TMcl;                       /*  0x6100 */
1570
1571         /* Tx Late Collision Packet Counter */
1572         u32 TLcl;                       /*  0x6104 */
1573
1574         /* Tx Excessive Collision Packet Counter */
1575         u32 TXcl;                       /*  0x6108 */
1576
1577         /* Tx Total Collision Packet Counter */
1578         u32 TNcl;                       /*  0x610C */
1579
1580         /* Tx Pause Frame Honored Counter */
1581         u32 TPfh;                       /*  0x6110 */
1582
1583         /* Tx Drop Frame Counter */
1584         u32 TDrp;                       /*  0x6114 */
1585
1586         /* Tx Jabber Frame Counter */
1587         u32 TJbr;                       /*  0x6118 */
1588
1589         /* Tx FCS Error Counter */
1590         u32 TFcs;                       /*  0x611C */
1591
1592         /* Tx Control Frame Counter */
1593         u32 TxCf;                       /*  0x6120 */
1594
1595         /* Tx Oversize Frame Counter */
1596         u32 TOvr;                       /*  0x6124 */
1597
1598         /* Tx Undersize Frame Counter */
1599         u32 TUnd;                       /*  0x6128 */
1600
1601         /* Tx Fragments Frame Counter */
1602         u32 TFrg;                       /*  0x612C */
1603
1604         /* Carry Register One Register */
1605         u32 Carry1;                     /*  0x6130 */
1606
1607         /* Carry Register Two Register */
1608         u32 Carry2;                     /*  0x6134 */
1609
1610         /* Carry Register One Mask Register */
1611         u32 Carry1M;                    /*  0x6138 */
1612
1613         /* Carry Register Two Mask Register */
1614         u32 Carry2M;                    /*  0x613C */
1615 } MAC_STAT_t, *PMAC_STAT_t;
1616
1617 /* END OF MAC STAT REGISTER ADDRESS MAP */
1618
1619
1620 /* START OF MMC REGISTER ADDRESS MAP */
1621
1622 /*
1623  * Main Memory Controller Control reg in mmc address map.
1624  * located at address 0x7000
1625  */
1626
1627 #define ET_MMC_ENABLE           1
1628 #define ET_MMC_ARB_DISABLE      2
1629 #define ET_MMC_RXMAC_DISABLE    4
1630 #define ET_MMC_TXMAC_DISABLE    8
1631 #define ET_MMC_TXDMA_DISABLE    16
1632 #define ET_MMC_RXDMA_DISABLE    32
1633 #define ET_MMC_FORCE_CE         64
1634
1635 /*
1636  * Main Memory Controller Host Memory Access Address reg in mmc
1637  * address map.  Located at address 0x7004. Top 16 bits hold the address bits
1638  */
1639
1640 #define ET_SRAM_REQ_ACCESS      1
1641 #define ET_SRAM_WR_ACCESS       2
1642 #define ET_SRAM_IS_CTRL         4
1643
1644 /*
1645  * structure for Main Memory Controller Host Memory Access Data reg in mmc
1646  * address map.  Located at address 0x7008 - 0x7014
1647  * Defined earlier (u32)
1648  */
1649
1650 /*
1651  * Memory Control Module of JAGCore Address Mapping
1652  */
1653 typedef struct _MMC_t {                 /* Location: */
1654         u32 mmc_ctrl;           /*  0x7000 */
1655         u32 sram_access;        /*  0x7004 */
1656         u32 sram_word1;         /*  0x7008 */
1657         u32 sram_word2;         /*  0x700C */
1658         u32 sram_word3;         /*  0x7010 */
1659         u32 sram_word4;         /*  0x7014 */
1660 } MMC_t, *PMMC_t;
1661
1662 /* END OF MMC REGISTER ADDRESS MAP */
1663
1664
1665 /*
1666  * JAGCore Address Mapping
1667  */
1668 typedef struct _ADDRESS_MAP_t {
1669         GLOBAL_t global;
1670         /* unused section of global address map */
1671         u8 unused_global[4096 - sizeof(GLOBAL_t)];
1672         TXDMA_t txdma;
1673         /* unused section of txdma address map */
1674         u8 unused_txdma[4096 - sizeof(TXDMA_t)];
1675         struct rxdma_regs rxdma;
1676         /* unused section of rxdma address map */
1677         u8 unused_rxdma[4096 - sizeof(struct rxdma_regs)];
1678         TXMAC_t txmac;
1679         /* unused section of txmac address map */
1680         u8 unused_txmac[4096 - sizeof(TXMAC_t)];
1681         RXMAC_t rxmac;
1682         /* unused section of rxmac address map */
1683         u8 unused_rxmac[4096 - sizeof(RXMAC_t)];
1684         MAC_t mac;
1685         /* unused section of mac address map */
1686         u8 unused_mac[4096 - sizeof(MAC_t)];
1687         MAC_STAT_t macStat;
1688         /* unused section of mac stat address map */
1689         u8 unused_mac_stat[4096 - sizeof(MAC_STAT_t)];
1690         MMC_t mmc;
1691         /* unused section of mmc address map */
1692         u8 unused_mmc[4096 - sizeof(MMC_t)];
1693         /* unused section of address map */
1694         u8 unused_[1015808];
1695
1696         u8 unused_exp_rom[4096];        /* MGS-size TBD */
1697         u8 unused__[524288];    /* unused section of address map */
1698 } ADDRESS_MAP_t, *PADDRESS_MAP_t;
1699
1700 #endif /* _ET1310_ADDRESS_MAP_H_ */