arch/ppc/kernel/traps.c

   1 /*
   2  *  arch/ppc/kernel/traps.c
   3  *
   4  *  Copyright (C) 1995-1996  Gary Thomas (gdt@linuxppc.org)
   5  *
   6  *  This program is free software; you can redistribute it and/or
   7  *  modify it under the terms of the GNU General Public License
   8  *  as published by the Free Software Foundation; either version
   9  *  2 of the License, or (at your option) any later version.
  10  *
  11  *  Modified by Cort Dougan (cort@cs.nmt.edu)
  12  *  and Paul Mackerras (paulus@cs.anu.edu.au)
  13  */
  14
  15 /*
  16  * This file handles the architecture-dependent parts of hardware exceptions
  17  */
  18
  19 #include <linux/errno.h>
  20 #include <linux/sched.h>
  21 #include <linux/kernel.h>
  22 #include <linux/mm.h>
  23 #include <linux/stddef.h>
  24 #include <linux/unistd.h>
  25 #include <linux/ptrace.h>
  26 #include <linux/slab.h>
  27 #include <linux/user.h>
  28 #include <linux/a.out.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/config.h>
  31 #include <linux/init.h>
  32 #include <linux/module.h>
  33 #include <linux/prctl.h>
  34
  35 #include <asm/pgtable.h>
  36 #include <asm/uaccess.h>
  37 #include <asm/system.h>
  38 #include <asm/io.h>
  39 #include <asm/reg.h>
  40 #include <asm/xmon.h>
  41 #ifdef CONFIG_PMAC_BACKLIGHT
  42 #include <asm/backlight.h>
  43 #endif
  44 #include <asm/perfmon.h>
  45
  46 #ifdef CONFIG_XMON
  47 void (*debugger)(struct pt_regs *regs) = xmon;
  48 int (*debugger_bpt)(struct pt_regs *regs) = xmon_bpt;
  49 int (*debugger_sstep)(struct pt_regs *regs) = xmon_sstep;
  50 int (*debugger_iabr_match)(struct pt_regs *regs) = xmon_iabr_match;
  51 int (*debugger_dabr_match)(struct pt_regs *regs) = xmon_dabr_match;
  52 void (*debugger_fault_handler)(struct pt_regs *regs);
  53 #else
  54 #ifdef CONFIG_KGDB
  55 void (*debugger)(struct pt_regs *regs);
  56 int (*debugger_bpt)(struct pt_regs *regs);
  57 int (*debugger_sstep)(struct pt_regs *regs);
  58 int (*debugger_iabr_match)(struct pt_regs *regs);
  59 int (*debugger_dabr_match)(struct pt_regs *regs);
  60 void (*debugger_fault_handler)(struct pt_regs *regs);
  61 #else
  62 #define debugger(regs)                  do { } while (0)
  63 #define debugger_bpt(regs)              0
  64 #define debugger_sstep(regs)            0
  65 #define debugger_iabr_match(regs)       0
  66 #define debugger_dabr_match(regs)       0
  67 #define debugger_fault_handler          ((void (*)(struct pt_regs *))0)
  68 #endif
  69 #endif
  70
  71 /*
  72  * Trap & Exception support
  73  */
  74
  75 DEFINE_SPINLOCK(die_lock);
  76
  77 void die(const char * str, struct pt_regs * fp, long err)
  78 {
  79         static int die_counter;
  80         int nl = 0;
  81         console_verbose();
  82         spin_lock_irq(&die_lock);
  83 #ifdef CONFIG_PMAC_BACKLIGHT
  84         if (_machine == _MACH_Pmac) {
  85                 set_backlight_enable(1);
  86                 set_backlight_level(BACKLIGHT_MAX);
  87         }
  88 #endif
  89         printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter);
  90 #ifdef CONFIG_PREEMPT
  91         printk("PREEMPT ");
  92         nl = 1;
  93 #endif
  94 #ifdef CONFIG_SMP
  95         printk("SMP NR_CPUS=%d ", NR_CPUS);
  96         nl = 1;
  97 #endif
  98         if (nl)
  99                 printk("\n");
 100         show_regs(fp);
 101         spin_unlock_irq(&die_lock);
 102         /* do_exit() should take care of panic'ing from an interrupt
 103          * context so we don't handle it here
 104          */
 105         do_exit(err);
 106 }
 107
 108 void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr)
 109 {
 110         siginfo_t info;
 111
 112         if (!user_mode(regs)) {
 113                 debugger(regs);
 114                 die("Exception in kernel mode", regs, signr);
 115         }
 116         info.si_signo = signr;
 117         info.si_errno = 0;
 118         info.si_code = code;
 119         info.si_addr = (void __user *) addr;
 120         force_sig_info(signr, &info, current);
 121
 122         /*
 123          * Init gets no signals that it doesn't have a handler for.
 124          * That's all very well, but if it has caused a synchronous
 125          * exception and we ignore the resulting signal, it will just
 126          * generate the same exception over and over again and we get
 127          * nowhere.  Better to kill it and let the kernel panic.
 128          */
 129         if (current->pid == 1) {
 130                 __sighandler_t handler;
 131
 132                 spin_lock_irq(&current->sighand->siglock);
 133                 handler = current->sighand->action[signr-1].sa.sa_handler;
 134                 spin_unlock_irq(&current->sighand->siglock);
 135                 if (handler == SIG_DFL) {
 136                         /* init has generated a synchronous exception
 137                            and it doesn't have a handler for the signal */
 138                         printk(KERN_CRIT "init has generated signal %d "
 139                                "but has no handler for it\n", signr);
 140                         do_exit(signr);
 141                 }
 142         }
 143 }
 144
 145 /*
 146  * I/O accesses can cause machine checks on powermacs.
 147  * Check if the NIP corresponds to the address of a sync
 148  * instruction for which there is an entry in the exception
 149  * table.
 150  * Note that the 601 only takes a machine check on TEA
 151  * (transfer error ack) signal assertion, and does not
 152  * set any of the top 16 bits of SRR1.
 153  *  -- paulus.
 154  */
 155 static inline int check_io_access(struct pt_regs *regs)
 156 {
 157 #ifdef CONFIG_PPC_PMAC
 158         unsigned long msr = regs->msr;
 159         const struct exception_table_entry *entry;
 160         unsigned int *nip = (unsigned int *)regs->nip;
 161
 162         if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000)))
 163             && (entry = search_exception_tables(regs->nip)) != NULL) {
 164                 /*
 165                  * Check that it's a sync instruction, or somewhere
 166                  * in the twi; isync; nop sequence that inb/inw/inl uses.
 167                  * As the address is in the exception table
 168                  * we should be able to read the instr there.
 169                  * For the debug message, we look at the preceding
 170                  * load or store.
 171                  */
 172                 if (*nip == 0x60000000)         /* nop */
 173                         nip -= 2;
 174                 else if (*nip == 0x4c00012c)    /* isync */
 175                         --nip;
 176                 if (*nip == 0x7c0004ac || (*nip >> 26) == 3) {
 177                         /* sync or twi */
 178                         unsigned int rb;
 179
 180                         --nip;
 181                         rb = (*nip >> 11) & 0x1f;
 182                         printk(KERN_DEBUG "%s bad port %lx at %p\n",
 183                                (*nip & 0x100)? "OUT to": "IN from",
 184                                regs->gpr[rb] - _IO_BASE, nip);
 185                         regs->msr |= MSR_RI;
 186                         regs->nip = entry->fixup;
 187                         return 1;
 188                 }
 189         }
 190 #endif /* CONFIG_PPC_PMAC */
 191         return 0;
 192 }
 193
 194 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
 195 /* On 4xx, the reason for the machine check or program exception
 196    is in the ESR. */
 197 #define get_reason(regs)        ((regs)->dsisr)
 198 #ifndef CONFIG_FSL_BOOKE
 199 #define get_mc_reason(regs)     ((regs)->dsisr)
 200 #else
 201 #define get_mc_reason(regs)     (mfspr(SPRN_MCSR))
 202 #endif
 203 #define REASON_FP               ESR_FP
 204 #define REASON_ILLEGAL          (ESR_PIL | ESR_PUO)
 205 #define REASON_PRIVILEGED       ESR_PPR
 206 #define REASON_TRAP             ESR_PTR
 207
 208 /* single-step stuff */
 209 #define single_stepping(regs)   (current->thread.dbcr0 & DBCR0_IC)
 210 #define clear_single_step(regs) (current->thread.dbcr0 &= ~DBCR0_IC)
 211
 212 #else
 213 /* On non-4xx, the reason for the machine check or program
 214    exception is in the MSR. */
 215 #define get_reason(regs)        ((regs)->msr)
 216 #define get_mc_reason(regs)     ((regs)->msr)
 217 #define REASON_FP               0x100000
 218 #define REASON_ILLEGAL          0x80000
 219 #define REASON_PRIVILEGED       0x40000
 220 #define REASON_TRAP             0x20000
 221
 222 #define single_stepping(regs)   ((regs)->msr & MSR_SE)
 223 #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE)
 224 #endif
 225
 226 /*
 227  * This is "fall-back" implementation for configurations
 228  * which don't provide platform-specific machine check info
 229  */
 230 void __attribute__ ((weak))
 231 platform_machine_check(struct pt_regs *regs)
 232 {
 233 }
 234
 235 void MachineCheckException(struct pt_regs *regs)
 236 {
 237         unsigned long reason = get_mc_reason(regs);
 238
 239         if (user_mode(regs)) {
 240                 regs->msr |= MSR_RI;
 241                 _exception(SIGBUS, regs, BUS_ADRERR, regs->nip);
 242                 return;
 243         }
 244
 245 #if defined(CONFIG_8xx) && defined(CONFIG_PCI)
 246         /* the qspan pci read routines can cause machine checks -- Cort */
 247         bad_page_fault(regs, regs->dar, SIGBUS);
 248         return;
 249 #endif
 250
 251         if (debugger_fault_handler) {
 252                 debugger_fault_handler(regs);
 253                 regs->msr |= MSR_RI;
 254                 return;
 255         }
 256
 257         if (check_io_access(regs))
 258                 return;
 259
 260 #if defined(CONFIG_4xx) && !defined(CONFIG_440A)
 261         if (reason & ESR_IMCP) {
 262                 printk("Instruction");
 263                 mtspr(SPRN_ESR, reason & ~ESR_IMCP);
 264         } else
 265                 printk("Data");
 266         printk(" machine check in kernel mode.\n");
 267 #elif defined(CONFIG_440A)
 268         printk("Machine check in kernel mode.\n");
 269         if (reason & ESR_IMCP){
 270                 printk("Instruction Synchronous Machine Check exception\n");
 271                 mtspr(SPRN_ESR, reason & ~ESR_IMCP);
 272         }
 273         else {
 274                 u32 mcsr = mfspr(SPRN_MCSR);
 275                 if (mcsr & MCSR_IB)
 276                         printk("Instruction Read PLB Error\n");
 277                 if (mcsr & MCSR_DRB)
 278                         printk("Data Read PLB Error\n");
 279                 if (mcsr & MCSR_DWB)
 280                         printk("Data Write PLB Error\n");
 281                 if (mcsr & MCSR_TLBP)
 282                         printk("TLB Parity Error\n");
 283                 if (mcsr & MCSR_ICP){
 284                         flush_instruction_cache();
 285                         printk("I-Cache Parity Error\n");
 286                 }
 287                 if (mcsr & MCSR_DCSP)
 288                         printk("D-Cache Search Parity Error\n");
 289                 if (mcsr & MCSR_DCFP)
 290                         printk("D-Cache Flush Parity Error\n");
 291                 if (mcsr & MCSR_IMPE)
 292                         printk("Machine Check exception is imprecise\n");
 293
 294                 /* Clear MCSR */
 295                 mtspr(SPRN_MCSR, mcsr);
 296         }
 297 #elif defined (CONFIG_E500)
 298         printk("Machine check in kernel mode.\n");
 299         printk("Caused by (from MCSR=%lx): ", reason);
 300
 301         if (reason & MCSR_MCP)
 302                 printk("Machine Check Signal\n");
 303         if (reason & MCSR_ICPERR)
 304                 printk("Instruction Cache Parity Error\n");
 305         if (reason & MCSR_DCP_PERR)
 306                 printk("Data Cache Push Parity Error\n");
 307         if (reason & MCSR_DCPERR)
 308                 printk("Data Cache Parity Error\n");
 309         if (reason & MCSR_GL_CI)
 310                 printk("Guarded Load or Cache-Inhibited stwcx.\n");
 311         if (reason & MCSR_BUS_IAERR)
 312                 printk("Bus - Instruction Address Error\n");
 313         if (reason & MCSR_BUS_RAERR)
 314                 printk("Bus - Read Address Error\n");
 315         if (reason & MCSR_BUS_WAERR)
 316                 printk("Bus - Write Address Error\n");
 317         if (reason & MCSR_BUS_IBERR)
 318                 printk("Bus - Instruction Data Error\n");
 319         if (reason & MCSR_BUS_RBERR)
 320                 printk("Bus - Read Data Bus Error\n");
 321         if (reason & MCSR_BUS_WBERR)
 322                 printk("Bus - Read Data Bus Error\n");
 323         if (reason & MCSR_BUS_IPERR)
 324                 printk("Bus - Instruction Parity Error\n");
 325         if (reason & MCSR_BUS_RPERR)
 326                 printk("Bus - Read Parity Error\n");
 327 #elif defined (CONFIG_E200)
 328         printk("Machine check in kernel mode.\n");
 329         printk("Caused by (from MCSR=%lx): ", reason);
 330
 331         if (reason & MCSR_MCP)
 332                 printk("Machine Check Signal\n");
 333         if (reason & MCSR_CP_PERR)
 334                 printk("Cache Push Parity Error\n");
 335         if (reason & MCSR_CPERR)
 336                 printk("Cache Parity Error\n");
 337         if (reason & MCSR_EXCP_ERR)
 338                 printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n");
 339         if (reason & MCSR_BUS_IRERR)
 340                 printk("Bus - Read Bus Error on instruction fetch\n");
 341         if (reason & MCSR_BUS_DRERR)
 342                 printk("Bus - Read Bus Error on data load\n");
 343         if (reason & MCSR_BUS_WRERR)
 344                 printk("Bus - Write Bus Error on buffered store or cache line push\n");
 345 #else /* !CONFIG_4xx && !CONFIG_E500 && !CONFIG_E200 */
 346         printk("Machine check in kernel mode.\n");
 347         printk("Caused by (from SRR1=%lx): ", reason);
 348         switch (reason & 0x601F0000) {
 349         case 0x80000:
 350                 printk("Machine check signal\n");
 351                 break;
 352         case 0:         /* for 601 */
 353         case 0x40000:
 354         case 0x140000:  /* 7450 MSS error and TEA */
 355                 printk("Transfer error ack signal\n");
 356                 break;
 357         case 0x20000:
 358                 printk("Data parity error signal\n");
 359                 break;
 360         case 0x10000:
 361                 printk("Address parity error signal\n");
 362                 break;
 363         case 0x20000000:
 364                 printk("L1 Data Cache error\n");
 365                 break;
 366         case 0x40000000:
 367                 printk("L1 Instruction Cache error\n");
 368                 break;
 369         case 0x00100000:
 370                 printk("L2 data cache parity error\n");
 371                 break;
 372         default:
 373                 printk("Unknown values in msr\n");
 374         }
 375 #endif /* CONFIG_4xx */
 376
 377         /*
 378          * Optional platform-provided routine to print out
 379          * additional info, e.g. bus error registers.
 380          */
 381         platform_machine_check(regs);
 382
 383         debugger(regs);
 384         die("machine check", regs, SIGBUS);
 385 }
 386
 387 void SMIException(struct pt_regs *regs)
 388 {
 389         debugger(regs);
 390 #if !(defined(CONFIG_XMON) || defined(CONFIG_KGDB))
 391         show_regs(regs);
 392         panic("System Management Interrupt");
 393 #endif
 394 }
 395
 396 void UnknownException(struct pt_regs *regs)
 397 {
 398         printk("Bad trap at PC: %lx, MSR: %lx, vector=%lx    %s\n",
 399                regs->nip, regs->msr, regs->trap, print_tainted());
 400         _exception(SIGTRAP, regs, 0, 0);
 401 }
 402
 403 void InstructionBreakpoint(struct pt_regs *regs)
 404 {
 405         if (debugger_iabr_match(regs))
 406                 return;
 407         _exception(SIGTRAP, regs, TRAP_BRKPT, 0);
 408 }
 409
 410 void RunModeException(struct pt_regs *regs)
 411 {
 412         _exception(SIGTRAP, regs, 0, 0);
 413 }
 414
 415 /* Illegal instruction emulation support.  Originally written to
 416  * provide the PVR to user applications using the mfspr rd, PVR.
 417  * Return non-zero if we can't emulate, or -EFAULT if the associated
 418  * memory access caused an access fault.  Return zero on success.
 419  *
 420  * There are a couple of ways to do this, either "decode" the instruction
 421  * or directly match lots of bits.  In this case, matching lots of
 422  * bits is faster and easier.
 423  *
 424  */
 425 #define INST_MFSPR_PVR          0x7c1f42a6
 426 #define INST_MFSPR_PVR_MASK     0xfc1fffff
 427
 428 #define INST_DCBA               0x7c0005ec
 429 #define INST_DCBA_MASK          0x7c0007fe
 430
 431 #define INST_MCRXR              0x7c000400
 432 #define INST_MCRXR_MASK         0x7c0007fe
 433
 434 #define INST_STRING             0x7c00042a
 435 #define INST_STRING_MASK        0x7c0007fe
 436 #define INST_STRING_GEN_MASK    0x7c00067e
 437 #define INST_LSWI               0x7c0004aa
 438 #define INST_LSWX               0x7c00042a
 439 #define INST_STSWI              0x7c0005aa
 440 #define INST_STSWX              0x7c00052a
 441
 442 static int emulate_string_inst(struct pt_regs *regs, u32 instword)
 443 {
 444         u8 rT = (instword >> 21) & 0x1f;
 445         u8 rA = (instword >> 16) & 0x1f;
 446         u8 NB_RB = (instword >> 11) & 0x1f;
 447         u32 num_bytes;
 448         unsigned long EA;
 449         int pos = 0;
 450
 451         /* Early out if we are an invalid form of lswx */
 452         if ((instword & INST_STRING_MASK) == INST_LSWX)
 453                 if ((rT == rA) || (rT == NB_RB))
 454                         return -EINVAL;
 455
 456         EA = (rA == 0) ? 0 : regs->gpr[rA];
 457
 458         switch (instword & INST_STRING_MASK) {
 459                 case INST_LSWX:
 460                 case INST_STSWX:
 461                         EA += NB_RB;
 462                         num_bytes = regs->xer & 0x7f;
 463                         break;
 464                 case INST_LSWI:
 465                 case INST_STSWI:
 466                         num_bytes = (NB_RB == 0) ? 32 : NB_RB;
 467                         break;
 468                 default:
 469                         return -EINVAL;
 470         }
 471
 472         while (num_bytes != 0)
 473         {
 474                 u8 val;
 475                 u32 shift = 8 * (3 - (pos & 0x3));
 476
 477                 switch ((instword & INST_STRING_MASK)) {
 478                         case INST_LSWX:
 479                         case INST_LSWI:
 480                                 if (get_user(val, (u8 __user *)EA))
 481                                         return -EFAULT;
 482                                 /* first time updating this reg,
 483                                  * zero it out */
 484                                 if (pos == 0)
 485                                         regs->gpr[rT] = 0;
 486                                 regs->gpr[rT] |= val << shift;
 487                                 break;
 488                         case INST_STSWI:
 489                         case INST_STSWX:
 490                                 val = regs->gpr[rT] >> shift;
 491                                 if (put_user(val, (u8 __user *)EA))
 492                                         return -EFAULT;
 493                                 break;
 494                 }
 495                 /* move EA to next address */
 496                 EA += 1;
 497                 num_bytes--;
 498
 499                 /* manage our position within the register */
 500                 if (++pos == 4) {
 501                         pos = 0;
 502                         if (++rT == 32)
 503                                 rT = 0;
 504                 }
 505         }
 506
 507         return 0;
 508 }
 509
 510 static int emulate_instruction(struct pt_regs *regs)
 511 {
 512         u32 instword;
 513         u32 rd;
 514
 515         if (!user_mode(regs))
 516                 return -EINVAL;
 517         CHECK_FULL_REGS(regs);
 518
 519         if (get_user(instword, (u32 __user *)(regs->nip)))
 520                 return -EFAULT;
 521
 522         /* Emulate the mfspr rD, PVR.
 523          */
 524         if ((instword & INST_MFSPR_PVR_MASK) == INST_MFSPR_PVR) {
 525                 rd = (instword >> 21) & 0x1f;
 526                 regs->gpr[rd] = mfspr(SPRN_PVR);
 527                 return 0;
 528         }
 529
 530         /* Emulating the dcba insn is just a no-op.  */
 531         if ((instword & INST_DCBA_MASK) == INST_DCBA)
 532                 return 0;
 533
 534         /* Emulate the mcrxr insn.  */
 535         if ((instword & INST_MCRXR_MASK) == INST_MCRXR) {
 536                 int shift = (instword >> 21) & 0x1c;
 537                 unsigned long msk = 0xf0000000UL >> shift;
 538
 539                 regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk);
 540                 regs->xer &= ~0xf0000000UL;
 541                 return 0;
 542         }
 543
 544         /* Emulate load/store string insn. */
 545         if ((instword & INST_STRING_GEN_MASK) == INST_STRING)
 546                 return emulate_string_inst(regs, instword);
 547
 548         return -EINVAL;
 549 }
 550
 551 /*
 552  * After we have successfully emulated an instruction, we have to
 553  * check if the instruction was being single-stepped, and if so,
 554  * pretend we got a single-step exception.  This was pointed out
 555  * by Kumar Gala.  -- paulus
 556  */
 557 static void emulate_single_step(struct pt_regs *regs)
 558 {
 559         if (single_stepping(regs)) {
 560                 clear_single_step(regs);
 561                 _exception(SIGTRAP, regs, TRAP_TRACE, 0);
 562         }
 563 }
 564
 565 /*
 566  * Look through the list of trap instructions that are used for BUG(),
 567  * BUG_ON() and WARN_ON() and see if we hit one.  At this point we know
 568  * that the exception was caused by a trap instruction of some kind.
 569  * Returns 1 if we should continue (i.e. it was a WARN_ON) or 0
 570  * otherwise.
 571  */
 572 extern struct bug_entry __start___bug_table[], __stop___bug_table[];
 573
 574 #ifndef CONFIG_MODULES
 575 #define module_find_bug(x)      NULL
 576 #endif
 577
 578 struct bug_entry *find_bug(unsigned long bugaddr)
 579 {
 580         struct bug_entry *bug;
 581
 582         for (bug = __start___bug_table; bug < __stop___bug_table; ++bug)
 583                 if (bugaddr == bug->bug_addr)
 584                         return bug;
 585         return module_find_bug(bugaddr);
 586 }
 587
 588 int check_bug_trap(struct pt_regs *regs)
 589 {
 590         struct bug_entry *bug;
 591         unsigned long addr;
 592
 593         if (regs->msr & MSR_PR)
 594                 return 0;       /* not in kernel */
 595         addr = regs->nip;       /* address of trap instruction */
 596         if (addr < PAGE_OFFSET)
 597                 return 0;
 598         bug = find_bug(regs->nip);
 599         if (bug == NULL)
 600                 return 0;
 601         if (bug->line & BUG_WARNING_TRAP) {
 602                 /* this is a WARN_ON rather than BUG/BUG_ON */
 603 #ifdef CONFIG_XMON
 604                 xmon_printf(KERN_ERR "Badness in %s at %s:%d\n",
 605                        bug->function, bug->file,
 606                        bug->line & ~BUG_WARNING_TRAP);
 607 #endif /* CONFIG_XMON */
 608                 printk(KERN_ERR "Badness in %s at %s:%d\n",
 609                        bug->function, bug->file,
 610                        bug->line & ~BUG_WARNING_TRAP);
 611                 dump_stack();
 612                 return 1;
 613         }
 614 #ifdef CONFIG_XMON
 615         xmon_printf(KERN_CRIT "kernel BUG in %s at %s:%d!\n",
 616                bug->function, bug->file, bug->line);
 617         xmon(regs);
 618 #endif /* CONFIG_XMON */
 619         printk(KERN_CRIT "kernel BUG in %s at %s:%d!\n",
 620                bug->function, bug->file, bug->line);
 621
 622         return 0;
 623 }
 624
 625 void ProgramCheckException(struct pt_regs *regs)
 626 {
 627         unsigned int reason = get_reason(regs);
 628         extern int do_mathemu(struct pt_regs *regs);
 629
 630 #ifdef CONFIG_MATH_EMULATION
 631         /* (reason & REASON_ILLEGAL) would be the obvious thing here,
 632          * but there seems to be a hardware bug on the 405GP (RevD)
 633          * that means ESR is sometimes set incorrectly - either to
 634          * ESR_DST (!?) or 0.  In the process of chasing this with the
 635          * hardware people - not sure if it can happen on any illegal
 636          * instruction or only on FP instructions, whether there is a
 637          * pattern to occurences etc. -dgibson 31/Mar/2003 */
 638         if (!(reason & REASON_TRAP) && do_mathemu(regs) == 0) {
 639                 emulate_single_step(regs);
 640                 return;
 641         }
 642 #endif /* CONFIG_MATH_EMULATION */
 643
 644         if (reason & REASON_FP) {
 645                 /* IEEE FP exception */
 646                 int code = 0;
 647                 u32 fpscr;
 648
 649                 /* We must make sure the FP state is consistent with
 650                  * our MSR_FP in regs
 651                  */
 652                 preempt_disable();
 653                 if (regs->msr & MSR_FP)
 654                         giveup_fpu(current);
 655                 preempt_enable();
 656
 657                 fpscr = current->thread.fpscr;
 658                 fpscr &= fpscr << 22;   /* mask summary bits with enables */
 659                 if (fpscr & FPSCR_VX)
 660                         code = FPE_FLTINV;
 661                 else if (fpscr & FPSCR_OX)
 662                         code = FPE_FLTOVF;
 663                 else if (fpscr & FPSCR_UX)
 664                         code = FPE_FLTUND;
 665                 else if (fpscr & FPSCR_ZX)
 666                         code = FPE_FLTDIV;
 667                 else if (fpscr & FPSCR_XX)
 668                         code = FPE_FLTRES;
 669                 _exception(SIGFPE, regs, code, regs->nip);
 670                 return;
 671         }
 672
 673         if (reason & REASON_TRAP) {
 674                 /* trap exception */
 675                 if (debugger_bpt(regs))
 676                         return;
 677                 if (check_bug_trap(regs)) {
 678                         regs->nip += 4;
 679                         return;
 680                 }
 681                 _exception(SIGTRAP, regs, TRAP_BRKPT, 0);
 682                 return;
 683         }
 684
 685         /* Try to emulate it if we should. */
 686         if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) {
 687                 switch (emulate_instruction(regs)) {
 688                 case 0:
 689                         regs->nip += 4;
 690                         emulate_single_step(regs);
 691                         return;
 692                 case -EFAULT:
 693                         _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
 694                         return;
 695                 }
 696         }
 697
 698         if (reason & REASON_PRIVILEGED)
 699                 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
 700         else
 701                 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
 702 }
 703
 704 void SingleStepException(struct pt_regs *regs)
 705 {
 706         regs->msr &= ~(MSR_SE | MSR_BE);  /* Turn off 'trace' bits */
 707         if (debugger_sstep(regs))
 708                 return;
 709         _exception(SIGTRAP, regs, TRAP_TRACE, 0);
 710 }
 711
 712 void AlignmentException(struct pt_regs *regs)
 713 {
 714         int fixed;
 715
 716         fixed = fix_alignment(regs);
 717         if (fixed == 1) {
 718                 regs->nip += 4; /* skip over emulated instruction */
 719                 emulate_single_step(regs);
 720                 return;
 721         }
 722         if (fixed == -EFAULT) {
 723                 /* fixed == -EFAULT means the operand address was bad */
 724                 if (user_mode(regs))
 725                         _exception(SIGSEGV, regs, SEGV_ACCERR, regs->dar);
 726                 else
 727                         bad_page_fault(regs, regs->dar, SIGSEGV);
 728                 return;
 729         }
 730         _exception(SIGBUS, regs, BUS_ADRALN, regs->dar);
 731 }
 732
 733 void StackOverflow(struct pt_regs *regs)
 734 {
 735         printk(KERN_CRIT "Kernel stack overflow in process %p, r1=%lx\n",
 736                current, regs->gpr[1]);
 737         debugger(regs);
 738         show_regs(regs);
 739         panic("kernel stack overflow");
 740 }
 741
 742 void nonrecoverable_exception(struct pt_regs *regs)
 743 {
 744         printk(KERN_ERR "Non-recoverable exception at PC=%lx MSR=%lx\n",
 745                regs->nip, regs->msr);
 746         debugger(regs);
 747         die("nonrecoverable exception", regs, SIGKILL);
 748 }
 749
 750 void trace_syscall(struct pt_regs *regs)
 751 {
 752         printk("Task: %p(%d), PC: %08lX/%08lX, Syscall: %3ld, Result: %s%ld    %s\n",
 753                current, current->pid, regs->nip, regs->link, regs->gpr[0],
 754                regs->ccr&0x10000000?"Error=":"", regs->gpr[3], print_tainted());
 755 }
 756
 757 #ifdef CONFIG_8xx
 758 void SoftwareEmulation(struct pt_regs *regs)
 759 {
 760         extern int do_mathemu(struct pt_regs *);
 761         extern int Soft_emulate_8xx(struct pt_regs *);
 762         int errcode;
 763
 764         CHECK_FULL_REGS(regs);
 765
 766         if (!user_mode(regs)) {
 767                 debugger(regs);
 768                 die("Kernel Mode Software FPU Emulation", regs, SIGFPE);
 769         }
 770
 771 #ifdef CONFIG_MATH_EMULATION
 772         errcode = do_mathemu(regs);
 773 #else
 774         errcode = Soft_emulate_8xx(regs);
 775 #endif
 776         if (errcode) {
 777                 if (errcode > 0)
 778                         _exception(SIGFPE, regs, 0, 0);
 779                 else if (errcode == -EFAULT)
 780                         _exception(SIGSEGV, regs, 0, 0);
 781                 else
 782                         _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
 783         } else
 784                 emulate_single_step(regs);
 785 }
 786 #endif /* CONFIG_8xx */
 787
 788 #if defined(CONFIG_40x) || defined(CONFIG_BOOKE)
 789
 790 void DebugException(struct pt_regs *regs, unsigned long debug_status)
 791 {
 792         if (debug_status & DBSR_IC) {   /* instruction completion */
 793                 regs->msr &= ~MSR_DE;
 794                 if (user_mode(regs)) {
 795                         current->thread.dbcr0 &= ~DBCR0_IC;
 796                 } else {
 797                         /* Disable instruction completion */
 798                         mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC);
 799                         /* Clear the instruction completion event */
 800                         mtspr(SPRN_DBSR, DBSR_IC);
 801                         if (debugger_sstep(regs))
 802                                 return;
 803                 }
 804                 _exception(SIGTRAP, regs, TRAP_TRACE, 0);
 805         }
 806 }
 807 #endif /* CONFIG_4xx || CONFIG_BOOKE */
 808
 809 #if !defined(CONFIG_TAU_INT)
 810 void TAUException(struct pt_regs *regs)
 811 {
 812         printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx    %s\n",
 813                regs->nip, regs->msr, regs->trap, print_tainted());
 814 }
 815 #endif /* CONFIG_INT_TAU */
 816
 817 void AltivecUnavailException(struct pt_regs *regs)
 818 {
 819         static int kernel_altivec_count;
 820
 821 #ifndef CONFIG_ALTIVEC
 822         if (user_mode(regs)) {
 823                 /* A user program has executed an altivec instruction,
 824                    but this kernel doesn't support altivec. */
 825                 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
 826                 return;
 827         }
 828 #endif
 829         /* The kernel has executed an altivec instruction without
 830            first enabling altivec.  Whinge but let it do it. */
 831         if (++kernel_altivec_count < 10)
 832                 printk(KERN_ERR "AltiVec used in kernel (task=%p, pc=%lx)\n",
 833                        current, regs->nip);
 834         regs->msr |= MSR_VEC;
 835 }
 836
 837 #ifdef CONFIG_ALTIVEC
 838 void AltivecAssistException(struct pt_regs *regs)
 839 {
 840         int err;
 841
 842         preempt_disable();
 843         if (regs->msr & MSR_VEC)
 844                 giveup_altivec(current);
 845         preempt_enable();
 846         if (!user_mode(regs)) {
 847                 printk(KERN_ERR "altivec assist exception in kernel mode"
 848                        " at %lx\n", regs->nip);
 849                 debugger(regs);
 850                 die("altivec assist exception", regs, SIGFPE);
 851                 return;
 852         }
 853
 854         err = emulate_altivec(regs);
 855         if (err == 0) {
 856                 regs->nip += 4;         /* skip emulated instruction */
 857                 emulate_single_step(regs);
 858                 return;
 859         }
 860
 861         if (err == -EFAULT) {
 862                 /* got an error reading the instruction */
 863                 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
 864         } else {
 865                 /* didn't recognize the instruction */
 866                 /* XXX quick hack for now: set the non-Java bit in the VSCR */
 867                 printk(KERN_ERR "unrecognized altivec instruction "
 868                        "in %s at %lx\n", current->comm, regs->nip);
 869                 current->thread.vscr.u[3] |= 0x10000;
 870         }
 871 }
 872 #endif /* CONFIG_ALTIVEC */
 873
 874 #ifdef CONFIG_E500
 875 void PerformanceMonitorException(struct pt_regs *regs)
 876 {
 877         perf_irq(regs);
 878 }
 879 #endif
 880
 881 #ifdef CONFIG_FSL_BOOKE
 882 void CacheLockingException(struct pt_regs *regs, unsigned long address,
 883                            unsigned long error_code)
 884 {
 885         /* We treat cache locking instructions from the user
 886          * as priv ops, in the future we could try to do
 887          * something smarter
 888          */
 889         if (error_code & (ESR_DLK|ESR_ILK))
 890                 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
 891         return;
 892 }
 893 #endif /* CONFIG_FSL_BOOKE */
 894
 895 #ifdef CONFIG_SPE
 896 void SPEFloatingPointException(struct pt_regs *regs)
 897 {
 898         unsigned long spefscr;
 899         int fpexc_mode;
 900         int code = 0;
 901
 902         spefscr = current->thread.spefscr;
 903         fpexc_mode = current->thread.fpexc_mode;
 904
 905         /* Hardware does not neccessarily set sticky
 906          * underflow/overflow/invalid flags */
 907         if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) {
 908                 code = FPE_FLTOVF;
 909                 spefscr |= SPEFSCR_FOVFS;
 910         }
 911         else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) {
 912                 code = FPE_FLTUND;
 913                 spefscr |= SPEFSCR_FUNFS;
 914         }
 915         else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV))
 916                 code = FPE_FLTDIV;
 917         else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) {
 918                 code = FPE_FLTINV;
 919                 spefscr |= SPEFSCR_FINVS;
 920         }
 921         else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES))
 922                 code = FPE_FLTRES;
 923
 924         current->thread.spefscr = spefscr;
 925
 926         _exception(SIGFPE, regs, code, regs->nip);
 927         return;
 928 }
 929 #endif
 930
 931 #ifdef CONFIG_BOOKE_WDT
 932 /*
 933  * Default handler for a Watchdog exception,
 934  * spins until a reboot occurs
 935  */
 936 void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs)
 937 {
 938         /* Generic WatchdogHandler, implement your own */
 939         mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE));
 940         return;
 941 }
 942
 943 void WatchdogException(struct pt_regs *regs)
 944 {
 945         printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n");
 946         WatchdogHandler(regs);
 947 }
 948 #endif
 949
 950 void __init trap_init(void)
 951 {
 952 }