2 * arch/arm/plat-s5pc1xx/gpiolib.c
4 * Copyright 2009 Samsung Electronics Co
5 * Kyungmin Park <kyungmin.park@samsung.com>
7 * S5PC1XX - GPIOlib support
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/kernel.h>
15 #include <linux/irq.h>
17 #include <linux/gpio.h>
21 #include <plat/gpio-core.h>
22 #include <plat/gpio-cfg.h>
23 #include <plat/gpio-cfg-helpers.h>
24 #include <plat/regs-gpio.h>
26 /* S5PC100 GPIO bank summary:
28 * Bank GPIOs Style INT Type
39 * F3 4 4Bit GPIO_INT10
40 * G0 8 4Bit GPIO_INT11
41 * G1 3 4Bit GPIO_INT12
42 * G2 7 4Bit GPIO_INT13
43 * G3 7 4Bit GPIO_INT14
49 * J0 8 4Bit GPIO_INT16
50 * J1 5 4Bit GPIO_INT17
51 * J2 8 4Bit GPIO_INT18
52 * J3 8 4Bit GPIO_INT19
53 * J4 4 4Bit GPIO_INT20
64 static int s5pc1xx_gpiolib_to_irq(struct gpio_chip
*chip
, unsigned int offset
)
66 return S3C_IRQ_GPIO(chip
->base
+ offset
);
69 static int s5pc1xx_gpiolib_to_eint(struct gpio_chip
*chip
, unsigned int offset
)
73 base
= chip
->base
- S5PC100_GPH0(0);
75 return IRQ_EINT(offset
);
76 base
= chip
->base
- S5PC100_GPH1(0);
78 return IRQ_EINT(8 + offset
);
79 base
= chip
->base
- S5PC100_GPH2(0);
81 return IRQ_EINT(16 + offset
);
82 base
= chip
->base
- S5PC100_GPH3(0);
84 return IRQ_EINT(24 + offset
);
88 static struct s3c_gpio_cfg gpio_cfg
= {
89 .set_config
= s3c_gpio_setcfg_s3c64xx_4bit
,
90 .set_pull
= s3c_gpio_setpull_updown
,
91 .get_pull
= s3c_gpio_getpull_updown
,
94 static struct s3c_gpio_cfg gpio_cfg_eint
= {
96 .set_config
= s3c_gpio_setcfg_s3c64xx_4bit
,
97 .set_pull
= s3c_gpio_setpull_updown
,
98 .get_pull
= s3c_gpio_getpull_updown
,
101 static struct s3c_gpio_cfg gpio_cfg_noint
= {
102 .set_config
= s3c_gpio_setcfg_s3c64xx_4bit
,
103 .set_pull
= s3c_gpio_setpull_updown
,
104 .get_pull
= s3c_gpio_getpull_updown
,
107 static struct s3c_gpio_chip s5pc100_gpio_chips
[] = {
109 .base
= S5PC100_GPA0_BASE
,
112 .base
= S5PC100_GPA0(0),
113 .ngpio
= S5PC100_GPIO_A0_NR
,
117 .base
= S5PC100_GPA1_BASE
,
120 .base
= S5PC100_GPA1(0),
121 .ngpio
= S5PC100_GPIO_A1_NR
,
125 .base
= S5PC100_GPB_BASE
,
128 .base
= S5PC100_GPB(0),
129 .ngpio
= S5PC100_GPIO_B_NR
,
133 .base
= S5PC100_GPC_BASE
,
136 .base
= S5PC100_GPC(0),
137 .ngpio
= S5PC100_GPIO_C_NR
,
141 .base
= S5PC100_GPD_BASE
,
144 .base
= S5PC100_GPD(0),
145 .ngpio
= S5PC100_GPIO_D_NR
,
149 .base
= S5PC100_GPE0_BASE
,
152 .base
= S5PC100_GPE0(0),
153 .ngpio
= S5PC100_GPIO_E0_NR
,
157 .base
= S5PC100_GPE1_BASE
,
160 .base
= S5PC100_GPE1(0),
161 .ngpio
= S5PC100_GPIO_E1_NR
,
165 .base
= S5PC100_GPF0_BASE
,
168 .base
= S5PC100_GPF0(0),
169 .ngpio
= S5PC100_GPIO_F0_NR
,
173 .base
= S5PC100_GPF1_BASE
,
176 .base
= S5PC100_GPF1(0),
177 .ngpio
= S5PC100_GPIO_F1_NR
,
181 .base
= S5PC100_GPF2_BASE
,
184 .base
= S5PC100_GPF2(0),
185 .ngpio
= S5PC100_GPIO_F2_NR
,
189 .base
= S5PC100_GPF3_BASE
,
192 .base
= S5PC100_GPF3(0),
193 .ngpio
= S5PC100_GPIO_F3_NR
,
197 .base
= S5PC100_GPG0_BASE
,
200 .base
= S5PC100_GPG0(0),
201 .ngpio
= S5PC100_GPIO_G0_NR
,
205 .base
= S5PC100_GPG1_BASE
,
208 .base
= S5PC100_GPG1(0),
209 .ngpio
= S5PC100_GPIO_G1_NR
,
213 .base
= S5PC100_GPG2_BASE
,
216 .base
= S5PC100_GPG2(0),
217 .ngpio
= S5PC100_GPIO_G2_NR
,
221 .base
= S5PC100_GPG3_BASE
,
224 .base
= S5PC100_GPG3(0),
225 .ngpio
= S5PC100_GPIO_G3_NR
,
229 .base
= S5PC100_GPH0_BASE
,
230 .config
= &gpio_cfg_eint
,
232 .base
= S5PC100_GPH0(0),
233 .ngpio
= S5PC100_GPIO_H0_NR
,
237 .base
= S5PC100_GPH1_BASE
,
238 .config
= &gpio_cfg_eint
,
240 .base
= S5PC100_GPH1(0),
241 .ngpio
= S5PC100_GPIO_H1_NR
,
245 .base
= S5PC100_GPH2_BASE
,
246 .config
= &gpio_cfg_eint
,
248 .base
= S5PC100_GPH2(0),
249 .ngpio
= S5PC100_GPIO_H2_NR
,
253 .base
= S5PC100_GPH3_BASE
,
254 .config
= &gpio_cfg_eint
,
256 .base
= S5PC100_GPH3(0),
257 .ngpio
= S5PC100_GPIO_H3_NR
,
261 .base
= S5PC100_GPI_BASE
,
264 .base
= S5PC100_GPI(0),
265 .ngpio
= S5PC100_GPIO_I_NR
,
269 .base
= S5PC100_GPJ0_BASE
,
272 .base
= S5PC100_GPJ0(0),
273 .ngpio
= S5PC100_GPIO_J0_NR
,
277 .base
= S5PC100_GPJ1_BASE
,
280 .base
= S5PC100_GPJ1(0),
281 .ngpio
= S5PC100_GPIO_J1_NR
,
285 .base
= S5PC100_GPJ2_BASE
,
288 .base
= S5PC100_GPJ2(0),
289 .ngpio
= S5PC100_GPIO_J2_NR
,
293 .base
= S5PC100_GPJ3_BASE
,
296 .base
= S5PC100_GPJ3(0),
297 .ngpio
= S5PC100_GPIO_J3_NR
,
301 .base
= S5PC100_GPJ4_BASE
,
304 .base
= S5PC100_GPJ4(0),
305 .ngpio
= S5PC100_GPIO_J4_NR
,
309 .base
= S5PC100_GPK0_BASE
,
310 .config
= &gpio_cfg_noint
,
312 .base
= S5PC100_GPK0(0),
313 .ngpio
= S5PC100_GPIO_K0_NR
,
317 .base
= S5PC100_GPK1_BASE
,
318 .config
= &gpio_cfg_noint
,
320 .base
= S5PC100_GPK1(0),
321 .ngpio
= S5PC100_GPIO_K1_NR
,
325 .base
= S5PC100_GPK2_BASE
,
326 .config
= &gpio_cfg_noint
,
328 .base
= S5PC100_GPK2(0),
329 .ngpio
= S5PC100_GPIO_K2_NR
,
333 .base
= S5PC100_GPK3_BASE
,
334 .config
= &gpio_cfg_noint
,
336 .base
= S5PC100_GPK3(0),
337 .ngpio
= S5PC100_GPIO_K3_NR
,
341 .base
= S5PC100_GPL0_BASE
,
342 .config
= &gpio_cfg_noint
,
344 .base
= S5PC100_GPL0(0),
345 .ngpio
= S5PC100_GPIO_L0_NR
,
349 .base
= S5PC100_GPL1_BASE
,
350 .config
= &gpio_cfg_noint
,
352 .base
= S5PC100_GPL1(0),
353 .ngpio
= S5PC100_GPIO_L1_NR
,
357 .base
= S5PC100_GPL2_BASE
,
358 .config
= &gpio_cfg_noint
,
360 .base
= S5PC100_GPL2(0),
361 .ngpio
= S5PC100_GPIO_L2_NR
,
365 .base
= S5PC100_GPL3_BASE
,
366 .config
= &gpio_cfg_noint
,
368 .base
= S5PC100_GPL3(0),
369 .ngpio
= S5PC100_GPIO_L3_NR
,
373 .base
= S5PC100_GPL4_BASE
,
374 .config
= &gpio_cfg_noint
,
376 .base
= S5PC100_GPL4(0),
377 .ngpio
= S5PC100_GPIO_L4_NR
,
383 /* FIXME move from irq-gpio.c */
384 extern struct irq_chip s5pc1xx_gpioint
;
385 extern void s5pc1xx_irq_gpioint_handler(unsigned int irq
, struct irq_desc
*desc
);
387 static __init
void s5pc100_gpiolib_link(struct s3c_gpio_chip
*chip
)
391 if (chip
->config
== &gpio_cfg
) {
394 chip
->chip
.to_irq
= s5pc1xx_gpiolib_to_irq
;
396 for (i
= 0; i
< chip
->chip
.ngpio
; i
++) {
397 irq
= S3C_IRQ_GPIO_BASE
+ chip
->chip
.base
+ i
;
398 set_irq_chip(irq
, &s5pc1xx_gpioint
);
399 set_irq_data(irq
, &chip
->chip
);
400 set_irq_handler(irq
, handle_level_irq
);
401 set_irq_flags(irq
, IRQF_VALID
);
403 } else if (chip
->config
== &gpio_cfg_eint
)
404 chip
->chip
.to_irq
= s5pc1xx_gpiolib_to_eint
;
407 static __init
int s5pc1xx_gpiolib_init(void)
409 struct s3c_gpio_chip
*chip
;
412 chip
= s5pc100_gpio_chips
;
413 nr_chips
= ARRAY_SIZE(s5pc100_gpio_chips
);
415 for (; nr_chips
> 0; nr_chips
--, chip
++)
416 s5pc100_gpiolib_link(chip
);
418 samsung_gpiolib_add_4bit_chips(s5pc100_gpio_chips
,
419 ARRAY_SIZE(s5pc100_gpio_chips
));
421 set_irq_chained_handler(IRQ_GPIOINT
, s5pc1xx_irq_gpioint_handler
);
425 core_initcall(s5pc1xx_gpiolib_init
);