2 * linux/arch/i386/nmi.c
4 * NMI watchdog support on APIC systems
6 * Started by Ingo Molnar <mingo@redhat.com>
9 * Mikael Pettersson : AMD K7 support for local APIC NMI watchdog.
10 * Mikael Pettersson : Power Management for local APIC NMI watchdog.
11 * Mikael Pettersson : Pentium 4 support for local APIC NMI watchdog.
13 * Mikael Pettersson : PM converted to driver model. Disable/enable API.
16 #include <linux/config.h>
17 #include <linux/delay.h>
18 #include <linux/interrupt.h>
19 #include <linux/module.h>
20 #include <linux/nmi.h>
21 #include <linux/sysdev.h>
22 #include <linux/sysctl.h>
23 #include <linux/percpu.h>
24 #include <linux/dmi.h>
28 #include <asm/kdebug.h>
29 #include <asm/intel_arch_perfmon.h>
31 #include "mach_traps.h"
33 /* perfctr_nmi_owner tracks the ownership of the perfctr registers:
34 * evtsel_nmi_owner tracks the ownership of the event selection
35 * - different performance counters/ event selection may be reserved for
36 * different subsystems this reservation system just tries to coordinate
39 static DEFINE_PER_CPU(unsigned long, perfctr_nmi_owner
);
40 static DEFINE_PER_CPU(unsigned long, evntsel_nmi_owner
[3]);
42 /* this number is calculated from Intel's MSR_P4_CRU_ESCR5 register and it's
43 * offset from MSR_P4_BSU_ESCR0. It will be the max for all platforms (for now)
45 #define NMI_MAX_COUNTER_BITS 66
48 * >0: the lapic NMI watchdog is active, but can be disabled
49 * <0: the lapic NMI watchdog has not been set up, and cannot
51 * 0: the lapic NMI watchdog is disabled, but can be enabled
53 atomic_t nmi_active
= ATOMIC_INIT(0); /* oprofile uses this */
55 unsigned int nmi_watchdog
= NMI_DEFAULT
;
56 static unsigned int nmi_hz
= HZ
;
58 struct nmi_watchdog_ctlblk
{
61 unsigned int cccr_msr
;
62 unsigned int perfctr_msr
; /* the MSR to reset in NMI handler */
63 unsigned int evntsel_msr
; /* the MSR to select the events to handle */
65 static DEFINE_PER_CPU(struct nmi_watchdog_ctlblk
, nmi_watchdog_ctlblk
);
67 /* local prototypes */
68 static int unknown_nmi_panic_callback(struct pt_regs
*regs
, int cpu
);
70 extern void show_registers(struct pt_regs
*regs
);
71 extern int unknown_nmi_panic
;
73 /* converts an msr to an appropriate reservation bit */
74 static inline unsigned int nmi_perfctr_msr_to_bit(unsigned int msr
)
76 /* returns the bit offset of the performance counter register */
77 switch (boot_cpu_data
.x86_vendor
) {
79 return (msr
- MSR_K7_PERFCTR0
);
80 case X86_VENDOR_INTEL
:
81 if (cpu_has(&boot_cpu_data
, X86_FEATURE_ARCH_PERFMON
))
82 return (msr
- MSR_ARCH_PERFMON_PERFCTR0
);
84 switch (boot_cpu_data
.x86
) {
86 return (msr
- MSR_P6_PERFCTR0
);
88 return (msr
- MSR_P4_BPU_PERFCTR0
);
94 /* converts an msr to an appropriate reservation bit */
95 static inline unsigned int nmi_evntsel_msr_to_bit(unsigned int msr
)
97 /* returns the bit offset of the event selection register */
98 switch (boot_cpu_data
.x86_vendor
) {
100 return (msr
- MSR_K7_EVNTSEL0
);
101 case X86_VENDOR_INTEL
:
102 if (cpu_has(&boot_cpu_data
, X86_FEATURE_ARCH_PERFMON
))
103 return (msr
- MSR_ARCH_PERFMON_EVENTSEL0
);
105 switch (boot_cpu_data
.x86
) {
107 return (msr
- MSR_P6_EVNTSEL0
);
109 return (msr
- MSR_P4_BSU_ESCR0
);
115 /* checks for a bit availability (hack for oprofile) */
116 int avail_to_resrv_perfctr_nmi_bit(unsigned int counter
)
118 BUG_ON(counter
> NMI_MAX_COUNTER_BITS
);
120 return (!test_bit(counter
, &__get_cpu_var(perfctr_nmi_owner
)));
123 /* checks the an msr for availability */
124 int avail_to_resrv_perfctr_nmi(unsigned int msr
)
126 unsigned int counter
;
128 counter
= nmi_perfctr_msr_to_bit(msr
);
129 BUG_ON(counter
> NMI_MAX_COUNTER_BITS
);
131 return (!test_bit(counter
, &__get_cpu_var(perfctr_nmi_owner
)));
134 int reserve_perfctr_nmi(unsigned int msr
)
136 unsigned int counter
;
138 counter
= nmi_perfctr_msr_to_bit(msr
);
139 BUG_ON(counter
> NMI_MAX_COUNTER_BITS
);
141 if (!test_and_set_bit(counter
, &__get_cpu_var(perfctr_nmi_owner
)))
146 void release_perfctr_nmi(unsigned int msr
)
148 unsigned int counter
;
150 counter
= nmi_perfctr_msr_to_bit(msr
);
151 BUG_ON(counter
> NMI_MAX_COUNTER_BITS
);
153 clear_bit(counter
, &__get_cpu_var(perfctr_nmi_owner
));
156 int reserve_evntsel_nmi(unsigned int msr
)
158 unsigned int counter
;
160 counter
= nmi_evntsel_msr_to_bit(msr
);
161 BUG_ON(counter
> NMI_MAX_COUNTER_BITS
);
163 if (!test_and_set_bit(counter
, &__get_cpu_var(evntsel_nmi_owner
)[0]))
168 void release_evntsel_nmi(unsigned int msr
)
170 unsigned int counter
;
172 counter
= nmi_evntsel_msr_to_bit(msr
);
173 BUG_ON(counter
> NMI_MAX_COUNTER_BITS
);
175 clear_bit(counter
, &__get_cpu_var(evntsel_nmi_owner
)[0]);
178 static __cpuinit
inline int nmi_known_cpu(void)
180 switch (boot_cpu_data
.x86_vendor
) {
182 return ((boot_cpu_data
.x86
== 15) || (boot_cpu_data
.x86
== 6));
183 case X86_VENDOR_INTEL
:
184 if (cpu_has(&boot_cpu_data
, X86_FEATURE_ARCH_PERFMON
))
187 return ((boot_cpu_data
.x86
== 15) || (boot_cpu_data
.x86
== 6));
193 /* The performance counters used by NMI_LOCAL_APIC don't trigger when
194 * the CPU is idle. To make sure the NMI watchdog really ticks on all
195 * CPUs during the test make them busy.
197 static __init
void nmi_cpu_busy(void *data
)
199 volatile int *endflag
= data
;
200 local_irq_enable_in_hardirq();
201 /* Intentionally don't use cpu_relax here. This is
202 to make sure that the performance counter really ticks,
203 even if there is a simulator or similar that catches the
204 pause instruction. On a real HT machine this is fine because
205 all other CPUs are busy with "useless" delay loops and don't
206 care if they get somewhat less cycles. */
207 while (*endflag
== 0)
212 static int __init
check_nmi_watchdog(void)
214 volatile int endflag
= 0;
215 unsigned int *prev_nmi_count
;
218 /* Enable NMI watchdog for newer systems.
219 Actually it should be safe for most systems before 2004 too except
220 for some IBM systems that corrupt registers when NMI happens
221 during SMM. Unfortunately we don't have more exact information
222 on these and use this coarse check. */
223 if (nmi_watchdog
== NMI_DEFAULT
&& dmi_get_year(DMI_BIOS_DATE
) >= 2004)
224 nmi_watchdog
= NMI_LOCAL_APIC
;
226 if ((nmi_watchdog
== NMI_NONE
) || (nmi_watchdog
== NMI_DEFAULT
))
229 if (!atomic_read(&nmi_active
))
232 prev_nmi_count
= kmalloc(NR_CPUS
* sizeof(int), GFP_KERNEL
);
236 printk(KERN_INFO
"Testing NMI watchdog ... ");
238 if (nmi_watchdog
== NMI_LOCAL_APIC
)
239 smp_call_function(nmi_cpu_busy
, (void *)&endflag
, 0, 0);
241 for_each_possible_cpu(cpu
)
242 prev_nmi_count
[cpu
] = per_cpu(irq_stat
, cpu
).__nmi_count
;
244 mdelay((10*1000)/nmi_hz
); // wait 10 ticks
246 for_each_possible_cpu(cpu
) {
248 /* Check cpu_callin_map here because that is set
249 after the timer is started. */
250 if (!cpu_isset(cpu
, cpu_callin_map
))
253 if (!per_cpu(nmi_watchdog_ctlblk
, cpu
).enabled
)
255 if (nmi_count(cpu
) - prev_nmi_count
[cpu
] <= 5) {
256 printk("CPU#%d: NMI appears to be stuck (%d->%d)!\n",
260 per_cpu(nmi_watchdog_ctlblk
, cpu
).enabled
= 0;
261 atomic_dec(&nmi_active
);
264 if (!atomic_read(&nmi_active
)) {
265 kfree(prev_nmi_count
);
266 atomic_set(&nmi_active
, -1);
272 /* now that we know it works we can reduce NMI frequency to
273 something more reasonable; makes a difference in some configs */
274 if (nmi_watchdog
== NMI_LOCAL_APIC
) {
275 struct nmi_watchdog_ctlblk
*wd
= &__get_cpu_var(nmi_watchdog_ctlblk
);
279 * On Intel CPUs with ARCH_PERFMON only 32 bits in the counter
280 * are writable, with higher bits sign extending from bit 31.
281 * So, we can only program the counter with 31 bit values and
282 * 32nd bit should be 1, for 33.. to be 1.
283 * Find the appropriate nmi_hz
285 if (wd
->perfctr_msr
== MSR_ARCH_PERFMON_PERFCTR0
&&
286 ((u64
)cpu_khz
* 1000) > 0x7fffffffULL
) {
287 u64 count
= (u64
)cpu_khz
* 1000;
288 do_div(count
, 0x7fffffffUL
);
293 kfree(prev_nmi_count
);
296 /* This needs to happen later in boot so counters are working */
297 late_initcall(check_nmi_watchdog
);
299 static int __init
setup_nmi_watchdog(char *str
)
303 get_option(&str
, &nmi
);
305 if ((nmi
>= NMI_INVALID
) || (nmi
< NMI_NONE
))
308 * If any other x86 CPU has a local APIC, then
309 * please test the NMI stuff there and send me the
310 * missing bits. Right now Intel P6/P4 and AMD K7 only.
312 if ((nmi
== NMI_LOCAL_APIC
) && (nmi_known_cpu() == 0))
313 return 0; /* no lapic support */
318 __setup("nmi_watchdog=", setup_nmi_watchdog
);
320 static void disable_lapic_nmi_watchdog(void)
322 BUG_ON(nmi_watchdog
!= NMI_LOCAL_APIC
);
324 if (atomic_read(&nmi_active
) <= 0)
327 on_each_cpu(stop_apic_nmi_watchdog
, NULL
, 0, 1);
329 BUG_ON(atomic_read(&nmi_active
) != 0);
332 static void enable_lapic_nmi_watchdog(void)
334 BUG_ON(nmi_watchdog
!= NMI_LOCAL_APIC
);
336 /* are we already enabled */
337 if (atomic_read(&nmi_active
) != 0)
340 /* are we lapic aware */
341 if (nmi_known_cpu() <= 0)
344 on_each_cpu(setup_apic_nmi_watchdog
, NULL
, 0, 1);
345 touch_nmi_watchdog();
348 void disable_timer_nmi_watchdog(void)
350 BUG_ON(nmi_watchdog
!= NMI_IO_APIC
);
352 if (atomic_read(&nmi_active
) <= 0)
356 on_each_cpu(stop_apic_nmi_watchdog
, NULL
, 0, 1);
358 BUG_ON(atomic_read(&nmi_active
) != 0);
361 void enable_timer_nmi_watchdog(void)
363 BUG_ON(nmi_watchdog
!= NMI_IO_APIC
);
365 if (atomic_read(&nmi_active
) == 0) {
366 touch_nmi_watchdog();
367 on_each_cpu(setup_apic_nmi_watchdog
, NULL
, 0, 1);
374 static int nmi_pm_active
; /* nmi_active before suspend */
376 static int lapic_nmi_suspend(struct sys_device
*dev
, pm_message_t state
)
378 /* only CPU0 goes here, other CPUs should be offline */
379 nmi_pm_active
= atomic_read(&nmi_active
);
380 stop_apic_nmi_watchdog(NULL
);
381 BUG_ON(atomic_read(&nmi_active
) != 0);
385 static int lapic_nmi_resume(struct sys_device
*dev
)
387 /* only CPU0 goes here, other CPUs should be offline */
388 if (nmi_pm_active
> 0) {
389 setup_apic_nmi_watchdog(NULL
);
390 touch_nmi_watchdog();
396 static struct sysdev_class nmi_sysclass
= {
397 set_kset_name("lapic_nmi"),
398 .resume
= lapic_nmi_resume
,
399 .suspend
= lapic_nmi_suspend
,
402 static struct sys_device device_lapic_nmi
= {
404 .cls
= &nmi_sysclass
,
407 static int __init
init_lapic_nmi_sysfs(void)
411 /* should really be a BUG_ON but b/c this is an
412 * init call, it just doesn't work. -dcz
414 if (nmi_watchdog
!= NMI_LOCAL_APIC
)
417 if ( atomic_read(&nmi_active
) < 0 )
420 error
= sysdev_class_register(&nmi_sysclass
);
422 error
= sysdev_register(&device_lapic_nmi
);
425 /* must come after the local APIC's device_initcall() */
426 late_initcall(init_lapic_nmi_sysfs
);
428 #endif /* CONFIG_PM */
431 * Activate the NMI watchdog via the local APIC.
432 * Original code written by Keith Owens.
435 static void write_watchdog_counter(unsigned int perfctr_msr
, const char *descr
)
437 u64 count
= (u64
)cpu_khz
* 1000;
439 do_div(count
, nmi_hz
);
441 Dprintk("setting %s to -0x%08Lx\n", descr
, count
);
442 wrmsrl(perfctr_msr
, 0 - count
);
445 /* Note that these events don't tick when the CPU idles. This means
446 the frequency varies with CPU load. */
448 #define K7_EVNTSEL_ENABLE (1 << 22)
449 #define K7_EVNTSEL_INT (1 << 20)
450 #define K7_EVNTSEL_OS (1 << 17)
451 #define K7_EVNTSEL_USR (1 << 16)
452 #define K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING 0x76
453 #define K7_NMI_EVENT K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING
455 static int setup_k7_watchdog(void)
457 unsigned int perfctr_msr
, evntsel_msr
;
458 unsigned int evntsel
;
459 struct nmi_watchdog_ctlblk
*wd
= &__get_cpu_var(nmi_watchdog_ctlblk
);
461 perfctr_msr
= MSR_K7_PERFCTR0
;
462 evntsel_msr
= MSR_K7_EVNTSEL0
;
463 if (!reserve_perfctr_nmi(perfctr_msr
))
466 if (!reserve_evntsel_nmi(evntsel_msr
))
469 wrmsrl(perfctr_msr
, 0UL);
471 evntsel
= K7_EVNTSEL_INT
476 /* setup the timer */
477 wrmsr(evntsel_msr
, evntsel
, 0);
478 write_watchdog_counter(perfctr_msr
, "K7_PERFCTR0");
479 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
480 evntsel
|= K7_EVNTSEL_ENABLE
;
481 wrmsr(evntsel_msr
, evntsel
, 0);
483 wd
->perfctr_msr
= perfctr_msr
;
484 wd
->evntsel_msr
= evntsel_msr
;
485 wd
->cccr_msr
= 0; //unused
486 wd
->check_bit
= 1ULL<<63;
489 release_perfctr_nmi(perfctr_msr
);
494 static void stop_k7_watchdog(void)
496 struct nmi_watchdog_ctlblk
*wd
= &__get_cpu_var(nmi_watchdog_ctlblk
);
498 wrmsr(wd
->evntsel_msr
, 0, 0);
500 release_evntsel_nmi(wd
->evntsel_msr
);
501 release_perfctr_nmi(wd
->perfctr_msr
);
504 #define P6_EVNTSEL0_ENABLE (1 << 22)
505 #define P6_EVNTSEL_INT (1 << 20)
506 #define P6_EVNTSEL_OS (1 << 17)
507 #define P6_EVNTSEL_USR (1 << 16)
508 #define P6_EVENT_CPU_CLOCKS_NOT_HALTED 0x79
509 #define P6_NMI_EVENT P6_EVENT_CPU_CLOCKS_NOT_HALTED
511 static int setup_p6_watchdog(void)
513 unsigned int perfctr_msr
, evntsel_msr
;
514 unsigned int evntsel
;
515 struct nmi_watchdog_ctlblk
*wd
= &__get_cpu_var(nmi_watchdog_ctlblk
);
517 perfctr_msr
= MSR_P6_PERFCTR0
;
518 evntsel_msr
= MSR_P6_EVNTSEL0
;
519 if (!reserve_perfctr_nmi(perfctr_msr
))
522 if (!reserve_evntsel_nmi(evntsel_msr
))
525 wrmsrl(perfctr_msr
, 0UL);
527 evntsel
= P6_EVNTSEL_INT
532 /* setup the timer */
533 wrmsr(evntsel_msr
, evntsel
, 0);
534 write_watchdog_counter(perfctr_msr
, "P6_PERFCTR0");
535 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
536 evntsel
|= P6_EVNTSEL0_ENABLE
;
537 wrmsr(evntsel_msr
, evntsel
, 0);
539 wd
->perfctr_msr
= perfctr_msr
;
540 wd
->evntsel_msr
= evntsel_msr
;
541 wd
->cccr_msr
= 0; //unused
542 wd
->check_bit
= 1ULL<<39;
545 release_perfctr_nmi(perfctr_msr
);
550 static void stop_p6_watchdog(void)
552 struct nmi_watchdog_ctlblk
*wd
= &__get_cpu_var(nmi_watchdog_ctlblk
);
554 wrmsr(wd
->evntsel_msr
, 0, 0);
556 release_evntsel_nmi(wd
->evntsel_msr
);
557 release_perfctr_nmi(wd
->perfctr_msr
);
560 /* Note that these events don't tick when the CPU idles. This means
561 the frequency varies with CPU load. */
563 #define MSR_P4_MISC_ENABLE_PERF_AVAIL (1<<7)
564 #define P4_ESCR_EVENT_SELECT(N) ((N)<<25)
565 #define P4_ESCR_OS (1<<3)
566 #define P4_ESCR_USR (1<<2)
567 #define P4_CCCR_OVF_PMI0 (1<<26)
568 #define P4_CCCR_OVF_PMI1 (1<<27)
569 #define P4_CCCR_THRESHOLD(N) ((N)<<20)
570 #define P4_CCCR_COMPLEMENT (1<<19)
571 #define P4_CCCR_COMPARE (1<<18)
572 #define P4_CCCR_REQUIRED (3<<16)
573 #define P4_CCCR_ESCR_SELECT(N) ((N)<<13)
574 #define P4_CCCR_ENABLE (1<<12)
575 #define P4_CCCR_OVF (1<<31)
576 /* Set up IQ_COUNTER0 to behave like a clock, by having IQ_CCCR0 filter
577 CRU_ESCR0 (with any non-null event selector) through a complemented
578 max threshold. [IA32-Vol3, Section 14.9.9] */
580 static int setup_p4_watchdog(void)
582 unsigned int perfctr_msr
, evntsel_msr
, cccr_msr
;
583 unsigned int evntsel
, cccr_val
;
584 unsigned int misc_enable
, dummy
;
586 struct nmi_watchdog_ctlblk
*wd
= &__get_cpu_var(nmi_watchdog_ctlblk
);
588 rdmsr(MSR_IA32_MISC_ENABLE
, misc_enable
, dummy
);
589 if (!(misc_enable
& MSR_P4_MISC_ENABLE_PERF_AVAIL
))
593 /* detect which hyperthread we are on */
594 if (smp_num_siblings
== 2) {
595 unsigned int ebx
, apicid
;
598 apicid
= (ebx
>> 24) & 0xff;
604 /* performance counters are shared resources
605 * assign each hyperthread its own set
606 * (re-use the ESCR0 register, seems safe
607 * and keeps the cccr_val the same)
611 perfctr_msr
= MSR_P4_IQ_PERFCTR0
;
612 evntsel_msr
= MSR_P4_CRU_ESCR0
;
613 cccr_msr
= MSR_P4_IQ_CCCR0
;
614 cccr_val
= P4_CCCR_OVF_PMI0
| P4_CCCR_ESCR_SELECT(4);
617 perfctr_msr
= MSR_P4_IQ_PERFCTR1
;
618 evntsel_msr
= MSR_P4_CRU_ESCR0
;
619 cccr_msr
= MSR_P4_IQ_CCCR1
;
620 cccr_val
= P4_CCCR_OVF_PMI1
| P4_CCCR_ESCR_SELECT(4);
623 if (!reserve_perfctr_nmi(perfctr_msr
))
626 if (!reserve_evntsel_nmi(evntsel_msr
))
629 evntsel
= P4_ESCR_EVENT_SELECT(0x3F)
633 cccr_val
|= P4_CCCR_THRESHOLD(15)
638 wrmsr(evntsel_msr
, evntsel
, 0);
639 wrmsr(cccr_msr
, cccr_val
, 0);
640 write_watchdog_counter(perfctr_msr
, "P4_IQ_COUNTER0");
641 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
642 cccr_val
|= P4_CCCR_ENABLE
;
643 wrmsr(cccr_msr
, cccr_val
, 0);
644 wd
->perfctr_msr
= perfctr_msr
;
645 wd
->evntsel_msr
= evntsel_msr
;
646 wd
->cccr_msr
= cccr_msr
;
647 wd
->check_bit
= 1ULL<<39;
650 release_perfctr_nmi(perfctr_msr
);
655 static void stop_p4_watchdog(void)
657 struct nmi_watchdog_ctlblk
*wd
= &__get_cpu_var(nmi_watchdog_ctlblk
);
659 wrmsr(wd
->cccr_msr
, 0, 0);
660 wrmsr(wd
->evntsel_msr
, 0, 0);
662 release_evntsel_nmi(wd
->evntsel_msr
);
663 release_perfctr_nmi(wd
->perfctr_msr
);
666 #define ARCH_PERFMON_NMI_EVENT_SEL ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL
667 #define ARCH_PERFMON_NMI_EVENT_UMASK ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK
669 static int setup_intel_arch_watchdog(void)
672 union cpuid10_eax eax
;
674 unsigned int perfctr_msr
, evntsel_msr
;
675 unsigned int evntsel
;
676 struct nmi_watchdog_ctlblk
*wd
= &__get_cpu_var(nmi_watchdog_ctlblk
);
679 * Check whether the Architectural PerfMon supports
680 * Unhalted Core Cycles Event or not.
681 * NOTE: Corresponding bit = 0 in ebx indicates event present.
683 cpuid(10, &(eax
.full
), &ebx
, &unused
, &unused
);
684 if ((eax
.split
.mask_length
< (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX
+1)) ||
685 (ebx
& ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT
))
688 perfctr_msr
= MSR_ARCH_PERFMON_PERFCTR0
;
689 evntsel_msr
= MSR_ARCH_PERFMON_EVENTSEL0
;
691 if (!reserve_perfctr_nmi(perfctr_msr
))
694 if (!reserve_evntsel_nmi(evntsel_msr
))
697 wrmsrl(perfctr_msr
, 0UL);
699 evntsel
= ARCH_PERFMON_EVENTSEL_INT
700 | ARCH_PERFMON_EVENTSEL_OS
701 | ARCH_PERFMON_EVENTSEL_USR
702 | ARCH_PERFMON_NMI_EVENT_SEL
703 | ARCH_PERFMON_NMI_EVENT_UMASK
;
705 /* setup the timer */
706 wrmsr(evntsel_msr
, evntsel
, 0);
707 write_watchdog_counter(perfctr_msr
, "INTEL_ARCH_PERFCTR0");
708 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
709 evntsel
|= ARCH_PERFMON_EVENTSEL0_ENABLE
;
710 wrmsr(evntsel_msr
, evntsel
, 0);
712 wd
->perfctr_msr
= perfctr_msr
;
713 wd
->evntsel_msr
= evntsel_msr
;
714 wd
->cccr_msr
= 0; //unused
715 wd
->check_bit
= 1ULL << (eax
.split
.bit_width
- 1);
718 release_perfctr_nmi(perfctr_msr
);
723 static void stop_intel_arch_watchdog(void)
726 union cpuid10_eax eax
;
728 struct nmi_watchdog_ctlblk
*wd
= &__get_cpu_var(nmi_watchdog_ctlblk
);
731 * Check whether the Architectural PerfMon supports
732 * Unhalted Core Cycles Event or not.
733 * NOTE: Corresponding bit = 0 in ebx indicates event present.
735 cpuid(10, &(eax
.full
), &ebx
, &unused
, &unused
);
736 if ((eax
.split
.mask_length
< (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX
+1)) ||
737 (ebx
& ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT
))
740 wrmsr(wd
->evntsel_msr
, 0, 0);
741 release_evntsel_nmi(wd
->evntsel_msr
);
742 release_perfctr_nmi(wd
->perfctr_msr
);
745 void setup_apic_nmi_watchdog (void *unused
)
747 struct nmi_watchdog_ctlblk
*wd
= &__get_cpu_var(nmi_watchdog_ctlblk
);
749 /* only support LOCAL and IO APICs for now */
750 if ((nmi_watchdog
!= NMI_LOCAL_APIC
) &&
751 (nmi_watchdog
!= NMI_IO_APIC
))
754 if (wd
->enabled
== 1)
757 /* cheap hack to support suspend/resume */
758 /* if cpu0 is not active neither should the other cpus */
759 if ((smp_processor_id() != 0) && (atomic_read(&nmi_active
) <= 0))
762 if (nmi_watchdog
== NMI_LOCAL_APIC
) {
763 switch (boot_cpu_data
.x86_vendor
) {
765 if (boot_cpu_data
.x86
!= 6 && boot_cpu_data
.x86
!= 15)
767 if (!setup_k7_watchdog())
770 case X86_VENDOR_INTEL
:
771 if (cpu_has(&boot_cpu_data
, X86_FEATURE_ARCH_PERFMON
)) {
772 if (!setup_intel_arch_watchdog())
776 switch (boot_cpu_data
.x86
) {
778 if (boot_cpu_data
.x86_model
> 0xd)
781 if (!setup_p6_watchdog())
785 if (boot_cpu_data
.x86_model
> 0x4)
788 if (!setup_p4_watchdog())
800 atomic_inc(&nmi_active
);
803 void stop_apic_nmi_watchdog(void *unused
)
805 struct nmi_watchdog_ctlblk
*wd
= &__get_cpu_var(nmi_watchdog_ctlblk
);
807 /* only support LOCAL and IO APICs for now */
808 if ((nmi_watchdog
!= NMI_LOCAL_APIC
) &&
809 (nmi_watchdog
!= NMI_IO_APIC
))
812 if (wd
->enabled
== 0)
815 if (nmi_watchdog
== NMI_LOCAL_APIC
) {
816 switch (boot_cpu_data
.x86_vendor
) {
820 case X86_VENDOR_INTEL
:
821 if (cpu_has(&boot_cpu_data
, X86_FEATURE_ARCH_PERFMON
)) {
822 stop_intel_arch_watchdog();
825 switch (boot_cpu_data
.x86
) {
827 if (boot_cpu_data
.x86_model
> 0xd)
832 if (boot_cpu_data
.x86_model
> 0x4)
843 atomic_dec(&nmi_active
);
847 * the best way to detect whether a CPU has a 'hard lockup' problem
848 * is to check it's local APIC timer IRQ counts. If they are not
849 * changing then that CPU has some problem.
851 * as these watchdog NMI IRQs are generated on every CPU, we only
852 * have to check the current processor.
854 * since NMIs don't listen to _any_ locks, we have to be extremely
855 * careful not to rely on unsafe variables. The printk might lock
856 * up though, so we have to break up any console locks first ...
857 * [when there will be more tty-related locks, break them up
862 last_irq_sums
[NR_CPUS
],
863 alert_counter
[NR_CPUS
];
865 void touch_nmi_watchdog (void)
870 * Just reset the alert counters, (other CPUs might be
871 * spinning on locks we hold):
873 for_each_possible_cpu(i
)
874 alert_counter
[i
] = 0;
877 * Tickle the softlockup detector too:
879 touch_softlockup_watchdog();
881 EXPORT_SYMBOL(touch_nmi_watchdog
);
883 extern void die_nmi(struct pt_regs
*, const char *msg
);
885 int nmi_watchdog_tick (struct pt_regs
* regs
, unsigned reason
)
889 * Since current_thread_info()-> is always on the stack, and we
890 * always switch the stack NMI-atomically, it's safe to use
891 * smp_processor_id().
895 int cpu
= smp_processor_id();
896 struct nmi_watchdog_ctlblk
*wd
= &__get_cpu_var(nmi_watchdog_ctlblk
);
900 /* check for other users first */
901 if (notify_die(DIE_NMI
, "nmi", regs
, reason
, 2, SIGINT
)
907 sum
= per_cpu(irq_stat
, cpu
).apic_timer_irqs
;
909 /* if the apic timer isn't firing, this cpu isn't doing much */
910 if (!touched
&& last_irq_sums
[cpu
] == sum
) {
912 * Ayiee, looks like this CPU is stuck ...
913 * wait a few IRQs (5 seconds) before doing the oops ...
915 alert_counter
[cpu
]++;
916 if (alert_counter
[cpu
] == 5*nmi_hz
)
918 * die_nmi will return ONLY if NOTIFY_STOP happens..
920 die_nmi(regs
, "BUG: NMI Watchdog detected LOCKUP");
922 last_irq_sums
[cpu
] = sum
;
923 alert_counter
[cpu
] = 0;
925 /* see if the nmi watchdog went off */
927 if (nmi_watchdog
== NMI_LOCAL_APIC
) {
928 rdmsrl(wd
->perfctr_msr
, dummy
);
929 if (dummy
& wd
->check_bit
){
930 /* this wasn't a watchdog timer interrupt */
934 /* only Intel P4 uses the cccr msr */
935 if (wd
->cccr_msr
!= 0) {
938 * - An overflown perfctr will assert its interrupt
939 * until the OVF flag in its CCCR is cleared.
940 * - LVTPC is masked on interrupt and must be
941 * unmasked by the LVTPC handler.
943 rdmsrl(wd
->cccr_msr
, dummy
);
944 dummy
&= ~P4_CCCR_OVF
;
945 wrmsrl(wd
->cccr_msr
, dummy
);
946 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
948 else if (wd
->perfctr_msr
== MSR_P6_PERFCTR0
||
949 wd
->perfctr_msr
== MSR_ARCH_PERFMON_PERFCTR0
) {
950 /* P6 based Pentium M need to re-unmask
951 * the apic vector but it doesn't hurt
953 * ArchPerfom/Core Duo also needs this */
954 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
956 /* start the cycle over again */
957 write_watchdog_counter(wd
->perfctr_msr
, NULL
);
959 } else if (nmi_watchdog
== NMI_IO_APIC
) {
960 /* don't know how to accurately check for this.
961 * just assume it was a watchdog timer interrupt
962 * This matches the old behaviour.
966 printk(KERN_WARNING
"Unknown enabled NMI hardware?!\n");
972 int do_nmi_callback(struct pt_regs
* regs
, int cpu
)
975 if (unknown_nmi_panic
)
976 return unknown_nmi_panic_callback(regs
, cpu
);
983 static int unknown_nmi_panic_callback(struct pt_regs
*regs
, int cpu
)
985 unsigned char reason
= get_nmi_reason();
988 sprintf(buf
, "NMI received for unknown reason %02x\n", reason
);
994 * proc handler for /proc/sys/kernel/nmi
996 int proc_nmi_enabled(struct ctl_table
*table
, int write
, struct file
*file
,
997 void __user
*buffer
, size_t *length
, loff_t
*ppos
)
1001 nmi_watchdog_enabled
= (atomic_read(&nmi_active
) > 0) ? 1 : 0;
1002 old_state
= nmi_watchdog_enabled
;
1003 proc_dointvec(table
, write
, file
, buffer
, length
, ppos
);
1004 if (!!old_state
== !!nmi_watchdog_enabled
)
1007 if (atomic_read(&nmi_active
) < 0) {
1008 printk( KERN_WARNING
"NMI watchdog is permanently disabled\n");
1012 if (nmi_watchdog
== NMI_DEFAULT
) {
1013 if (nmi_known_cpu() > 0)
1014 nmi_watchdog
= NMI_LOCAL_APIC
;
1016 nmi_watchdog
= NMI_IO_APIC
;
1019 if (nmi_watchdog
== NMI_LOCAL_APIC
) {
1020 if (nmi_watchdog_enabled
)
1021 enable_lapic_nmi_watchdog();
1023 disable_lapic_nmi_watchdog();
1025 printk( KERN_WARNING
1026 "NMI watchdog doesn't know what hardware to touch\n");
1034 EXPORT_SYMBOL(nmi_active
);
1035 EXPORT_SYMBOL(nmi_watchdog
);
1036 EXPORT_SYMBOL(avail_to_resrv_perfctr_nmi
);
1037 EXPORT_SYMBOL(avail_to_resrv_perfctr_nmi_bit
);
1038 EXPORT_SYMBOL(reserve_perfctr_nmi
);
1039 EXPORT_SYMBOL(release_perfctr_nmi
);
1040 EXPORT_SYMBOL(reserve_evntsel_nmi
);
1041 EXPORT_SYMBOL(release_evntsel_nmi
);
1042 EXPORT_SYMBOL(disable_timer_nmi_watchdog
);
1043 EXPORT_SYMBOL(enable_timer_nmi_watchdog
);