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usb: dwc3: core: fix cached revision on our structure
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / gpio / gpio-ml-ioh.c
blobea8e73869250c24be2fd3e1fc35439fb3271f917
1 /*
2 * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
16 */
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/slab.h>
20 #include <linux/pci.h>
21 #include <linux/gpio.h>
22 #include <linux/interrupt.h>
23 #include <linux/irq.h>
24
25 #define IOH_EDGE_FALLING 0
26 #define IOH_EDGE_RISING BIT(0)
27 #define IOH_LEVEL_L BIT(1)
28 #define IOH_LEVEL_H (BIT(0) | BIT(1))
29 #define IOH_EDGE_BOTH BIT(2)
30 #define IOH_IM_MASK (BIT(0) | BIT(1) | BIT(2))
31
32 #define IOH_IRQ_BASE 0
33
34 #define PCI_VENDOR_ID_ROHM 0x10DB
35
36 struct ioh_reg_comn {
37 u32 ien;
38 u32 istatus;
39 u32 idisp;
40 u32 iclr;
41 u32 imask;
42 u32 imaskclr;
43 u32 po;
44 u32 pi;
45 u32 pm;
46 u32 im_0;
47 u32 im_1;
48 u32 reserved;
49 };
50
51 struct ioh_regs {
52 struct ioh_reg_comn regs[8];
53 u32 reserve1[16];
54 u32 ioh_sel_reg[4];
55 u32 reserve2[11];
56 u32 srst;
57 };
58
59 /**
60 * struct ioh_gpio_reg_data - The register store data.
61 * @ien_reg To store contents of interrupt enable register.
62 * @imask_reg: To store contents of interrupt mask regist
63 * @po_reg: To store contents of PO register.
64 * @pm_reg: To store contents of PM register.
65 * @im0_reg: To store contents of interrupt mode regist0
66 * @im1_reg: To store contents of interrupt mode regist1
67 * @use_sel_reg: To store contents of GPIO_USE_SEL0~3
68 */
69 struct ioh_gpio_reg_data {
70 u32 ien_reg;
71 u32 imask_reg;
72 u32 po_reg;
73 u32 pm_reg;
74 u32 im0_reg;
75 u32 im1_reg;
76 u32 use_sel_reg;
77 };
78
79 /**
80 * struct ioh_gpio - GPIO private data structure.
81 * @base: PCI base address of Memory mapped I/O register.
82 * @reg: Memory mapped IOH GPIO register list.
83 * @dev: Pointer to device structure.
84 * @gpio: Data for GPIO infrastructure.
85 * @ioh_gpio_reg: Memory mapped Register data is saved here
86 * when suspend.
87 * @gpio_use_sel: Save GPIO_USE_SEL1~4 register for PM
88 * @ch: Indicate GPIO channel
89 * @irq_base: Save base of IRQ number for interrupt
90 * @spinlock: Used for register access protection in
91 * interrupt context ioh_irq_type and PM;
92 */
93 struct ioh_gpio {
94 void __iomem *base;
95 struct ioh_regs __iomem *reg;
96 struct device *dev;
97 struct gpio_chip gpio;
98 struct ioh_gpio_reg_data ioh_gpio_reg;
99 u32 gpio_use_sel;
100 struct mutex lock;
101 int ch;
102 int irq_base;
103 spinlock_t spinlock;
104 };
105
106 static const int num_ports[] = {6, 12, 16, 16, 15, 16, 16, 12};
107
108 static void ioh_gpio_set(struct gpio_chip *gpio, unsigned nr, int val)
109 {
110 u32 reg_val;
111 struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio);
112
113 mutex_lock(&chip->lock);
114 reg_val = ioread32(&chip->reg->regs[chip->ch].po);
115 if (val)
116 reg_val |= (1 << nr);
117 else
118 reg_val &= ~(1 << nr);
119
120 iowrite32(reg_val, &chip->reg->regs[chip->ch].po);
121 mutex_unlock(&chip->lock);
122 }
123
124 static int ioh_gpio_get(struct gpio_chip *gpio, unsigned nr)
125 {
126 struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio);
127
128 return ioread32(&chip->reg->regs[chip->ch].pi) & (1 << nr);
129 }
130
131 static int ioh_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
132 int val)
133 {
134 struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio);
135 u32 pm;
136 u32 reg_val;
137
138 mutex_lock(&chip->lock);
139 pm = ioread32(&chip->reg->regs[chip->ch].pm) &
140 ((1 << num_ports[chip->ch]) - 1);
141 pm |= (1 << nr);
142 iowrite32(pm, &chip->reg->regs[chip->ch].pm);
143
144 reg_val = ioread32(&chip->reg->regs[chip->ch].po);
145 if (val)
146 reg_val |= (1 << nr);
147 else
148 reg_val &= ~(1 << nr);
149 iowrite32(reg_val, &chip->reg->regs[chip->ch].po);
150
151 mutex_unlock(&chip->lock);
152
153 return 0;
154 }
155
156 static int ioh_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
157 {
158 struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio);
159 u32 pm;
160
161 mutex_lock(&chip->lock);
162 pm = ioread32(&chip->reg->regs[chip->ch].pm) &
163 ((1 << num_ports[chip->ch]) - 1);
164 pm &= ~(1 << nr);
165 iowrite32(pm, &chip->reg->regs[chip->ch].pm);
166 mutex_unlock(&chip->lock);
167
168 return 0;
169 }
170
171 #ifdef CONFIG_PM
172 /*
173 * Save register configuration and disable interrupts.
174 */
175 static void ioh_gpio_save_reg_conf(struct ioh_gpio *chip)
176 {
177 int i;
178
179 for (i = 0; i < 8; i ++, chip++) {
180 chip->ioh_gpio_reg.po_reg =
181 ioread32(&chip->reg->regs[chip->ch].po);
182 chip->ioh_gpio_reg.pm_reg =
183 ioread32(&chip->reg->regs[chip->ch].pm);
184 chip->ioh_gpio_reg.ien_reg =
185 ioread32(&chip->reg->regs[chip->ch].ien);
186 chip->ioh_gpio_reg.imask_reg =
187 ioread32(&chip->reg->regs[chip->ch].imask);
188 chip->ioh_gpio_reg.im0_reg =
189 ioread32(&chip->reg->regs[chip->ch].im_0);
190 chip->ioh_gpio_reg.im1_reg =
191 ioread32(&chip->reg->regs[chip->ch].im_1);
192 if (i < 4)
193 chip->ioh_gpio_reg.use_sel_reg =
194 ioread32(&chip->reg->ioh_sel_reg[i]);
195 }
196 }
197
198 /*
199 * This function restores the register configuration of the GPIO device.
200 */
201 static void ioh_gpio_restore_reg_conf(struct ioh_gpio *chip)
202 {
203 int i;
204
205 for (i = 0; i < 8; i ++, chip++) {
206 iowrite32(chip->ioh_gpio_reg.po_reg,
207 &chip->reg->regs[chip->ch].po);
208 iowrite32(chip->ioh_gpio_reg.pm_reg,
209 &chip->reg->regs[chip->ch].pm);
210 iowrite32(chip->ioh_gpio_reg.ien_reg,
211 &chip->reg->regs[chip->ch].ien);
212 iowrite32(chip->ioh_gpio_reg.imask_reg,
213 &chip->reg->regs[chip->ch].imask);
214 iowrite32(chip->ioh_gpio_reg.im0_reg,
215 &chip->reg->regs[chip->ch].im_0);
216 iowrite32(chip->ioh_gpio_reg.im1_reg,
217 &chip->reg->regs[chip->ch].im_1);
218 if (i < 4)
219 iowrite32(chip->ioh_gpio_reg.use_sel_reg,
220 &chip->reg->ioh_sel_reg[i]);
221 }
222 }
223 #endif
224
225 static int ioh_gpio_to_irq(struct gpio_chip *gpio, unsigned offset)
226 {
227 struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio);
228 return chip->irq_base + offset;
229 }
230
231 static void ioh_gpio_setup(struct ioh_gpio *chip, int num_port)
232 {
233 struct gpio_chip *gpio = &chip->gpio;
234
235 gpio->label = dev_name(chip->dev);
236 gpio->owner = THIS_MODULE;
237 gpio->direction_input = ioh_gpio_direction_input;
238 gpio->get = ioh_gpio_get;
239 gpio->direction_output = ioh_gpio_direction_output;
240 gpio->set = ioh_gpio_set;
241 gpio->dbg_show = NULL;
242 gpio->base = -1;
243 gpio->ngpio = num_port;
244 gpio->can_sleep = 0;
245 gpio->to_irq = ioh_gpio_to_irq;
246 }
247
248 static int ioh_irq_type(struct irq_data *d, unsigned int type)
249 {
250 u32 im;
251 u32 *im_reg;
252 u32 ien;
253 u32 im_pos;
254 int ch;
255 unsigned long flags;
256 u32 val;
257 int irq = d->irq;
258 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
259 struct ioh_gpio *chip = gc->private;
260
261 ch = irq - chip->irq_base;
262 if (irq <= chip->irq_base + 7) {
263 im_reg = &chip->reg->regs[chip->ch].im_0;
264 im_pos = ch;
265 } else {
266 im_reg = &chip->reg->regs[chip->ch].im_1;
267 im_pos = ch - 8;
268 }
269 dev_dbg(chip->dev, "%s:irq=%d type=%d ch=%d pos=%d type=%d\n",
270 __func__, irq, type, ch, im_pos, type);
271
272 spin_lock_irqsave(&chip->spinlock, flags);
273
274 switch (type) {
275 case IRQ_TYPE_EDGE_RISING:
276 val = IOH_EDGE_RISING;
277 break;
278 case IRQ_TYPE_EDGE_FALLING:
279 val = IOH_EDGE_FALLING;
280 break;
281 case IRQ_TYPE_EDGE_BOTH:
282 val = IOH_EDGE_BOTH;
283 break;
284 case IRQ_TYPE_LEVEL_HIGH:
285 val = IOH_LEVEL_H;
286 break;
287 case IRQ_TYPE_LEVEL_LOW:
288 val = IOH_LEVEL_L;
289 break;
290 case IRQ_TYPE_PROBE:
291 goto end;
292 default:
293 dev_warn(chip->dev, "%s: unknown type(%dd)",
294 __func__, type);
295 goto end;
296 }
297
298 /* Set interrupt mode */
299 im = ioread32(im_reg) & ~(IOH_IM_MASK << (im_pos * 4));
300 iowrite32(im | (val << (im_pos * 4)), im_reg);
301
302 /* iclr */
303 iowrite32(BIT(ch), &chip->reg->regs[chip->ch].iclr);
304
305 /* IMASKCLR */
306 iowrite32(BIT(ch), &chip->reg->regs[chip->ch].imaskclr);
307
308 /* Enable interrupt */
309 ien = ioread32(&chip->reg->regs[chip->ch].ien);
310 iowrite32(ien | BIT(ch), &chip->reg->regs[chip->ch].ien);
311 end:
312 spin_unlock_irqrestore(&chip->spinlock, flags);
313
314 return 0;
315 }
316
317 static void ioh_irq_unmask(struct irq_data *d)
318 {
319 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
320 struct ioh_gpio *chip = gc->private;
321
322 iowrite32(1 << (d->irq - chip->irq_base),
323 &chip->reg->regs[chip->ch].imaskclr);
324 }
325
326 static void ioh_irq_mask(struct irq_data *d)
327 {
328 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
329 struct ioh_gpio *chip = gc->private;
330
331 iowrite32(1 << (d->irq - chip->irq_base),
332 &chip->reg->regs[chip->ch].imask);
333 }
334
335 static irqreturn_t ioh_gpio_handler(int irq, void *dev_id)
336 {
337 struct ioh_gpio *chip = dev_id;
338 u32 reg_val;
339 int i, j;
340 int ret = IRQ_NONE;
341
342 for (i = 0; i < 8; i++) {
343 reg_val = ioread32(&chip->reg->regs[i].istatus);
344 for (j = 0; j < num_ports[i]; j++) {
345 if (reg_val & BIT(j)) {
346 dev_dbg(chip->dev,
347 "%s:[%d]:irq=%d status=0x%x\n",
348 __func__, j, irq, reg_val);
349 iowrite32(BIT(j),
350 &chip->reg->regs[chip->ch].iclr);
351 generic_handle_irq(chip->irq_base + j);
352 ret = IRQ_HANDLED;
353 }
354 }
355 }
356 return ret;
357 }
358
359 static __devinit void ioh_gpio_alloc_generic_chip(struct ioh_gpio *chip,
360 unsigned int irq_start, unsigned int num)
361 {
362 struct irq_chip_generic *gc;
363 struct irq_chip_type *ct;
364
365 gc = irq_alloc_generic_chip("ioh_gpio", 1, irq_start, chip->base,
366 handle_simple_irq);
367 gc->private = chip;
368 ct = gc->chip_types;
369
370 ct->chip.irq_mask = ioh_irq_mask;
371 ct->chip.irq_unmask = ioh_irq_unmask;
372 ct->chip.irq_set_type = ioh_irq_type;
373
374 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
375 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
376 }
377
378 static int __devinit ioh_gpio_probe(struct pci_dev *pdev,
379 const struct pci_device_id *id)
380 {
381 int ret;
382 int i, j;
383 struct ioh_gpio *chip;
384 void __iomem *base;
385 void __iomem *chip_save;
386 int irq_base;
387
388 ret = pci_enable_device(pdev);
389 if (ret) {
390 dev_err(&pdev->dev, "%s : pci_enable_device failed", __func__);
391 goto err_pci_enable;
392 }
393
394 ret = pci_request_regions(pdev, KBUILD_MODNAME);
395 if (ret) {
396 dev_err(&pdev->dev, "pci_request_regions failed-%d", ret);
397 goto err_request_regions;
398 }
399
400 base = pci_iomap(pdev, 1, 0);
401 if (base == 0) {
402 dev_err(&pdev->dev, "%s : pci_iomap failed", __func__);
403 ret = -ENOMEM;
404 goto err_iomap;
405 }
406
407 chip_save = kzalloc(sizeof(*chip) * 8, GFP_KERNEL);
408 if (chip_save == NULL) {
409 dev_err(&pdev->dev, "%s : kzalloc failed", __func__);
410 ret = -ENOMEM;
411 goto err_kzalloc;
412 }
413
414 chip = chip_save;
415 for (i = 0; i < 8; i++, chip++) {
416 chip->dev = &pdev->dev;
417 chip->base = base;
418 chip->reg = chip->base;
419 chip->ch = i;
420 mutex_init(&chip->lock);
421 ioh_gpio_setup(chip, num_ports[i]);
422 ret = gpiochip_add(&chip->gpio);
423 if (ret) {
424 dev_err(&pdev->dev, "IOH gpio: Failed to register GPIO\n");
425 goto err_gpiochip_add;
426 }
427 }
428
429 chip = chip_save;
430 for (j = 0; j < 8; j++, chip++) {
431 irq_base = irq_alloc_descs(-1, IOH_IRQ_BASE, num_ports[j],
432 NUMA_NO_NODE);
433 if (irq_base < 0) {
434 dev_warn(&pdev->dev,
435 "ml_ioh_gpio: Failed to get IRQ base num\n");
436 chip->irq_base = -1;
437 goto err_irq_alloc_descs;
438 }
439 chip->irq_base = irq_base;
440 ioh_gpio_alloc_generic_chip(chip, irq_base, num_ports[j]);
441 }
442
443 chip = chip_save;
444 ret = request_irq(pdev->irq, ioh_gpio_handler,
445 IRQF_SHARED, KBUILD_MODNAME, chip);
446 if (ret != 0) {
447 dev_err(&pdev->dev,
448 "%s request_irq failed\n", __func__);
449 goto err_request_irq;
450 }
451
452 pci_set_drvdata(pdev, chip);
453
454 return 0;
455
456 err_request_irq:
457 chip = chip_save;
458 err_irq_alloc_descs:
459 while (--j >= 0) {
460 chip--;
461 irq_free_descs(chip->irq_base, num_ports[j]);
462 }
463
464 chip = chip_save;
465 err_gpiochip_add:
466 while (--i >= 0) {
467 chip--;
468 ret = gpiochip_remove(&chip->gpio);
469 if (ret)
470 dev_err(&pdev->dev, "Failed gpiochip_remove(%d)\n", i);
471 }
472 kfree(chip_save);
473
474 err_kzalloc:
475 pci_iounmap(pdev, base);
476
477 err_iomap:
478 pci_release_regions(pdev);
479
480 err_request_regions:
481 pci_disable_device(pdev);
482
483 err_pci_enable:
484
485 dev_err(&pdev->dev, "%s Failed returns %d\n", __func__, ret);
486 return ret;
487 }
488
489 static void __devexit ioh_gpio_remove(struct pci_dev *pdev)
490 {
491 int err;
492 int i;
493 struct ioh_gpio *chip = pci_get_drvdata(pdev);
494 void __iomem *chip_save;
495
496 chip_save = chip;
497
498 free_irq(pdev->irq, chip);
499
500 for (i = 0; i < 8; i++, chip++) {
501 irq_free_descs(chip->irq_base, num_ports[i]);
502 err = gpiochip_remove(&chip->gpio);
503 if (err)
504 dev_err(&pdev->dev, "Failed gpiochip_remove\n");
505 }
506
507 chip = chip_save;
508 pci_iounmap(pdev, chip->base);
509 pci_release_regions(pdev);
510 pci_disable_device(pdev);
511 kfree(chip);
512 }
513
514 #ifdef CONFIG_PM
515 static int ioh_gpio_suspend(struct pci_dev *pdev, pm_message_t state)
516 {
517 s32 ret;
518 struct ioh_gpio *chip = pci_get_drvdata(pdev);
519 unsigned long flags;
520
521 spin_lock_irqsave(&chip->spinlock, flags);
522 ioh_gpio_save_reg_conf(chip);
523 spin_unlock_irqrestore(&chip->spinlock, flags);
524
525 ret = pci_save_state(pdev);
526 if (ret) {
527 dev_err(&pdev->dev, "pci_save_state Failed-%d\n", ret);
528 return ret;
529 }
530 pci_disable_device(pdev);
531 pci_set_power_state(pdev, PCI_D0);
532 ret = pci_enable_wake(pdev, PCI_D0, 1);
533 if (ret)
534 dev_err(&pdev->dev, "pci_enable_wake Failed -%d\n", ret);
535
536 return 0;
537 }
538
539 static int ioh_gpio_resume(struct pci_dev *pdev)
540 {
541 s32 ret;
542 struct ioh_gpio *chip = pci_get_drvdata(pdev);
543 unsigned long flags;
544
545 ret = pci_enable_wake(pdev, PCI_D0, 0);
546
547 pci_set_power_state(pdev, PCI_D0);
548 ret = pci_enable_device(pdev);
549 if (ret) {
550 dev_err(&pdev->dev, "pci_enable_device Failed-%d ", ret);
551 return ret;
552 }
553 pci_restore_state(pdev);
554
555 spin_lock_irqsave(&chip->spinlock, flags);
556 iowrite32(0x01, &chip->reg->srst);
557 iowrite32(0x00, &chip->reg->srst);
558 ioh_gpio_restore_reg_conf(chip);
559 spin_unlock_irqrestore(&chip->spinlock, flags);
560
561 return 0;
562 }
563 #else
564 #define ioh_gpio_suspend NULL
565 #define ioh_gpio_resume NULL
566 #endif
567
568 static DEFINE_PCI_DEVICE_TABLE(ioh_gpio_pcidev_id) = {
569 { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x802E) },
570 { 0, }
571 };
572 MODULE_DEVICE_TABLE(pci, ioh_gpio_pcidev_id);
573
574 static struct pci_driver ioh_gpio_driver = {
575 .name = "ml_ioh_gpio",
576 .id_table = ioh_gpio_pcidev_id,
577 .probe = ioh_gpio_probe,
578 .remove = __devexit_p(ioh_gpio_remove),
579 .suspend = ioh_gpio_suspend,
580 .resume = ioh_gpio_resume
581 };
582
583 static int __init ioh_gpio_pci_init(void)
584 {
585 return pci_register_driver(&ioh_gpio_driver);
586 }
587 module_init(ioh_gpio_pci_init);
588
589 static void __exit ioh_gpio_pci_exit(void)
590 {
591 pci_unregister_driver(&ioh_gpio_driver);
592 }
593 module_exit(ioh_gpio_pci_exit);
594
595 MODULE_DESCRIPTION("OKI SEMICONDUCTOR ML-IOH series GPIO Driver");
596 MODULE_LICENSE("GPL");
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree