1 /* cg14.c: CGFOURTEEN frame buffer driver
3 * Copyright (C) 2003 David S. Miller (davem@redhat.com)
4 * Copyright (C) 1996,1998 Jakub Jelinek (jj@ultra.linux.cz)
5 * Copyright (C) 1995 Miguel de Icaza (miguel@nuclecu.unam.mx)
7 * Driver layout based loosely on tgafb.c, see that file for credits.
10 #include <linux/module.h>
11 #include <linux/kernel.h>
12 #include <linux/errno.h>
13 #include <linux/string.h>
14 #include <linux/slab.h>
15 #include <linux/delay.h>
16 #include <linux/init.h>
22 #include <asm/oplib.h>
31 static int cg14_setcolreg(unsigned, unsigned, unsigned, unsigned,
32 unsigned, struct fb_info
*);
34 static int cg14_mmap(struct fb_info
*, struct vm_area_struct
*);
35 static int cg14_ioctl(struct fb_info
*, unsigned int, unsigned long);
36 static int cg14_pan_display(struct fb_var_screeninfo
*, struct fb_info
*);
39 * Frame buffer operations
42 static struct fb_ops cg14_ops
= {
44 .fb_setcolreg
= cg14_setcolreg
,
45 .fb_pan_display
= cg14_pan_display
,
46 .fb_fillrect
= cfb_fillrect
,
47 .fb_copyarea
= cfb_copyarea
,
48 .fb_imageblit
= cfb_imageblit
,
50 .fb_ioctl
= cg14_ioctl
,
52 .fb_compat_ioctl
= sbusfb_compat_ioctl
,
56 #define CG14_MCR_INTENABLE_SHIFT 7
57 #define CG14_MCR_INTENABLE_MASK 0x80
58 #define CG14_MCR_VIDENABLE_SHIFT 6
59 #define CG14_MCR_VIDENABLE_MASK 0x40
60 #define CG14_MCR_PIXMODE_SHIFT 4
61 #define CG14_MCR_PIXMODE_MASK 0x30
62 #define CG14_MCR_TMR_SHIFT 2
63 #define CG14_MCR_TMR_MASK 0x0c
64 #define CG14_MCR_TMENABLE_SHIFT 1
65 #define CG14_MCR_TMENABLE_MASK 0x02
66 #define CG14_MCR_RESET_SHIFT 0
67 #define CG14_MCR_RESET_MASK 0x01
68 #define CG14_REV_REVISION_SHIFT 4
69 #define CG14_REV_REVISION_MASK 0xf0
70 #define CG14_REV_IMPL_SHIFT 0
71 #define CG14_REV_IMPL_MASK 0x0f
72 #define CG14_VBR_FRAMEBASE_SHIFT 12
73 #define CG14_VBR_FRAMEBASE_MASK 0x00fff000
74 #define CG14_VMCR1_SETUP_SHIFT 0
75 #define CG14_VMCR1_SETUP_MASK 0x000001ff
76 #define CG14_VMCR1_VCONFIG_SHIFT 9
77 #define CG14_VMCR1_VCONFIG_MASK 0x00000e00
78 #define CG14_VMCR2_REFRESH_SHIFT 0
79 #define CG14_VMCR2_REFRESH_MASK 0x00000001
80 #define CG14_VMCR2_TESTROWCNT_SHIFT 1
81 #define CG14_VMCR2_TESTROWCNT_MASK 0x00000002
82 #define CG14_VMCR2_FBCONFIG_SHIFT 2
83 #define CG14_VMCR2_FBCONFIG_MASK 0x0000000c
84 #define CG14_VCR_REFRESHREQ_SHIFT 0
85 #define CG14_VCR_REFRESHREQ_MASK 0x000003ff
86 #define CG14_VCR1_REFRESHENA_SHIFT 10
87 #define CG14_VCR1_REFRESHENA_MASK 0x00000400
88 #define CG14_VCA_CAD_SHIFT 0
89 #define CG14_VCA_CAD_MASK 0x000003ff
90 #define CG14_VCA_VERS_SHIFT 10
91 #define CG14_VCA_VERS_MASK 0x00000c00
92 #define CG14_VCA_RAMSPEED_SHIFT 12
93 #define CG14_VCA_RAMSPEED_MASK 0x00001000
94 #define CG14_VCA_8MB_SHIFT 13
95 #define CG14_VCA_8MB_MASK 0x00002000
97 #define CG14_MCR_PIXMODE_8 0
98 #define CG14_MCR_PIXMODE_16 2
99 #define CG14_MCR_PIXMODE_32 3
102 volatile u8 mcr
; /* Master Control Reg */
103 volatile u8 ppr
; /* Packed Pixel Reg */
104 volatile u8 tms
[2]; /* Test Mode Status Regs */
105 volatile u8 msr
; /* Master Status Reg */
106 volatile u8 fsr
; /* Fault Status Reg */
107 volatile u8 rev
; /* Revision & Impl */
108 volatile u8 ccr
; /* Clock Control Reg */
109 volatile u32 tmr
; /* Test Mode Read Back */
110 volatile u8 mod
; /* Monitor Operation Data Reg */
111 volatile u8 acr
; /* Aux Control */
113 volatile u16 hct
; /* Hor Counter */
114 volatile u16 vct
; /* Vert Counter */
115 volatile u16 hbs
; /* Hor Blank Start */
116 volatile u16 hbc
; /* Hor Blank Clear */
117 volatile u16 hss
; /* Hor Sync Start */
118 volatile u16 hsc
; /* Hor Sync Clear */
119 volatile u16 csc
; /* Composite Sync Clear */
120 volatile u16 vbs
; /* Vert Blank Start */
121 volatile u16 vbc
; /* Vert Blank Clear */
122 volatile u16 vss
; /* Vert Sync Start */
123 volatile u16 vsc
; /* Vert Sync Clear */
126 volatile u16 fsa
; /* Fault Status Address */
127 volatile u16 adr
; /* Address Registers */
129 volatile u8 pcg
[0x100]; /* Pixel Clock Generator */
130 volatile u32 vbr
; /* Frame Base Row */
131 volatile u32 vmcr
; /* VBC Master Control */
132 volatile u32 vcr
; /* VBC refresh */
133 volatile u32 vca
; /* VBC Config */
136 #define CG14_CCR_ENABLE 0x04
137 #define CG14_CCR_SELECT 0x02 /* HW/Full screen */
140 volatile u32 cpl0
[32]; /* Enable plane 0 */
141 volatile u32 cpl1
[32]; /* Color selection plane */
142 volatile u8 ccr
; /* Cursor Control Reg */
144 volatile u16 cursx
; /* Cursor x,y position */
145 volatile u16 cursy
; /* Cursor x,y position */
149 volatile u32 cpl0i
[32]; /* Enable plane 0 autoinc */
150 volatile u32 cpl1i
[32]; /* Color selection autoinc */
154 volatile u8 addr
; /* Address Register */
156 volatile u8 glut
; /* Gamma table */
158 volatile u8 select
; /* Register Select */
160 volatile u8 mode
; /* Mode Register */
164 volatile u8 x_xlut
[256];
165 volatile u8 x_xlutd
[256];
167 volatile u8 x_xlut_inc
[256];
168 volatile u8 x_xlutd_inc
[256];
171 /* Color look up table (clut) */
172 /* Each one of these arrays hold the color lookup table (for 256
173 * colors) for each MDI page (I assume then there should be 4 MDI
174 * pages, I still wonder what they are. I have seen NeXTStep split
175 * the screen in four parts, while operating in 24 bits mode. Each
176 * integer holds 4 values: alpha value (transparency channel, thanks
177 * go to John Stone (johns@umr.edu) from OpenBSD), red, green and blue
179 * I currently use the clut instead of the Xlut
183 u32 c_clutd
[256]; /* i wonder what the 'd' is for */
184 u32 c_clut_inc
[256];
185 u32 c_clutd_inc
[256];
188 #define CG14_MMAP_ENTRIES 16
192 struct cg14_regs __iomem
*regs
;
193 struct cg14_clut __iomem
*clut
;
194 struct cg14_cursor __iomem
*cursor
;
197 #define CG14_FLAG_BLANKED 0x00000001
199 unsigned long physbase
;
200 unsigned long iospace
;
201 unsigned long fbsize
;
203 struct sbus_mmap_map mmap_map
[CG14_MMAP_ENTRIES
];
207 struct sbus_dev
*sdev
;
210 static void __cg14_reset(struct cg14_par
*par
)
212 struct cg14_regs __iomem
*regs
= par
->regs
;
215 val
= sbus_readb(®s
->mcr
);
216 val
&= ~(CG14_MCR_PIXMODE_MASK
);
217 sbus_writeb(val
, ®s
->mcr
);
220 static int cg14_pan_display(struct fb_var_screeninfo
*var
, struct fb_info
*info
)
222 struct cg14_par
*par
= (struct cg14_par
*) info
->par
;
225 /* We just use this to catch switches out of
228 spin_lock_irqsave(&par
->lock
, flags
);
230 spin_unlock_irqrestore(&par
->lock
, flags
);
232 if (var
->xoffset
|| var
->yoffset
|| var
->vmode
)
238 * cg14_setcolreg - Optional function. Sets a color register.
239 * @regno: boolean, 0 copy local, 1 get_user() function
240 * @red: frame buffer colormap structure
241 * @green: The green value which can be up to 16 bits wide
242 * @blue: The blue value which can be up to 16 bits wide.
243 * @transp: If supported the alpha value which can be up to 16 bits wide.
244 * @info: frame buffer info structure
246 static int cg14_setcolreg(unsigned regno
,
247 unsigned red
, unsigned green
, unsigned blue
,
248 unsigned transp
, struct fb_info
*info
)
250 struct cg14_par
*par
= (struct cg14_par
*) info
->par
;
251 struct cg14_clut __iomem
*clut
= par
->clut
;
261 val
= (red
| (green
<< 8) | (blue
<< 16));
263 spin_lock_irqsave(&par
->lock
, flags
);
264 sbus_writel(val
, &clut
->c_clut
[regno
]);
265 spin_unlock_irqrestore(&par
->lock
, flags
);
270 static int cg14_mmap(struct fb_info
*info
, struct vm_area_struct
*vma
)
272 struct cg14_par
*par
= (struct cg14_par
*) info
->par
;
274 return sbusfb_mmap_helper(par
->mmap_map
,
275 par
->physbase
, par
->fbsize
,
279 static int cg14_ioctl(struct fb_info
*info
, unsigned int cmd
, unsigned long arg
)
281 struct cg14_par
*par
= (struct cg14_par
*) info
->par
;
282 struct cg14_regs __iomem
*regs
= par
->regs
;
283 struct mdi_cfginfo kmdi
, __user
*mdii
;
285 int cur_mode
, mode
, ret
= 0;
289 spin_lock_irqsave(&par
->lock
, flags
);
291 spin_unlock_irqrestore(&par
->lock
, flags
);
294 case MDI_GET_CFGINFO
:
295 memset(&kmdi
, 0, sizeof(kmdi
));
297 spin_lock_irqsave(&par
->lock
, flags
);
298 kmdi
.mdi_type
= FBTYPE_MDICOLOR
;
299 kmdi
.mdi_height
= info
->var
.yres
;
300 kmdi
.mdi_width
= info
->var
.xres
;
301 kmdi
.mdi_mode
= par
->mode
;
302 kmdi
.mdi_pixfreq
= 72; /* FIXME */
303 kmdi
.mdi_size
= par
->ramsize
;
304 spin_unlock_irqrestore(&par
->lock
, flags
);
306 mdii
= (struct mdi_cfginfo __user
*) arg
;
307 if (copy_to_user(mdii
, &kmdi
, sizeof(kmdi
)))
311 case MDI_SET_PIXELMODE
:
312 if (get_user(mode
, (int __user
*) arg
)) {
317 spin_lock_irqsave(&par
->lock
, flags
);
318 cur_mode
= sbus_readb(®s
->mcr
);
319 cur_mode
&= ~CG14_MCR_PIXMODE_MASK
;
322 cur_mode
|= (CG14_MCR_PIXMODE_32
<<
323 CG14_MCR_PIXMODE_SHIFT
);
327 cur_mode
|= (CG14_MCR_PIXMODE_16
<<
328 CG14_MCR_PIXMODE_SHIFT
);
339 sbus_writeb(cur_mode
, ®s
->mcr
);
342 spin_unlock_irqrestore(&par
->lock
, flags
);
346 ret
= sbusfb_ioctl_helper(cmd
, arg
, info
,
347 FBTYPE_MDICOLOR
, 8, par
->fbsize
);
358 static void cg14_init_fix(struct fb_info
*info
, int linebytes
)
360 struct cg14_par
*par
= (struct cg14_par
*)info
->par
;
365 name
= par
->sdev
->prom_name
;
367 strlcpy(info
->fix
.id
, name
, sizeof(info
->fix
.id
));
369 info
->fix
.type
= FB_TYPE_PACKED_PIXELS
;
370 info
->fix
.visual
= FB_VISUAL_PSEUDOCOLOR
;
372 info
->fix
.line_length
= linebytes
;
374 info
->fix
.accel
= FB_ACCEL_SUN_CG14
;
377 static struct sbus_mmap_map __cg14_mmap_map
[CG14_MMAP_ENTRIES
] __initdata
= {
404 .voff
= CG3_MMAP_OFFSET
- 0x7000,
409 .voff
= CG3_MMAP_OFFSET
,
411 .size
= SBUS_MMAP_FBSIZE(1)
414 .voff
= MDI_CURSOR_MAP
,
419 .voff
= MDI_CHUNKY_BGR_MAP
,
424 .voff
= MDI_PLANAR_X16_MAP
,
429 .voff
= MDI_PLANAR_C16_MAP
,
434 .voff
= MDI_PLANAR_X32_MAP
,
439 .voff
= MDI_PLANAR_B32_MAP
,
444 .voff
= MDI_PLANAR_G32_MAP
,
449 .voff
= MDI_PLANAR_R32_MAP
,
459 struct list_head list
;
461 static LIST_HEAD(cg14_list
);
463 static void cg14_init_one(struct sbus_dev
*sdev
, int node
, int parent_node
)
465 struct all_info
*all
;
466 unsigned long phys
, rphys
;
468 int is_8mb
, linebytes
, i
;
471 if (prom_getproperty(node
, "address",
472 (char *) &bases
[0], sizeof(bases
)) <= 0
474 printk(KERN_ERR
"cg14: Device is not mapped.\n");
477 if (__get_iospace(bases
[0]) != __get_iospace(bases
[1])) {
478 printk(KERN_ERR
"cg14: I/O spaces don't match.\n");
483 all
= kmalloc(sizeof(*all
), GFP_KERNEL
);
485 printk(KERN_ERR
"cg14: Cannot allocate memory.\n");
488 memset(all
, 0, sizeof(*all
));
490 INIT_LIST_HEAD(&all
->list
);
492 spin_lock_init(&all
->par
.lock
);
494 sbusfb_fill_var(&all
->info
.var
, node
, 8);
495 all
->info
.var
.red
.length
= 8;
496 all
->info
.var
.green
.length
= 8;
497 all
->info
.var
.blue
.length
= 8;
499 linebytes
= prom_getintdefault(node
, "linebytes",
501 all
->par
.fbsize
= PAGE_ALIGN(linebytes
* all
->info
.var
.yres
);
503 all
->par
.sdev
= sdev
;
505 rphys
= sdev
->reg_addrs
[0].phys_addr
;
506 all
->par
.physbase
= phys
= sdev
->reg_addrs
[1].phys_addr
;
507 all
->par
.iospace
= sdev
->reg_addrs
[0].which_io
;
509 all
->par
.regs
= sbus_ioremap(&sdev
->resource
[0], 0,
510 sizeof(struct cg14_regs
),
512 all
->par
.clut
= sbus_ioremap(&sdev
->resource
[0], CG14_CLUT1
,
513 sizeof(struct cg14_clut
),
515 all
->par
.cursor
= sbus_ioremap(&sdev
->resource
[0], CG14_CURSORREGS
,
516 sizeof(struct cg14_cursor
),
518 all
->info
.screen_base
= sbus_ioremap(&sdev
->resource
[1], 0,
519 all
->par
.fbsize
, "cg14 ram");
521 rphys
= __get_phys(bases
[0]);
522 all
->par
.physbase
= phys
= __get_phys(bases
[1]);
523 all
->par
.iospace
= __get_iospace(bases
[0]);
524 all
->par
.regs
= (struct cg14_regs __iomem
*)(unsigned long)bases
[0];
525 all
->par
.clut
= (struct cg14_clut __iomem
*)((unsigned long)bases
[0] +
528 (struct cg14_cursor __iomem
*)((unsigned long)bases
[0] +
531 all
->info
.screen_base
= (char __iomem
*)(unsigned long)bases
[1];
534 prom_getproperty(node
, "reg", (char *) &bases
[0], sizeof(bases
));
535 is_8mb
= (bases
[5] == 0x800000);
537 if (sizeof(all
->par
.mmap_map
) != sizeof(__cg14_mmap_map
)) {
538 extern void __cg14_mmap_sized_wrongly(void);
540 __cg14_mmap_sized_wrongly();
543 memcpy(&all
->par
.mmap_map
, &__cg14_mmap_map
, sizeof(all
->par
.mmap_map
));
544 for (i
= 0; i
< CG14_MMAP_ENTRIES
; i
++) {
545 struct sbus_mmap_map
*map
= &all
->par
.mmap_map
[i
];
549 if (map
->poff
& 0x80000000)
550 map
->poff
= (map
->poff
& 0x7fffffff) + rphys
- phys
;
552 map
->size
>= 0x100000 &&
553 map
->size
<= 0x400000)
557 all
->par
.mode
= MDI_8_PIX
;
558 all
->par
.ramsize
= (is_8mb
? 0x800000 : 0x400000);
560 all
->info
.flags
= FBINFO_DEFAULT
| FBINFO_HWACCEL_YPAN
;
561 all
->info
.fbops
= &cg14_ops
;
562 all
->info
.par
= &all
->par
;
564 __cg14_reset(&all
->par
);
566 if (fb_alloc_cmap(&all
->info
.cmap
, 256, 0)) {
567 printk(KERN_ERR
"cg14: Could not allocate color map.\n");
571 fb_set_cmap(&all
->info
.cmap
, &all
->info
);
573 cg14_init_fix(&all
->info
, linebytes
);
575 if (register_framebuffer(&all
->info
) < 0) {
576 printk(KERN_ERR
"cg14: Could not register framebuffer.\n");
577 fb_dealloc_cmap(&all
->info
.cmap
);
582 list_add(&all
->list
, &cg14_list
);
584 printk("cg14: cgfourteen at %lx:%lx, %dMB\n",
585 all
->par
.iospace
, all
->par
.physbase
, all
->par
.ramsize
>> 20);
589 int __init
cg14_init(void)
591 struct sbus_bus
*sbus
;
592 struct sbus_dev
*sdev
;
594 if (fb_get_options("cg14fb", NULL
))
597 #ifdef CONFIG_SPARC32
601 root
= prom_getchild(prom_root_node
);
602 root
= prom_searchsiblings(root
, "obio");
604 node
= prom_searchsiblings(prom_getchild(root
),
607 cg14_init_one(NULL
, node
, root
);
611 for_all_sbusdev(sdev
, sbus
) {
612 if (!strcmp(sdev
->prom_name
, "cgfourteen"))
613 cg14_init_one(sdev
, sdev
->prom_node
, sbus
->prom_node
);
619 void __exit
cg14_exit(void)
621 struct list_head
*pos
, *tmp
;
623 list_for_each_safe(pos
, tmp
, &cg14_list
) {
624 struct all_info
*all
= list_entry(pos
, typeof(*all
), list
);
626 unregister_framebuffer(&all
->info
);
627 fb_dealloc_cmap(&all
->info
.cmap
);
633 cg14_setup(char *arg
)
635 /* No cmdline options yet... */
639 module_init(cg14_init
);
642 module_exit(cg14_exit
);
645 MODULE_DESCRIPTION("framebuffer driver for CGfourteen chipsets");
646 MODULE_AUTHOR("David S. Miller <davem@redhat.com>");
647 MODULE_LICENSE("GPL");