drivers/net/bnx2x.h

   1 /* bnx2x.h: Broadcom Everest network driver.
   2  *
   3  * Copyright (c) 2007-2009 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  *
   9  * Maintained by: Eilon Greenstein <eilong@broadcom.com>
  10  * Written by: Eliezer Tamir
  11  * Based on code from Michael Chan's bnx2 driver
  12  */
  13
  14 #ifndef BNX2X_H
  15 #define BNX2X_H
  16
  17 /* compilation time flags */
  18
  19 /* define this to make the driver freeze on error to allow getting debug info
  20  * (you will need to reboot afterwards) */
  21 /* #define BNX2X_STOP_ON_ERROR */
  22
  23 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  24 #define BCM_VLAN                        1
  25 #endif
  26
  27 #if defined(CONFIG_CNIC) || defined(CONFIG_CNIC_MODULE)
  28 #define BCM_CNIC 1
  29 #include "cnic_if.h"
  30 #endif
  31
  32 #define BNX2X_MULTI_QUEUE
  33
  34 #define BNX2X_NEW_NAPI
  35
  36
  37
  38 #include <linux/mdio.h>
  39 #include "bnx2x_reg.h"
  40 #include "bnx2x_fw_defs.h"
  41 #include "bnx2x_hsi.h"
  42 #include "bnx2x_link.h"
  43
  44 /* error/debug prints */
  45
  46 #define DRV_MODULE_NAME         "bnx2x"
  47 #define PFX DRV_MODULE_NAME     ": "
  48
  49 /* for messages that are currently off */
  50 #define BNX2X_MSG_OFF                   0
  51 #define BNX2X_MSG_MCP                   0x010000 /* was: NETIF_MSG_HW */
  52 #define BNX2X_MSG_STATS                 0x020000 /* was: NETIF_MSG_TIMER */
  53 #define BNX2X_MSG_NVM                   0x040000 /* was: NETIF_MSG_HW */
  54 #define BNX2X_MSG_DMAE                  0x080000 /* was: NETIF_MSG_HW */
  55 #define BNX2X_MSG_SP                    0x100000 /* was: NETIF_MSG_INTR */
  56 #define BNX2X_MSG_FP                    0x200000 /* was: NETIF_MSG_INTR */
  57
  58 #define DP_LEVEL                        KERN_NOTICE     /* was: KERN_DEBUG */
  59
  60 /* regular debug print */
  61 #define DP(__mask, __fmt, __args...) do { \
  62         if (bp->msglevel & (__mask)) \
  63                 printk(DP_LEVEL "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
  64                         bp->dev ? (bp->dev->name) : "?", ##__args); \
  65         } while (0)
  66
  67 /* errors debug print */
  68 #define BNX2X_DBG_ERR(__fmt, __args...) do { \
  69         if (bp->msglevel & NETIF_MSG_PROBE) \
  70                 printk(KERN_ERR "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
  71                         bp->dev ? (bp->dev->name) : "?", ##__args); \
  72         } while (0)
  73
  74 /* for errors (never masked) */
  75 #define BNX2X_ERR(__fmt, __args...) do { \
  76         printk(KERN_ERR "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
  77                 bp->dev ? (bp->dev->name) : "?", ##__args); \
  78         } while (0)
  79
  80 /* before we have a dev->name use dev_info() */
  81 #define BNX2X_DEV_INFO(__fmt, __args...) do { \
  82         if (bp->msglevel & NETIF_MSG_PROBE) \
  83                 dev_info(&bp->pdev->dev, __fmt, ##__args); \
  84         } while (0)
  85
  86
  87 #ifdef BNX2X_STOP_ON_ERROR
  88 #define bnx2x_panic() do { \
  89                 bp->panic = 1; \
  90                 BNX2X_ERR("driver assert\n"); \
  91                 bnx2x_int_disable(bp); \
  92                 bnx2x_panic_dump(bp); \
  93         } while (0)
  94 #else
  95 #define bnx2x_panic() do { \
  96                 bp->panic = 1; \
  97                 BNX2X_ERR("driver assert\n"); \
  98                 bnx2x_panic_dump(bp); \
  99         } while (0)
 100 #endif
 101
 102
 103 #define U64_LO(x)                       (u32)(((u64)(x)) & 0xffffffff)
 104 #define U64_HI(x)                       (u32)(((u64)(x)) >> 32)
 105 #define HILO_U64(hi, lo)                ((((u64)(hi)) << 32) + (lo))
 106
 107
 108 #define REG_ADDR(bp, offset)            (bp->regview + offset)
 109
 110 #define REG_RD(bp, offset)              readl(REG_ADDR(bp, offset))
 111 #define REG_RD8(bp, offset)             readb(REG_ADDR(bp, offset))
 112
 113 #define REG_WR(bp, offset, val)         writel((u32)val, REG_ADDR(bp, offset))
 114 #define REG_WR8(bp, offset, val)        writeb((u8)val, REG_ADDR(bp, offset))
 115 #define REG_WR16(bp, offset, val)       writew((u16)val, REG_ADDR(bp, offset))
 116
 117 #define REG_RD_IND(bp, offset)          bnx2x_reg_rd_ind(bp, offset)
 118 #define REG_WR_IND(bp, offset, val)     bnx2x_reg_wr_ind(bp, offset, val)
 119
 120 #define REG_RD_DMAE(bp, offset, valp, len32) \
 121         do { \
 122                 bnx2x_read_dmae(bp, offset, len32);\
 123                 memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \
 124         } while (0)
 125
 126 #define REG_WR_DMAE(bp, offset, valp, len32) \
 127         do { \
 128                 memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \
 129                 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \
 130                                  offset, len32); \
 131         } while (0)
 132
 133 #define VIRT_WR_DMAE_LEN(bp, data, addr, len32) \
 134         do { \
 135                 memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \
 136                 bnx2x_write_big_buf_wb(bp, addr, len32); \
 137         } while (0)
 138
 139 #define SHMEM_ADDR(bp, field)           (bp->common.shmem_base + \
 140                                          offsetof(struct shmem_region, field))
 141 #define SHMEM_RD(bp, field)             REG_RD(bp, SHMEM_ADDR(bp, field))
 142 #define SHMEM_WR(bp, field, val)        REG_WR(bp, SHMEM_ADDR(bp, field), val)
 143
 144 #define SHMEM2_ADDR(bp, field)          (bp->common.shmem2_base + \
 145                                          offsetof(struct shmem2_region, field))
 146 #define SHMEM2_RD(bp, field)            REG_RD(bp, SHMEM2_ADDR(bp, field))
 147 #define SHMEM2_WR(bp, field, val)       REG_WR(bp, SHMEM2_ADDR(bp, field), val)
 148
 149 #define EMAC_RD(bp, reg)                REG_RD(bp, emac_base + reg)
 150 #define EMAC_WR(bp, reg, val)           REG_WR(bp, emac_base + reg, val)
 151
 152
 153 /* fast path */
 154
 155 struct sw_rx_bd {
 156         struct sk_buff  *skb;
 157         DECLARE_PCI_UNMAP_ADDR(mapping)
 158 };
 159
 160 struct sw_tx_bd {
 161         struct sk_buff  *skb;
 162         u16             first_bd;
 163         u8              flags;
 164 /* Set on the first BD descriptor when there is a split BD */
 165 #define BNX2X_TSO_SPLIT_BD              (1<<0)
 166 };
 167
 168 struct sw_rx_page {
 169         struct page     *page;
 170         DECLARE_PCI_UNMAP_ADDR(mapping)
 171 };
 172
 173 union db_prod {
 174         struct doorbell_set_prod data;
 175         u32             raw;
 176 };
 177
 178
 179 /* MC hsi */
 180 #define BCM_PAGE_SHIFT                  12
 181 #define BCM_PAGE_SIZE                   (1 << BCM_PAGE_SHIFT)
 182 #define BCM_PAGE_MASK                   (~(BCM_PAGE_SIZE - 1))
 183 #define BCM_PAGE_ALIGN(addr)    (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK)
 184
 185 #define PAGES_PER_SGE_SHIFT             0
 186 #define PAGES_PER_SGE                   (1 << PAGES_PER_SGE_SHIFT)
 187 #define SGE_PAGE_SIZE                   PAGE_SIZE
 188 #define SGE_PAGE_SHIFT                  PAGE_SHIFT
 189 #define SGE_PAGE_ALIGN(addr)            PAGE_ALIGN((typeof(PAGE_SIZE))(addr))
 190
 191 /* SGE ring related macros */
 192 #define NUM_RX_SGE_PAGES                2
 193 #define RX_SGE_CNT              (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge))
 194 #define MAX_RX_SGE_CNT                  (RX_SGE_CNT - 2)
 195 /* RX_SGE_CNT is promised to be a power of 2 */
 196 #define RX_SGE_MASK                     (RX_SGE_CNT - 1)
 197 #define NUM_RX_SGE                      (RX_SGE_CNT * NUM_RX_SGE_PAGES)
 198 #define MAX_RX_SGE                      (NUM_RX_SGE - 1)
 199 #define NEXT_SGE_IDX(x)         ((((x) & RX_SGE_MASK) == \
 200                                   (MAX_RX_SGE_CNT - 1)) ? (x) + 3 : (x) + 1)
 201 #define RX_SGE(x)                       ((x) & MAX_RX_SGE)
 202
 203 /* SGE producer mask related macros */
 204 /* Number of bits in one sge_mask array element */
 205 #define RX_SGE_MASK_ELEM_SZ             64
 206 #define RX_SGE_MASK_ELEM_SHIFT          6
 207 #define RX_SGE_MASK_ELEM_MASK           ((u64)RX_SGE_MASK_ELEM_SZ - 1)
 208
 209 /* Creates a bitmask of all ones in less significant bits.
 210    idx - index of the most significant bit in the created mask */
 211 #define RX_SGE_ONES_MASK(idx) \
 212                 (((u64)0x1 << (((idx) & RX_SGE_MASK_ELEM_MASK) + 1)) - 1)
 213 #define RX_SGE_MASK_ELEM_ONE_MASK       ((u64)(~0))
 214
 215 /* Number of u64 elements in SGE mask array */
 216 #define RX_SGE_MASK_LEN                 ((NUM_RX_SGE_PAGES * RX_SGE_CNT) / \
 217                                          RX_SGE_MASK_ELEM_SZ)
 218 #define RX_SGE_MASK_LEN_MASK            (RX_SGE_MASK_LEN - 1)
 219 #define NEXT_SGE_MASK_ELEM(el)          (((el) + 1) & RX_SGE_MASK_LEN_MASK)
 220
 221
 222 struct bnx2x_eth_q_stats {
 223         u32 total_bytes_received_hi;
 224         u32 total_bytes_received_lo;
 225         u32 total_bytes_transmitted_hi;
 226         u32 total_bytes_transmitted_lo;
 227         u32 total_unicast_packets_received_hi;
 228         u32 total_unicast_packets_received_lo;
 229         u32 total_multicast_packets_received_hi;
 230         u32 total_multicast_packets_received_lo;
 231         u32 total_broadcast_packets_received_hi;
 232         u32 total_broadcast_packets_received_lo;
 233         u32 total_unicast_packets_transmitted_hi;
 234         u32 total_unicast_packets_transmitted_lo;
 235         u32 total_multicast_packets_transmitted_hi;
 236         u32 total_multicast_packets_transmitted_lo;
 237         u32 total_broadcast_packets_transmitted_hi;
 238         u32 total_broadcast_packets_transmitted_lo;
 239         u32 valid_bytes_received_hi;
 240         u32 valid_bytes_received_lo;
 241
 242         u32 error_bytes_received_hi;
 243         u32 error_bytes_received_lo;
 244         u32 etherstatsoverrsizepkts_hi;
 245         u32 etherstatsoverrsizepkts_lo;
 246         u32 no_buff_discard_hi;
 247         u32 no_buff_discard_lo;
 248
 249         u32 driver_xoff;
 250         u32 rx_err_discard_pkt;
 251         u32 rx_skb_alloc_failed;
 252         u32 hw_csum_err;
 253 };
 254
 255 #define BNX2X_NUM_Q_STATS               11
 256 #define Q_STATS_OFFSET32(stat_name) \
 257                         (offsetof(struct bnx2x_eth_q_stats, stat_name) / 4)
 258
 259 struct bnx2x_fastpath {
 260
 261         struct napi_struct      napi;
 262         struct host_status_block *status_blk;
 263         dma_addr_t              status_blk_mapping;
 264
 265         struct sw_tx_bd         *tx_buf_ring;
 266
 267         union eth_tx_bd_types   *tx_desc_ring;
 268         dma_addr_t              tx_desc_mapping;
 269
 270         struct sw_rx_bd         *rx_buf_ring;   /* BDs mappings ring */
 271         struct sw_rx_page       *rx_page_ring;  /* SGE pages mappings ring */
 272
 273         struct eth_rx_bd        *rx_desc_ring;
 274         dma_addr_t              rx_desc_mapping;
 275
 276         union eth_rx_cqe        *rx_comp_ring;
 277         dma_addr_t              rx_comp_mapping;
 278
 279         /* SGE ring */
 280         struct eth_rx_sge       *rx_sge_ring;
 281         dma_addr_t              rx_sge_mapping;
 282
 283         u64                     sge_mask[RX_SGE_MASK_LEN];
 284
 285         int                     state;
 286 #define BNX2X_FP_STATE_CLOSED           0
 287 #define BNX2X_FP_STATE_IRQ              0x80000
 288 #define BNX2X_FP_STATE_OPENING          0x90000
 289 #define BNX2X_FP_STATE_OPEN             0xa0000
 290 #define BNX2X_FP_STATE_HALTING          0xb0000
 291 #define BNX2X_FP_STATE_HALTED           0xc0000
 292
 293         u8                      index;  /* number in fp array */
 294         u8                      cl_id;  /* eth client id */
 295         u8                      sb_id;  /* status block number in HW */
 296
 297         union db_prod           tx_db;
 298
 299         u16                     tx_pkt_prod;
 300         u16                     tx_pkt_cons;
 301         u16                     tx_bd_prod;
 302         u16                     tx_bd_cons;
 303         __le16                  *tx_cons_sb;
 304
 305         __le16                  fp_c_idx;
 306         __le16                  fp_u_idx;
 307
 308         u16                     rx_bd_prod;
 309         u16                     rx_bd_cons;
 310         u16                     rx_comp_prod;
 311         u16                     rx_comp_cons;
 312         u16                     rx_sge_prod;
 313         /* The last maximal completed SGE */
 314         u16                     last_max_sge;
 315         __le16                  *rx_cons_sb;
 316         __le16                  *rx_bd_cons_sb;
 317
 318
 319         unsigned long           tx_pkt,
 320                                 rx_pkt,
 321                                 rx_calls;
 322
 323         /* TPA related */
 324         struct sw_rx_bd         tpa_pool[ETH_MAX_AGGREGATION_QUEUES_E1H];
 325         u8                      tpa_state[ETH_MAX_AGGREGATION_QUEUES_E1H];
 326 #define BNX2X_TPA_START                 1
 327 #define BNX2X_TPA_STOP                  2
 328         u8                      disable_tpa;
 329 #ifdef BNX2X_STOP_ON_ERROR
 330         u64                     tpa_queue_used;
 331 #endif
 332
 333         struct tstorm_per_client_stats old_tclient;
 334         struct ustorm_per_client_stats old_uclient;
 335         struct xstorm_per_client_stats old_xclient;
 336         struct bnx2x_eth_q_stats eth_q_stats;
 337
 338         /* The size is calculated using the following:
 339              sizeof name field from netdev structure +
 340              4 ('-Xx-' string) +
 341              4 (for the digits and to make it DWORD aligned) */
 342 #define FP_NAME_SIZE            (sizeof(((struct net_device *)0)->name) + 8)
 343         char                    name[FP_NAME_SIZE];
 344         struct bnx2x            *bp; /* parent */
 345 };
 346
 347 #define bnx2x_fp(bp, nr, var)           (bp->fp[nr].var)
 348
 349
 350 /* MC hsi */
 351 #define MAX_FETCH_BD                    13      /* HW max BDs per packet */
 352 #define RX_COPY_THRESH                  92
 353
 354 #define NUM_TX_RINGS                    16
 355 #define TX_DESC_CNT             (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types))
 356 #define MAX_TX_DESC_CNT                 (TX_DESC_CNT - 1)
 357 #define NUM_TX_BD                       (TX_DESC_CNT * NUM_TX_RINGS)
 358 #define MAX_TX_BD                       (NUM_TX_BD - 1)
 359 #define MAX_TX_AVAIL                    (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2)
 360 #define NEXT_TX_IDX(x)          ((((x) & MAX_TX_DESC_CNT) == \
 361                                   (MAX_TX_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
 362 #define TX_BD(x)                        ((x) & MAX_TX_BD)
 363 #define TX_BD_POFF(x)                   ((x) & MAX_TX_DESC_CNT)
 364
 365 /* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */
 366 #define NUM_RX_RINGS                    8
 367 #define RX_DESC_CNT             (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
 368 #define MAX_RX_DESC_CNT                 (RX_DESC_CNT - 2)
 369 #define RX_DESC_MASK                    (RX_DESC_CNT - 1)
 370 #define NUM_RX_BD                       (RX_DESC_CNT * NUM_RX_RINGS)
 371 #define MAX_RX_BD                       (NUM_RX_BD - 1)
 372 #define MAX_RX_AVAIL                    (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2)
 373 #define NEXT_RX_IDX(x)          ((((x) & RX_DESC_MASK) == \
 374                                   (MAX_RX_DESC_CNT - 1)) ? (x) + 3 : (x) + 1)
 375 #define RX_BD(x)                        ((x) & MAX_RX_BD)
 376
 377 /* As long as CQE is 4 times bigger than BD entry we have to allocate
 378    4 times more pages for CQ ring in order to keep it balanced with
 379    BD ring */
 380 #define NUM_RCQ_RINGS                   (NUM_RX_RINGS * 4)
 381 #define RCQ_DESC_CNT            (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))
 382 #define MAX_RCQ_DESC_CNT                (RCQ_DESC_CNT - 1)
 383 #define NUM_RCQ_BD                      (RCQ_DESC_CNT * NUM_RCQ_RINGS)
 384 #define MAX_RCQ_BD                      (NUM_RCQ_BD - 1)
 385 #define MAX_RCQ_AVAIL                   (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2)
 386 #define NEXT_RCQ_IDX(x)         ((((x) & MAX_RCQ_DESC_CNT) == \
 387                                   (MAX_RCQ_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
 388 #define RCQ_BD(x)                       ((x) & MAX_RCQ_BD)
 389
 390
 391 /* This is needed for determining of last_max */
 392 #define SUB_S16(a, b)                   (s16)((s16)(a) - (s16)(b))
 393
 394 #define __SGE_MASK_SET_BIT(el, bit) \
 395         do { \
 396                 el = ((el) | ((u64)0x1 << (bit))); \
 397         } while (0)
 398
 399 #define __SGE_MASK_CLEAR_BIT(el, bit) \
 400         do { \
 401                 el = ((el) & (~((u64)0x1 << (bit)))); \
 402         } while (0)
 403
 404 #define SGE_MASK_SET_BIT(fp, idx) \
 405         __SGE_MASK_SET_BIT(fp->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \
 406                            ((idx) & RX_SGE_MASK_ELEM_MASK))
 407
 408 #define SGE_MASK_CLEAR_BIT(fp, idx) \
 409         __SGE_MASK_CLEAR_BIT(fp->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \
 410                              ((idx) & RX_SGE_MASK_ELEM_MASK))
 411
 412
 413 /* used on a CID received from the HW */
 414 #define SW_CID(x)                       (le32_to_cpu(x) & \
 415                                          (COMMON_RAMROD_ETH_RX_CQE_CID >> 7))
 416 #define CQE_CMD(x)                      (le32_to_cpu(x) >> \
 417                                         COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
 418
 419 #define BD_UNMAP_ADDR(bd)               HILO_U64(le32_to_cpu((bd)->addr_hi), \
 420                                                  le32_to_cpu((bd)->addr_lo))
 421 #define BD_UNMAP_LEN(bd)                (le16_to_cpu((bd)->nbytes))
 422
 423
 424 #define DPM_TRIGER_TYPE                 0x40
 425 #define DOORBELL(bp, cid, val) \
 426         do { \
 427                 writel((u32)(val), bp->doorbells + (BCM_PAGE_SIZE * (cid)) + \
 428                        DPM_TRIGER_TYPE); \
 429         } while (0)
 430
 431
 432 /* TX CSUM helpers */
 433 #define SKB_CS_OFF(skb)         (offsetof(struct tcphdr, check) - \
 434                                  skb->csum_offset)
 435 #define SKB_CS(skb)             (*(u16 *)(skb_transport_header(skb) + \
 436                                           skb->csum_offset))
 437
 438 #define pbd_tcp_flags(skb)      (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff)
 439
 440 #define XMIT_PLAIN                      0
 441 #define XMIT_CSUM_V4                    0x1
 442 #define XMIT_CSUM_V6                    0x2
 443 #define XMIT_CSUM_TCP                   0x4
 444 #define XMIT_GSO_V4                     0x8
 445 #define XMIT_GSO_V6                     0x10
 446
 447 #define XMIT_CSUM                       (XMIT_CSUM_V4 | XMIT_CSUM_V6)
 448 #define XMIT_GSO                        (XMIT_GSO_V4 | XMIT_GSO_V6)
 449
 450
 451 /* stuff added to make the code fit 80Col */
 452
 453 #define CQE_TYPE(cqe_fp_flags)  ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
 454
 455 #define TPA_TYPE_START                  ETH_FAST_PATH_RX_CQE_START_FLG
 456 #define TPA_TYPE_END                    ETH_FAST_PATH_RX_CQE_END_FLG
 457 #define TPA_TYPE(cqe_fp_flags)          ((cqe_fp_flags) & \
 458                                          (TPA_TYPE_START | TPA_TYPE_END))
 459
 460 #define ETH_RX_ERROR_FALGS              ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG
 461
 462 #define BNX2X_IP_CSUM_ERR(cqe) \
 463                         (!((cqe)->fast_path_cqe.status_flags & \
 464                            ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG) && \
 465                          ((cqe)->fast_path_cqe.type_error_flags & \
 466                           ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG))
 467
 468 #define BNX2X_L4_CSUM_ERR(cqe) \
 469                         (!((cqe)->fast_path_cqe.status_flags & \
 470                            ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG) && \
 471                          ((cqe)->fast_path_cqe.type_error_flags & \
 472                           ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG))
 473
 474 #define BNX2X_RX_CSUM_OK(cqe) \
 475                         (!(BNX2X_L4_CSUM_ERR(cqe) || BNX2X_IP_CSUM_ERR(cqe)))
 476
 477 #define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \
 478                                 (((le16_to_cpu(flags) & \
 479                                    PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \
 480                                   PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \
 481                                  == PRS_FLAG_OVERETH_IPV4)
 482 #define BNX2X_RX_SUM_FIX(cqe) \
 483         BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags)
 484
 485
 486 #define FP_USB_FUNC_OFF                 (2 + 2*HC_USTORM_SB_NUM_INDICES)
 487 #define FP_CSB_FUNC_OFF                 (2 + 2*HC_CSTORM_SB_NUM_INDICES)
 488
 489 #define U_SB_ETH_RX_CQ_INDEX            HC_INDEX_U_ETH_RX_CQ_CONS
 490 #define U_SB_ETH_RX_BD_INDEX            HC_INDEX_U_ETH_RX_BD_CONS
 491 #define C_SB_ETH_TX_CQ_INDEX            HC_INDEX_C_ETH_TX_CQ_CONS
 492
 493 #define BNX2X_RX_SB_INDEX \
 494         (&fp->status_blk->u_status_block.index_values[U_SB_ETH_RX_CQ_INDEX])
 495
 496 #define BNX2X_RX_SB_BD_INDEX \
 497         (&fp->status_blk->u_status_block.index_values[U_SB_ETH_RX_BD_INDEX])
 498
 499 #define BNX2X_RX_SB_INDEX_NUM \
 500                 (((U_SB_ETH_RX_CQ_INDEX << \
 501                    USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER_SHIFT) & \
 502                   USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER) | \
 503                  ((U_SB_ETH_RX_BD_INDEX << \
 504                    USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER_SHIFT) & \
 505                   USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER))
 506
 507 #define BNX2X_TX_SB_INDEX \
 508         (&fp->status_blk->c_status_block.index_values[C_SB_ETH_TX_CQ_INDEX])
 509
 510
 511 /* end of fast path */
 512
 513 /* common */
 514
 515 struct bnx2x_common {
 516
 517         u32                     chip_id;
 518 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
 519 #define CHIP_ID(bp)                     (bp->common.chip_id & 0xfffffff0)
 520
 521 #define CHIP_NUM(bp)                    (bp->common.chip_id >> 16)
 522 #define CHIP_NUM_57710                  0x164e
 523 #define CHIP_NUM_57711                  0x164f
 524 #define CHIP_NUM_57711E                 0x1650
 525 #define CHIP_IS_E1(bp)                  (CHIP_NUM(bp) == CHIP_NUM_57710)
 526 #define CHIP_IS_57711(bp)               (CHIP_NUM(bp) == CHIP_NUM_57711)
 527 #define CHIP_IS_57711E(bp)              (CHIP_NUM(bp) == CHIP_NUM_57711E)
 528 #define CHIP_IS_E1H(bp)                 (CHIP_IS_57711(bp) || \
 529                                          CHIP_IS_57711E(bp))
 530 #define IS_E1H_OFFSET                   CHIP_IS_E1H(bp)
 531
 532 #define CHIP_REV(bp)                    (bp->common.chip_id & 0x0000f000)
 533 #define CHIP_REV_Ax                     0x00000000
 534 /* assume maximum 5 revisions */
 535 #define CHIP_REV_IS_SLOW(bp)            (CHIP_REV(bp) > 0x00005000)
 536 /* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */
 537 #define CHIP_REV_IS_EMUL(bp)            ((CHIP_REV_IS_SLOW(bp)) && \
 538                                          !(CHIP_REV(bp) & 0x00001000))
 539 /* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */
 540 #define CHIP_REV_IS_FPGA(bp)            ((CHIP_REV_IS_SLOW(bp)) && \
 541                                          (CHIP_REV(bp) & 0x00001000))
 542
 543 #define CHIP_TIME(bp)                   ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \
 544                                         ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1))
 545
 546 #define CHIP_METAL(bp)                  (bp->common.chip_id & 0x00000ff0)
 547 #define CHIP_BOND_ID(bp)                (bp->common.chip_id & 0x0000000f)
 548
 549         int                     flash_size;
 550 #define NVRAM_1MB_SIZE                  0x20000 /* 1M bit in bytes */
 551 #define NVRAM_TIMEOUT_COUNT             30000
 552 #define NVRAM_PAGE_SIZE                 256
 553
 554         u32                     shmem_base;
 555         u32                     shmem2_base;
 556
 557         u32                     hw_config;
 558
 559         u32                     bc_ver;
 560 };
 561
 562
 563 /* end of common */
 564
 565 /* port */
 566
 567 struct nig_stats {
 568         u32 brb_discard;
 569         u32 brb_packet;
 570         u32 brb_truncate;
 571         u32 flow_ctrl_discard;
 572         u32 flow_ctrl_octets;
 573         u32 flow_ctrl_packet;
 574         u32 mng_discard;
 575         u32 mng_octet_inp;
 576         u32 mng_octet_out;
 577         u32 mng_packet_inp;
 578         u32 mng_packet_out;
 579         u32 pbf_octets;
 580         u32 pbf_packet;
 581         u32 safc_inp;
 582         u32 egress_mac_pkt0_lo;
 583         u32 egress_mac_pkt0_hi;
 584         u32 egress_mac_pkt1_lo;
 585         u32 egress_mac_pkt1_hi;
 586 };
 587
 588 struct bnx2x_port {
 589         u32                     pmf;
 590
 591         u32                     link_config;
 592
 593         u32                     supported;
 594 /* link settings - missing defines */
 595 #define SUPPORTED_2500baseX_Full        (1 << 15)
 596
 597         u32                     advertising;
 598 /* link settings - missing defines */
 599 #define ADVERTISED_2500baseX_Full       (1 << 15)
 600
 601         u32                     phy_addr;
 602
 603         /* used to synchronize phy accesses */
 604         struct mutex            phy_mutex;
 605         int                     need_hw_lock;
 606
 607         u32                     port_stx;
 608
 609         struct nig_stats        old_nig_stats;
 610 };
 611
 612 /* end of port */
 613
 614
 615 enum bnx2x_stats_event {
 616         STATS_EVENT_PMF = 0,
 617         STATS_EVENT_LINK_UP,
 618         STATS_EVENT_UPDATE,
 619         STATS_EVENT_STOP,
 620         STATS_EVENT_MAX
 621 };
 622
 623 enum bnx2x_stats_state {
 624         STATS_STATE_DISABLED = 0,
 625         STATS_STATE_ENABLED,
 626         STATS_STATE_MAX
 627 };
 628
 629 struct bnx2x_eth_stats {
 630         u32 total_bytes_received_hi;
 631         u32 total_bytes_received_lo;
 632         u32 total_bytes_transmitted_hi;
 633         u32 total_bytes_transmitted_lo;
 634         u32 total_unicast_packets_received_hi;
 635         u32 total_unicast_packets_received_lo;
 636         u32 total_multicast_packets_received_hi;
 637         u32 total_multicast_packets_received_lo;
 638         u32 total_broadcast_packets_received_hi;
 639         u32 total_broadcast_packets_received_lo;
 640         u32 total_unicast_packets_transmitted_hi;
 641         u32 total_unicast_packets_transmitted_lo;
 642         u32 total_multicast_packets_transmitted_hi;
 643         u32 total_multicast_packets_transmitted_lo;
 644         u32 total_broadcast_packets_transmitted_hi;
 645         u32 total_broadcast_packets_transmitted_lo;
 646         u32 valid_bytes_received_hi;
 647         u32 valid_bytes_received_lo;
 648
 649         u32 error_bytes_received_hi;
 650         u32 error_bytes_received_lo;
 651         u32 etherstatsoverrsizepkts_hi;
 652         u32 etherstatsoverrsizepkts_lo;
 653         u32 no_buff_discard_hi;
 654         u32 no_buff_discard_lo;
 655
 656         u32 rx_stat_ifhcinbadoctets_hi;
 657         u32 rx_stat_ifhcinbadoctets_lo;
 658         u32 tx_stat_ifhcoutbadoctets_hi;
 659         u32 tx_stat_ifhcoutbadoctets_lo;
 660         u32 rx_stat_dot3statsfcserrors_hi;
 661         u32 rx_stat_dot3statsfcserrors_lo;
 662         u32 rx_stat_dot3statsalignmenterrors_hi;
 663         u32 rx_stat_dot3statsalignmenterrors_lo;
 664         u32 rx_stat_dot3statscarriersenseerrors_hi;
 665         u32 rx_stat_dot3statscarriersenseerrors_lo;
 666         u32 rx_stat_falsecarriererrors_hi;
 667         u32 rx_stat_falsecarriererrors_lo;
 668         u32 rx_stat_etherstatsundersizepkts_hi;
 669         u32 rx_stat_etherstatsundersizepkts_lo;
 670         u32 rx_stat_dot3statsframestoolong_hi;
 671         u32 rx_stat_dot3statsframestoolong_lo;
 672         u32 rx_stat_etherstatsfragments_hi;
 673         u32 rx_stat_etherstatsfragments_lo;
 674         u32 rx_stat_etherstatsjabbers_hi;
 675         u32 rx_stat_etherstatsjabbers_lo;
 676         u32 rx_stat_maccontrolframesreceived_hi;
 677         u32 rx_stat_maccontrolframesreceived_lo;
 678         u32 rx_stat_bmac_xpf_hi;
 679         u32 rx_stat_bmac_xpf_lo;
 680         u32 rx_stat_bmac_xcf_hi;
 681         u32 rx_stat_bmac_xcf_lo;
 682         u32 rx_stat_xoffstateentered_hi;
 683         u32 rx_stat_xoffstateentered_lo;
 684         u32 rx_stat_xonpauseframesreceived_hi;
 685         u32 rx_stat_xonpauseframesreceived_lo;
 686         u32 rx_stat_xoffpauseframesreceived_hi;
 687         u32 rx_stat_xoffpauseframesreceived_lo;
 688         u32 tx_stat_outxonsent_hi;
 689         u32 tx_stat_outxonsent_lo;
 690         u32 tx_stat_outxoffsent_hi;
 691         u32 tx_stat_outxoffsent_lo;
 692         u32 tx_stat_flowcontroldone_hi;
 693         u32 tx_stat_flowcontroldone_lo;
 694         u32 tx_stat_etherstatscollisions_hi;
 695         u32 tx_stat_etherstatscollisions_lo;
 696         u32 tx_stat_dot3statssinglecollisionframes_hi;
 697         u32 tx_stat_dot3statssinglecollisionframes_lo;
 698         u32 tx_stat_dot3statsmultiplecollisionframes_hi;
 699         u32 tx_stat_dot3statsmultiplecollisionframes_lo;
 700         u32 tx_stat_dot3statsdeferredtransmissions_hi;
 701         u32 tx_stat_dot3statsdeferredtransmissions_lo;
 702         u32 tx_stat_dot3statsexcessivecollisions_hi;
 703         u32 tx_stat_dot3statsexcessivecollisions_lo;
 704         u32 tx_stat_dot3statslatecollisions_hi;
 705         u32 tx_stat_dot3statslatecollisions_lo;
 706         u32 tx_stat_etherstatspkts64octets_hi;
 707         u32 tx_stat_etherstatspkts64octets_lo;
 708         u32 tx_stat_etherstatspkts65octetsto127octets_hi;
 709         u32 tx_stat_etherstatspkts65octetsto127octets_lo;
 710         u32 tx_stat_etherstatspkts128octetsto255octets_hi;
 711         u32 tx_stat_etherstatspkts128octetsto255octets_lo;
 712         u32 tx_stat_etherstatspkts256octetsto511octets_hi;
 713         u32 tx_stat_etherstatspkts256octetsto511octets_lo;
 714         u32 tx_stat_etherstatspkts512octetsto1023octets_hi;
 715         u32 tx_stat_etherstatspkts512octetsto1023octets_lo;
 716         u32 tx_stat_etherstatspkts1024octetsto1522octets_hi;
 717         u32 tx_stat_etherstatspkts1024octetsto1522octets_lo;
 718         u32 tx_stat_etherstatspktsover1522octets_hi;
 719         u32 tx_stat_etherstatspktsover1522octets_lo;
 720         u32 tx_stat_bmac_2047_hi;
 721         u32 tx_stat_bmac_2047_lo;
 722         u32 tx_stat_bmac_4095_hi;
 723         u32 tx_stat_bmac_4095_lo;
 724         u32 tx_stat_bmac_9216_hi;
 725         u32 tx_stat_bmac_9216_lo;
 726         u32 tx_stat_bmac_16383_hi;
 727         u32 tx_stat_bmac_16383_lo;
 728         u32 tx_stat_dot3statsinternalmactransmiterrors_hi;
 729         u32 tx_stat_dot3statsinternalmactransmiterrors_lo;
 730         u32 tx_stat_bmac_ufl_hi;
 731         u32 tx_stat_bmac_ufl_lo;
 732
 733         u32 pause_frames_received_hi;
 734         u32 pause_frames_received_lo;
 735         u32 pause_frames_sent_hi;
 736         u32 pause_frames_sent_lo;
 737
 738         u32 etherstatspkts1024octetsto1522octets_hi;
 739         u32 etherstatspkts1024octetsto1522octets_lo;
 740         u32 etherstatspktsover1522octets_hi;
 741         u32 etherstatspktsover1522octets_lo;
 742
 743         u32 brb_drop_hi;
 744         u32 brb_drop_lo;
 745         u32 brb_truncate_hi;
 746         u32 brb_truncate_lo;
 747
 748         u32 mac_filter_discard;
 749         u32 xxoverflow_discard;
 750         u32 brb_truncate_discard;
 751         u32 mac_discard;
 752
 753         u32 driver_xoff;
 754         u32 rx_err_discard_pkt;
 755         u32 rx_skb_alloc_failed;
 756         u32 hw_csum_err;
 757
 758         u32 nig_timer_max;
 759 };
 760
 761 #define BNX2X_NUM_STATS                 41
 762 #define STATS_OFFSET32(stat_name) \
 763                         (offsetof(struct bnx2x_eth_stats, stat_name) / 4)
 764
 765
 766 #ifdef BCM_CNIC
 767 #define MAX_CONTEXT                     15
 768 #else
 769 #define MAX_CONTEXT                     16
 770 #endif
 771
 772 union cdu_context {
 773         struct eth_context eth;
 774         char pad[1024];
 775 };
 776
 777 #define MAX_DMAE_C                      8
 778
 779 /* DMA memory not used in fastpath */
 780 struct bnx2x_slowpath {
 781         union cdu_context               context[MAX_CONTEXT];
 782         struct eth_stats_query          fw_stats;
 783         struct mac_configuration_cmd    mac_config;
 784         struct mac_configuration_cmd    mcast_config;
 785
 786         /* used by dmae command executer */
 787         struct dmae_command             dmae[MAX_DMAE_C];
 788
 789         u32                             stats_comp;
 790         union mac_stats                 mac_stats;
 791         struct nig_stats                nig_stats;
 792         struct host_port_stats          port_stats;
 793         struct host_func_stats          func_stats;
 794         struct host_func_stats          func_stats_base;
 795
 796         u32                             wb_comp;
 797         u32                             wb_data[4];
 798 };
 799
 800 #define bnx2x_sp(bp, var)               (&bp->slowpath->var)
 801 #define bnx2x_sp_mapping(bp, var) \
 802                 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var))
 803
 804
 805 /* attn group wiring */
 806 #define MAX_DYNAMIC_ATTN_GRPS           8
 807
 808 struct attn_route {
 809         u32     sig[4];
 810 };
 811
 812 struct bnx2x {
 813         /* Fields used in the tx and intr/napi performance paths
 814          * are grouped together in the beginning of the structure
 815          */
 816         struct bnx2x_fastpath   fp[MAX_CONTEXT];
 817         void __iomem            *regview;
 818         void __iomem            *doorbells;
 819 #ifdef BCM_CNIC
 820 #define BNX2X_DB_SIZE           (18*BCM_PAGE_SIZE)
 821 #else
 822 #define BNX2X_DB_SIZE           (16*BCM_PAGE_SIZE)
 823 #endif
 824
 825         struct net_device       *dev;
 826         struct pci_dev          *pdev;
 827
 828         atomic_t                intr_sem;
 829 #ifdef BCM_CNIC
 830         struct msix_entry       msix_table[MAX_CONTEXT+2];
 831 #else
 832         struct msix_entry       msix_table[MAX_CONTEXT+1];
 833 #endif
 834 #define INT_MODE_INTx                   1
 835 #define INT_MODE_MSI                    2
 836 #define INT_MODE_MSIX                   3
 837
 838         int                     tx_ring_size;
 839
 840 #ifdef BCM_VLAN
 841         struct vlan_group       *vlgrp;
 842 #endif
 843
 844         u32                     rx_csum;
 845         u32                     rx_buf_size;
 846 #define ETH_OVREHEAD                    (ETH_HLEN + 8)  /* 8 for CRC + VLAN */
 847 #define ETH_MIN_PACKET_SIZE             60
 848 #define ETH_MAX_PACKET_SIZE             1500
 849 #define ETH_MAX_JUMBO_PACKET_SIZE       9600
 850
 851         /* Max supported alignment is 256 (8 shift) */
 852 #define BNX2X_RX_ALIGN_SHIFT            ((L1_CACHE_SHIFT < 8) ? \
 853                                          L1_CACHE_SHIFT : 8)
 854 #define BNX2X_RX_ALIGN                  (1 << BNX2X_RX_ALIGN_SHIFT)
 855
 856         struct host_def_status_block *def_status_blk;
 857 #define DEF_SB_ID                       16
 858         __le16                  def_c_idx;
 859         __le16                  def_u_idx;
 860         __le16                  def_x_idx;
 861         __le16                  def_t_idx;
 862         __le16                  def_att_idx;
 863         u32                     attn_state;
 864         struct attn_route       attn_group[MAX_DYNAMIC_ATTN_GRPS];
 865
 866         /* slow path ring */
 867         struct eth_spe          *spq;
 868         dma_addr_t              spq_mapping;
 869         u16                     spq_prod_idx;
 870         struct eth_spe          *spq_prod_bd;
 871         struct eth_spe          *spq_last_bd;
 872         __le16                  *dsb_sp_prod;
 873         u16                     spq_left; /* serialize spq */
 874         /* used to synchronize spq accesses */
 875         spinlock_t              spq_lock;
 876
 877         /* Flags for marking that there is a STAT_QUERY or
 878            SET_MAC ramrod pending */
 879         int                     stats_pending;
 880         int                     set_mac_pending;
 881
 882         /* End of fields used in the performance code paths */
 883
 884         int                     panic;
 885         int                     msglevel;
 886
 887         u32                     flags;
 888 #define PCIX_FLAG                       1
 889 #define PCI_32BIT_FLAG                  2
 890 #define ONE_PORT_FLAG                   4
 891 #define NO_WOL_FLAG                     8
 892 #define USING_DAC_FLAG                  0x10
 893 #define USING_MSIX_FLAG                 0x20
 894 #define USING_MSI_FLAG                  0x40
 895 #define TPA_ENABLE_FLAG                 0x80
 896 #define NO_MCP_FLAG                     0x100
 897 #define BP_NOMCP(bp)                    (bp->flags & NO_MCP_FLAG)
 898 #define HW_VLAN_TX_FLAG                 0x400
 899 #define HW_VLAN_RX_FLAG                 0x800
 900 #define MF_FUNC_DIS                     0x1000
 901
 902         int                     func;
 903 #define BP_PORT(bp)                     (bp->func % PORT_MAX)
 904 #define BP_FUNC(bp)                     (bp->func)
 905 #define BP_E1HVN(bp)                    (bp->func >> 1)
 906 #define BP_L_ID(bp)                     (BP_E1HVN(bp) << 2)
 907
 908 #ifdef BCM_CNIC
 909 #define BCM_CNIC_CID_START              16
 910 #define BCM_ISCSI_ETH_CL_ID             17
 911 #endif
 912
 913         int                     pm_cap;
 914         int                     pcie_cap;
 915         int                     mrrs;
 916
 917         struct delayed_work     sp_task;
 918         struct work_struct      reset_task;
 919
 920         struct timer_list       timer;
 921         int                     current_interval;
 922
 923         u16                     fw_seq;
 924         u16                     fw_drv_pulse_wr_seq;
 925         u32                     func_stx;
 926
 927         struct link_params      link_params;
 928         struct link_vars        link_vars;
 929         struct mdio_if_info     mdio;
 930
 931         struct bnx2x_common     common;
 932         struct bnx2x_port       port;
 933
 934         struct cmng_struct_per_port cmng;
 935         u32                     vn_weight_sum;
 936
 937         u32                     mf_config;
 938         u16                     e1hov;
 939         u8                      e1hmf;
 940 #define IS_E1HMF(bp)                    (bp->e1hmf != 0)
 941
 942         u8                      wol;
 943
 944         int                     rx_ring_size;
 945
 946         u16                     tx_quick_cons_trip_int;
 947         u16                     tx_quick_cons_trip;
 948         u16                     tx_ticks_int;
 949         u16                     tx_ticks;
 950
 951         u16                     rx_quick_cons_trip_int;
 952         u16                     rx_quick_cons_trip;
 953         u16                     rx_ticks_int;
 954         u16                     rx_ticks;
 955
 956         u32                     lin_cnt;
 957
 958         int                     state;
 959 #define BNX2X_STATE_CLOSED              0
 960 #define BNX2X_STATE_OPENING_WAIT4_LOAD  0x1000
 961 #define BNX2X_STATE_OPENING_WAIT4_PORT  0x2000
 962 #define BNX2X_STATE_OPEN                0x3000
 963 #define BNX2X_STATE_CLOSING_WAIT4_HALT  0x4000
 964 #define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000
 965 #define BNX2X_STATE_CLOSING_WAIT4_UNLOAD 0x6000
 966 #define BNX2X_STATE_DIAG                0xe000
 967 #define BNX2X_STATE_ERROR               0xf000
 968
 969         int                     multi_mode;
 970         int                     num_queues;
 971
 972         u32                     rx_mode;
 973 #define BNX2X_RX_MODE_NONE              0
 974 #define BNX2X_RX_MODE_NORMAL            1
 975 #define BNX2X_RX_MODE_ALLMULTI          2
 976 #define BNX2X_RX_MODE_PROMISC           3
 977 #define BNX2X_MAX_MULTICAST             64
 978 #define BNX2X_MAX_EMUL_MULTI            16
 979
 980         u32                     rx_mode_cl_mask;
 981
 982         dma_addr_t              def_status_blk_mapping;
 983
 984         struct bnx2x_slowpath   *slowpath;
 985         dma_addr_t              slowpath_mapping;
 986
 987         int                     dropless_fc;
 988
 989 #ifdef BCM_CNIC
 990         u32                     cnic_flags;
 991 #define BNX2X_CNIC_FLAG_MAC_SET         1
 992
 993         void                    *t1;
 994         dma_addr_t              t1_mapping;
 995         void                    *t2;
 996         dma_addr_t              t2_mapping;
 997         void                    *timers;
 998         dma_addr_t              timers_mapping;
 999         void                    *qm;
1000         dma_addr_t              qm_mapping;
1001         struct cnic_ops         *cnic_ops;
1002         void                    *cnic_data;
1003         u32                     cnic_tag;
1004         struct cnic_eth_dev     cnic_eth_dev;
1005         struct host_status_block *cnic_sb;
1006         dma_addr_t              cnic_sb_mapping;
1007 #define CNIC_SB_ID(bp)                  BP_L_ID(bp)
1008         struct eth_spe          *cnic_kwq;
1009         struct eth_spe          *cnic_kwq_prod;
1010         struct eth_spe          *cnic_kwq_cons;
1011         struct eth_spe          *cnic_kwq_last;
1012         u16                     cnic_kwq_pending;
1013         u16                     cnic_spq_pending;
1014         struct mutex            cnic_mutex;
1015         u8                      iscsi_mac[6];
1016 #endif
1017
1018         int                     dmae_ready;
1019         /* used to synchronize dmae accesses */
1020         struct mutex            dmae_mutex;
1021
1022         /* used to protect the FW mail box */
1023         struct mutex            fw_mb_mutex;
1024
1025         /* used to synchronize stats collecting */
1026         int                     stats_state;
1027         /* used by dmae command loader */
1028         struct dmae_command     stats_dmae;
1029         int                     executer_idx;
1030
1031         u16                     stats_counter;
1032         struct bnx2x_eth_stats  eth_stats;
1033
1034         struct z_stream_s       *strm;
1035         void                    *gunzip_buf;
1036         dma_addr_t              gunzip_mapping;
1037         int                     gunzip_outlen;
1038 #define FW_BUF_SIZE                     0x8000
1039 #define GUNZIP_BUF(bp)                  (bp->gunzip_buf)
1040 #define GUNZIP_PHYS(bp)                 (bp->gunzip_mapping)
1041 #define GUNZIP_OUTLEN(bp)               (bp->gunzip_outlen)
1042
1043         struct raw_op           *init_ops;
1044         /* Init blocks offsets inside init_ops */
1045         u16                     *init_ops_offsets;
1046         /* Data blob - has 32 bit granularity */
1047         u32                     *init_data;
1048         /* Zipped PRAM blobs - raw data */
1049         const u8                *tsem_int_table_data;
1050         const u8                *tsem_pram_data;
1051         const u8                *usem_int_table_data;
1052         const u8                *usem_pram_data;
1053         const u8                *xsem_int_table_data;
1054         const u8                *xsem_pram_data;
1055         const u8                *csem_int_table_data;
1056         const u8                *csem_pram_data;
1057 #define INIT_OPS(bp)                    (bp->init_ops)
1058 #define INIT_OPS_OFFSETS(bp)            (bp->init_ops_offsets)
1059 #define INIT_DATA(bp)                   (bp->init_data)
1060 #define INIT_TSEM_INT_TABLE_DATA(bp)    (bp->tsem_int_table_data)
1061 #define INIT_TSEM_PRAM_DATA(bp)         (bp->tsem_pram_data)
1062 #define INIT_USEM_INT_TABLE_DATA(bp)    (bp->usem_int_table_data)
1063 #define INIT_USEM_PRAM_DATA(bp)         (bp->usem_pram_data)
1064 #define INIT_XSEM_INT_TABLE_DATA(bp)    (bp->xsem_int_table_data)
1065 #define INIT_XSEM_PRAM_DATA(bp)         (bp->xsem_pram_data)
1066 #define INIT_CSEM_INT_TABLE_DATA(bp)    (bp->csem_int_table_data)
1067 #define INIT_CSEM_PRAM_DATA(bp)         (bp->csem_pram_data)
1068
1069         const struct firmware   *firmware;
1070 };
1071
1072
1073 #define BNX2X_MAX_QUEUES(bp)    (IS_E1HMF(bp) ? (MAX_CONTEXT/E1HVN_MAX) \
1074                                               : MAX_CONTEXT)
1075 #define BNX2X_NUM_QUEUES(bp)    (bp->num_queues)
1076 #define is_multi(bp)            (BNX2X_NUM_QUEUES(bp) > 1)
1077
1078 #define for_each_queue(bp, var) \
1079                         for (var = 0; var < BNX2X_NUM_QUEUES(bp); var++)
1080 #define for_each_nondefault_queue(bp, var) \
1081                         for (var = 1; var < BNX2X_NUM_QUEUES(bp); var++)
1082
1083
1084 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
1085 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
1086                       u32 len32);
1087 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port);
1088 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
1089 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
1090 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command);
1091 void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val);
1092 void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
1093                                u32 addr, u32 len);
1094
1095 static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
1096                            int wait)
1097 {
1098         u32 val;
1099
1100         do {
1101                 val = REG_RD(bp, reg);
1102                 if (val == expected)
1103                         break;
1104                 ms -= wait;
1105                 msleep(wait);
1106
1107         } while (ms > 0);
1108
1109         return val;
1110 }
1111
1112
1113 /* load/unload mode */
1114 #define LOAD_NORMAL                     0
1115 #define LOAD_OPEN                       1
1116 #define LOAD_DIAG                       2
1117 #define UNLOAD_NORMAL                   0
1118 #define UNLOAD_CLOSE                    1
1119
1120
1121 /* DMAE command defines */
1122 #define DMAE_CMD_SRC_PCI                0
1123 #define DMAE_CMD_SRC_GRC                DMAE_COMMAND_SRC
1124
1125 #define DMAE_CMD_DST_PCI                (1 << DMAE_COMMAND_DST_SHIFT)
1126 #define DMAE_CMD_DST_GRC                (2 << DMAE_COMMAND_DST_SHIFT)
1127
1128 #define DMAE_CMD_C_DST_PCI              0
1129 #define DMAE_CMD_C_DST_GRC              (1 << DMAE_COMMAND_C_DST_SHIFT)
1130
1131 #define DMAE_CMD_C_ENABLE               DMAE_COMMAND_C_TYPE_ENABLE
1132
1133 #define DMAE_CMD_ENDIANITY_NO_SWAP      (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
1134 #define DMAE_CMD_ENDIANITY_B_SWAP       (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
1135 #define DMAE_CMD_ENDIANITY_DW_SWAP      (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
1136 #define DMAE_CMD_ENDIANITY_B_DW_SWAP    (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
1137
1138 #define DMAE_CMD_PORT_0                 0
1139 #define DMAE_CMD_PORT_1                 DMAE_COMMAND_PORT
1140
1141 #define DMAE_CMD_SRC_RESET              DMAE_COMMAND_SRC_RESET
1142 #define DMAE_CMD_DST_RESET              DMAE_COMMAND_DST_RESET
1143 #define DMAE_CMD_E1HVN_SHIFT            DMAE_COMMAND_E1HVN_SHIFT
1144
1145 #define DMAE_LEN32_RD_MAX               0x80
1146 #define DMAE_LEN32_WR_MAX               0x400
1147
1148 #define DMAE_COMP_VAL                   0xe0d0d0ae
1149
1150 #define MAX_DMAE_C_PER_PORT             8
1151 #define INIT_DMAE_C(bp)                 (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
1152                                          BP_E1HVN(bp))
1153 #define PMF_DMAE_C(bp)                  (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
1154                                          E1HVN_MAX)
1155
1156
1157 /* PCIE link and speed */
1158 #define PCICFG_LINK_WIDTH               0x1f00000
1159 #define PCICFG_LINK_WIDTH_SHIFT         20
1160 #define PCICFG_LINK_SPEED               0xf0000
1161 #define PCICFG_LINK_SPEED_SHIFT         16
1162
1163
1164 #define BNX2X_NUM_TESTS                 7
1165
1166 #define BNX2X_PHY_LOOPBACK              0
1167 #define BNX2X_MAC_LOOPBACK              1
1168 #define BNX2X_PHY_LOOPBACK_FAILED       1
1169 #define BNX2X_MAC_LOOPBACK_FAILED       2
1170 #define BNX2X_LOOPBACK_FAILED           (BNX2X_MAC_LOOPBACK_FAILED | \
1171                                          BNX2X_PHY_LOOPBACK_FAILED)
1172
1173
1174 #define STROM_ASSERT_ARRAY_SIZE         50
1175
1176
1177 /* must be used on a CID before placing it on a HW ring */
1178 #define HW_CID(bp, x)                   ((BP_PORT(bp) << 23) | \
1179                                          (BP_E1HVN(bp) << 17) | (x))
1180
1181 #define SP_DESC_CNT             (BCM_PAGE_SIZE / sizeof(struct eth_spe))
1182 #define MAX_SP_DESC_CNT                 (SP_DESC_CNT - 1)
1183
1184
1185 #define BNX2X_BTR                       1
1186 #define MAX_SPQ_PENDING                 8
1187
1188
1189 /* CMNG constants
1190    derived from lab experiments, and not from system spec calculations !!! */
1191 #define DEF_MIN_RATE                    100
1192 /* resolution of the rate shaping timer - 100 usec */
1193 #define RS_PERIODIC_TIMEOUT_USEC        100
1194 /* resolution of fairness algorithm in usecs -
1195    coefficient for calculating the actual t fair */
1196 #define T_FAIR_COEF                     10000000
1197 /* number of bytes in single QM arbitration cycle -
1198    coefficient for calculating the fairness timer */
1199 #define QM_ARB_BYTES                    40000
1200 #define FAIR_MEM                        2
1201
1202
1203 #define ATTN_NIG_FOR_FUNC               (1L << 8)
1204 #define ATTN_SW_TIMER_4_FUNC            (1L << 9)
1205 #define GPIO_2_FUNC                     (1L << 10)
1206 #define GPIO_3_FUNC                     (1L << 11)
1207 #define GPIO_4_FUNC                     (1L << 12)
1208 #define ATTN_GENERAL_ATTN_1             (1L << 13)
1209 #define ATTN_GENERAL_ATTN_2             (1L << 14)
1210 #define ATTN_GENERAL_ATTN_3             (1L << 15)
1211 #define ATTN_GENERAL_ATTN_4             (1L << 13)
1212 #define ATTN_GENERAL_ATTN_5             (1L << 14)
1213 #define ATTN_GENERAL_ATTN_6             (1L << 15)
1214
1215 #define ATTN_HARD_WIRED_MASK            0xff00
1216 #define ATTENTION_ID                    4
1217
1218
1219 /* stuff added to make the code fit 80Col */
1220
1221 #define BNX2X_PMF_LINK_ASSERT \
1222         GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp))
1223
1224 #define BNX2X_MC_ASSERT_BITS \
1225         (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1226          GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1227          GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1228          GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
1229
1230 #define BNX2X_MCP_ASSERT \
1231         GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
1232
1233 #define BNX2X_GRC_TIMEOUT       GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
1234 #define BNX2X_GRC_RSV           (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \
1235                                  GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \
1236                                  GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \
1237                                  GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \
1238                                  GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
1239                                  GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
1240
1241 #define HW_INTERRUT_ASSERT_SET_0 \
1242                                 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \
1243                                  AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \
1244                                  AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \
1245                                  AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT)
1246 #define HW_PRTY_ASSERT_SET_0    (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \
1247                                  AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \
1248                                  AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \
1249                                  AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
1250                                  AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR)
1251 #define HW_INTERRUT_ASSERT_SET_1 \
1252                                 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \
1253                                  AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \
1254                                  AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \
1255                                  AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \
1256                                  AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \
1257                                  AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \
1258                                  AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \
1259                                  AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \
1260                                  AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \
1261                                  AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \
1262                                  AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
1263 #define HW_PRTY_ASSERT_SET_1    (AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR |\
1264                                  AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \
1265                                  AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \
1266                                  AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \
1267                                  AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
1268                              AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
1269                                  AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \
1270                                  AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \
1271                                  AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \
1272                                  AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \
1273                                  AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR)
1274 #define HW_INTERRUT_ASSERT_SET_2 \
1275                                 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \
1276                                  AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \
1277                                  AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \
1278                         AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\
1279                                  AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
1280 #define HW_PRTY_ASSERT_SET_2    (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \
1281                                  AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \
1282                         AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
1283                                  AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \
1284                                  AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \
1285                                  AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \
1286                                  AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
1287
1288
1289 #define MULTI_FLAGS(bp) \
1290                 (TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY | \
1291                  TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY | \
1292                  TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY | \
1293                  TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY | \
1294                  (bp->multi_mode << \
1295                   TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT))
1296 #define MULTI_MASK                      0x7f
1297
1298
1299 #define DEF_USB_FUNC_OFF                (2 + 2*HC_USTORM_DEF_SB_NUM_INDICES)
1300 #define DEF_CSB_FUNC_OFF                (2 + 2*HC_CSTORM_DEF_SB_NUM_INDICES)
1301 #define DEF_XSB_FUNC_OFF                (2 + 2*HC_XSTORM_DEF_SB_NUM_INDICES)
1302 #define DEF_TSB_FUNC_OFF                (2 + 2*HC_TSTORM_DEF_SB_NUM_INDICES)
1303
1304 #define C_DEF_SB_SP_INDEX               HC_INDEX_DEF_C_ETH_SLOW_PATH
1305
1306 #define BNX2X_SP_DSB_INDEX \
1307 (&bp->def_status_blk->c_def_status_block.index_values[C_DEF_SB_SP_INDEX])
1308
1309
1310 #define CAM_IS_INVALID(x) \
1311 (x.target_table_entry.flags == TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE)
1312
1313 #define CAM_INVALIDATE(x) \
1314         (x.target_table_entry.flags = TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE)
1315
1316
1317 /* Number of u32 elements in MC hash array */
1318 #define MC_HASH_SIZE                    8
1319 #define MC_HASH_OFFSET(bp, i)           (BAR_TSTRORM_INTMEM + \
1320         TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4)
1321
1322
1323 #ifndef PXP2_REG_PXP2_INT_STS
1324 #define PXP2_REG_PXP2_INT_STS           PXP2_REG_PXP2_INT_STS_0
1325 #endif
1326
1327 /* MISC_REG_RESET_REG - this is here for the hsi to work don't touch */
1328
1329 #endif /* bnx2x.h */