2 * Copyright (C) 2007-2009 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/pci.h>
21 #include <linux/gfp.h>
22 #include <linux/bitops.h>
23 #include <linux/debugfs.h>
24 #include <linux/scatterlist.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/iommu-helper.h>
27 #include <linux/iommu.h>
28 #include <asm/proto.h>
29 #include <asm/iommu.h>
31 #include <asm/amd_iommu_proto.h>
32 #include <asm/amd_iommu_types.h>
33 #include <asm/amd_iommu.h>
35 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
37 #define EXIT_LOOP_COUNT 10000000
39 static DEFINE_RWLOCK(amd_iommu_devtable_lock
);
41 /* A list of preallocated protection domains */
42 static LIST_HEAD(iommu_pd_list
);
43 static DEFINE_SPINLOCK(iommu_pd_list_lock
);
46 * Domain for untranslated devices - only allocated
47 * if iommu=pt passed on kernel cmd line.
49 static struct protection_domain
*pt_domain
;
51 static struct iommu_ops amd_iommu_ops
;
54 * general struct to manage commands send to an IOMMU
60 static void reset_iommu_command_buffer(struct amd_iommu
*iommu
);
61 static void update_domain(struct protection_domain
*domain
);
63 /****************************************************************************
67 ****************************************************************************/
69 static inline u16
get_device_id(struct device
*dev
)
71 struct pci_dev
*pdev
= to_pci_dev(dev
);
73 return calc_devid(pdev
->bus
->number
, pdev
->devfn
);
76 static struct iommu_dev_data
*get_dev_data(struct device
*dev
)
78 return dev
->archdata
.iommu
;
82 * In this function the list of preallocated protection domains is traversed to
83 * find the domain for a specific device
85 static struct dma_ops_domain
*find_protection_domain(u16 devid
)
87 struct dma_ops_domain
*entry
, *ret
= NULL
;
89 u16 alias
= amd_iommu_alias_table
[devid
];
91 if (list_empty(&iommu_pd_list
))
94 spin_lock_irqsave(&iommu_pd_list_lock
, flags
);
96 list_for_each_entry(entry
, &iommu_pd_list
, list
) {
97 if (entry
->target_dev
== devid
||
98 entry
->target_dev
== alias
) {
104 spin_unlock_irqrestore(&iommu_pd_list_lock
, flags
);
110 * This function checks if the driver got a valid device from the caller to
111 * avoid dereferencing invalid pointers.
113 static bool check_device(struct device
*dev
)
117 if (!dev
|| !dev
->dma_mask
)
120 /* No device or no PCI device */
121 if (!dev
|| dev
->bus
!= &pci_bus_type
)
124 devid
= get_device_id(dev
);
126 /* Out of our scope? */
127 if (devid
> amd_iommu_last_bdf
)
130 if (amd_iommu_rlookup_table
[devid
] == NULL
)
136 static int iommu_init_device(struct device
*dev
)
138 struct iommu_dev_data
*dev_data
;
139 struct pci_dev
*pdev
;
142 if (dev
->archdata
.iommu
)
145 dev_data
= kzalloc(sizeof(*dev_data
), GFP_KERNEL
);
149 devid
= get_device_id(dev
);
150 alias
= amd_iommu_alias_table
[devid
];
151 pdev
= pci_get_bus_and_slot(PCI_BUS(alias
), alias
& 0xff);
153 dev_data
->alias
= &pdev
->dev
;
155 atomic_set(&dev_data
->bind
, 0);
157 dev
->archdata
.iommu
= dev_data
;
163 static void iommu_uninit_device(struct device
*dev
)
165 kfree(dev
->archdata
.iommu
);
167 #ifdef CONFIG_AMD_IOMMU_STATS
170 * Initialization code for statistics collection
173 DECLARE_STATS_COUNTER(compl_wait
);
174 DECLARE_STATS_COUNTER(cnt_map_single
);
175 DECLARE_STATS_COUNTER(cnt_unmap_single
);
176 DECLARE_STATS_COUNTER(cnt_map_sg
);
177 DECLARE_STATS_COUNTER(cnt_unmap_sg
);
178 DECLARE_STATS_COUNTER(cnt_alloc_coherent
);
179 DECLARE_STATS_COUNTER(cnt_free_coherent
);
180 DECLARE_STATS_COUNTER(cross_page
);
181 DECLARE_STATS_COUNTER(domain_flush_single
);
182 DECLARE_STATS_COUNTER(domain_flush_all
);
183 DECLARE_STATS_COUNTER(alloced_io_mem
);
184 DECLARE_STATS_COUNTER(total_map_requests
);
186 static struct dentry
*stats_dir
;
187 static struct dentry
*de_fflush
;
189 static void amd_iommu_stats_add(struct __iommu_counter
*cnt
)
191 if (stats_dir
== NULL
)
194 cnt
->dent
= debugfs_create_u64(cnt
->name
, 0444, stats_dir
,
198 static void amd_iommu_stats_init(void)
200 stats_dir
= debugfs_create_dir("amd-iommu", NULL
);
201 if (stats_dir
== NULL
)
204 de_fflush
= debugfs_create_bool("fullflush", 0444, stats_dir
,
205 (u32
*)&amd_iommu_unmap_flush
);
207 amd_iommu_stats_add(&compl_wait
);
208 amd_iommu_stats_add(&cnt_map_single
);
209 amd_iommu_stats_add(&cnt_unmap_single
);
210 amd_iommu_stats_add(&cnt_map_sg
);
211 amd_iommu_stats_add(&cnt_unmap_sg
);
212 amd_iommu_stats_add(&cnt_alloc_coherent
);
213 amd_iommu_stats_add(&cnt_free_coherent
);
214 amd_iommu_stats_add(&cross_page
);
215 amd_iommu_stats_add(&domain_flush_single
);
216 amd_iommu_stats_add(&domain_flush_all
);
217 amd_iommu_stats_add(&alloced_io_mem
);
218 amd_iommu_stats_add(&total_map_requests
);
223 /****************************************************************************
225 * Interrupt handling functions
227 ****************************************************************************/
229 static void dump_dte_entry(u16 devid
)
233 for (i
= 0; i
< 8; ++i
)
234 pr_err("AMD-Vi: DTE[%d]: %08x\n", i
,
235 amd_iommu_dev_table
[devid
].data
[i
]);
238 static void dump_command(unsigned long phys_addr
)
240 struct iommu_cmd
*cmd
= phys_to_virt(phys_addr
);
243 for (i
= 0; i
< 4; ++i
)
244 pr_err("AMD-Vi: CMD[%d]: %08x\n", i
, cmd
->data
[i
]);
247 static void iommu_print_event(struct amd_iommu
*iommu
, void *__evt
)
250 int type
= (event
[1] >> EVENT_TYPE_SHIFT
) & EVENT_TYPE_MASK
;
251 int devid
= (event
[0] >> EVENT_DEVID_SHIFT
) & EVENT_DEVID_MASK
;
252 int domid
= (event
[1] >> EVENT_DOMID_SHIFT
) & EVENT_DOMID_MASK
;
253 int flags
= (event
[1] >> EVENT_FLAGS_SHIFT
) & EVENT_FLAGS_MASK
;
254 u64 address
= (u64
)(((u64
)event
[3]) << 32) | event
[2];
256 printk(KERN_ERR
"AMD-Vi: Event logged [");
259 case EVENT_TYPE_ILL_DEV
:
260 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
261 "address=0x%016llx flags=0x%04x]\n",
262 PCI_BUS(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
264 dump_dte_entry(devid
);
266 case EVENT_TYPE_IO_FAULT
:
267 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
268 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
269 PCI_BUS(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
270 domid
, address
, flags
);
272 case EVENT_TYPE_DEV_TAB_ERR
:
273 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
274 "address=0x%016llx flags=0x%04x]\n",
275 PCI_BUS(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
278 case EVENT_TYPE_PAGE_TAB_ERR
:
279 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
280 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
281 PCI_BUS(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
282 domid
, address
, flags
);
284 case EVENT_TYPE_ILL_CMD
:
285 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address
);
286 reset_iommu_command_buffer(iommu
);
287 dump_command(address
);
289 case EVENT_TYPE_CMD_HARD_ERR
:
290 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
291 "flags=0x%04x]\n", address
, flags
);
293 case EVENT_TYPE_IOTLB_INV_TO
:
294 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
295 "address=0x%016llx]\n",
296 PCI_BUS(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
299 case EVENT_TYPE_INV_DEV_REQ
:
300 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
301 "address=0x%016llx flags=0x%04x]\n",
302 PCI_BUS(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
306 printk(KERN_ERR
"UNKNOWN type=0x%02x]\n", type
);
310 static void iommu_poll_events(struct amd_iommu
*iommu
)
315 spin_lock_irqsave(&iommu
->lock
, flags
);
317 head
= readl(iommu
->mmio_base
+ MMIO_EVT_HEAD_OFFSET
);
318 tail
= readl(iommu
->mmio_base
+ MMIO_EVT_TAIL_OFFSET
);
320 while (head
!= tail
) {
321 iommu_print_event(iommu
, iommu
->evt_buf
+ head
);
322 head
= (head
+ EVENT_ENTRY_SIZE
) % iommu
->evt_buf_size
;
325 writel(head
, iommu
->mmio_base
+ MMIO_EVT_HEAD_OFFSET
);
327 spin_unlock_irqrestore(&iommu
->lock
, flags
);
330 irqreturn_t
amd_iommu_int_handler(int irq
, void *data
)
332 struct amd_iommu
*iommu
;
334 for_each_iommu(iommu
)
335 iommu_poll_events(iommu
);
340 /****************************************************************************
342 * IOMMU command queuing functions
344 ****************************************************************************/
347 * Writes the command to the IOMMUs command buffer and informs the
348 * hardware about the new command. Must be called with iommu->lock held.
350 static int __iommu_queue_command(struct amd_iommu
*iommu
, struct iommu_cmd
*cmd
)
355 tail
= readl(iommu
->mmio_base
+ MMIO_CMD_TAIL_OFFSET
);
356 target
= iommu
->cmd_buf
+ tail
;
357 memcpy_toio(target
, cmd
, sizeof(*cmd
));
358 tail
= (tail
+ sizeof(*cmd
)) % iommu
->cmd_buf_size
;
359 head
= readl(iommu
->mmio_base
+ MMIO_CMD_HEAD_OFFSET
);
362 writel(tail
, iommu
->mmio_base
+ MMIO_CMD_TAIL_OFFSET
);
368 * General queuing function for commands. Takes iommu->lock and calls
369 * __iommu_queue_command().
371 static int iommu_queue_command(struct amd_iommu
*iommu
, struct iommu_cmd
*cmd
)
376 spin_lock_irqsave(&iommu
->lock
, flags
);
377 ret
= __iommu_queue_command(iommu
, cmd
);
379 iommu
->need_sync
= true;
380 spin_unlock_irqrestore(&iommu
->lock
, flags
);
386 * This function waits until an IOMMU has completed a completion
389 static void __iommu_wait_for_completion(struct amd_iommu
*iommu
)
395 INC_STATS_COUNTER(compl_wait
);
397 while (!ready
&& (i
< EXIT_LOOP_COUNT
)) {
399 /* wait for the bit to become one */
400 status
= readl(iommu
->mmio_base
+ MMIO_STATUS_OFFSET
);
401 ready
= status
& MMIO_STATUS_COM_WAIT_INT_MASK
;
404 /* set bit back to zero */
405 status
&= ~MMIO_STATUS_COM_WAIT_INT_MASK
;
406 writel(status
, iommu
->mmio_base
+ MMIO_STATUS_OFFSET
);
408 if (unlikely(i
== EXIT_LOOP_COUNT
)) {
409 spin_unlock(&iommu
->lock
);
410 reset_iommu_command_buffer(iommu
);
411 spin_lock(&iommu
->lock
);
416 * This function queues a completion wait command into the command
419 static int __iommu_completion_wait(struct amd_iommu
*iommu
)
421 struct iommu_cmd cmd
;
423 memset(&cmd
, 0, sizeof(cmd
));
424 cmd
.data
[0] = CMD_COMPL_WAIT_INT_MASK
;
425 CMD_SET_TYPE(&cmd
, CMD_COMPL_WAIT
);
427 return __iommu_queue_command(iommu
, &cmd
);
431 * This function is called whenever we need to ensure that the IOMMU has
432 * completed execution of all commands we sent. It sends a
433 * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs
434 * us about that by writing a value to a physical address we pass with
437 static int iommu_completion_wait(struct amd_iommu
*iommu
)
442 spin_lock_irqsave(&iommu
->lock
, flags
);
444 if (!iommu
->need_sync
)
447 ret
= __iommu_completion_wait(iommu
);
449 iommu
->need_sync
= false;
454 __iommu_wait_for_completion(iommu
);
457 spin_unlock_irqrestore(&iommu
->lock
, flags
);
462 static void iommu_flush_complete(struct protection_domain
*domain
)
466 for (i
= 0; i
< amd_iommus_present
; ++i
) {
467 if (!domain
->dev_iommu
[i
])
471 * Devices of this domain are behind this IOMMU
472 * We need to wait for completion of all commands.
474 iommu_completion_wait(amd_iommus
[i
]);
479 * Command send function for invalidating a device table entry
481 static int iommu_queue_inv_dev_entry(struct amd_iommu
*iommu
, u16 devid
)
483 struct iommu_cmd cmd
;
486 BUG_ON(iommu
== NULL
);
488 memset(&cmd
, 0, sizeof(cmd
));
489 CMD_SET_TYPE(&cmd
, CMD_INV_DEV_ENTRY
);
492 ret
= iommu_queue_command(iommu
, &cmd
);
497 static void __iommu_build_inv_iommu_pages(struct iommu_cmd
*cmd
, u64 address
,
498 u16 domid
, int pde
, int s
)
500 memset(cmd
, 0, sizeof(*cmd
));
501 address
&= PAGE_MASK
;
502 CMD_SET_TYPE(cmd
, CMD_INV_IOMMU_PAGES
);
503 cmd
->data
[1] |= domid
;
504 cmd
->data
[2] = lower_32_bits(address
);
505 cmd
->data
[3] = upper_32_bits(address
);
506 if (s
) /* size bit - we flush more than one 4kb page */
507 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK
;
508 if (pde
) /* PDE bit - we wan't flush everything not only the PTEs */
509 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK
;
513 * Generic command send function for invalidaing TLB entries
515 static int iommu_queue_inv_iommu_pages(struct amd_iommu
*iommu
,
516 u64 address
, u16 domid
, int pde
, int s
)
518 struct iommu_cmd cmd
;
521 __iommu_build_inv_iommu_pages(&cmd
, address
, domid
, pde
, s
);
523 ret
= iommu_queue_command(iommu
, &cmd
);
529 * TLB invalidation function which is called from the mapping functions.
530 * It invalidates a single PTE if the range to flush is within a single
531 * page. Otherwise it flushes the whole TLB of the IOMMU.
533 static void __iommu_flush_pages(struct protection_domain
*domain
,
534 u64 address
, size_t size
, int pde
)
537 unsigned long pages
= iommu_num_pages(address
, size
, PAGE_SIZE
);
539 address
&= PAGE_MASK
;
543 * If we have to flush more than one page, flush all
544 * TLB entries for this domain
546 address
= CMD_INV_IOMMU_ALL_PAGES_ADDRESS
;
551 for (i
= 0; i
< amd_iommus_present
; ++i
) {
552 if (!domain
->dev_iommu
[i
])
556 * Devices of this domain are behind this IOMMU
557 * We need a TLB flush
559 iommu_queue_inv_iommu_pages(amd_iommus
[i
], address
,
566 static void iommu_flush_pages(struct protection_domain
*domain
,
567 u64 address
, size_t size
)
569 __iommu_flush_pages(domain
, address
, size
, 0);
572 /* Flush the whole IO/TLB for a given protection domain */
573 static void iommu_flush_tlb(struct protection_domain
*domain
)
575 __iommu_flush_pages(domain
, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS
, 0);
578 /* Flush the whole IO/TLB for a given protection domain - including PDE */
579 static void iommu_flush_tlb_pde(struct protection_domain
*domain
)
581 __iommu_flush_pages(domain
, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS
, 1);
585 * This function flushes all domains that have devices on the given IOMMU
587 static void flush_all_domains_on_iommu(struct amd_iommu
*iommu
)
589 u64 address
= CMD_INV_IOMMU_ALL_PAGES_ADDRESS
;
590 struct protection_domain
*domain
;
593 spin_lock_irqsave(&amd_iommu_pd_lock
, flags
);
595 list_for_each_entry(domain
, &amd_iommu_pd_list
, list
) {
596 if (domain
->dev_iommu
[iommu
->index
] == 0)
599 spin_lock(&domain
->lock
);
600 iommu_queue_inv_iommu_pages(iommu
, address
, domain
->id
, 1, 1);
601 iommu_flush_complete(domain
);
602 spin_unlock(&domain
->lock
);
605 spin_unlock_irqrestore(&amd_iommu_pd_lock
, flags
);
609 * This function uses heavy locking and may disable irqs for some time. But
610 * this is no issue because it is only called during resume.
612 void amd_iommu_flush_all_domains(void)
614 struct protection_domain
*domain
;
617 spin_lock_irqsave(&amd_iommu_pd_lock
, flags
);
619 list_for_each_entry(domain
, &amd_iommu_pd_list
, list
) {
620 spin_lock(&domain
->lock
);
621 iommu_flush_tlb_pde(domain
);
622 iommu_flush_complete(domain
);
623 spin_unlock(&domain
->lock
);
626 spin_unlock_irqrestore(&amd_iommu_pd_lock
, flags
);
629 static void flush_all_devices_for_iommu(struct amd_iommu
*iommu
)
633 for (i
= 0; i
<= amd_iommu_last_bdf
; ++i
) {
634 if (iommu
!= amd_iommu_rlookup_table
[i
])
637 iommu_queue_inv_dev_entry(iommu
, i
);
638 iommu_completion_wait(iommu
);
642 static void flush_devices_by_domain(struct protection_domain
*domain
)
644 struct amd_iommu
*iommu
;
647 for (i
= 0; i
<= amd_iommu_last_bdf
; ++i
) {
648 if ((domain
== NULL
&& amd_iommu_pd_table
[i
] == NULL
) ||
649 (amd_iommu_pd_table
[i
] != domain
))
652 iommu
= amd_iommu_rlookup_table
[i
];
656 iommu_queue_inv_dev_entry(iommu
, i
);
657 iommu_completion_wait(iommu
);
661 static void reset_iommu_command_buffer(struct amd_iommu
*iommu
)
663 pr_err("AMD-Vi: Resetting IOMMU command buffer\n");
665 if (iommu
->reset_in_progress
)
666 panic("AMD-Vi: ILLEGAL_COMMAND_ERROR while resetting command buffer\n");
668 iommu
->reset_in_progress
= true;
670 amd_iommu_reset_cmd_buffer(iommu
);
671 flush_all_devices_for_iommu(iommu
);
672 flush_all_domains_on_iommu(iommu
);
674 iommu
->reset_in_progress
= false;
677 void amd_iommu_flush_all_devices(void)
679 flush_devices_by_domain(NULL
);
682 /****************************************************************************
684 * The functions below are used the create the page table mappings for
685 * unity mapped regions.
687 ****************************************************************************/
690 * This function is used to add another level to an IO page table. Adding
691 * another level increases the size of the address space by 9 bits to a size up
694 static bool increase_address_space(struct protection_domain
*domain
,
699 if (domain
->mode
== PAGE_MODE_6_LEVEL
)
700 /* address space already 64 bit large */
703 pte
= (void *)get_zeroed_page(gfp
);
707 *pte
= PM_LEVEL_PDE(domain
->mode
,
708 virt_to_phys(domain
->pt_root
));
709 domain
->pt_root
= pte
;
711 domain
->updated
= true;
716 static u64
*alloc_pte(struct protection_domain
*domain
,
717 unsigned long address
,
725 while (address
> PM_LEVEL_SIZE(domain
->mode
))
726 increase_address_space(domain
, gfp
);
728 level
= domain
->mode
- 1;
729 pte
= &domain
->pt_root
[PM_LEVEL_INDEX(level
, address
)];
731 while (level
> end_lvl
) {
732 if (!IOMMU_PTE_PRESENT(*pte
)) {
733 page
= (u64
*)get_zeroed_page(gfp
);
736 *pte
= PM_LEVEL_PDE(level
, virt_to_phys(page
));
741 pte
= IOMMU_PTE_PAGE(*pte
);
743 if (pte_page
&& level
== end_lvl
)
746 pte
= &pte
[PM_LEVEL_INDEX(level
, address
)];
753 * This function checks if there is a PTE for a given dma address. If
754 * there is one, it returns the pointer to it.
756 static u64
*fetch_pte(struct protection_domain
*domain
,
757 unsigned long address
, int map_size
)
762 level
= domain
->mode
- 1;
763 pte
= &domain
->pt_root
[PM_LEVEL_INDEX(level
, address
)];
765 while (level
> map_size
) {
766 if (!IOMMU_PTE_PRESENT(*pte
))
771 pte
= IOMMU_PTE_PAGE(*pte
);
772 pte
= &pte
[PM_LEVEL_INDEX(level
, address
)];
774 if ((PM_PTE_LEVEL(*pte
) == 0) && level
!= map_size
) {
784 * Generic mapping functions. It maps a physical address into a DMA
785 * address space. It allocates the page table pages if necessary.
786 * In the future it can be extended to a generic mapping function
787 * supporting all features of AMD IOMMU page tables like level skipping
788 * and full 64 bit address spaces.
790 static int iommu_map_page(struct protection_domain
*dom
,
791 unsigned long bus_addr
,
792 unsigned long phys_addr
,
798 bus_addr
= PAGE_ALIGN(bus_addr
);
799 phys_addr
= PAGE_ALIGN(phys_addr
);
801 BUG_ON(!PM_ALIGNED(map_size
, bus_addr
));
802 BUG_ON(!PM_ALIGNED(map_size
, phys_addr
));
804 if (!(prot
& IOMMU_PROT_MASK
))
807 pte
= alloc_pte(dom
, bus_addr
, map_size
, NULL
, GFP_KERNEL
);
809 if (IOMMU_PTE_PRESENT(*pte
))
812 __pte
= phys_addr
| IOMMU_PTE_P
;
813 if (prot
& IOMMU_PROT_IR
)
814 __pte
|= IOMMU_PTE_IR
;
815 if (prot
& IOMMU_PROT_IW
)
816 __pte
|= IOMMU_PTE_IW
;
825 static void iommu_unmap_page(struct protection_domain
*dom
,
826 unsigned long bus_addr
, int map_size
)
828 u64
*pte
= fetch_pte(dom
, bus_addr
, map_size
);
835 * This function checks if a specific unity mapping entry is needed for
836 * this specific IOMMU.
838 static int iommu_for_unity_map(struct amd_iommu
*iommu
,
839 struct unity_map_entry
*entry
)
843 for (i
= entry
->devid_start
; i
<= entry
->devid_end
; ++i
) {
844 bdf
= amd_iommu_alias_table
[i
];
845 if (amd_iommu_rlookup_table
[bdf
] == iommu
)
853 * This function actually applies the mapping to the page table of the
856 static int dma_ops_unity_map(struct dma_ops_domain
*dma_dom
,
857 struct unity_map_entry
*e
)
862 for (addr
= e
->address_start
; addr
< e
->address_end
;
864 ret
= iommu_map_page(&dma_dom
->domain
, addr
, addr
, e
->prot
,
869 * if unity mapping is in aperture range mark the page
870 * as allocated in the aperture
872 if (addr
< dma_dom
->aperture_size
)
873 __set_bit(addr
>> PAGE_SHIFT
,
874 dma_dom
->aperture
[0]->bitmap
);
881 * Init the unity mappings for a specific IOMMU in the system
883 * Basically iterates over all unity mapping entries and applies them to
884 * the default domain DMA of that IOMMU if necessary.
886 static int iommu_init_unity_mappings(struct amd_iommu
*iommu
)
888 struct unity_map_entry
*entry
;
891 list_for_each_entry(entry
, &amd_iommu_unity_map
, list
) {
892 if (!iommu_for_unity_map(iommu
, entry
))
894 ret
= dma_ops_unity_map(iommu
->default_dom
, entry
);
903 * Inits the unity mappings required for a specific device
905 static int init_unity_mappings_for_device(struct dma_ops_domain
*dma_dom
,
908 struct unity_map_entry
*e
;
911 list_for_each_entry(e
, &amd_iommu_unity_map
, list
) {
912 if (!(devid
>= e
->devid_start
&& devid
<= e
->devid_end
))
914 ret
= dma_ops_unity_map(dma_dom
, e
);
922 /****************************************************************************
924 * The next functions belong to the address allocator for the dma_ops
925 * interface functions. They work like the allocators in the other IOMMU
926 * drivers. Its basically a bitmap which marks the allocated pages in
927 * the aperture. Maybe it could be enhanced in the future to a more
928 * efficient allocator.
930 ****************************************************************************/
933 * The address allocator core functions.
935 * called with domain->lock held
939 * Used to reserve address ranges in the aperture (e.g. for exclusion
942 static void dma_ops_reserve_addresses(struct dma_ops_domain
*dom
,
943 unsigned long start_page
,
946 unsigned int i
, last_page
= dom
->aperture_size
>> PAGE_SHIFT
;
948 if (start_page
+ pages
> last_page
)
949 pages
= last_page
- start_page
;
951 for (i
= start_page
; i
< start_page
+ pages
; ++i
) {
952 int index
= i
/ APERTURE_RANGE_PAGES
;
953 int page
= i
% APERTURE_RANGE_PAGES
;
954 __set_bit(page
, dom
->aperture
[index
]->bitmap
);
959 * This function is used to add a new aperture range to an existing
960 * aperture in case of dma_ops domain allocation or address allocation
963 static int alloc_new_range(struct dma_ops_domain
*dma_dom
,
964 bool populate
, gfp_t gfp
)
966 int index
= dma_dom
->aperture_size
>> APERTURE_RANGE_SHIFT
;
967 struct amd_iommu
*iommu
;
970 #ifdef CONFIG_IOMMU_STRESS
974 if (index
>= APERTURE_MAX_RANGES
)
977 dma_dom
->aperture
[index
] = kzalloc(sizeof(struct aperture_range
), gfp
);
978 if (!dma_dom
->aperture
[index
])
981 dma_dom
->aperture
[index
]->bitmap
= (void *)get_zeroed_page(gfp
);
982 if (!dma_dom
->aperture
[index
]->bitmap
)
985 dma_dom
->aperture
[index
]->offset
= dma_dom
->aperture_size
;
988 unsigned long address
= dma_dom
->aperture_size
;
989 int i
, num_ptes
= APERTURE_RANGE_PAGES
/ 512;
992 for (i
= 0; i
< num_ptes
; ++i
) {
993 pte
= alloc_pte(&dma_dom
->domain
, address
, PM_MAP_4k
,
998 dma_dom
->aperture
[index
]->pte_pages
[i
] = pte_page
;
1000 address
+= APERTURE_RANGE_SIZE
/ 64;
1004 dma_dom
->aperture_size
+= APERTURE_RANGE_SIZE
;
1006 /* Intialize the exclusion range if necessary */
1007 for_each_iommu(iommu
) {
1008 if (iommu
->exclusion_start
&&
1009 iommu
->exclusion_start
>= dma_dom
->aperture
[index
]->offset
1010 && iommu
->exclusion_start
< dma_dom
->aperture_size
) {
1011 unsigned long startpage
;
1012 int pages
= iommu_num_pages(iommu
->exclusion_start
,
1013 iommu
->exclusion_length
,
1015 startpage
= iommu
->exclusion_start
>> PAGE_SHIFT
;
1016 dma_ops_reserve_addresses(dma_dom
, startpage
, pages
);
1021 * Check for areas already mapped as present in the new aperture
1022 * range and mark those pages as reserved in the allocator. Such
1023 * mappings may already exist as a result of requested unity
1024 * mappings for devices.
1026 for (i
= dma_dom
->aperture
[index
]->offset
;
1027 i
< dma_dom
->aperture_size
;
1029 u64
*pte
= fetch_pte(&dma_dom
->domain
, i
, PM_MAP_4k
);
1030 if (!pte
|| !IOMMU_PTE_PRESENT(*pte
))
1033 dma_ops_reserve_addresses(dma_dom
, i
<< PAGE_SHIFT
, 1);
1036 update_domain(&dma_dom
->domain
);
1041 update_domain(&dma_dom
->domain
);
1043 free_page((unsigned long)dma_dom
->aperture
[index
]->bitmap
);
1045 kfree(dma_dom
->aperture
[index
]);
1046 dma_dom
->aperture
[index
] = NULL
;
1051 static unsigned long dma_ops_area_alloc(struct device
*dev
,
1052 struct dma_ops_domain
*dom
,
1054 unsigned long align_mask
,
1056 unsigned long start
)
1058 unsigned long next_bit
= dom
->next_address
% APERTURE_RANGE_SIZE
;
1059 int max_index
= dom
->aperture_size
>> APERTURE_RANGE_SHIFT
;
1060 int i
= start
>> APERTURE_RANGE_SHIFT
;
1061 unsigned long boundary_size
;
1062 unsigned long address
= -1;
1063 unsigned long limit
;
1065 next_bit
>>= PAGE_SHIFT
;
1067 boundary_size
= ALIGN(dma_get_seg_boundary(dev
) + 1,
1068 PAGE_SIZE
) >> PAGE_SHIFT
;
1070 for (;i
< max_index
; ++i
) {
1071 unsigned long offset
= dom
->aperture
[i
]->offset
>> PAGE_SHIFT
;
1073 if (dom
->aperture
[i
]->offset
>= dma_mask
)
1076 limit
= iommu_device_max_index(APERTURE_RANGE_PAGES
, offset
,
1077 dma_mask
>> PAGE_SHIFT
);
1079 address
= iommu_area_alloc(dom
->aperture
[i
]->bitmap
,
1080 limit
, next_bit
, pages
, 0,
1081 boundary_size
, align_mask
);
1082 if (address
!= -1) {
1083 address
= dom
->aperture
[i
]->offset
+
1084 (address
<< PAGE_SHIFT
);
1085 dom
->next_address
= address
+ (pages
<< PAGE_SHIFT
);
1095 static unsigned long dma_ops_alloc_addresses(struct device
*dev
,
1096 struct dma_ops_domain
*dom
,
1098 unsigned long align_mask
,
1101 unsigned long address
;
1103 #ifdef CONFIG_IOMMU_STRESS
1104 dom
->next_address
= 0;
1105 dom
->need_flush
= true;
1108 address
= dma_ops_area_alloc(dev
, dom
, pages
, align_mask
,
1109 dma_mask
, dom
->next_address
);
1111 if (address
== -1) {
1112 dom
->next_address
= 0;
1113 address
= dma_ops_area_alloc(dev
, dom
, pages
, align_mask
,
1115 dom
->need_flush
= true;
1118 if (unlikely(address
== -1))
1119 address
= DMA_ERROR_CODE
;
1121 WARN_ON((address
+ (PAGE_SIZE
*pages
)) > dom
->aperture_size
);
1127 * The address free function.
1129 * called with domain->lock held
1131 static void dma_ops_free_addresses(struct dma_ops_domain
*dom
,
1132 unsigned long address
,
1135 unsigned i
= address
>> APERTURE_RANGE_SHIFT
;
1136 struct aperture_range
*range
= dom
->aperture
[i
];
1138 BUG_ON(i
>= APERTURE_MAX_RANGES
|| range
== NULL
);
1140 #ifdef CONFIG_IOMMU_STRESS
1145 if (address
>= dom
->next_address
)
1146 dom
->need_flush
= true;
1148 address
= (address
% APERTURE_RANGE_SIZE
) >> PAGE_SHIFT
;
1150 iommu_area_free(range
->bitmap
, address
, pages
);
1154 /****************************************************************************
1156 * The next functions belong to the domain allocation. A domain is
1157 * allocated for every IOMMU as the default domain. If device isolation
1158 * is enabled, every device get its own domain. The most important thing
1159 * about domains is the page table mapping the DMA address space they
1162 ****************************************************************************/
1165 * This function adds a protection domain to the global protection domain list
1167 static void add_domain_to_list(struct protection_domain
*domain
)
1169 unsigned long flags
;
1171 spin_lock_irqsave(&amd_iommu_pd_lock
, flags
);
1172 list_add(&domain
->list
, &amd_iommu_pd_list
);
1173 spin_unlock_irqrestore(&amd_iommu_pd_lock
, flags
);
1177 * This function removes a protection domain to the global
1178 * protection domain list
1180 static void del_domain_from_list(struct protection_domain
*domain
)
1182 unsigned long flags
;
1184 spin_lock_irqsave(&amd_iommu_pd_lock
, flags
);
1185 list_del(&domain
->list
);
1186 spin_unlock_irqrestore(&amd_iommu_pd_lock
, flags
);
1189 static u16
domain_id_alloc(void)
1191 unsigned long flags
;
1194 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
1195 id
= find_first_zero_bit(amd_iommu_pd_alloc_bitmap
, MAX_DOMAIN_ID
);
1197 if (id
> 0 && id
< MAX_DOMAIN_ID
)
1198 __set_bit(id
, amd_iommu_pd_alloc_bitmap
);
1201 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
1206 static void domain_id_free(int id
)
1208 unsigned long flags
;
1210 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
1211 if (id
> 0 && id
< MAX_DOMAIN_ID
)
1212 __clear_bit(id
, amd_iommu_pd_alloc_bitmap
);
1213 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
1216 static void free_pagetable(struct protection_domain
*domain
)
1221 p1
= domain
->pt_root
;
1226 for (i
= 0; i
< 512; ++i
) {
1227 if (!IOMMU_PTE_PRESENT(p1
[i
]))
1230 p2
= IOMMU_PTE_PAGE(p1
[i
]);
1231 for (j
= 0; j
< 512; ++j
) {
1232 if (!IOMMU_PTE_PRESENT(p2
[j
]))
1234 p3
= IOMMU_PTE_PAGE(p2
[j
]);
1235 free_page((unsigned long)p3
);
1238 free_page((unsigned long)p2
);
1241 free_page((unsigned long)p1
);
1243 domain
->pt_root
= NULL
;
1247 * Free a domain, only used if something went wrong in the
1248 * allocation path and we need to free an already allocated page table
1250 static void dma_ops_domain_free(struct dma_ops_domain
*dom
)
1257 del_domain_from_list(&dom
->domain
);
1259 free_pagetable(&dom
->domain
);
1261 for (i
= 0; i
< APERTURE_MAX_RANGES
; ++i
) {
1262 if (!dom
->aperture
[i
])
1264 free_page((unsigned long)dom
->aperture
[i
]->bitmap
);
1265 kfree(dom
->aperture
[i
]);
1272 * Allocates a new protection domain usable for the dma_ops functions.
1273 * It also intializes the page table and the address allocator data
1274 * structures required for the dma_ops interface
1276 static struct dma_ops_domain
*dma_ops_domain_alloc(void)
1278 struct dma_ops_domain
*dma_dom
;
1280 dma_dom
= kzalloc(sizeof(struct dma_ops_domain
), GFP_KERNEL
);
1284 spin_lock_init(&dma_dom
->domain
.lock
);
1286 dma_dom
->domain
.id
= domain_id_alloc();
1287 if (dma_dom
->domain
.id
== 0)
1289 dma_dom
->domain
.mode
= PAGE_MODE_2_LEVEL
;
1290 dma_dom
->domain
.pt_root
= (void *)get_zeroed_page(GFP_KERNEL
);
1291 dma_dom
->domain
.flags
= PD_DMA_OPS_MASK
;
1292 dma_dom
->domain
.priv
= dma_dom
;
1293 if (!dma_dom
->domain
.pt_root
)
1296 dma_dom
->need_flush
= false;
1297 dma_dom
->target_dev
= 0xffff;
1299 add_domain_to_list(&dma_dom
->domain
);
1301 if (alloc_new_range(dma_dom
, true, GFP_KERNEL
))
1305 * mark the first page as allocated so we never return 0 as
1306 * a valid dma-address. So we can use 0 as error value
1308 dma_dom
->aperture
[0]->bitmap
[0] = 1;
1309 dma_dom
->next_address
= 0;
1315 dma_ops_domain_free(dma_dom
);
1321 * little helper function to check whether a given protection domain is a
1324 static bool dma_ops_domain(struct protection_domain
*domain
)
1326 return domain
->flags
& PD_DMA_OPS_MASK
;
1329 static void set_dte_entry(u16 devid
, struct protection_domain
*domain
)
1331 struct amd_iommu
*iommu
= amd_iommu_rlookup_table
[devid
];
1332 u64 pte_root
= virt_to_phys(domain
->pt_root
);
1334 BUG_ON(amd_iommu_pd_table
[devid
] != NULL
);
1336 pte_root
|= (domain
->mode
& DEV_ENTRY_MODE_MASK
)
1337 << DEV_ENTRY_MODE_SHIFT
;
1338 pte_root
|= IOMMU_PTE_IR
| IOMMU_PTE_IW
| IOMMU_PTE_P
| IOMMU_PTE_TV
;
1340 amd_iommu_dev_table
[devid
].data
[2] = domain
->id
;
1341 amd_iommu_dev_table
[devid
].data
[1] = upper_32_bits(pte_root
);
1342 amd_iommu_dev_table
[devid
].data
[0] = lower_32_bits(pte_root
);
1344 amd_iommu_pd_table
[devid
] = domain
;
1346 /* Do reference counting */
1347 domain
->dev_iommu
[iommu
->index
] += 1;
1348 domain
->dev_cnt
+= 1;
1350 /* Flush the changes DTE entry */
1351 iommu_queue_inv_dev_entry(iommu
, devid
);
1354 static void clear_dte_entry(u16 devid
)
1356 struct protection_domain
*domain
= amd_iommu_pd_table
[devid
];
1357 struct amd_iommu
*iommu
= amd_iommu_rlookup_table
[devid
];
1359 BUG_ON(domain
== NULL
);
1361 /* remove domain from the lookup table */
1362 amd_iommu_pd_table
[devid
] = NULL
;
1364 /* remove entry from the device table seen by the hardware */
1365 amd_iommu_dev_table
[devid
].data
[0] = IOMMU_PTE_P
| IOMMU_PTE_TV
;
1366 amd_iommu_dev_table
[devid
].data
[1] = 0;
1367 amd_iommu_dev_table
[devid
].data
[2] = 0;
1369 amd_iommu_apply_erratum_63(devid
);
1371 /* decrease reference counters */
1372 domain
->dev_iommu
[iommu
->index
] -= 1;
1373 domain
->dev_cnt
-= 1;
1375 iommu_queue_inv_dev_entry(iommu
, devid
);
1379 * If a device is not yet associated with a domain, this function does
1380 * assigns it visible for the hardware
1382 static int __attach_device(struct device
*dev
,
1383 struct protection_domain
*domain
)
1385 struct iommu_dev_data
*dev_data
, *alias_data
;
1388 devid
= get_device_id(dev
);
1389 alias
= amd_iommu_alias_table
[devid
];
1390 dev_data
= get_dev_data(dev
);
1391 alias_data
= get_dev_data(dev_data
->alias
);
1396 spin_lock(&domain
->lock
);
1398 /* Some sanity checks */
1399 if (alias_data
->domain
!= NULL
&&
1400 alias_data
->domain
!= domain
)
1403 if (dev_data
->domain
!= NULL
&&
1404 dev_data
->domain
!= domain
)
1407 /* Do real assignment */
1408 if (alias
!= devid
) {
1409 if (alias_data
->domain
== NULL
) {
1410 alias_data
->domain
= domain
;
1411 set_dte_entry(alias
, domain
);
1414 atomic_inc(&alias_data
->bind
);
1417 if (dev_data
->domain
== NULL
) {
1418 dev_data
->domain
= domain
;
1419 set_dte_entry(devid
, domain
);
1422 atomic_inc(&dev_data
->bind
);
1425 spin_unlock(&domain
->lock
);
1431 * If a device is not yet associated with a domain, this function does
1432 * assigns it visible for the hardware
1434 static int attach_device(struct device
*dev
,
1435 struct protection_domain
*domain
)
1437 unsigned long flags
;
1440 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
1441 ret
= __attach_device(dev
, domain
);
1442 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
1445 * We might boot into a crash-kernel here. The crashed kernel
1446 * left the caches in the IOMMU dirty. So we have to flush
1447 * here to evict all dirty stuff.
1449 iommu_flush_tlb_pde(domain
);
1455 * Removes a device from a protection domain (unlocked)
1457 static void __detach_device(struct device
*dev
)
1459 u16 devid
= get_device_id(dev
), alias
;
1460 struct amd_iommu
*iommu
= amd_iommu_rlookup_table
[devid
];
1461 struct iommu_dev_data
*dev_data
= get_dev_data(dev
);
1462 struct iommu_dev_data
*alias_data
;
1466 devid
= get_device_id(dev
);
1467 alias
= get_device_id(dev_data
->alias
);
1469 if (devid
!= alias
) {
1470 alias_data
= get_dev_data(dev_data
->alias
);
1471 if (atomic_dec_and_test(&alias_data
->bind
)) {
1472 clear_dte_entry(alias
);
1473 alias_data
->domain
= NULL
;
1477 if (atomic_dec_and_test(&dev_data
->bind
)) {
1478 clear_dte_entry(devid
);
1479 dev_data
->domain
= NULL
;
1483 * If we run in passthrough mode the device must be assigned to the
1484 * passthrough domain if it is detached from any other domain
1486 if (iommu_pass_through
&& dev_data
->domain
== NULL
)
1487 __attach_device(dev
, pt_domain
);
1491 * Removes a device from a protection domain (with devtable_lock held)
1493 static void detach_device(struct device
*dev
)
1495 unsigned long flags
;
1497 /* lock device table */
1498 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
1499 __detach_device(dev
);
1500 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
1504 * Find out the protection domain structure for a given PCI device. This
1505 * will give us the pointer to the page table root for example.
1507 static struct protection_domain
*domain_for_device(struct device
*dev
)
1509 struct protection_domain
*dom
;
1510 struct iommu_dev_data
*dev_data
, *alias_data
;
1511 unsigned long flags
;
1514 devid
= get_device_id(dev
);
1515 alias
= amd_iommu_alias_table
[devid
];
1516 dev_data
= get_dev_data(dev
);
1517 alias_data
= get_dev_data(dev_data
->alias
);
1521 read_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
1522 dom
= dev_data
->domain
;
1524 alias_data
->domain
!= NULL
) {
1525 __attach_device(dev
, alias_data
->domain
);
1526 dom
= alias_data
->domain
;
1529 read_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
1534 static int device_change_notifier(struct notifier_block
*nb
,
1535 unsigned long action
, void *data
)
1537 struct device
*dev
= data
;
1539 struct protection_domain
*domain
;
1540 struct dma_ops_domain
*dma_domain
;
1541 struct amd_iommu
*iommu
;
1542 unsigned long flags
;
1544 if (!check_device(dev
))
1547 devid
= get_device_id(dev
);
1548 iommu
= amd_iommu_rlookup_table
[devid
];
1551 case BUS_NOTIFY_UNBOUND_DRIVER
:
1553 domain
= domain_for_device(dev
);
1557 if (iommu_pass_through
)
1561 case BUS_NOTIFY_ADD_DEVICE
:
1563 iommu_init_device(dev
);
1565 domain
= domain_for_device(dev
);
1567 /* allocate a protection domain if a device is added */
1568 dma_domain
= find_protection_domain(devid
);
1571 dma_domain
= dma_ops_domain_alloc();
1574 dma_domain
->target_dev
= devid
;
1576 spin_lock_irqsave(&iommu_pd_list_lock
, flags
);
1577 list_add_tail(&dma_domain
->list
, &iommu_pd_list
);
1578 spin_unlock_irqrestore(&iommu_pd_list_lock
, flags
);
1581 case BUS_NOTIFY_DEL_DEVICE
:
1583 iommu_uninit_device(dev
);
1589 iommu_queue_inv_dev_entry(iommu
, devid
);
1590 iommu_completion_wait(iommu
);
1596 static struct notifier_block device_nb
= {
1597 .notifier_call
= device_change_notifier
,
1600 /*****************************************************************************
1602 * The next functions belong to the dma_ops mapping/unmapping code.
1604 *****************************************************************************/
1607 * In the dma_ops path we only have the struct device. This function
1608 * finds the corresponding IOMMU, the protection domain and the
1609 * requestor id for a given device.
1610 * If the device is not yet associated with a domain this is also done
1613 static struct protection_domain
*get_domain(struct device
*dev
)
1615 struct protection_domain
*domain
;
1616 struct dma_ops_domain
*dma_dom
;
1617 u16 devid
= get_device_id(dev
);
1619 if (!check_device(dev
))
1620 return ERR_PTR(-EINVAL
);
1622 domain
= domain_for_device(dev
);
1623 if (domain
!= NULL
&& !dma_ops_domain(domain
))
1624 return ERR_PTR(-EBUSY
);
1629 /* Device not bount yet - bind it */
1630 dma_dom
= find_protection_domain(devid
);
1632 dma_dom
= amd_iommu_rlookup_table
[devid
]->default_dom
;
1633 attach_device(dev
, &dma_dom
->domain
);
1634 DUMP_printk("Using protection domain %d for device %s\n",
1635 dma_dom
->domain
.id
, dev_name(dev
));
1637 return &dma_dom
->domain
;
1640 static void update_device_table(struct protection_domain
*domain
)
1642 unsigned long flags
;
1645 for (i
= 0; i
<= amd_iommu_last_bdf
; ++i
) {
1646 if (amd_iommu_pd_table
[i
] != domain
)
1648 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
1649 set_dte_entry(i
, domain
);
1650 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
1654 static void update_domain(struct protection_domain
*domain
)
1656 if (!domain
->updated
)
1659 update_device_table(domain
);
1660 flush_devices_by_domain(domain
);
1661 iommu_flush_tlb_pde(domain
);
1663 domain
->updated
= false;
1667 * This function fetches the PTE for a given address in the aperture
1669 static u64
* dma_ops_get_pte(struct dma_ops_domain
*dom
,
1670 unsigned long address
)
1672 struct aperture_range
*aperture
;
1673 u64
*pte
, *pte_page
;
1675 aperture
= dom
->aperture
[APERTURE_RANGE_INDEX(address
)];
1679 pte
= aperture
->pte_pages
[APERTURE_PAGE_INDEX(address
)];
1681 pte
= alloc_pte(&dom
->domain
, address
, PM_MAP_4k
, &pte_page
,
1683 aperture
->pte_pages
[APERTURE_PAGE_INDEX(address
)] = pte_page
;
1685 pte
+= PM_LEVEL_INDEX(0, address
);
1687 update_domain(&dom
->domain
);
1693 * This is the generic map function. It maps one 4kb page at paddr to
1694 * the given address in the DMA address space for the domain.
1696 static dma_addr_t
dma_ops_domain_map(struct dma_ops_domain
*dom
,
1697 unsigned long address
,
1703 WARN_ON(address
> dom
->aperture_size
);
1707 pte
= dma_ops_get_pte(dom
, address
);
1709 return DMA_ERROR_CODE
;
1711 __pte
= paddr
| IOMMU_PTE_P
| IOMMU_PTE_FC
;
1713 if (direction
== DMA_TO_DEVICE
)
1714 __pte
|= IOMMU_PTE_IR
;
1715 else if (direction
== DMA_FROM_DEVICE
)
1716 __pte
|= IOMMU_PTE_IW
;
1717 else if (direction
== DMA_BIDIRECTIONAL
)
1718 __pte
|= IOMMU_PTE_IR
| IOMMU_PTE_IW
;
1724 return (dma_addr_t
)address
;
1728 * The generic unmapping function for on page in the DMA address space.
1730 static void dma_ops_domain_unmap(struct dma_ops_domain
*dom
,
1731 unsigned long address
)
1733 struct aperture_range
*aperture
;
1736 if (address
>= dom
->aperture_size
)
1739 aperture
= dom
->aperture
[APERTURE_RANGE_INDEX(address
)];
1743 pte
= aperture
->pte_pages
[APERTURE_PAGE_INDEX(address
)];
1747 pte
+= PM_LEVEL_INDEX(0, address
);
1755 * This function contains common code for mapping of a physically
1756 * contiguous memory region into DMA address space. It is used by all
1757 * mapping functions provided with this IOMMU driver.
1758 * Must be called with the domain lock held.
1760 static dma_addr_t
__map_single(struct device
*dev
,
1761 struct dma_ops_domain
*dma_dom
,
1768 dma_addr_t offset
= paddr
& ~PAGE_MASK
;
1769 dma_addr_t address
, start
, ret
;
1771 unsigned long align_mask
= 0;
1774 pages
= iommu_num_pages(paddr
, size
, PAGE_SIZE
);
1777 INC_STATS_COUNTER(total_map_requests
);
1780 INC_STATS_COUNTER(cross_page
);
1783 align_mask
= (1UL << get_order(size
)) - 1;
1786 address
= dma_ops_alloc_addresses(dev
, dma_dom
, pages
, align_mask
,
1788 if (unlikely(address
== DMA_ERROR_CODE
)) {
1790 * setting next_address here will let the address
1791 * allocator only scan the new allocated range in the
1792 * first run. This is a small optimization.
1794 dma_dom
->next_address
= dma_dom
->aperture_size
;
1796 if (alloc_new_range(dma_dom
, false, GFP_ATOMIC
))
1800 * aperture was sucessfully enlarged by 128 MB, try
1807 for (i
= 0; i
< pages
; ++i
) {
1808 ret
= dma_ops_domain_map(dma_dom
, start
, paddr
, dir
);
1809 if (ret
== DMA_ERROR_CODE
)
1817 ADD_STATS_COUNTER(alloced_io_mem
, size
);
1819 if (unlikely(dma_dom
->need_flush
&& !amd_iommu_unmap_flush
)) {
1820 iommu_flush_tlb(&dma_dom
->domain
);
1821 dma_dom
->need_flush
= false;
1822 } else if (unlikely(amd_iommu_np_cache
))
1823 iommu_flush_pages(&dma_dom
->domain
, address
, size
);
1830 for (--i
; i
>= 0; --i
) {
1832 dma_ops_domain_unmap(dma_dom
, start
);
1835 dma_ops_free_addresses(dma_dom
, address
, pages
);
1837 return DMA_ERROR_CODE
;
1841 * Does the reverse of the __map_single function. Must be called with
1842 * the domain lock held too
1844 static void __unmap_single(struct dma_ops_domain
*dma_dom
,
1845 dma_addr_t dma_addr
,
1849 dma_addr_t i
, start
;
1852 if ((dma_addr
== DMA_ERROR_CODE
) ||
1853 (dma_addr
+ size
> dma_dom
->aperture_size
))
1856 pages
= iommu_num_pages(dma_addr
, size
, PAGE_SIZE
);
1857 dma_addr
&= PAGE_MASK
;
1860 for (i
= 0; i
< pages
; ++i
) {
1861 dma_ops_domain_unmap(dma_dom
, start
);
1865 SUB_STATS_COUNTER(alloced_io_mem
, size
);
1867 dma_ops_free_addresses(dma_dom
, dma_addr
, pages
);
1869 if (amd_iommu_unmap_flush
|| dma_dom
->need_flush
) {
1870 iommu_flush_pages(&dma_dom
->domain
, dma_addr
, size
);
1871 dma_dom
->need_flush
= false;
1876 * The exported map_single function for dma_ops.
1878 static dma_addr_t
map_page(struct device
*dev
, struct page
*page
,
1879 unsigned long offset
, size_t size
,
1880 enum dma_data_direction dir
,
1881 struct dma_attrs
*attrs
)
1883 unsigned long flags
;
1884 struct protection_domain
*domain
;
1887 phys_addr_t paddr
= page_to_phys(page
) + offset
;
1889 INC_STATS_COUNTER(cnt_map_single
);
1891 domain
= get_domain(dev
);
1892 if (PTR_ERR(domain
) == -EINVAL
)
1893 return (dma_addr_t
)paddr
;
1894 else if (IS_ERR(domain
))
1895 return DMA_ERROR_CODE
;
1897 dma_mask
= *dev
->dma_mask
;
1899 spin_lock_irqsave(&domain
->lock
, flags
);
1901 addr
= __map_single(dev
, domain
->priv
, paddr
, size
, dir
, false,
1903 if (addr
== DMA_ERROR_CODE
)
1906 iommu_flush_complete(domain
);
1909 spin_unlock_irqrestore(&domain
->lock
, flags
);
1915 * The exported unmap_single function for dma_ops.
1917 static void unmap_page(struct device
*dev
, dma_addr_t dma_addr
, size_t size
,
1918 enum dma_data_direction dir
, struct dma_attrs
*attrs
)
1920 unsigned long flags
;
1921 struct protection_domain
*domain
;
1923 INC_STATS_COUNTER(cnt_unmap_single
);
1925 domain
= get_domain(dev
);
1929 spin_lock_irqsave(&domain
->lock
, flags
);
1931 __unmap_single(domain
->priv
, dma_addr
, size
, dir
);
1933 iommu_flush_complete(domain
);
1935 spin_unlock_irqrestore(&domain
->lock
, flags
);
1939 * This is a special map_sg function which is used if we should map a
1940 * device which is not handled by an AMD IOMMU in the system.
1942 static int map_sg_no_iommu(struct device
*dev
, struct scatterlist
*sglist
,
1943 int nelems
, int dir
)
1945 struct scatterlist
*s
;
1948 for_each_sg(sglist
, s
, nelems
, i
) {
1949 s
->dma_address
= (dma_addr_t
)sg_phys(s
);
1950 s
->dma_length
= s
->length
;
1957 * The exported map_sg function for dma_ops (handles scatter-gather
1960 static int map_sg(struct device
*dev
, struct scatterlist
*sglist
,
1961 int nelems
, enum dma_data_direction dir
,
1962 struct dma_attrs
*attrs
)
1964 unsigned long flags
;
1965 struct protection_domain
*domain
;
1967 struct scatterlist
*s
;
1969 int mapped_elems
= 0;
1972 INC_STATS_COUNTER(cnt_map_sg
);
1974 domain
= get_domain(dev
);
1975 if (PTR_ERR(domain
) == -EINVAL
)
1976 return map_sg_no_iommu(dev
, sglist
, nelems
, dir
);
1977 else if (IS_ERR(domain
))
1980 dma_mask
= *dev
->dma_mask
;
1982 spin_lock_irqsave(&domain
->lock
, flags
);
1984 for_each_sg(sglist
, s
, nelems
, i
) {
1987 s
->dma_address
= __map_single(dev
, domain
->priv
,
1988 paddr
, s
->length
, dir
, false,
1991 if (s
->dma_address
) {
1992 s
->dma_length
= s
->length
;
1998 iommu_flush_complete(domain
);
2001 spin_unlock_irqrestore(&domain
->lock
, flags
);
2003 return mapped_elems
;
2005 for_each_sg(sglist
, s
, mapped_elems
, i
) {
2007 __unmap_single(domain
->priv
, s
->dma_address
,
2008 s
->dma_length
, dir
);
2009 s
->dma_address
= s
->dma_length
= 0;
2018 * The exported map_sg function for dma_ops (handles scatter-gather
2021 static void unmap_sg(struct device
*dev
, struct scatterlist
*sglist
,
2022 int nelems
, enum dma_data_direction dir
,
2023 struct dma_attrs
*attrs
)
2025 unsigned long flags
;
2026 struct protection_domain
*domain
;
2027 struct scatterlist
*s
;
2030 INC_STATS_COUNTER(cnt_unmap_sg
);
2032 domain
= get_domain(dev
);
2036 spin_lock_irqsave(&domain
->lock
, flags
);
2038 for_each_sg(sglist
, s
, nelems
, i
) {
2039 __unmap_single(domain
->priv
, s
->dma_address
,
2040 s
->dma_length
, dir
);
2041 s
->dma_address
= s
->dma_length
= 0;
2044 iommu_flush_complete(domain
);
2046 spin_unlock_irqrestore(&domain
->lock
, flags
);
2050 * The exported alloc_coherent function for dma_ops.
2052 static void *alloc_coherent(struct device
*dev
, size_t size
,
2053 dma_addr_t
*dma_addr
, gfp_t flag
)
2055 unsigned long flags
;
2057 struct protection_domain
*domain
;
2059 u64 dma_mask
= dev
->coherent_dma_mask
;
2061 INC_STATS_COUNTER(cnt_alloc_coherent
);
2063 domain
= get_domain(dev
);
2064 if (PTR_ERR(domain
) == -EINVAL
) {
2065 virt_addr
= (void *)__get_free_pages(flag
, get_order(size
));
2066 *dma_addr
= __pa(virt_addr
);
2068 } else if (IS_ERR(domain
))
2071 dma_mask
= dev
->coherent_dma_mask
;
2072 flag
&= ~(__GFP_DMA
| __GFP_HIGHMEM
| __GFP_DMA32
);
2075 virt_addr
= (void *)__get_free_pages(flag
, get_order(size
));
2079 paddr
= virt_to_phys(virt_addr
);
2082 dma_mask
= *dev
->dma_mask
;
2084 spin_lock_irqsave(&domain
->lock
, flags
);
2086 *dma_addr
= __map_single(dev
, domain
->priv
, paddr
,
2087 size
, DMA_BIDIRECTIONAL
, true, dma_mask
);
2089 if (*dma_addr
== DMA_ERROR_CODE
) {
2090 spin_unlock_irqrestore(&domain
->lock
, flags
);
2094 iommu_flush_complete(domain
);
2096 spin_unlock_irqrestore(&domain
->lock
, flags
);
2102 free_pages((unsigned long)virt_addr
, get_order(size
));
2108 * The exported free_coherent function for dma_ops.
2110 static void free_coherent(struct device
*dev
, size_t size
,
2111 void *virt_addr
, dma_addr_t dma_addr
)
2113 unsigned long flags
;
2114 struct protection_domain
*domain
;
2116 INC_STATS_COUNTER(cnt_free_coherent
);
2118 domain
= get_domain(dev
);
2122 spin_lock_irqsave(&domain
->lock
, flags
);
2124 __unmap_single(domain
->priv
, dma_addr
, size
, DMA_BIDIRECTIONAL
);
2126 iommu_flush_complete(domain
);
2128 spin_unlock_irqrestore(&domain
->lock
, flags
);
2131 free_pages((unsigned long)virt_addr
, get_order(size
));
2135 * This function is called by the DMA layer to find out if we can handle a
2136 * particular device. It is part of the dma_ops.
2138 static int amd_iommu_dma_supported(struct device
*dev
, u64 mask
)
2140 return check_device(dev
);
2144 * The function for pre-allocating protection domains.
2146 * If the driver core informs the DMA layer if a driver grabs a device
2147 * we don't need to preallocate the protection domains anymore.
2148 * For now we have to.
2150 static void prealloc_protection_domains(void)
2152 struct pci_dev
*dev
= NULL
;
2153 struct dma_ops_domain
*dma_dom
;
2156 while ((dev
= pci_get_device(PCI_ANY_ID
, PCI_ANY_ID
, dev
)) != NULL
) {
2158 /* Do we handle this device? */
2159 if (!check_device(&dev
->dev
))
2162 iommu_init_device(&dev
->dev
);
2164 /* Is there already any domain for it? */
2165 if (domain_for_device(&dev
->dev
))
2168 devid
= get_device_id(&dev
->dev
);
2170 dma_dom
= dma_ops_domain_alloc();
2173 init_unity_mappings_for_device(dma_dom
, devid
);
2174 dma_dom
->target_dev
= devid
;
2176 attach_device(&dev
->dev
, &dma_dom
->domain
);
2178 list_add_tail(&dma_dom
->list
, &iommu_pd_list
);
2182 static struct dma_map_ops amd_iommu_dma_ops
= {
2183 .alloc_coherent
= alloc_coherent
,
2184 .free_coherent
= free_coherent
,
2185 .map_page
= map_page
,
2186 .unmap_page
= unmap_page
,
2188 .unmap_sg
= unmap_sg
,
2189 .dma_supported
= amd_iommu_dma_supported
,
2193 * The function which clues the AMD IOMMU driver into dma_ops.
2195 int __init
amd_iommu_init_dma_ops(void)
2197 struct amd_iommu
*iommu
;
2201 * first allocate a default protection domain for every IOMMU we
2202 * found in the system. Devices not assigned to any other
2203 * protection domain will be assigned to the default one.
2205 for_each_iommu(iommu
) {
2206 iommu
->default_dom
= dma_ops_domain_alloc();
2207 if (iommu
->default_dom
== NULL
)
2209 iommu
->default_dom
->domain
.flags
|= PD_DEFAULT_MASK
;
2210 ret
= iommu_init_unity_mappings(iommu
);
2216 * Pre-allocate the protection domains for each device.
2218 prealloc_protection_domains();
2222 #ifdef CONFIG_GART_IOMMU
2223 gart_iommu_aperture_disabled
= 1;
2224 gart_iommu_aperture
= 0;
2227 /* Make the driver finally visible to the drivers */
2228 dma_ops
= &amd_iommu_dma_ops
;
2230 register_iommu(&amd_iommu_ops
);
2232 bus_register_notifier(&pci_bus_type
, &device_nb
);
2234 amd_iommu_stats_init();
2240 for_each_iommu(iommu
) {
2241 if (iommu
->default_dom
)
2242 dma_ops_domain_free(iommu
->default_dom
);
2248 /*****************************************************************************
2250 * The following functions belong to the exported interface of AMD IOMMU
2252 * This interface allows access to lower level functions of the IOMMU
2253 * like protection domain handling and assignement of devices to domains
2254 * which is not possible with the dma_ops interface.
2256 *****************************************************************************/
2258 static void cleanup_domain(struct protection_domain
*domain
)
2260 unsigned long flags
;
2263 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
2265 for (devid
= 0; devid
<= amd_iommu_last_bdf
; ++devid
)
2266 if (amd_iommu_pd_table
[devid
] == domain
)
2267 clear_dte_entry(devid
);
2269 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
2272 static void protection_domain_free(struct protection_domain
*domain
)
2277 del_domain_from_list(domain
);
2280 domain_id_free(domain
->id
);
2285 static struct protection_domain
*protection_domain_alloc(void)
2287 struct protection_domain
*domain
;
2289 domain
= kzalloc(sizeof(*domain
), GFP_KERNEL
);
2293 spin_lock_init(&domain
->lock
);
2294 domain
->id
= domain_id_alloc();
2298 add_domain_to_list(domain
);
2308 static int amd_iommu_domain_init(struct iommu_domain
*dom
)
2310 struct protection_domain
*domain
;
2312 domain
= protection_domain_alloc();
2316 domain
->mode
= PAGE_MODE_3_LEVEL
;
2317 domain
->pt_root
= (void *)get_zeroed_page(GFP_KERNEL
);
2318 if (!domain
->pt_root
)
2326 protection_domain_free(domain
);
2331 static void amd_iommu_domain_destroy(struct iommu_domain
*dom
)
2333 struct protection_domain
*domain
= dom
->priv
;
2338 if (domain
->dev_cnt
> 0)
2339 cleanup_domain(domain
);
2341 BUG_ON(domain
->dev_cnt
!= 0);
2343 free_pagetable(domain
);
2345 domain_id_free(domain
->id
);
2352 static void amd_iommu_detach_device(struct iommu_domain
*dom
,
2355 struct iommu_dev_data
*dev_data
= dev
->archdata
.iommu
;
2356 struct amd_iommu
*iommu
;
2359 if (!check_device(dev
))
2362 devid
= get_device_id(dev
);
2364 if (dev_data
->domain
!= NULL
)
2367 iommu
= amd_iommu_rlookup_table
[devid
];
2371 iommu_queue_inv_dev_entry(iommu
, devid
);
2372 iommu_completion_wait(iommu
);
2375 static int amd_iommu_attach_device(struct iommu_domain
*dom
,
2378 struct protection_domain
*domain
= dom
->priv
;
2379 struct iommu_dev_data
*dev_data
;
2380 struct amd_iommu
*iommu
;
2384 if (!check_device(dev
))
2387 dev_data
= dev
->archdata
.iommu
;
2389 devid
= get_device_id(dev
);
2391 iommu
= amd_iommu_rlookup_table
[devid
];
2395 if (dev_data
->domain
)
2398 ret
= attach_device(dev
, domain
);
2400 iommu_completion_wait(iommu
);
2405 static int amd_iommu_map_range(struct iommu_domain
*dom
,
2406 unsigned long iova
, phys_addr_t paddr
,
2407 size_t size
, int iommu_prot
)
2409 struct protection_domain
*domain
= dom
->priv
;
2410 unsigned long i
, npages
= iommu_num_pages(paddr
, size
, PAGE_SIZE
);
2414 if (iommu_prot
& IOMMU_READ
)
2415 prot
|= IOMMU_PROT_IR
;
2416 if (iommu_prot
& IOMMU_WRITE
)
2417 prot
|= IOMMU_PROT_IW
;
2422 for (i
= 0; i
< npages
; ++i
) {
2423 ret
= iommu_map_page(domain
, iova
, paddr
, prot
, PM_MAP_4k
);
2434 static void amd_iommu_unmap_range(struct iommu_domain
*dom
,
2435 unsigned long iova
, size_t size
)
2438 struct protection_domain
*domain
= dom
->priv
;
2439 unsigned long i
, npages
= iommu_num_pages(iova
, size
, PAGE_SIZE
);
2443 for (i
= 0; i
< npages
; ++i
) {
2444 iommu_unmap_page(domain
, iova
, PM_MAP_4k
);
2448 iommu_flush_tlb_pde(domain
);
2451 static phys_addr_t
amd_iommu_iova_to_phys(struct iommu_domain
*dom
,
2454 struct protection_domain
*domain
= dom
->priv
;
2455 unsigned long offset
= iova
& ~PAGE_MASK
;
2459 pte
= fetch_pte(domain
, iova
, PM_MAP_4k
);
2461 if (!pte
|| !IOMMU_PTE_PRESENT(*pte
))
2464 paddr
= *pte
& IOMMU_PAGE_MASK
;
2470 static int amd_iommu_domain_has_cap(struct iommu_domain
*domain
,
2476 static struct iommu_ops amd_iommu_ops
= {
2477 .domain_init
= amd_iommu_domain_init
,
2478 .domain_destroy
= amd_iommu_domain_destroy
,
2479 .attach_dev
= amd_iommu_attach_device
,
2480 .detach_dev
= amd_iommu_detach_device
,
2481 .map
= amd_iommu_map_range
,
2482 .unmap
= amd_iommu_unmap_range
,
2483 .iova_to_phys
= amd_iommu_iova_to_phys
,
2484 .domain_has_cap
= amd_iommu_domain_has_cap
,
2487 /*****************************************************************************
2489 * The next functions do a basic initialization of IOMMU for pass through
2492 * In passthrough mode the IOMMU is initialized and enabled but not used for
2493 * DMA-API translation.
2495 *****************************************************************************/
2497 int __init
amd_iommu_init_passthrough(void)
2499 struct amd_iommu
*iommu
;
2500 struct pci_dev
*dev
= NULL
;
2503 /* allocate passthroug domain */
2504 pt_domain
= protection_domain_alloc();
2508 pt_domain
->mode
|= PAGE_MODE_NONE
;
2510 while ((dev
= pci_get_device(PCI_ANY_ID
, PCI_ANY_ID
, dev
)) != NULL
) {
2512 if (!check_device(&dev
->dev
))
2515 devid
= get_device_id(&dev
->dev
);
2517 iommu
= amd_iommu_rlookup_table
[devid
];
2521 attach_device(&dev
->dev
, pt_domain
);
2524 pr_info("AMD-Vi: Initialized for Passthrough Mode\n");