2 * Code to handle x86 style IRQs plus some generic interrupt stuff.
4 * Copyright (C) 1992 Linus Torvalds
5 * Copyright (C) 1994, 1995, 1996, 1997, 1998 Ralf Baechle
6 * Copyright (C) 1999 SuSE GmbH (Philipp Rumpf, prumpf@tux.org)
7 * Copyright (C) 1999-2000 Grant Grundler
8 * Copyright (c) 2005 Matthew Wilcox
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2, or (at your option)
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 #include <linux/bitops.h>
25 #include <linux/errno.h>
26 #include <linux/init.h>
27 #include <linux/interrupt.h>
28 #include <linux/kernel_stat.h>
29 #include <linux/seq_file.h>
30 #include <linux/spinlock.h>
31 #include <linux/types.h>
36 #undef PARISC_IRQ_CR16_COUNTS
38 extern irqreturn_t
timer_interrupt(int, void *);
39 extern irqreturn_t
ipi_interrupt(int, void *);
41 #define EIEM_MASK(irq) (1UL<<(CPU_IRQ_MAX - irq))
43 /* Bits in EIEM correlate with cpu_irq_action[].
44 ** Numbered *Big Endian*! (ie bit 0 is MSB)
46 static volatile unsigned long cpu_eiem
= 0;
49 ** local ACK bitmap ... habitually set to 1, but reset to zero
50 ** between ->ack() and ->end() of the interrupt to prevent
51 ** re-interruption of a processing interrupt.
53 static DEFINE_PER_CPU(unsigned long, local_ack_eiem
) = ~0UL;
55 static void cpu_mask_irq(unsigned int irq
)
57 unsigned long eirr_bit
= EIEM_MASK(irq
);
59 cpu_eiem
&= ~eirr_bit
;
60 /* Do nothing on the other CPUs. If they get this interrupt,
61 * The & cpu_eiem in the do_cpu_irq_mask() ensures they won't
62 * handle it, and the set_eiem() at the bottom will ensure it
63 * then gets disabled */
66 static void cpu_unmask_irq(unsigned int irq
)
68 unsigned long eirr_bit
= EIEM_MASK(irq
);
72 /* This is just a simple NOP IPI. But what it does is cause
73 * all the other CPUs to do a set_eiem(cpu_eiem) at the end
74 * of the interrupt handler */
78 void no_ack_irq(unsigned int irq
) { }
79 void no_end_irq(unsigned int irq
) { }
81 void cpu_ack_irq(unsigned int irq
)
83 unsigned long mask
= EIEM_MASK(irq
);
84 int cpu
= smp_processor_id();
86 /* Clear in EIEM so we can no longer process */
87 per_cpu(local_ack_eiem
, cpu
) &= ~mask
;
89 /* disable the interrupt */
90 set_eiem(cpu_eiem
& per_cpu(local_ack_eiem
, cpu
));
96 void cpu_eoi_irq(unsigned int irq
)
98 unsigned long mask
= EIEM_MASK(irq
);
99 int cpu
= smp_processor_id();
101 /* set it in the eiems---it's no longer in process */
102 per_cpu(local_ack_eiem
, cpu
) |= mask
;
104 /* enable the interrupt */
105 set_eiem(cpu_eiem
& per_cpu(local_ack_eiem
, cpu
));
109 int cpu_check_affinity(unsigned int irq
, const struct cpumask
*dest
)
113 /* timer and ipi have to always be received on all CPUs */
114 if (CHECK_IRQ_PER_CPU(irq
)) {
115 /* Bad linux design decision. The mask has already
116 * been set; we must reset it */
117 cpumask_setall(irq_desc
[irq
].affinity
);
121 /* whatever mask they set, we just allow one CPU */
122 cpu_dest
= first_cpu(*dest
);
127 static int cpu_set_affinity_irq(unsigned int irq
, const struct cpumask
*dest
)
131 cpu_dest
= cpu_check_affinity(irq
, dest
);
135 cpumask_copy(irq_desc
[irq
].affinity
, dest
);
141 static struct irq_chip cpu_interrupt_type
= {
143 .mask
= cpu_mask_irq
,
144 .unmask
= cpu_unmask_irq
,
148 .set_affinity
= cpu_set_affinity_irq
,
150 /* XXX: Needs to be written. We managed without it so far, but
151 * we really ought to write it.
156 int show_interrupts(struct seq_file
*p
, void *v
)
158 int i
= *(loff_t
*) v
, j
;
163 for_each_online_cpu(j
)
164 seq_printf(p
, " CPU%d", j
);
166 #ifdef PARISC_IRQ_CR16_COUNTS
167 seq_printf(p
, " [min/avg/max] (CPU cycle counts)");
173 struct irqaction
*action
;
175 raw_spin_lock_irqsave(&irq_desc
[i
].lock
, flags
);
176 action
= irq_desc
[i
].action
;
179 seq_printf(p
, "%3d: ", i
);
181 for_each_online_cpu(j
)
182 seq_printf(p
, "%10u ", kstat_irqs_cpu(i
, j
));
184 seq_printf(p
, "%10u ", kstat_irqs(i
));
187 seq_printf(p
, " %14s", irq_desc
[i
].chip
->name
);
188 #ifndef PARISC_IRQ_CR16_COUNTS
189 seq_printf(p
, " %s", action
->name
);
191 while ((action
= action
->next
))
192 seq_printf(p
, ", %s", action
->name
);
194 for ( ;action
; action
= action
->next
) {
195 unsigned int k
, avg
, min
, max
;
197 min
= max
= action
->cr16_hist
[0];
199 for (avg
= k
= 0; k
< PARISC_CR16_HIST_SIZE
; k
++) {
200 int hist
= action
->cr16_hist
[k
];
207 if (hist
> max
) max
= hist
;
208 if (hist
< min
) min
= hist
;
212 seq_printf(p
, " %s[%d/%d/%d]", action
->name
,
219 raw_spin_unlock_irqrestore(&irq_desc
[i
].lock
, flags
);
228 ** The following form a "set": Virtual IRQ, Transaction Address, Trans Data.
229 ** Respectively, these map to IRQ region+EIRR, Processor HPA, EIRR bit.
231 ** To use txn_XXX() interfaces, get a Virtual IRQ first.
232 ** Then use that to get the Transaction address and data.
235 int cpu_claim_irq(unsigned int irq
, struct irq_chip
*type
, void *data
)
237 if (irq_desc
[irq
].action
)
239 if (irq_desc
[irq
].chip
!= &cpu_interrupt_type
)
242 /* for iosapic interrupts */
244 set_irq_chip_and_handler(irq
, type
, handle_level_irq
);
245 set_irq_chip_data(irq
, data
);
251 int txn_claim_irq(int irq
)
253 return cpu_claim_irq(irq
, NULL
, NULL
) ? -1 : irq
;
257 * The bits_wide parameter accommodates the limitations of the HW/SW which
259 * Legacy PA I/O (GSC/NIO): 5 bits (architected EIM register)
260 * V-class (EPIC): 6 bits
261 * N/L/A-class (iosapic): 8 bits
262 * PCI 2.2 MSI: 16 bits
263 * Some PCI devices: 32 bits (Symbios SCSI/ATM/HyperFabric)
265 * On the service provider side:
266 * o PA 1.1 (and PA2.0 narrow mode) 5-bits (width of EIR register)
267 * o PA 2.0 wide mode 6-bits (per processor)
268 * o IA64 8-bits (0-256 total)
270 * So a Legacy PA I/O device on a PA 2.0 box can't use all the bits supported
271 * by the processor...and the N/L-class I/O subsystem supports more bits than
272 * PA2.0 has. The first case is the problem.
274 int txn_alloc_irq(unsigned int bits_wide
)
278 /* never return irq 0 cause that's the interval timer */
279 for (irq
= CPU_IRQ_BASE
+ 1; irq
<= CPU_IRQ_MAX
; irq
++) {
280 if (cpu_claim_irq(irq
, NULL
, NULL
) < 0)
282 if ((irq
- CPU_IRQ_BASE
) >= (1 << bits_wide
))
287 /* unlikely, but be prepared */
292 unsigned long txn_affinity_addr(unsigned int irq
, int cpu
)
295 cpumask_copy(irq_desc
[irq
].affinity
, cpumask_of(cpu
));
298 return per_cpu(cpu_data
, cpu
).txn_addr
;
302 unsigned long txn_alloc_addr(unsigned int virt_irq
)
304 static int next_cpu
= -1;
306 next_cpu
++; /* assign to "next" CPU we want this bugger on */
309 while ((next_cpu
< nr_cpu_ids
) &&
310 (!per_cpu(cpu_data
, next_cpu
).txn_addr
||
311 !cpu_online(next_cpu
)))
314 if (next_cpu
>= nr_cpu_ids
)
315 next_cpu
= 0; /* nothing else, assign monarch */
317 return txn_affinity_addr(virt_irq
, next_cpu
);
321 unsigned int txn_alloc_data(unsigned int virt_irq
)
323 return virt_irq
- CPU_IRQ_BASE
;
326 static inline int eirr_to_irq(unsigned long eirr
)
328 int bit
= fls_long(eirr
);
329 return (BITS_PER_LONG
- bit
) + TIMER_IRQ
;
332 /* ONLY called from entry.S:intr_extint() */
333 void do_cpu_irq_mask(struct pt_regs
*regs
)
335 struct pt_regs
*old_regs
;
336 unsigned long eirr_val
;
337 int irq
, cpu
= smp_processor_id();
342 old_regs
= set_irq_regs(regs
);
346 eirr_val
= mfctl(23) & cpu_eiem
& per_cpu(local_ack_eiem
, cpu
);
349 irq
= eirr_to_irq(eirr_val
);
352 cpumask_copy(&dest
, irq_desc
[irq
].affinity
);
353 if (CHECK_IRQ_PER_CPU(irq_desc
[irq
].status
) &&
354 !cpu_isset(smp_processor_id(), dest
)) {
355 int cpu
= first_cpu(dest
);
357 printk(KERN_DEBUG
"redirecting irq %d from CPU %d to %d\n",
358 irq
, smp_processor_id(), cpu
);
359 gsc_writel(irq
+ CPU_IRQ_BASE
,
360 per_cpu(cpu_data
, cpu
).hpa
);
364 generic_handle_irq(irq
);
368 set_irq_regs(old_regs
);
372 set_eiem(cpu_eiem
& per_cpu(local_ack_eiem
, cpu
));
376 static struct irqaction timer_action
= {
377 .handler
= timer_interrupt
,
379 .flags
= IRQF_DISABLED
| IRQF_TIMER
| IRQF_PERCPU
| IRQF_IRQPOLL
,
383 static struct irqaction ipi_action
= {
384 .handler
= ipi_interrupt
,
386 .flags
= IRQF_DISABLED
| IRQF_PERCPU
,
390 static void claim_cpu_irqs(void)
393 for (i
= CPU_IRQ_BASE
; i
<= CPU_IRQ_MAX
; i
++) {
394 set_irq_chip_and_handler(i
, &cpu_interrupt_type
,
398 set_irq_handler(TIMER_IRQ
, handle_percpu_irq
);
399 setup_irq(TIMER_IRQ
, &timer_action
);
401 set_irq_handler(IPI_IRQ
, handle_percpu_irq
);
402 setup_irq(IPI_IRQ
, &ipi_action
);
406 void __init
init_IRQ(void)
408 local_irq_disable(); /* PARANOID - should already be disabled */
409 mtctl(~0UL, 23); /* EIRR : clear all pending external intr */
413 cpu_eiem
= EIEM_MASK(IPI_IRQ
) | EIEM_MASK(TIMER_IRQ
);
415 cpu_eiem
= EIEM_MASK(TIMER_IRQ
);
417 set_eiem(cpu_eiem
); /* EIEM : enable all external intr */