2 * linux/arch/arm/mach-sa1100/jornada720.c
4 * HP Jornada720 init code
6 * Copyright (C) 2007 Kristoffer Ericson <Kristoffer.Ericson@gmail.com>
7 * Copyright (C) 2006 Filip Zyzniewski <filip.zyzniewski@tefnet.pl>
8 * Copyright (C) 2005 Michael Gernoth <michael@gernoth.net>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
16 #include <linux/init.h>
17 #include <linux/kernel.h>
18 #include <linux/tty.h>
19 #include <linux/delay.h>
20 #include <linux/platform_device.h>
21 #include <linux/ioport.h>
22 #include <linux/mtd/mtd.h>
23 #include <linux/mtd/partitions.h>
24 #include <video/s1d13xxxfb.h>
26 #include <mach/hardware.h>
27 #include <asm/hardware/sa1111.h>
29 #include <asm/mach-types.h>
30 #include <asm/setup.h>
31 #include <asm/mach/arch.h>
32 #include <asm/mach/flash.h>
33 #include <asm/mach/map.h>
34 #include <asm/mach/serial_sa1100.h>
39 * HP Documentation referred in this file:
40 * http://www.jlime.com/downloads/development/docs/jornada7xx/jornada720.txt
43 /* line 110 of HP's doc */
44 #define TUCR_VAL 0x20000400
46 /* memory space (line 52 of HP's doc) */
47 #define SA1111REGSTART 0x40000000
48 #define SA1111REGLEN 0x00001fff
49 #define EPSONREGSTART 0x48000000
50 #define EPSONREGLEN 0x00100000
51 #define EPSONFBSTART 0x48200000
52 /* 512kB framebuffer */
53 #define EPSONFBLEN 512*1024
55 static struct s1d13xxxfb_regval s1d13xxxfb_initregs
[] = {
56 /* line 344 of HP's doc */
57 {0x0001,0x00}, // Miscellaneous Register
58 {0x01FC,0x00}, // Display Mode Register
59 {0x0004,0x00}, // General IO Pins Configuration Register 0
60 {0x0005,0x00}, // General IO Pins Configuration Register 1
61 {0x0008,0x00}, // General IO Pins Control Register 0
62 {0x0009,0x00}, // General IO Pins Control Register 1
63 {0x0010,0x01}, // Memory Clock Configuration Register
64 {0x0014,0x11}, // LCD Pixel Clock Configuration Register
65 {0x0018,0x01}, // CRT/TV Pixel Clock Configuration Register
66 {0x001C,0x01}, // MediaPlug Clock Configuration Register
67 {0x001E,0x01}, // CPU To Memory Wait State Select Register
68 {0x0020,0x00}, // Memory Configuration Register
69 {0x0021,0x45}, // DRAM Refresh Rate Register
70 {0x002A,0x01}, // DRAM Timings Control Register 0
71 {0x002B,0x03}, // DRAM Timings Control Register 1
72 {0x0030,0x1c}, // Panel Type Register
73 {0x0031,0x00}, // MOD Rate Register
74 {0x0032,0x4F}, // LCD Horizontal Display Width Register
75 {0x0034,0x07}, // LCD Horizontal Non-Display Period Register
76 {0x0035,0x01}, // TFT FPLINE Start Position Register
77 {0x0036,0x0B}, // TFT FPLINE Pulse Width Register
78 {0x0038,0xEF}, // LCD Vertical Display Height Register 0
79 {0x0039,0x00}, // LCD Vertical Display Height Register 1
80 {0x003A,0x13}, // LCD Vertical Non-Display Period Register
81 {0x003B,0x0B}, // TFT FPFRAME Start Position Register
82 {0x003C,0x01}, // TFT FPFRAME Pulse Width Register
83 {0x0040,0x05}, // LCD Display Mode Register (2:4bpp,3:8bpp,5:16bpp)
84 {0x0041,0x00}, // LCD Miscellaneous Register
85 {0x0042,0x00}, // LCD Display Start Address Register 0
86 {0x0043,0x00}, // LCD Display Start Address Register 1
87 {0x0044,0x00}, // LCD Display Start Address Register 2
88 {0x0046,0x80}, // LCD Memory Address Offset Register 0
89 {0x0047,0x02}, // LCD Memory Address Offset Register 1
90 {0x0048,0x00}, // LCD Pixel Panning Register
91 {0x004A,0x00}, // LCD Display FIFO High Threshold Control Register
92 {0x004B,0x00}, // LCD Display FIFO Low Threshold Control Register
93 {0x0050,0x4F}, // CRT/TV Horizontal Display Width Register
94 {0x0052,0x13}, // CRT/TV Horizontal Non-Display Period Register
95 {0x0053,0x01}, // CRT/TV HRTC Start Position Register
96 {0x0054,0x0B}, // CRT/TV HRTC Pulse Width Register
97 {0x0056,0xDF}, // CRT/TV Vertical Display Height Register 0
98 {0x0057,0x01}, // CRT/TV Vertical Display Height Register 1
99 {0x0058,0x2B}, // CRT/TV Vertical Non-Display Period Register
100 {0x0059,0x09}, // CRT/TV VRTC Start Position Register
101 {0x005A,0x01}, // CRT/TV VRTC Pulse Width Register
102 {0x005B,0x10}, // TV Output Control Register
103 {0x0060,0x03}, // CRT/TV Display Mode Register (2:4bpp,3:8bpp,5:16bpp)
104 {0x0062,0x00}, // CRT/TV Display Start Address Register 0
105 {0x0063,0x00}, // CRT/TV Display Start Address Register 1
106 {0x0064,0x00}, // CRT/TV Display Start Address Register 2
107 {0x0066,0x40}, // CRT/TV Memory Address Offset Register 0
108 {0x0067,0x01}, // CRT/TV Memory Address Offset Register 1
109 {0x0068,0x00}, // CRT/TV Pixel Panning Register
110 {0x006A,0x00}, // CRT/TV Display FIFO High Threshold Control Register
111 {0x006B,0x00}, // CRT/TV Display FIFO Low Threshold Control Register
112 {0x0070,0x00}, // LCD Ink/Cursor Control Register
113 {0x0071,0x01}, // LCD Ink/Cursor Start Address Register
114 {0x0072,0x00}, // LCD Cursor X Position Register 0
115 {0x0073,0x00}, // LCD Cursor X Position Register 1
116 {0x0074,0x00}, // LCD Cursor Y Position Register 0
117 {0x0075,0x00}, // LCD Cursor Y Position Register 1
118 {0x0076,0x00}, // LCD Ink/Cursor Blue Color 0 Register
119 {0x0077,0x00}, // LCD Ink/Cursor Green Color 0 Register
120 {0x0078,0x00}, // LCD Ink/Cursor Red Color 0 Register
121 {0x007A,0x1F}, // LCD Ink/Cursor Blue Color 1 Register
122 {0x007B,0x3F}, // LCD Ink/Cursor Green Color 1 Register
123 {0x007C,0x1F}, // LCD Ink/Cursor Red Color 1 Register
124 {0x007E,0x00}, // LCD Ink/Cursor FIFO Threshold Register
125 {0x0080,0x00}, // CRT/TV Ink/Cursor Control Register
126 {0x0081,0x01}, // CRT/TV Ink/Cursor Start Address Register
127 {0x0082,0x00}, // CRT/TV Cursor X Position Register 0
128 {0x0083,0x00}, // CRT/TV Cursor X Position Register 1
129 {0x0084,0x00}, // CRT/TV Cursor Y Position Register 0
130 {0x0085,0x00}, // CRT/TV Cursor Y Position Register 1
131 {0x0086,0x00}, // CRT/TV Ink/Cursor Blue Color 0 Register
132 {0x0087,0x00}, // CRT/TV Ink/Cursor Green Color 0 Register
133 {0x0088,0x00}, // CRT/TV Ink/Cursor Red Color 0 Register
134 {0x008A,0x1F}, // CRT/TV Ink/Cursor Blue Color 1 Register
135 {0x008B,0x3F}, // CRT/TV Ink/Cursor Green Color 1 Register
136 {0x008C,0x1F}, // CRT/TV Ink/Cursor Red Color 1 Register
137 {0x008E,0x00}, // CRT/TV Ink/Cursor FIFO Threshold Register
138 {0x0100,0x00}, // BitBlt Control Register 0
139 {0x0101,0x00}, // BitBlt Control Register 1
140 {0x0102,0x00}, // BitBlt ROP Code/Color Expansion Register
141 {0x0103,0x00}, // BitBlt Operation Register
142 {0x0104,0x00}, // BitBlt Source Start Address Register 0
143 {0x0105,0x00}, // BitBlt Source Start Address Register 1
144 {0x0106,0x00}, // BitBlt Source Start Address Register 2
145 {0x0108,0x00}, // BitBlt Destination Start Address Register 0
146 {0x0109,0x00}, // BitBlt Destination Start Address Register 1
147 {0x010A,0x00}, // BitBlt Destination Start Address Register 2
148 {0x010C,0x00}, // BitBlt Memory Address Offset Register 0
149 {0x010D,0x00}, // BitBlt Memory Address Offset Register 1
150 {0x0110,0x00}, // BitBlt Width Register 0
151 {0x0111,0x00}, // BitBlt Width Register 1
152 {0x0112,0x00}, // BitBlt Height Register 0
153 {0x0113,0x00}, // BitBlt Height Register 1
154 {0x0114,0x00}, // BitBlt Background Color Register 0
155 {0x0115,0x00}, // BitBlt Background Color Register 1
156 {0x0118,0x00}, // BitBlt Foreground Color Register 0
157 {0x0119,0x00}, // BitBlt Foreground Color Register 1
158 {0x01E0,0x00}, // Look-Up Table Mode Register
159 {0x01E2,0x00}, // Look-Up Table Address Register
160 /* not sure, wouldn't like to mess with the driver */
161 {0x01E4,0x00}, // Look-Up Table Data Register
162 /* jornada doc says 0x00, but I trust the driver */
163 {0x01F0,0x10}, // Power Save Configuration Register
164 {0x01F1,0x00}, // Power Save Status Register
165 {0x01F4,0x00}, // CPU-to-Memory Access Watchdog Timer Register
166 {0x01FC,0x01}, // Display Mode Register(0x01:LCD, 0x02:CRT, 0x03:LCD&CRT)
169 static struct s1d13xxxfb_pdata s1d13xxxfb_data
= {
170 .initregs
= s1d13xxxfb_initregs
,
171 .initregssize
= ARRAY_SIZE(s1d13xxxfb_initregs
),
172 .platform_init_video
= NULL
175 static struct resource s1d13xxxfb_resources
[] = {
177 .start
= EPSONFBSTART
,
178 .end
= EPSONFBSTART
+ EPSONFBLEN
,
179 .flags
= IORESOURCE_MEM
,
182 .start
= EPSONREGSTART
,
183 .end
= EPSONREGSTART
+ EPSONREGLEN
,
184 .flags
= IORESOURCE_MEM
,
188 static struct platform_device s1d13xxxfb_device
= {
189 .name
= S1D_DEVICENAME
,
192 .platform_data
= &s1d13xxxfb_data
,
194 .num_resources
= ARRAY_SIZE(s1d13xxxfb_resources
),
195 .resource
= s1d13xxxfb_resources
,
198 static struct resource sa1111_resources
[] = {
200 .start
= SA1111REGSTART
,
201 .end
= SA1111REGSTART
+ SA1111REGLEN
,
202 .flags
= IORESOURCE_MEM
,
207 .flags
= IORESOURCE_IRQ
,
211 static struct sa1111_platform_data sa1111_info
= {
212 .irq_base
= IRQ_BOARD_END
,
215 static u64 sa1111_dmamask
= 0xffffffffUL
;
217 static struct platform_device sa1111_device
= {
221 .dma_mask
= &sa1111_dmamask
,
222 .coherent_dma_mask
= 0xffffffff,
223 .platform_data
= &sa1111_info
,
225 .num_resources
= ARRAY_SIZE(sa1111_resources
),
226 .resource
= sa1111_resources
,
229 static struct platform_device jornada_ssp_device
= {
230 .name
= "jornada_ssp",
234 static struct platform_device jornada_kbd_device
= {
235 .name
= "jornada720_kbd",
239 static struct platform_device jornada_ts_device
= {
240 .name
= "jornada_ts",
244 static struct platform_device
*devices
[] __initdata
= {
252 static int __init
jornada720_init(void)
256 if (machine_is_jornada720()) {
257 /* we want to use gpio20 as input to drive the clock of our uart 3 */
258 GPDR
|= GPIO_GPIO20
; /* Clear gpio20 pin as input */
260 GPSR
= GPIO_GPIO20
; /* start gpio20 pin */
262 GPCR
= GPIO_GPIO20
; /* stop gpio20 */
264 GPSR
= GPIO_GPIO20
; /* restart gpio20 */
265 udelay(20); /* give it some time to restart */
267 ret
= platform_add_devices(devices
, ARRAY_SIZE(devices
));
273 arch_initcall(jornada720_init
);
275 static struct map_desc jornada720_io_desc
[] __initdata
= {
276 { /* Epson registers */
277 .virtual = 0xf0000000,
278 .pfn
= __phys_to_pfn(EPSONREGSTART
),
279 .length
= EPSONREGLEN
,
281 }, { /* Epson frame buffer */
282 .virtual = 0xf1000000,
283 .pfn
= __phys_to_pfn(EPSONFBSTART
),
284 .length
= EPSONFBLEN
,
287 .virtual = 0xf4000000,
288 .pfn
= __phys_to_pfn(SA1111REGSTART
),
289 .length
= SA1111REGLEN
,
294 static void __init
jornada720_map_io(void)
297 iotable_init(jornada720_io_desc
, ARRAY_SIZE(jornada720_io_desc
));
299 sa1100_register_uart(0, 3);
300 sa1100_register_uart(1, 1);
303 static struct mtd_partition jornada720_partitions
[] = {
305 .name
= "JORNADA720 boot firmware",
308 .mask_flags
= MTD_WRITEABLE
, /* force read-only */
310 .name
= "JORNADA720 kernel",
312 .offset
= 0x00040000,
314 .name
= "JORNADA720 params",
316 .offset
= 0x00100000,
318 .name
= "JORNADA720 initrd",
320 .offset
= 0x00140000,
322 .name
= "JORNADA720 root cramfs",
324 .offset
= 0x00240000,
326 .name
= "JORNADA720 usr cramfs",
328 .offset
= 0x00540000,
330 .name
= "JORNADA720 usr local",
331 .size
= 0, /* will expand to the end of the flash */
332 .offset
= 0x00d00000,
336 static void jornada720_set_vpp(int vpp
)
339 /* enabling flash write (line 470 of HP's doc) */
342 /* disabling flash write (line 470 of HP's doc) */
347 static struct flash_platform_data jornada720_flash_data
= {
348 .map_name
= "cfi_probe",
349 .set_vpp
= jornada720_set_vpp
,
350 .parts
= jornada720_partitions
,
351 .nr_parts
= ARRAY_SIZE(jornada720_partitions
),
354 static struct resource jornada720_flash_resource
= {
355 .start
= SA1100_CS0_PHYS
,
356 .end
= SA1100_CS0_PHYS
+ SZ_32M
- 1,
357 .flags
= IORESOURCE_MEM
,
360 static void __init
jornada720_mach_init(void)
362 sa11x0_register_mtd(&jornada720_flash_data
, &jornada720_flash_resource
, 1);
365 MACHINE_START(JORNADA720
, "HP Jornada 720")
366 /* Maintainer: Kristoffer Ericson <Kristoffer.Ericson@gmail.com> */
367 .boot_params
= 0xc0000100,
368 .map_io
= jornada720_map_io
,
369 .init_irq
= sa1100_init_irq
,
370 .timer
= &sa1100_timer
,
371 .init_machine
= jornada720_mach_init
,