arch/arm/mach-s5p64x0/gpio.c

   1 /* linux/arch/arm/mach-s5p64x0/gpio.c
   2  *
   3  * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com
   5  *
   6  * S5P64X0 - GPIOlib support
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/irq.h>
  15 #include <linux/io.h>
  16 #include <linux/gpio.h>
  17
  18 #include <mach/map.h>
  19 #include <mach/regs-gpio.h>
  20
  21 #include <plat/gpio-core.h>
  22 #include <plat/gpio-cfg.h>
  23 #include <plat/gpio-cfg-helpers.h>
  24
  25 /* To be implemented S5P6450 GPIO */
  26
  27 /*
  28  * S5P6440 GPIO bank summary:
  29  *
  30  * Bank GPIOs   Style   SlpCon  ExtInt Group
  31  * A    6       4Bit    Yes     1
  32  * B    7       4Bit    Yes     1
  33  * C    8       4Bit    Yes     2
  34  * F    2       2Bit    Yes     4 [1]
  35  * G    7       4Bit    Yes     5
  36  * H    10      4Bit[2] Yes     6
  37  * I    16      2Bit    Yes     None
  38  * J    12      2Bit    Yes     None
  39  * N    16      2Bit    No      IRQ_EINT
  40  * P    8       2Bit    Yes     8
  41  * R    15      4Bit[2] Yes     8
  42  *
  43  * [1] BANKF pins 14,15 do not form part of the external interrupt sources
  44  * [2] BANK has two control registers, GPxCON0 and GPxCON1
  45  */
  46
  47 static int s5p64x0_gpiolib_rbank_4bit2_input(struct gpio_chip *chip,
  48                                              unsigned int offset)
  49 {
  50         struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
  51         void __iomem *base = ourchip->base;
  52         void __iomem *regcon = base;
  53         unsigned long con;
  54         unsigned long flags;
  55
  56         switch (offset) {
  57         case 6:
  58                 offset += 1;
  59         case 0:
  60         case 1:
  61         case 2:
  62         case 3:
  63         case 4:
  64         case 5:
  65                 regcon -= 4;
  66                 break;
  67         default:
  68                 offset -= 7;
  69                 break;
  70         }
  71
  72         s3c_gpio_lock(ourchip, flags);
  73
  74         con = __raw_readl(regcon);
  75         con &= ~(0xf << con_4bit_shift(offset));
  76         __raw_writel(con, regcon);
  77
  78         s3c_gpio_unlock(ourchip, flags);
  79
  80         return 0;
  81 }
  82
  83 static int s5p64x0_gpiolib_rbank_4bit2_output(struct gpio_chip *chip,
  84                                               unsigned int offset, int value)
  85 {
  86         struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
  87         void __iomem *base = ourchip->base;
  88         void __iomem *regcon = base;
  89         unsigned long con;
  90         unsigned long dat;
  91         unsigned long flags;
  92         unsigned con_offset  = offset;
  93
  94         switch (con_offset) {
  95         case 6:
  96                 con_offset += 1;
  97         case 0:
  98         case 1:
  99         case 2:
 100         case 3:
 101         case 4:
 102         case 5:
 103                 regcon -= 4;
 104                 break;
 105         default:
 106                 con_offset -= 7;
 107                 break;
 108         }
 109
 110         s3c_gpio_lock(ourchip, flags);
 111
 112         con = __raw_readl(regcon);
 113         con &= ~(0xf << con_4bit_shift(con_offset));
 114         con |= 0x1 << con_4bit_shift(con_offset);
 115
 116         dat = __raw_readl(base + GPIODAT_OFF);
 117         if (value)
 118                 dat |= 1 << offset;
 119         else
 120                 dat &= ~(1 << offset);
 121
 122         __raw_writel(con, regcon);
 123         __raw_writel(dat, base + GPIODAT_OFF);
 124
 125         s3c_gpio_unlock(ourchip, flags);
 126
 127         return 0;
 128 }
 129
 130 int s5p64x0_gpio_setcfg_4bit_rbank(struct s3c_gpio_chip *chip,
 131                                    unsigned int off, unsigned int cfg)
 132 {
 133         void __iomem *reg = chip->base;
 134         unsigned int shift;
 135         u32 con;
 136
 137         switch (off) {
 138         case 0:
 139         case 1:
 140         case 2:
 141         case 3:
 142         case 4:
 143         case 5:
 144                 shift = (off & 7) * 4;
 145                 reg -= 4;
 146                 break;
 147         case 6:
 148                 shift = ((off + 1) & 7) * 4;
 149                 reg -= 4;
 150         default:
 151                 shift = ((off + 1) & 7) * 4;
 152                 break;
 153         }
 154
 155         if (s3c_gpio_is_cfg_special(cfg)) {
 156                 cfg &= 0xf;
 157                 cfg <<= shift;
 158         }
 159
 160         con = __raw_readl(reg);
 161         con &= ~(0xf << shift);
 162         con |= cfg;
 163         __raw_writel(con, reg);
 164
 165         return 0;
 166 }
 167
 168 static struct s3c_gpio_cfg s5p64x0_gpio_cfgs[] = {
 169         {
 170                 .cfg_eint       = 0,
 171         }, {
 172                 .cfg_eint       = 7,
 173         }, {
 174                 .cfg_eint       = 3,
 175                 .set_config     = s5p64x0_gpio_setcfg_4bit_rbank,
 176         }, {
 177                 .cfg_eint       = 0,
 178                 .set_config     = s3c_gpio_setcfg_s3c24xx,
 179                 .get_config     = s3c_gpio_getcfg_s3c24xx,
 180         }, {
 181                 .cfg_eint       = 2,
 182                 .set_config     = s3c_gpio_setcfg_s3c24xx,
 183                 .get_config     = s3c_gpio_getcfg_s3c24xx,
 184         }, {
 185                 .cfg_eint       = 3,
 186                 .set_config     = s3c_gpio_setcfg_s3c24xx,
 187                 .get_config     = s3c_gpio_getcfg_s3c24xx,
 188         },
 189 };
 190
 191 static struct s3c_gpio_chip s5p6440_gpio_4bit[] = {
 192         {
 193                 .base   = S5P6440_GPA_BASE,
 194                 .config = &s5p64x0_gpio_cfgs[1],
 195                 .chip   = {
 196                         .base   = S5P6440_GPA(0),
 197                         .ngpio  = S5P6440_GPIO_A_NR,
 198                         .label  = "GPA",
 199                 },
 200         }, {
 201                 .base   = S5P6440_GPB_BASE,
 202                 .config = &s5p64x0_gpio_cfgs[1],
 203                 .chip   = {
 204                         .base   = S5P6440_GPB(0),
 205                         .ngpio  = S5P6440_GPIO_B_NR,
 206                         .label  = "GPB",
 207                 },
 208         }, {
 209                 .base   = S5P6440_GPC_BASE,
 210                 .config = &s5p64x0_gpio_cfgs[1],
 211                 .chip   = {
 212                         .base   = S5P6440_GPC(0),
 213                         .ngpio  = S5P6440_GPIO_C_NR,
 214                         .label  = "GPC",
 215                 },
 216         }, {
 217                 .base   = S5P6440_GPG_BASE,
 218                 .config = &s5p64x0_gpio_cfgs[1],
 219                 .chip   = {
 220                         .base   = S5P6440_GPG(0),
 221                         .ngpio  = S5P6440_GPIO_G_NR,
 222                         .label  = "GPG",
 223                 },
 224         },
 225 };
 226
 227 static struct s3c_gpio_chip s5p6440_gpio_4bit2[] = {
 228         {
 229                 .base   = S5P6440_GPH_BASE + 0x4,
 230                 .config = &s5p64x0_gpio_cfgs[1],
 231                 .chip   = {
 232                         .base   = S5P6440_GPH(0),
 233                         .ngpio  = S5P6440_GPIO_H_NR,
 234                         .label  = "GPH",
 235                 },
 236         },
 237 };
 238
 239 static struct s3c_gpio_chip s5p6440_gpio_rbank_4bit2[] = {
 240         {
 241                 .base   = S5P6440_GPR_BASE + 0x4,
 242                 .config = &s5p64x0_gpio_cfgs[2],
 243                 .chip   = {
 244                         .base   = S5P6440_GPR(0),
 245                         .ngpio  = S5P6440_GPIO_R_NR,
 246                         .label  = "GPR",
 247                 },
 248         },
 249 };
 250
 251 static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
 252         {
 253                 .base   = S5P6440_GPF_BASE,
 254                 .config = &s5p64x0_gpio_cfgs[5],
 255                 .chip   = {
 256                         .base   = S5P6440_GPF(0),
 257                         .ngpio  = S5P6440_GPIO_F_NR,
 258                         .label  = "GPF",
 259                 },
 260         }, {
 261                 .base   = S5P6440_GPI_BASE,
 262                 .config = &s5p64x0_gpio_cfgs[3],
 263                 .chip   = {
 264                         .base   = S5P6440_GPI(0),
 265                         .ngpio  = S5P6440_GPIO_I_NR,
 266                         .label  = "GPI",
 267                 },
 268         }, {
 269                 .base   = S5P6440_GPJ_BASE,
 270                 .config = &s5p64x0_gpio_cfgs[3],
 271                 .chip   = {
 272                         .base   = S5P6440_GPJ(0),
 273                         .ngpio  = S5P6440_GPIO_J_NR,
 274                         .label  = "GPJ",
 275                 },
 276         }, {
 277                 .base   = S5P6440_GPN_BASE,
 278                 .config = &s5p64x0_gpio_cfgs[4],
 279                 .chip   = {
 280                         .base   = S5P6440_GPN(0),
 281                         .ngpio  = S5P6440_GPIO_N_NR,
 282                         .label  = "GPN",
 283                 },
 284         }, {
 285                 .base   = S5P6440_GPP_BASE,
 286                 .config = &s5p64x0_gpio_cfgs[5],
 287                 .chip   = {
 288                         .base   = S5P6440_GPP(0),
 289                         .ngpio  = S5P6440_GPIO_P_NR,
 290                         .label  = "GPP",
 291                 },
 292         },
 293 };
 294
 295 void __init s5p64x0_gpiolib_set_cfg(struct s3c_gpio_cfg *chipcfg, int nr_chips)
 296 {
 297         for (; nr_chips > 0; nr_chips--, chipcfg++) {
 298                 if (!chipcfg->set_config)
 299                         chipcfg->set_config     = s3c_gpio_setcfg_s3c64xx_4bit;
 300                 if (!chipcfg->get_config)
 301                         chipcfg->get_config     = s3c_gpio_getcfg_s3c64xx_4bit;
 302                 if (!chipcfg->set_pull)
 303                         chipcfg->set_pull       = s3c_gpio_setpull_updown;
 304                 if (!chipcfg->get_pull)
 305                         chipcfg->get_pull       = s3c_gpio_getpull_updown;
 306         }
 307 }
 308
 309 static void __init s5p64x0_gpio_add_rbank_4bit2(struct s3c_gpio_chip *chip,
 310                                                 int nr_chips)
 311 {
 312         for (; nr_chips > 0; nr_chips--, chip++) {
 313                 chip->chip.direction_input = s5p64x0_gpiolib_rbank_4bit2_input;
 314                 chip->chip.direction_output =
 315                                         s5p64x0_gpiolib_rbank_4bit2_output;
 316                 s3c_gpiolib_add(chip);
 317         }
 318 }
 319
 320 static int __init s5p6440_gpiolib_init(void)
 321 {
 322         struct s3c_gpio_chip *chips = s5p6440_gpio_2bit;
 323         int nr_chips = ARRAY_SIZE(s5p6440_gpio_2bit);
 324
 325         s5p64x0_gpiolib_set_cfg(s5p64x0_gpio_cfgs,
 326                                 ARRAY_SIZE(s5p64x0_gpio_cfgs));
 327
 328         for (; nr_chips > 0; nr_chips--, chips++)
 329                 s3c_gpiolib_add(chips);
 330
 331         samsung_gpiolib_add_4bit_chips(s5p6440_gpio_4bit,
 332                                 ARRAY_SIZE(s5p6440_gpio_4bit));
 333
 334         samsung_gpiolib_add_4bit2_chips(s5p6440_gpio_4bit2,
 335                                 ARRAY_SIZE(s5p6440_gpio_4bit2));
 336
 337         s5p64x0_gpio_add_rbank_4bit2(s5p6440_gpio_rbank_4bit2,
 338                                 ARRAY_SIZE(s5p6440_gpio_rbank_4bit2));
 339
 340         return 0;
 341 }
 342 arch_initcall(s5p6440_gpiolib_init);