2 * linux/arch/arm/kernel/entry-armv.S
4 * Copyright (C) 1996,1997,1998 Russell King.
5 * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk)
6 * nommu support by Hyok S. Choi (hyok.choi@samsung.com)
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * Low-level vector interface routines
14 * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction
15 * that causes it to save wrong values... Be aware!
18 #include <asm/memory.h>
20 #include <asm/vfpmacros.h>
21 #include <mach/entry-macro.S>
22 #include <asm/thread_notify.h>
23 #include <asm/unwind.h>
24 #include <asm/unistd.h>
27 #include "entry-header.S"
30 * Interrupt handling. Preserves r7, r8, r9
33 get_irqnr_preamble r5, lr
34 1: get_irqnr_and_base r0, r6, r5, lr
37 @ routine called with r0 = irq number, r1 = struct pt_regs *
46 * this macro assumes that irqstat (r6) and base (r5) are
47 * preserved from get_irqnr_and_base above
49 ALT_SMP(test_for_ipi r0, r6, r5, lr)
55 #ifdef CONFIG_LOCAL_TIMERS
56 test_for_ltirq r0, r6, r5, lr
67 .section .kprobes.text,"ax",%progbits
73 * Invalid mode handlers
75 .macro inv_entry, reason
76 sub sp, sp, #S_FRAME_SIZE
77 ARM( stmib sp, {r1 - lr} )
78 THUMB( stmia sp, {r0 - r12} )
79 THUMB( str sp, [sp, #S_SP] )
80 THUMB( str lr, [sp, #S_LR] )
85 inv_entry BAD_PREFETCH
87 ENDPROC(__pabt_invalid)
92 ENDPROC(__dabt_invalid)
97 ENDPROC(__irq_invalid)
100 inv_entry BAD_UNDEFINSTR
103 @ XXX fall through to common_invalid
107 @ common_invalid - generic code for failed exception (re-entrant version of handlers)
113 add r0, sp, #S_PC @ here for interlock avoidance
114 mov r7, #-1 @ "" "" "" ""
115 str r4, [sp] @ save preserved r0
116 stmia r0, {r5 - r7} @ lr_<exception>,
117 @ cpsr_<exception>, "old_r0"
121 ENDPROC(__und_invalid)
127 #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5)
128 #define SPFIX(code...) code
130 #define SPFIX(code...)
133 .macro svc_entry, stack_hole=0
135 UNWIND(.save {r0 - pc} )
136 sub sp, sp, #(S_FRAME_SIZE + \stack_hole - 4)
137 #ifdef CONFIG_THUMB2_KERNEL
138 SPFIX( str r0, [sp] ) @ temporarily saved
140 SPFIX( tst r0, #4 ) @ test original stack alignment
141 SPFIX( ldr r0, [sp] ) @ restored
145 SPFIX( subeq sp, sp, #4 )
149 add r5, sp, #S_SP - 4 @ here for interlock avoidance
150 mov r4, #-1 @ "" "" "" ""
151 add r0, sp, #(S_FRAME_SIZE + \stack_hole - 4)
152 SPFIX( addeq r0, r0, #4 )
153 str r1, [sp, #-4]! @ save the "real" r0 copied
154 @ from the exception stack
159 @ We are now ready to fill in the remaining blanks on the stack:
163 @ r2 - lr_<exception>, already fixed up for correct return/restart
164 @ r3 - spsr_<exception>
165 @ r4 - orig_r0 (see pt_regs definition in ptrace.h)
175 @ get ready to re-enable interrupts if appropriate
179 biceq r9, r9, #PSR_I_BIT
182 @ Call the processor-specific abort handler:
184 @ r2 - aborted context pc
185 @ r3 - aborted context cpsr
187 @ The abort handler must return the aborted address in r0, and
188 @ the fault status register in r1. r9 must be preserved.
193 ldr pc, [r4, #PROCESSOR_DABT_FUNC]
195 bl CPU_DABORT_HANDLER
199 @ set desired IRQ state, then call main handler
206 @ IRQs off again before pulling preserved data off the stack
211 @ restore SPSR and restart the instruction
214 svc_exit r2 @ return from exception
222 #ifdef CONFIG_TRACE_IRQFLAGS
223 bl trace_hardirqs_off
225 #ifdef CONFIG_PREEMPT
227 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
228 add r7, r8, #1 @ increment it
229 str r7, [tsk, #TI_PREEMPT]
233 #ifdef CONFIG_PREEMPT
234 str r8, [tsk, #TI_PREEMPT] @ restore preempt count
235 ldr r0, [tsk, #TI_FLAGS] @ get flags
236 teq r8, #0 @ if preempt count != 0
237 movne r0, #0 @ force flags to 0
238 tst r0, #_TIF_NEED_RESCHED
241 ldr r4, [sp, #S_PSR] @ irqs are already disabled
242 #ifdef CONFIG_TRACE_IRQFLAGS
244 bleq trace_hardirqs_on
246 svc_exit r4 @ return from exception
252 #ifdef CONFIG_PREEMPT
255 1: bl preempt_schedule_irq @ irq en/disable is done inside
256 ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS
257 tst r0, #_TIF_NEED_RESCHED
258 moveq pc, r8 @ go again
264 #ifdef CONFIG_KPROBES
265 @ If a kprobe is about to simulate a "stmdb sp..." instruction,
266 @ it obviously needs free stack space which then will belong to
274 @ call emulation code, which returns using r9 if it has emulated
275 @ the instruction, or the more conventional lr if we are to treat
276 @ this as a real undefined instruction
280 #ifndef CONFIG_THUMB2_KERNEL
283 ldrh r0, [r2, #-2] @ Thumb instruction at LR - 2
285 cmp r9, #0xe800 @ 32-bit instruction if xx >= 0
286 ldrhhs r9, [r2] @ bottom 16 bits
287 orrhs r0, r9, r0, lsl #16
292 mov r0, sp @ struct pt_regs *regs
296 @ IRQs off again before pulling preserved data off the stack
298 1: disable_irq_notrace
301 @ restore SPSR and restart the instruction
303 ldr r2, [sp, #S_PSR] @ Get SVC cpsr
304 svc_exit r2 @ return from exception
313 @ re-enable interrupts if appropriate
317 biceq r9, r9, #PSR_I_BIT
319 mov r0, r2 @ pass address of aborted instruction.
323 ldr pc, [r4, #PROCESSOR_PABT_FUNC]
325 bl CPU_PABORT_HANDLER
327 msr cpsr_c, r9 @ Maybe enable interrupts
329 bl do_PrefetchAbort @ call abort handler
332 @ IRQs off again before pulling preserved data off the stack
337 @ restore SPSR and restart the instruction
340 svc_exit r2 @ return from exception
357 * EABI note: sp_svc is always 64-bit aligned here, so should S_FRAME_SIZE
360 #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (S_FRAME_SIZE & 7)
361 #error "sizeof(struct pt_regs) must be a multiple of 8"
366 UNWIND(.cantunwind ) @ don't unwind the user space
367 sub sp, sp, #S_FRAME_SIZE
368 ARM( stmib sp, {r1 - r12} )
369 THUMB( stmia sp, {r0 - r12} )
372 add r0, sp, #S_PC @ here for interlock avoidance
373 mov r4, #-1 @ "" "" "" ""
375 str r1, [sp] @ save the "real" r0 copied
376 @ from the exception stack
379 @ We are now ready to fill in the remaining blanks on the stack:
381 @ r2 - lr_<exception>, already fixed up for correct return/restart
382 @ r3 - spsr_<exception>
383 @ r4 - orig_r0 (see pt_regs definition in ptrace.h)
385 @ Also, separately save sp_usr and lr_usr
388 ARM( stmdb r0, {sp, lr}^ )
389 THUMB( store_user_sp_lr r0, r1, S_SP - S_PC )
392 @ Enable the alignment trap while in kernel mode
397 @ Clear FP to mark the first stack frame
402 .macro kuser_cmpxchg_check
403 #if __LINUX_ARM_ARCH__ < 6 && !defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
405 #warning "NPTL on non MMU needs fixing"
407 @ Make sure our user space atomic helper is restarted
408 @ if it was interrupted in a critical region. Here we
409 @ perform a quick test inline since it should be false
410 @ 99.9999% of the time. The rest is done out of line.
412 blhs kuser_cmpxchg_fixup
423 @ Call the processor-specific abort handler:
425 @ r2 - aborted context pc
426 @ r3 - aborted context cpsr
428 @ The abort handler must return the aborted address in r0, and
429 @ the fault status register in r1.
434 ldr pc, [r4, #PROCESSOR_DABT_FUNC]
436 bl CPU_DABORT_HANDLER
440 @ IRQs on, then call the main handler
444 adr lr, BSYM(ret_from_exception)
455 #ifdef CONFIG_PREEMPT
456 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
457 add r7, r8, #1 @ increment it
458 str r7, [tsk, #TI_PREEMPT]
462 #ifdef CONFIG_PREEMPT
463 ldr r0, [tsk, #TI_PREEMPT]
464 str r8, [tsk, #TI_PREEMPT]
466 ARM( strne r0, [r0, -r0] )
467 THUMB( movne r0, #0 )
468 THUMB( strne r0, [r0] )
483 @ fall through to the emulation code, which returns using r9 if
484 @ it has emulated the instruction, or the more conventional lr
485 @ if we are to treat this as a real undefined instruction
489 adr r9, BSYM(ret_from_exception)
490 adr lr, BSYM(__und_usr_unknown)
491 tst r3, #PSR_T_BIT @ Thumb mode?
492 itet eq @ explicit IT needed for the 1f label
493 subeq r4, r2, #4 @ ARM instr at LR - 4
494 subne r4, r2, #2 @ Thumb instr at LR - 2
496 #ifdef CONFIG_CPU_ENDIAN_BE8
497 reveq r0, r0 @ little endian instruction
501 #if __LINUX_ARM_ARCH__ >= 7
503 ARM( ldrht r5, [r4], #2 )
504 THUMB( ldrht r5, [r4] )
505 THUMB( add r4, r4, #2 )
506 and r0, r5, #0xf800 @ mask bits 111x x... .... ....
507 cmp r0, #0xe800 @ 32bit instruction if xx != 0
508 blo __und_usr_unknown
510 add r2, r2, #2 @ r2 is PC + 2, make it PC + 4
511 orr r0, r0, r5, lsl #16
519 @ fallthrough to call_fpe
523 * The out of line fixup for the ldrt above.
525 .pushsection .fixup, "ax"
528 .pushsection __ex_table,"a"
530 #if __LINUX_ARM_ARCH__ >= 7
537 * Check whether the instruction is a co-processor instruction.
538 * If yes, we need to call the relevant co-processor handler.
540 * Note that we don't do a full check here for the co-processor
541 * instructions; all instructions with bit 27 set are well
542 * defined. The only instructions that should fault are the
543 * co-processor instructions. However, we have to watch out
544 * for the ARM6/ARM7 SWI bug.
546 * NEON is a special case that has to be handled here. Not all
547 * NEON instructions are co-processor instructions, so we have
548 * to make a special case of checking for them. Plus, there's
549 * five groups of them, so we have a table of mask/opcode pairs
550 * to check against, and if any match then we branch off into the
553 * Emulators may wish to make use of the following registers:
554 * r0 = instruction opcode.
556 * r9 = normal "successful" return address
557 * r10 = this threads thread_info structure.
558 * lr = unrecognised instruction return address
561 @ Fall-through from Thumb-2 __und_usr
564 adr r6, .LCneon_thumb_opcodes
569 adr r6, .LCneon_arm_opcodes
571 ldr r7, [r6], #4 @ mask value
572 cmp r7, #0 @ end mask?
575 ldr r7, [r6], #4 @ opcode bits matching in mask
576 cmp r8, r7 @ NEON instruction?
580 strb r7, [r10, #TI_USED_CP + 10] @ mark CP#10 as used
581 strb r7, [r10, #TI_USED_CP + 11] @ mark CP#11 as used
582 b do_vfp @ let VFP handler handle this
585 tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27
586 tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2
587 #if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710)
588 and r8, r0, #0x0f000000 @ mask out op-code bits
589 teqne r8, #0x0f000000 @ SWI (ARM6/7 bug)?
592 get_thread_info r10 @ get current thread
593 and r8, r0, #0x00000f00 @ mask out CP number
594 THUMB( lsr r8, r8, #8 )
596 add r6, r10, #TI_USED_CP
597 ARM( strb r7, [r6, r8, lsr #8] ) @ set appropriate used_cp[]
598 THUMB( strb r7, [r6, r8] ) @ set appropriate used_cp[]
600 @ Test if we need to give access to iWMMXt coprocessors
601 ldr r5, [r10, #TI_FLAGS]
602 rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only
603 movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1)
604 bcs iwmmxt_task_enable
606 ARM( add pc, pc, r8, lsr #6 )
607 THUMB( lsl r8, r8, #2 )
612 W(b) do_fpe @ CP#1 (FPE)
613 W(b) do_fpe @ CP#2 (FPE)
616 b crunch_task_enable @ CP#4 (MaverickCrunch)
617 b crunch_task_enable @ CP#5 (MaverickCrunch)
618 b crunch_task_enable @ CP#6 (MaverickCrunch)
628 W(b) do_vfp @ CP#10 (VFP)
629 W(b) do_vfp @ CP#11 (VFP)
631 movw_pc lr @ CP#10 (VFP)
632 movw_pc lr @ CP#11 (VFP)
636 movw_pc lr @ CP#14 (Debug)
637 movw_pc lr @ CP#15 (Control)
643 .word 0xfe000000 @ mask
644 .word 0xf2000000 @ opcode
646 .word 0xff100000 @ mask
647 .word 0xf4000000 @ opcode
649 .word 0x00000000 @ mask
650 .word 0x00000000 @ opcode
652 .LCneon_thumb_opcodes:
653 .word 0xef000000 @ mask
654 .word 0xef000000 @ opcode
656 .word 0xff100000 @ mask
657 .word 0xf9000000 @ opcode
659 .word 0x00000000 @ mask
660 .word 0x00000000 @ opcode
666 add r10, r10, #TI_FPSTATE @ r10 = workspace
667 ldr pc, [r4] @ Call FP module USR entry point
670 * The FP module is called with these registers set:
673 * r9 = normal "successful" return address
675 * lr = unrecognised FP instruction return address
690 adr lr, BSYM(ret_from_exception)
692 ENDPROC(__und_usr_unknown)
698 mov r0, r2 @ pass address of aborted instruction.
702 ldr pc, [r4, #PROCESSOR_PABT_FUNC]
704 bl CPU_PABORT_HANDLER
706 enable_irq @ Enable interrupts
708 bl do_PrefetchAbort @ call abort handler
712 * This is the return code to user mode for abort handlers
714 ENTRY(ret_from_exception)
722 ENDPROC(ret_from_exception)
725 * Register switch for ARMv3 and ARMv4 processors
726 * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info
727 * previous and next are guaranteed not to be the same.
732 add ip, r1, #TI_CPU_SAVE
733 ldr r3, [r2, #TI_TP_VALUE]
734 ARM( stmia ip!, {r4 - sl, fp, sp, lr} ) @ Store most regs on stack
735 THUMB( stmia ip!, {r4 - sl, fp} ) @ Store most regs on stack
736 THUMB( str sp, [ip], #4 )
737 THUMB( str lr, [ip], #4 )
739 ldr r6, [r2, #TI_CPU_DOMAIN]
742 #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
743 ldr r7, [r2, #TI_TASK]
744 ldr r8, =__stack_chk_guard
745 ldr r7, [r7, #TSK_STACK_CANARY]
748 mcr p15, 0, r6, c3, c0, 0 @ Set domain register
751 add r4, r2, #TI_CPU_SAVE
752 ldr r0, =thread_notify_head
753 mov r1, #THREAD_NOTIFY_SWITCH
754 bl atomic_notifier_call_chain
755 #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
760 ARM( ldmia r4, {r4 - sl, fp, sp, pc} ) @ Load all regs saved previously
761 THUMB( ldmia ip!, {r4 - sl, fp} ) @ Load all regs saved previously
762 THUMB( ldr sp, [ip], #4 )
763 THUMB( ldr pc, [ip] )
772 * These are segment of kernel provided user code reachable from user space
773 * at a fixed address in kernel memory. This is used to provide user space
774 * with some operations which require kernel help because of unimplemented
775 * native feature and/or instructions in many ARM CPUs. The idea is for
776 * this code to be executed directly in user mode for best efficiency but
777 * which is too intimate with the kernel counter part to be left to user
778 * libraries. In fact this code might even differ from one CPU to another
779 * depending on the available instruction set and restrictions like on
780 * SMP systems. In other words, the kernel reserves the right to change
781 * this code as needed without warning. Only the entry points and their
782 * results are guaranteed to be stable.
784 * Each segment is 32-byte aligned and will be moved to the top of the high
785 * vector page. New segments (if ever needed) must be added in front of
786 * existing ones. This mechanism should be used only for things that are
787 * really small and justified, and not be abused freely.
789 * User space is expected to implement those things inline when optimizing
790 * for a processor that has the necessary native support, but only if such
791 * resulting binaries are already to be incompatible with earlier ARM
792 * processors due to the use of unsupported instructions other than what
793 * is provided here. In other words don't make binaries unable to run on
794 * earlier processors just for the sake of not using these kernel helpers
795 * if your compiled code is not going to use the new instructions for other
801 #ifdef CONFIG_ARM_THUMB
809 .globl __kuser_helper_start
810 __kuser_helper_start:
813 * Reference prototype:
815 * void __kernel_memory_barrier(void)
819 * lr = return address
829 * Definition and user space usage example:
831 * typedef void (__kernel_dmb_t)(void);
832 * #define __kernel_dmb (*(__kernel_dmb_t *)0xffff0fa0)
834 * Apply any needed memory barrier to preserve consistency with data modified
835 * manually and __kuser_cmpxchg usage.
837 * This could be used as follows:
839 * #define __kernel_dmb() \
840 * asm volatile ( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #95" \
841 * : : : "r0", "lr","cc" )
844 __kuser_memory_barrier: @ 0xffff0fa0
851 * Reference prototype:
853 * int __kernel_cmpxchg(int oldval, int newval, int *ptr)
860 * lr = return address
864 * r0 = returned value (zero or non-zero)
865 * C flag = set if r0 == 0, clear if r0 != 0
871 * Definition and user space usage example:
873 * typedef int (__kernel_cmpxchg_t)(int oldval, int newval, int *ptr);
874 * #define __kernel_cmpxchg (*(__kernel_cmpxchg_t *)0xffff0fc0)
876 * Atomically store newval in *ptr if *ptr is equal to oldval for user space.
877 * Return zero if *ptr was changed or non-zero if no exchange happened.
878 * The C flag is also set if *ptr was changed to allow for assembly
879 * optimization in the calling code.
883 * - This routine already includes memory barriers as needed.
885 * For example, a user space atomic_add implementation could look like this:
887 * #define atomic_add(ptr, val) \
888 * ({ register unsigned int *__ptr asm("r2") = (ptr); \
889 * register unsigned int __result asm("r1"); \
891 * "1: @ atomic_add\n\t" \
892 * "ldr r0, [r2]\n\t" \
893 * "mov r3, #0xffff0fff\n\t" \
894 * "add lr, pc, #4\n\t" \
895 * "add r1, r0, %2\n\t" \
896 * "add pc, r3, #(0xffff0fc0 - 0xffff0fff)\n\t" \
898 * : "=&r" (__result) \
899 * : "r" (__ptr), "rIL" (val) \
900 * : "r0","r3","ip","lr","cc","memory" ); \
904 __kuser_cmpxchg: @ 0xffff0fc0
906 #if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
909 * Poor you. No fast solution possible...
910 * The kernel itself must perform the operation.
911 * A special ghost syscall is used for that (see traps.c).
914 ldr r7, =1f @ it's 20 bits
917 1: .word __ARM_NR_cmpxchg
919 #elif __LINUX_ARM_ARCH__ < 6
924 * The only thing that can break atomicity in this cmpxchg
925 * implementation is either an IRQ or a data abort exception
926 * causing another process/thread to be scheduled in the middle
927 * of the critical sequence. To prevent this, code is added to
928 * the IRQ and data abort exception handlers to set the pc back
929 * to the beginning of the critical section if it is found to be
930 * within that critical section (see kuser_cmpxchg_fixup).
932 1: ldr r3, [r2] @ load current val
933 subs r3, r3, r0 @ compare with oldval
934 2: streq r1, [r2] @ store newval if eq
935 rsbs r0, r3, #0 @ set return val and C flag
940 @ Called from kuser_cmpxchg_check macro.
941 @ r2 = address of interrupted insn (must be preserved).
942 @ sp = saved regs. r7 and r8 are clobbered.
943 @ 1b = first critical insn, 2b = last critical insn.
944 @ If r2 >= 1b and r2 <= 2b then saved pc_usr is set to 1b.
946 sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg)))
948 rsbcss r8, r8, #(2b - 1b)
949 strcs r7, [sp, #S_PC]
954 #warning "NPTL on non MMU needs fixing"
969 /* beware -- each __kuser slot must be 8 instructions max */
970 ALT_SMP(b __kuser_memory_barrier)
978 * Reference prototype:
980 * int __kernel_get_tls(void)
984 * lr = return address
994 * Definition and user space usage example:
996 * typedef int (__kernel_get_tls_t)(void);
997 * #define __kernel_get_tls (*(__kernel_get_tls_t *)0xffff0fe0)
999 * Get the TLS value as previously set via the __ARM_NR_set_tls syscall.
1001 * This could be used as follows:
1003 * #define __kernel_get_tls() \
1004 * ({ register unsigned int __val asm("r0"); \
1005 * asm( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #31" \
1006 * : "=r" (__val) : : "lr","cc" ); \
1010 __kuser_get_tls: @ 0xffff0fe0
1011 ldr r0, [pc, #(16 - 8)] @ read TLS, set in kuser_get_tls_init
1013 mrc p15, 0, r0, c13, c0, 3 @ 0xffff0fe8 hardware TLS code
1015 .word 0 @ 0xffff0ff0 software TLS value, then
1016 .endr @ pad up to __kuser_helper_version
1019 * Reference declaration:
1021 * extern unsigned int __kernel_helper_version;
1023 * Definition and user space usage example:
1025 * #define __kernel_helper_version (*(unsigned int *)0xffff0ffc)
1027 * User space may read this to determine the curent number of helpers
1031 __kuser_helper_version: @ 0xffff0ffc
1032 .word ((__kuser_helper_end - __kuser_helper_start) >> 5)
1034 .globl __kuser_helper_end
1042 * This code is copied to 0xffff0200 so we can use branches in the
1043 * vectors, rather than ldr's. Note that this code must not
1044 * exceed 0x300 bytes.
1046 * Common stub entry macro:
1047 * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
1049 * SP points to a minimal amount of processor-private memory, the address
1050 * of which is copied into r0 for the mode specific abort handler.
1052 .macro vector_stub, name, mode, correction=0
1057 sub lr, lr, #\correction
1061 @ Save r0, lr_<exception> (parent PC) and spsr_<exception>
1064 stmia sp, {r0, lr} @ save r0, lr
1066 str lr, [sp, #8] @ save spsr
1069 @ Prepare for SVC32 mode. IRQs remain disabled.
1072 eor r0, r0, #(\mode ^ SVC_MODE | PSR_ISETSTATE)
1076 @ the branch table must immediately follow this code
1080 THUMB( ldr lr, [r0, lr, lsl #2] )
1082 ARM( ldr lr, [pc, lr, lsl #2] )
1083 movs pc, lr @ branch to handler in SVC mode
1084 ENDPROC(vector_\name)
1087 @ handler addresses follow this label
1091 .globl __stubs_start
1094 * Interrupt dispatcher
1096 vector_stub irq, IRQ_MODE, 4
1098 .long __irq_usr @ 0 (USR_26 / USR_32)
1099 .long __irq_invalid @ 1 (FIQ_26 / FIQ_32)
1100 .long __irq_invalid @ 2 (IRQ_26 / IRQ_32)
1101 .long __irq_svc @ 3 (SVC_26 / SVC_32)
1102 .long __irq_invalid @ 4
1103 .long __irq_invalid @ 5
1104 .long __irq_invalid @ 6
1105 .long __irq_invalid @ 7
1106 .long __irq_invalid @ 8
1107 .long __irq_invalid @ 9
1108 .long __irq_invalid @ a
1109 .long __irq_invalid @ b
1110 .long __irq_invalid @ c
1111 .long __irq_invalid @ d
1112 .long __irq_invalid @ e
1113 .long __irq_invalid @ f
1116 * Data abort dispatcher
1117 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
1119 vector_stub dabt, ABT_MODE, 8
1121 .long __dabt_usr @ 0 (USR_26 / USR_32)
1122 .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32)
1123 .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32)
1124 .long __dabt_svc @ 3 (SVC_26 / SVC_32)
1125 .long __dabt_invalid @ 4
1126 .long __dabt_invalid @ 5
1127 .long __dabt_invalid @ 6
1128 .long __dabt_invalid @ 7
1129 .long __dabt_invalid @ 8
1130 .long __dabt_invalid @ 9
1131 .long __dabt_invalid @ a
1132 .long __dabt_invalid @ b
1133 .long __dabt_invalid @ c
1134 .long __dabt_invalid @ d
1135 .long __dabt_invalid @ e
1136 .long __dabt_invalid @ f
1139 * Prefetch abort dispatcher
1140 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
1142 vector_stub pabt, ABT_MODE, 4
1144 .long __pabt_usr @ 0 (USR_26 / USR_32)
1145 .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32)
1146 .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32)
1147 .long __pabt_svc @ 3 (SVC_26 / SVC_32)
1148 .long __pabt_invalid @ 4
1149 .long __pabt_invalid @ 5
1150 .long __pabt_invalid @ 6
1151 .long __pabt_invalid @ 7
1152 .long __pabt_invalid @ 8
1153 .long __pabt_invalid @ 9
1154 .long __pabt_invalid @ a
1155 .long __pabt_invalid @ b
1156 .long __pabt_invalid @ c
1157 .long __pabt_invalid @ d
1158 .long __pabt_invalid @ e
1159 .long __pabt_invalid @ f
1162 * Undef instr entry dispatcher
1163 * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
1165 vector_stub und, UND_MODE
1167 .long __und_usr @ 0 (USR_26 / USR_32)
1168 .long __und_invalid @ 1 (FIQ_26 / FIQ_32)
1169 .long __und_invalid @ 2 (IRQ_26 / IRQ_32)
1170 .long __und_svc @ 3 (SVC_26 / SVC_32)
1171 .long __und_invalid @ 4
1172 .long __und_invalid @ 5
1173 .long __und_invalid @ 6
1174 .long __und_invalid @ 7
1175 .long __und_invalid @ 8
1176 .long __und_invalid @ 9
1177 .long __und_invalid @ a
1178 .long __und_invalid @ b
1179 .long __und_invalid @ c
1180 .long __und_invalid @ d
1181 .long __und_invalid @ e
1182 .long __und_invalid @ f
1186 /*=============================================================================
1188 *-----------------------------------------------------------------------------
1189 * Enter in FIQ mode, spsr = ANY CPSR, lr = ANY PC
1190 * MUST PRESERVE SVC SPSR, but need to switch to SVC mode to show our msg.
1191 * Basically to switch modes, we *HAVE* to clobber one register... brain
1192 * damage alert! I don't think that we can execute any code in here in any
1193 * other mode than FIQ... Ok you can switch to another mode, but you can't
1194 * get out of that mode without clobbering one register.
1200 /*=============================================================================
1201 * Address exception handler
1202 *-----------------------------------------------------------------------------
1203 * These aren't too critical.
1204 * (they're not supposed to happen, and won't happen in 32-bit data mode).
1211 * We group all the following data together to optimise
1212 * for CPUs with separate I & D caches.
1222 .equ stubs_offset, __vectors_start + 0x200 - __stubs_start
1224 .globl __vectors_start
1226 ARM( swi SYS_ERROR0 )
1229 W(b) vector_und + stubs_offset
1230 W(ldr) pc, .LCvswi + stubs_offset
1231 W(b) vector_pabt + stubs_offset
1232 W(b) vector_dabt + stubs_offset
1233 W(b) vector_addrexcptn + stubs_offset
1234 W(b) vector_irq + stubs_offset
1235 W(b) vector_fiq + stubs_offset
1237 .globl __vectors_end
1243 .globl cr_no_alignment