2 * Intel GTT (Graphics Translation Table) routines
4 * Caveat: This driver implements the linux agp interface, but this is far from
5 * a agp driver! GTT support ended up here for purely historical reasons: The
6 * old userspace intel graphics drivers needed an interface to map memory into
7 * the GTT. And the drm provides a default interface for graphic devices sitting
8 * on an agp port. So it made sense to fake the GTT support as an agp port to
9 * avoid having to create a new api.
11 * With gem this does not make much sense anymore, just needlessly complicates
12 * the code. But as long as the old graphics stack is still support, it's stuck
15 * /fairy-tale-mode off
18 #include <linux/module.h>
19 #include <linux/pci.h>
20 #include <linux/init.h>
21 #include <linux/kernel.h>
22 #include <linux/pagemap.h>
23 #include <linux/agp_backend.h>
26 #include "intel-agp.h"
27 #include <linux/intel-gtt.h>
28 #include <drm/intel-gtt.h>
31 * If we have Intel graphics, we're not going to have anything other than
32 * an Intel IOMMU. So make the correct use of the PCI DMA API contingent
33 * on the Intel IOMMU support (CONFIG_DMAR).
34 * Only newer chipsets need to bother with this, of course.
37 #define USE_PCI_DMA_API 1
40 /* Max amount of stolen space, anything above will be returned to Linux */
41 int intel_max_stolen
= 32 * 1024 * 1024;
42 EXPORT_SYMBOL(intel_max_stolen
);
44 static const struct aper_size_info_fixed intel_i810_sizes
[] =
47 /* The 32M mode still requires a 64k gatt */
51 #define AGP_DCACHE_MEMORY 1
52 #define AGP_PHYS_MEMORY 2
53 #define INTEL_AGP_CACHED_MEMORY 3
55 static struct gatt_mask intel_i810_masks
[] =
57 {.mask
= I810_PTE_VALID
, .type
= 0},
58 {.mask
= (I810_PTE_VALID
| I810_PTE_LOCAL
), .type
= AGP_DCACHE_MEMORY
},
59 {.mask
= I810_PTE_VALID
, .type
= 0},
60 {.mask
= I810_PTE_VALID
| I830_PTE_SYSTEM_CACHED
,
61 .type
= INTEL_AGP_CACHED_MEMORY
}
64 #define INTEL_AGP_UNCACHED_MEMORY 0
65 #define INTEL_AGP_CACHED_MEMORY_LLC 1
66 #define INTEL_AGP_CACHED_MEMORY_LLC_GFDT 2
67 #define INTEL_AGP_CACHED_MEMORY_LLC_MLC 3
68 #define INTEL_AGP_CACHED_MEMORY_LLC_MLC_GFDT 4
70 static struct gatt_mask intel_gen6_masks
[] =
72 {.mask
= I810_PTE_VALID
| GEN6_PTE_UNCACHED
,
73 .type
= INTEL_AGP_UNCACHED_MEMORY
},
74 {.mask
= I810_PTE_VALID
| GEN6_PTE_LLC
,
75 .type
= INTEL_AGP_CACHED_MEMORY_LLC
},
76 {.mask
= I810_PTE_VALID
| GEN6_PTE_LLC
| GEN6_PTE_GFDT
,
77 .type
= INTEL_AGP_CACHED_MEMORY_LLC_GFDT
},
78 {.mask
= I810_PTE_VALID
| GEN6_PTE_LLC_MLC
,
79 .type
= INTEL_AGP_CACHED_MEMORY_LLC_MLC
},
80 {.mask
= I810_PTE_VALID
| GEN6_PTE_LLC_MLC
| GEN6_PTE_GFDT
,
81 .type
= INTEL_AGP_CACHED_MEMORY_LLC_MLC_GFDT
},
84 struct intel_gtt_driver
{
86 unsigned int is_g33
: 1;
87 unsigned int is_pineview
: 1;
88 unsigned int is_ironlake
: 1;
89 /* Chipset specific GTT setup */
93 static struct _intel_private
{
94 struct intel_gtt base
;
95 const struct intel_gtt_driver
*driver
;
96 struct pci_dev
*pcidev
; /* device one */
97 struct pci_dev
*bridge_dev
;
98 u8 __iomem
*registers
;
99 phys_addr_t gtt_bus_addr
;
100 phys_addr_t gma_bus_addr
;
101 u32 __iomem
*gtt
; /* I915G */
102 int num_dcache_entries
;
104 void __iomem
*i9xx_flush_page
;
105 void *i8xx_flush_page
;
107 struct page
*i8xx_page
;
108 struct resource ifp_resource
;
112 #define INTEL_GTT_GEN intel_private.driver->gen
113 #define IS_G33 intel_private.driver->is_g33
114 #define IS_PINEVIEW intel_private.driver->is_pineview
115 #define IS_IRONLAKE intel_private.driver->is_ironlake
117 #ifdef USE_PCI_DMA_API
118 static int intel_agp_map_page(struct page
*page
, dma_addr_t
*ret
)
120 *ret
= pci_map_page(intel_private
.pcidev
, page
, 0,
121 PAGE_SIZE
, PCI_DMA_BIDIRECTIONAL
);
122 if (pci_dma_mapping_error(intel_private
.pcidev
, *ret
))
127 static void intel_agp_unmap_page(struct page
*page
, dma_addr_t dma
)
129 pci_unmap_page(intel_private
.pcidev
, dma
,
130 PAGE_SIZE
, PCI_DMA_BIDIRECTIONAL
);
133 static void intel_agp_free_sglist(struct agp_memory
*mem
)
137 st
.sgl
= mem
->sg_list
;
138 st
.orig_nents
= st
.nents
= mem
->page_count
;
146 static int intel_agp_map_memory(struct agp_memory
*mem
)
149 struct scatterlist
*sg
;
152 DBG("try mapping %lu pages\n", (unsigned long)mem
->page_count
);
154 if (sg_alloc_table(&st
, mem
->page_count
, GFP_KERNEL
))
157 mem
->sg_list
= sg
= st
.sgl
;
159 for (i
= 0 ; i
< mem
->page_count
; i
++, sg
= sg_next(sg
))
160 sg_set_page(sg
, mem
->pages
[i
], PAGE_SIZE
, 0);
162 mem
->num_sg
= pci_map_sg(intel_private
.pcidev
, mem
->sg_list
,
163 mem
->page_count
, PCI_DMA_BIDIRECTIONAL
);
164 if (unlikely(!mem
->num_sg
))
174 static void intel_agp_unmap_memory(struct agp_memory
*mem
)
176 DBG("try unmapping %lu pages\n", (unsigned long)mem
->page_count
);
178 pci_unmap_sg(intel_private
.pcidev
, mem
->sg_list
,
179 mem
->page_count
, PCI_DMA_BIDIRECTIONAL
);
180 intel_agp_free_sglist(mem
);
183 static void intel_agp_insert_sg_entries(struct agp_memory
*mem
,
184 off_t pg_start
, int mask_type
)
186 struct scatterlist
*sg
;
191 WARN_ON(!mem
->num_sg
);
193 if (mem
->num_sg
== mem
->page_count
) {
194 for_each_sg(mem
->sg_list
, sg
, mem
->page_count
, i
) {
195 writel(agp_bridge
->driver
->mask_memory(agp_bridge
,
196 sg_dma_address(sg
), mask_type
),
197 intel_private
.gtt
+j
);
201 /* sg may merge pages, but we have to separate
202 * per-page addr for GTT */
205 for_each_sg(mem
->sg_list
, sg
, mem
->num_sg
, i
) {
206 len
= sg_dma_len(sg
) / PAGE_SIZE
;
207 for (m
= 0; m
< len
; m
++) {
208 writel(agp_bridge
->driver
->mask_memory(agp_bridge
,
209 sg_dma_address(sg
) + m
* PAGE_SIZE
,
211 intel_private
.gtt
+j
);
216 readl(intel_private
.gtt
+j
-1);
221 static void intel_agp_insert_sg_entries(struct agp_memory
*mem
,
222 off_t pg_start
, int mask_type
)
226 for (i
= 0, j
= pg_start
; i
< mem
->page_count
; i
++, j
++) {
227 writel(agp_bridge
->driver
->mask_memory(agp_bridge
,
228 page_to_phys(mem
->pages
[i
]), mask_type
),
229 intel_private
.gtt
+j
);
232 readl(intel_private
.gtt
+j
-1);
237 static int intel_i810_fetch_size(void)
240 struct aper_size_info_fixed
*values
;
242 pci_read_config_dword(intel_private
.bridge_dev
,
243 I810_SMRAM_MISCC
, &smram_miscc
);
244 values
= A_SIZE_FIX(agp_bridge
->driver
->aperture_sizes
);
246 if ((smram_miscc
& I810_GMS
) == I810_GMS_DISABLE
) {
247 dev_warn(&intel_private
.bridge_dev
->dev
, "i810 is disabled\n");
250 if ((smram_miscc
& I810_GFX_MEM_WIN_SIZE
) == I810_GFX_MEM_WIN_32M
) {
251 agp_bridge
->current_size
= (void *) (values
+ 1);
252 agp_bridge
->aperture_size_idx
= 1;
253 return values
[1].size
;
255 agp_bridge
->current_size
= (void *) (values
);
256 agp_bridge
->aperture_size_idx
= 0;
257 return values
[0].size
;
263 static int intel_i810_configure(void)
265 struct aper_size_info_fixed
*current_size
;
269 current_size
= A_SIZE_FIX(agp_bridge
->current_size
);
271 if (!intel_private
.registers
) {
272 pci_read_config_dword(intel_private
.pcidev
, I810_MMADDR
, &temp
);
275 intel_private
.registers
= ioremap(temp
, 128 * 4096);
276 if (!intel_private
.registers
) {
277 dev_err(&intel_private
.pcidev
->dev
,
278 "can't remap memory\n");
283 if ((readl(intel_private
.registers
+I810_DRAM_CTL
)
284 & I810_DRAM_ROW_0
) == I810_DRAM_ROW_0_SDRAM
) {
285 /* This will need to be dynamically assigned */
286 dev_info(&intel_private
.pcidev
->dev
,
287 "detected 4MB dedicated video ram\n");
288 intel_private
.num_dcache_entries
= 1024;
290 pci_read_config_dword(intel_private
.pcidev
, I810_GMADDR
, &temp
);
291 agp_bridge
->gart_bus_addr
= (temp
& PCI_BASE_ADDRESS_MEM_MASK
);
292 writel(agp_bridge
->gatt_bus_addr
| I810_PGETBL_ENABLED
, intel_private
.registers
+I810_PGETBL_CTL
);
293 readl(intel_private
.registers
+I810_PGETBL_CTL
); /* PCI Posting. */
295 if (agp_bridge
->driver
->needs_scratch_page
) {
296 for (i
= 0; i
< current_size
->num_entries
; i
++) {
297 writel(agp_bridge
->scratch_page
, intel_private
.registers
+I810_PTE_BASE
+(i
*4));
299 readl(intel_private
.registers
+I810_PTE_BASE
+((i
-1)*4)); /* PCI posting. */
301 global_cache_flush();
305 static void intel_i810_cleanup(void)
307 writel(0, intel_private
.registers
+I810_PGETBL_CTL
);
308 readl(intel_private
.registers
); /* PCI Posting. */
309 iounmap(intel_private
.registers
);
312 static void intel_fake_agp_enable(struct agp_bridge_data
*bridge
, u32 mode
)
317 /* Exists to support ARGB cursors */
318 static struct page
*i8xx_alloc_pages(void)
322 page
= alloc_pages(GFP_KERNEL
| GFP_DMA32
, 2);
326 if (set_pages_uc(page
, 4) < 0) {
327 set_pages_wb(page
, 4);
328 __free_pages(page
, 2);
332 atomic_inc(&agp_bridge
->current_memory_agp
);
336 static void i8xx_destroy_pages(struct page
*page
)
341 set_pages_wb(page
, 4);
343 __free_pages(page
, 2);
344 atomic_dec(&agp_bridge
->current_memory_agp
);
347 static int intel_i830_type_to_mask_type(struct agp_bridge_data
*bridge
,
350 if (type
< AGP_USER_TYPES
)
352 else if (type
== AGP_USER_CACHED_MEMORY
)
353 return INTEL_AGP_CACHED_MEMORY
;
358 static int intel_gen6_type_to_mask_type(struct agp_bridge_data
*bridge
,
361 unsigned int type_mask
= type
& ~AGP_USER_CACHED_MEMORY_GFDT
;
362 unsigned int gfdt
= type
& AGP_USER_CACHED_MEMORY_GFDT
;
364 if (type_mask
== AGP_USER_UNCACHED_MEMORY
)
365 return INTEL_AGP_UNCACHED_MEMORY
;
366 else if (type_mask
== AGP_USER_CACHED_MEMORY_LLC_MLC
)
367 return gfdt
? INTEL_AGP_CACHED_MEMORY_LLC_MLC_GFDT
:
368 INTEL_AGP_CACHED_MEMORY_LLC_MLC
;
369 else /* set 'normal'/'cached' to LLC by default */
370 return gfdt
? INTEL_AGP_CACHED_MEMORY_LLC_GFDT
:
371 INTEL_AGP_CACHED_MEMORY_LLC
;
375 static int intel_i810_insert_entries(struct agp_memory
*mem
, off_t pg_start
,
378 int i
, j
, num_entries
;
383 if (mem
->page_count
== 0)
386 temp
= agp_bridge
->current_size
;
387 num_entries
= A_SIZE_FIX(temp
)->num_entries
;
389 if ((pg_start
+ mem
->page_count
) > num_entries
)
393 for (j
= pg_start
; j
< (pg_start
+ mem
->page_count
); j
++) {
394 if (!PGE_EMPTY(agp_bridge
, readl(agp_bridge
->gatt_table
+j
))) {
400 if (type
!= mem
->type
)
403 mask_type
= agp_bridge
->driver
->agp_type_to_mask_type(agp_bridge
, type
);
406 case AGP_DCACHE_MEMORY
:
407 if (!mem
->is_flushed
)
408 global_cache_flush();
409 for (i
= pg_start
; i
< (pg_start
+ mem
->page_count
); i
++) {
410 writel((i
*4096)|I810_PTE_LOCAL
|I810_PTE_VALID
,
411 intel_private
.registers
+I810_PTE_BASE
+(i
*4));
413 readl(intel_private
.registers
+I810_PTE_BASE
+((i
-1)*4));
415 case AGP_PHYS_MEMORY
:
416 case AGP_NORMAL_MEMORY
:
417 if (!mem
->is_flushed
)
418 global_cache_flush();
419 for (i
= 0, j
= pg_start
; i
< mem
->page_count
; i
++, j
++) {
420 writel(agp_bridge
->driver
->mask_memory(agp_bridge
,
421 page_to_phys(mem
->pages
[i
]), mask_type
),
422 intel_private
.registers
+I810_PTE_BASE
+(j
*4));
424 readl(intel_private
.registers
+I810_PTE_BASE
+((j
-1)*4));
433 mem
->is_flushed
= true;
437 static int intel_i810_remove_entries(struct agp_memory
*mem
, off_t pg_start
,
442 if (mem
->page_count
== 0)
445 for (i
= pg_start
; i
< (mem
->page_count
+ pg_start
); i
++) {
446 writel(agp_bridge
->scratch_page
, intel_private
.registers
+I810_PTE_BASE
+(i
*4));
448 readl(intel_private
.registers
+I810_PTE_BASE
+((i
-1)*4));
454 * The i810/i830 requires a physical address to program its mouse
455 * pointer into hardware.
456 * However the Xserver still writes to it through the agp aperture.
458 static struct agp_memory
*alloc_agpphysmem_i8xx(size_t pg_count
, int type
)
460 struct agp_memory
*new;
464 case 1: page
= agp_bridge
->driver
->agp_alloc_page(agp_bridge
);
467 /* kludge to get 4 physical pages for ARGB cursor */
468 page
= i8xx_alloc_pages();
477 new = agp_create_memory(pg_count
);
481 new->pages
[0] = page
;
483 /* kludge to get 4 physical pages for ARGB cursor */
484 new->pages
[1] = new->pages
[0] + 1;
485 new->pages
[2] = new->pages
[1] + 1;
486 new->pages
[3] = new->pages
[2] + 1;
488 new->page_count
= pg_count
;
489 new->num_scratch_pages
= pg_count
;
490 new->type
= AGP_PHYS_MEMORY
;
491 new->physical
= page_to_phys(new->pages
[0]);
495 static struct agp_memory
*intel_i810_alloc_by_type(size_t pg_count
, int type
)
497 struct agp_memory
*new;
499 if (type
== AGP_DCACHE_MEMORY
) {
500 if (pg_count
!= intel_private
.num_dcache_entries
)
503 new = agp_create_memory(1);
507 new->type
= AGP_DCACHE_MEMORY
;
508 new->page_count
= pg_count
;
509 new->num_scratch_pages
= 0;
510 agp_free_page_array(new);
513 if (type
== AGP_PHYS_MEMORY
)
514 return alloc_agpphysmem_i8xx(pg_count
, type
);
518 static void intel_i810_free_by_type(struct agp_memory
*curr
)
520 agp_free_key(curr
->key
);
521 if (curr
->type
== AGP_PHYS_MEMORY
) {
522 if (curr
->page_count
== 4)
523 i8xx_destroy_pages(curr
->pages
[0]);
525 agp_bridge
->driver
->agp_destroy_page(curr
->pages
[0],
526 AGP_PAGE_DESTROY_UNMAP
);
527 agp_bridge
->driver
->agp_destroy_page(curr
->pages
[0],
528 AGP_PAGE_DESTROY_FREE
);
530 agp_free_page_array(curr
);
535 static unsigned long intel_i810_mask_memory(struct agp_bridge_data
*bridge
,
536 dma_addr_t addr
, int type
)
538 /* Type checking must be done elsewhere */
539 return addr
| bridge
->driver
->masks
[type
].mask
;
542 static struct aper_size_info_fixed intel_fake_agp_sizes
[] =
545 /* The 64M mode still requires a 128k gatt */
551 static unsigned int intel_gtt_stolen_entries(void)
556 static const int ddt
[4] = { 0, 16, 32, 64 };
557 unsigned int overhead_entries
, stolen_entries
;
558 unsigned int stolen_size
= 0;
560 pci_read_config_word(intel_private
.bridge_dev
,
561 I830_GMCH_CTRL
, &gmch_ctrl
);
563 if (INTEL_GTT_GEN
> 4 || IS_PINEVIEW
)
564 overhead_entries
= 0;
566 overhead_entries
= intel_private
.base
.gtt_mappable_entries
569 overhead_entries
+= 1; /* BIOS popup */
571 if (intel_private
.bridge_dev
->device
== PCI_DEVICE_ID_INTEL_82830_HB
||
572 intel_private
.bridge_dev
->device
== PCI_DEVICE_ID_INTEL_82845G_HB
) {
573 switch (gmch_ctrl
& I830_GMCH_GMS_MASK
) {
574 case I830_GMCH_GMS_STOLEN_512
:
575 stolen_size
= KB(512);
577 case I830_GMCH_GMS_STOLEN_1024
:
580 case I830_GMCH_GMS_STOLEN_8192
:
583 case I830_GMCH_GMS_LOCAL
:
584 rdct
= readb(intel_private
.registers
+I830_RDRAM_CHANNEL_TYPE
);
585 stolen_size
= (I830_RDRAM_ND(rdct
) + 1) *
586 MB(ddt
[I830_RDRAM_DDT(rdct
)]);
593 } else if (INTEL_GTT_GEN
== 6) {
595 * SandyBridge has new memory control reg at 0x50.w
598 pci_read_config_word(intel_private
.pcidev
, SNB_GMCH_CTRL
, &snb_gmch_ctl
);
599 switch (snb_gmch_ctl
& SNB_GMCH_GMS_STOLEN_MASK
) {
600 case SNB_GMCH_GMS_STOLEN_32M
:
601 stolen_size
= MB(32);
603 case SNB_GMCH_GMS_STOLEN_64M
:
604 stolen_size
= MB(64);
606 case SNB_GMCH_GMS_STOLEN_96M
:
607 stolen_size
= MB(96);
609 case SNB_GMCH_GMS_STOLEN_128M
:
610 stolen_size
= MB(128);
612 case SNB_GMCH_GMS_STOLEN_160M
:
613 stolen_size
= MB(160);
615 case SNB_GMCH_GMS_STOLEN_192M
:
616 stolen_size
= MB(192);
618 case SNB_GMCH_GMS_STOLEN_224M
:
619 stolen_size
= MB(224);
621 case SNB_GMCH_GMS_STOLEN_256M
:
622 stolen_size
= MB(256);
624 case SNB_GMCH_GMS_STOLEN_288M
:
625 stolen_size
= MB(288);
627 case SNB_GMCH_GMS_STOLEN_320M
:
628 stolen_size
= MB(320);
630 case SNB_GMCH_GMS_STOLEN_352M
:
631 stolen_size
= MB(352);
633 case SNB_GMCH_GMS_STOLEN_384M
:
634 stolen_size
= MB(384);
636 case SNB_GMCH_GMS_STOLEN_416M
:
637 stolen_size
= MB(416);
639 case SNB_GMCH_GMS_STOLEN_448M
:
640 stolen_size
= MB(448);
642 case SNB_GMCH_GMS_STOLEN_480M
:
643 stolen_size
= MB(480);
645 case SNB_GMCH_GMS_STOLEN_512M
:
646 stolen_size
= MB(512);
650 switch (gmch_ctrl
& I855_GMCH_GMS_MASK
) {
651 case I855_GMCH_GMS_STOLEN_1M
:
654 case I855_GMCH_GMS_STOLEN_4M
:
657 case I855_GMCH_GMS_STOLEN_8M
:
660 case I855_GMCH_GMS_STOLEN_16M
:
661 stolen_size
= MB(16);
663 case I855_GMCH_GMS_STOLEN_32M
:
664 stolen_size
= MB(32);
666 case I915_GMCH_GMS_STOLEN_48M
:
667 stolen_size
= MB(48);
669 case I915_GMCH_GMS_STOLEN_64M
:
670 stolen_size
= MB(64);
672 case G33_GMCH_GMS_STOLEN_128M
:
673 stolen_size
= MB(128);
675 case G33_GMCH_GMS_STOLEN_256M
:
676 stolen_size
= MB(256);
678 case INTEL_GMCH_GMS_STOLEN_96M
:
679 stolen_size
= MB(96);
681 case INTEL_GMCH_GMS_STOLEN_160M
:
682 stolen_size
= MB(160);
684 case INTEL_GMCH_GMS_STOLEN_224M
:
685 stolen_size
= MB(224);
687 case INTEL_GMCH_GMS_STOLEN_352M
:
688 stolen_size
= MB(352);
696 if (!local
&& stolen_size
> intel_max_stolen
) {
697 dev_info(&intel_private
.bridge_dev
->dev
,
698 "detected %dK stolen memory, trimming to %dK\n",
699 stolen_size
/ KB(1), intel_max_stolen
/ KB(1));
700 stolen_size
= intel_max_stolen
;
701 } else if (stolen_size
> 0) {
702 dev_info(&intel_private
.bridge_dev
->dev
, "detected %dK %s memory\n",
703 stolen_size
/ KB(1), local
? "local" : "stolen");
705 dev_info(&intel_private
.bridge_dev
->dev
,
706 "no pre-allocated video memory detected\n");
710 stolen_entries
= stolen_size
/KB(4) - overhead_entries
;
712 return stolen_entries
;
715 static unsigned int intel_gtt_total_entries(void)
719 if (IS_G33
|| INTEL_GTT_GEN
== 4 || INTEL_GTT_GEN
== 5) {
721 pgetbl_ctl
= readl(intel_private
.registers
+I810_PGETBL_CTL
);
723 switch (pgetbl_ctl
& I965_PGETBL_SIZE_MASK
) {
724 case I965_PGETBL_SIZE_128KB
:
727 case I965_PGETBL_SIZE_256KB
:
730 case I965_PGETBL_SIZE_512KB
:
733 case I965_PGETBL_SIZE_1MB
:
736 case I965_PGETBL_SIZE_2MB
:
739 case I965_PGETBL_SIZE_1_5MB
:
740 size
= KB(1024 + 512);
743 dev_info(&intel_private
.pcidev
->dev
,
744 "unknown page table size, assuming 512KB\n");
749 } else if (INTEL_GTT_GEN
== 6) {
752 pci_read_config_word(intel_private
.pcidev
, SNB_GMCH_CTRL
, &snb_gmch_ctl
);
753 switch (snb_gmch_ctl
& SNB_GTT_SIZE_MASK
) {
755 case SNB_GTT_SIZE_0M
:
756 printk(KERN_ERR
"Bad GTT size mask: 0x%04x.\n", snb_gmch_ctl
);
759 case SNB_GTT_SIZE_1M
:
762 case SNB_GTT_SIZE_2M
:
768 /* On previous hardware, the GTT size was just what was
769 * required to map the aperture.
771 return intel_private
.base
.gtt_mappable_entries
;
775 static unsigned int intel_gtt_mappable_entries(void)
777 unsigned int aperture_size
;
780 aperture_size
= 1024 * 1024;
782 pci_read_config_word(intel_private
.bridge_dev
,
783 I830_GMCH_CTRL
, &gmch_ctrl
);
785 if (INTEL_GTT_GEN
== 2) {
786 if ((gmch_ctrl
& I830_GMCH_MEM_MASK
) == I830_GMCH_MEM_64M
)
789 aperture_size
*= 128;
791 /* 9xx supports large sizes, just look at the length */
792 aperture_size
= pci_resource_len(intel_private
.pcidev
, 2);
795 return aperture_size
>> PAGE_SHIFT
;
798 static int intel_gtt_init(void)
803 intel_private
.base
.gtt_mappable_entries
= intel_gtt_mappable_entries();
805 ret
= intel_private
.driver
->setup();
809 intel_private
.base
.gtt_mappable_entries
= intel_gtt_mappable_entries();
810 intel_private
.base
.gtt_total_entries
= intel_gtt_total_entries();
812 gtt_map_size
= intel_private
.base
.gtt_total_entries
* 4;
814 intel_private
.gtt
= ioremap(intel_private
.gtt_bus_addr
,
816 if (!intel_private
.gtt
) {
817 iounmap(intel_private
.registers
);
821 global_cache_flush(); /* FIXME: ? */
823 /* we have to call this as early as possible after the MMIO base address is known */
824 intel_private
.base
.gtt_stolen_entries
= intel_gtt_stolen_entries();
825 if (intel_private
.base
.gtt_stolen_entries
== 0) {
826 iounmap(intel_private
.registers
);
827 iounmap(intel_private
.gtt
);
834 static int intel_fake_agp_fetch_size(void)
836 unsigned int aper_size
;
838 int num_sizes
= ARRAY_SIZE(intel_fake_agp_sizes
);
840 aper_size
= (intel_private
.base
.gtt_mappable_entries
<< PAGE_SHIFT
)
843 for (i
= 0; i
< num_sizes
; i
++) {
844 if (aper_size
== intel_fake_agp_sizes
[i
].size
) {
845 agp_bridge
->current_size
= intel_fake_agp_sizes
+ i
;
853 static void intel_i830_fini_flush(void)
855 kunmap(intel_private
.i8xx_page
);
856 intel_private
.i8xx_flush_page
= NULL
;
857 unmap_page_from_agp(intel_private
.i8xx_page
);
859 __free_page(intel_private
.i8xx_page
);
860 intel_private
.i8xx_page
= NULL
;
863 static void intel_i830_setup_flush(void)
865 /* return if we've already set the flush mechanism up */
866 if (intel_private
.i8xx_page
)
869 intel_private
.i8xx_page
= alloc_page(GFP_KERNEL
| __GFP_ZERO
| GFP_DMA32
);
870 if (!intel_private
.i8xx_page
)
873 intel_private
.i8xx_flush_page
= kmap(intel_private
.i8xx_page
);
874 if (!intel_private
.i8xx_flush_page
)
875 intel_i830_fini_flush();
878 /* The chipset_flush interface needs to get data that has already been
879 * flushed out of the CPU all the way out to main memory, because the GPU
880 * doesn't snoop those buffers.
882 * The 8xx series doesn't have the same lovely interface for flushing the
883 * chipset write buffers that the later chips do. According to the 865
884 * specs, it's 64 octwords, or 1KB. So, to get those previous things in
885 * that buffer out, we just fill 1KB and clflush it out, on the assumption
886 * that it'll push whatever was in there out. It appears to work.
888 static void intel_i830_chipset_flush(struct agp_bridge_data
*bridge
)
890 unsigned int *pg
= intel_private
.i8xx_flush_page
;
895 clflush_cache_range(pg
, 1024);
896 else if (wbinvd_on_all_cpus() != 0)
897 printk(KERN_ERR
"Timed out waiting for cache flush.\n");
900 static void intel_enable_gtt(void)
902 u32 ptetbl_addr
, gma_addr
;
905 ptetbl_addr
= readl(intel_private
.registers
+I810_PGETBL_CTL
) & 0xfffff000;
907 if (INTEL_GTT_GEN
== 2)
908 pci_read_config_dword(intel_private
.pcidev
, I810_GMADDR
,
911 pci_read_config_dword(intel_private
.pcidev
, I915_GMADDR
,
914 intel_private
.gma_bus_addr
= (gma_addr
& PCI_BASE_ADDRESS_MEM_MASK
);
916 pci_read_config_word(intel_private
.bridge_dev
, I830_GMCH_CTRL
, &gmch_ctrl
);
917 gmch_ctrl
|= I830_GMCH_ENABLED
;
918 pci_write_config_word(intel_private
.bridge_dev
, I830_GMCH_CTRL
, gmch_ctrl
);
920 writel(ptetbl_addr
|I810_PGETBL_ENABLED
, intel_private
.registers
+I810_PGETBL_CTL
);
921 readl(intel_private
.registers
+I810_PGETBL_CTL
); /* PCI Posting. */
924 static int i830_setup(void)
928 pci_read_config_dword(intel_private
.pcidev
, I810_MMADDR
, ®_addr
);
929 reg_addr
&= 0xfff80000;
931 intel_private
.registers
= ioremap(reg_addr
, KB(64));
932 if (!intel_private
.registers
)
935 intel_private
.gtt_bus_addr
= reg_addr
+ I810_PTE_BASE
;
937 intel_i830_setup_flush();
942 static int intel_fake_agp_create_gatt_table(struct agp_bridge_data
*bridge
)
944 agp_bridge
->gatt_table_real
= NULL
;
945 agp_bridge
->gatt_table
= NULL
;
946 agp_bridge
->gatt_bus_addr
= 0;
951 static int intel_fake_agp_free_gatt_table(struct agp_bridge_data
*bridge
)
956 static int intel_i830_configure(void)
962 agp_bridge
->gart_bus_addr
= intel_private
.gma_bus_addr
;
964 if (agp_bridge
->driver
->needs_scratch_page
) {
965 for (i
= intel_private
.base
.gtt_stolen_entries
;
966 i
< intel_private
.base
.gtt_total_entries
; i
++) {
967 writel(agp_bridge
->scratch_page
, intel_private
.gtt
+i
);
969 readl(intel_private
.gtt
+i
-1); /* PCI Posting. */
972 global_cache_flush();
977 static int intel_i830_insert_entries(struct agp_memory
*mem
, off_t pg_start
,
980 int i
, j
, num_entries
;
985 if (mem
->page_count
== 0)
988 temp
= agp_bridge
->current_size
;
989 num_entries
= A_SIZE_FIX(temp
)->num_entries
;
991 if (pg_start
< intel_private
.base
.gtt_stolen_entries
) {
992 dev_printk(KERN_DEBUG
, &intel_private
.pcidev
->dev
,
993 "pg_start == 0x%.8lx, gtt_stolen_entries == 0x%.8x\n",
994 pg_start
, intel_private
.base
.gtt_stolen_entries
);
996 dev_info(&intel_private
.pcidev
->dev
,
997 "trying to insert into local/stolen memory\n");
1001 if ((pg_start
+ mem
->page_count
) > num_entries
)
1004 /* The i830 can't check the GTT for entries since its read only,
1005 * depend on the caller to make the correct offset decisions.
1008 if (type
!= mem
->type
)
1011 mask_type
= agp_bridge
->driver
->agp_type_to_mask_type(agp_bridge
, type
);
1013 if (mask_type
!= 0 && mask_type
!= AGP_PHYS_MEMORY
&&
1014 mask_type
!= INTEL_AGP_CACHED_MEMORY
)
1017 if (!mem
->is_flushed
)
1018 global_cache_flush();
1020 for (i
= 0, j
= pg_start
; i
< mem
->page_count
; i
++, j
++) {
1021 writel(agp_bridge
->driver
->mask_memory(agp_bridge
,
1022 page_to_phys(mem
->pages
[i
]), mask_type
),
1023 intel_private
.gtt
+j
);
1025 readl(intel_private
.gtt
+j
-1);
1030 mem
->is_flushed
= true;
1034 static int intel_i830_remove_entries(struct agp_memory
*mem
, off_t pg_start
,
1039 if (mem
->page_count
== 0)
1042 if (pg_start
< intel_private
.base
.gtt_stolen_entries
) {
1043 dev_info(&intel_private
.pcidev
->dev
,
1044 "trying to disable local/stolen memory\n");
1048 for (i
= pg_start
; i
< (mem
->page_count
+ pg_start
); i
++) {
1049 writel(agp_bridge
->scratch_page
, intel_private
.gtt
+i
);
1051 readl(intel_private
.gtt
+i
-1);
1056 static struct agp_memory
*intel_fake_agp_alloc_by_type(size_t pg_count
,
1059 if (type
== AGP_PHYS_MEMORY
)
1060 return alloc_agpphysmem_i8xx(pg_count
, type
);
1061 /* always return NULL for other allocation types for now */
1065 static int intel_alloc_chipset_flush_resource(void)
1068 ret
= pci_bus_alloc_resource(intel_private
.bridge_dev
->bus
, &intel_private
.ifp_resource
, PAGE_SIZE
,
1069 PAGE_SIZE
, PCIBIOS_MIN_MEM
, 0,
1070 pcibios_align_resource
, intel_private
.bridge_dev
);
1075 static void intel_i915_setup_chipset_flush(void)
1080 pci_read_config_dword(intel_private
.bridge_dev
, I915_IFPADDR
, &temp
);
1081 if (!(temp
& 0x1)) {
1082 intel_alloc_chipset_flush_resource();
1083 intel_private
.resource_valid
= 1;
1084 pci_write_config_dword(intel_private
.bridge_dev
, I915_IFPADDR
, (intel_private
.ifp_resource
.start
& 0xffffffff) | 0x1);
1088 intel_private
.resource_valid
= 1;
1089 intel_private
.ifp_resource
.start
= temp
;
1090 intel_private
.ifp_resource
.end
= temp
+ PAGE_SIZE
;
1091 ret
= request_resource(&iomem_resource
, &intel_private
.ifp_resource
);
1092 /* some BIOSes reserve this area in a pnp some don't */
1094 intel_private
.resource_valid
= 0;
1098 static void intel_i965_g33_setup_chipset_flush(void)
1100 u32 temp_hi
, temp_lo
;
1103 pci_read_config_dword(intel_private
.bridge_dev
, I965_IFPADDR
+ 4, &temp_hi
);
1104 pci_read_config_dword(intel_private
.bridge_dev
, I965_IFPADDR
, &temp_lo
);
1106 if (!(temp_lo
& 0x1)) {
1108 intel_alloc_chipset_flush_resource();
1110 intel_private
.resource_valid
= 1;
1111 pci_write_config_dword(intel_private
.bridge_dev
, I965_IFPADDR
+ 4,
1112 upper_32_bits(intel_private
.ifp_resource
.start
));
1113 pci_write_config_dword(intel_private
.bridge_dev
, I965_IFPADDR
, (intel_private
.ifp_resource
.start
& 0xffffffff) | 0x1);
1118 l64
= ((u64
)temp_hi
<< 32) | temp_lo
;
1120 intel_private
.resource_valid
= 1;
1121 intel_private
.ifp_resource
.start
= l64
;
1122 intel_private
.ifp_resource
.end
= l64
+ PAGE_SIZE
;
1123 ret
= request_resource(&iomem_resource
, &intel_private
.ifp_resource
);
1124 /* some BIOSes reserve this area in a pnp some don't */
1126 intel_private
.resource_valid
= 0;
1130 static void intel_i9xx_setup_flush(void)
1132 /* return if already configured */
1133 if (intel_private
.ifp_resource
.start
)
1136 if (INTEL_GTT_GEN
== 6)
1139 /* setup a resource for this object */
1140 intel_private
.ifp_resource
.name
= "Intel Flush Page";
1141 intel_private
.ifp_resource
.flags
= IORESOURCE_MEM
;
1143 /* Setup chipset flush for 915 */
1144 if (IS_G33
|| INTEL_GTT_GEN
>= 4) {
1145 intel_i965_g33_setup_chipset_flush();
1147 intel_i915_setup_chipset_flush();
1150 if (intel_private
.ifp_resource
.start
)
1151 intel_private
.i9xx_flush_page
= ioremap_nocache(intel_private
.ifp_resource
.start
, PAGE_SIZE
);
1152 if (!intel_private
.i9xx_flush_page
)
1153 dev_err(&intel_private
.pcidev
->dev
,
1154 "can't ioremap flush page - no chipset flushing\n");
1157 static int intel_i9xx_configure(void)
1163 agp_bridge
->gart_bus_addr
= intel_private
.gma_bus_addr
;
1165 if (agp_bridge
->driver
->needs_scratch_page
) {
1166 for (i
= intel_private
.base
.gtt_stolen_entries
; i
<
1167 intel_private
.base
.gtt_total_entries
; i
++) {
1168 writel(agp_bridge
->scratch_page
, intel_private
.gtt
+i
);
1170 readl(intel_private
.gtt
+i
-1); /* PCI Posting. */
1173 global_cache_flush();
1178 static void intel_gtt_cleanup(void)
1180 if (intel_private
.i9xx_flush_page
)
1181 iounmap(intel_private
.i9xx_flush_page
);
1182 if (intel_private
.resource_valid
)
1183 release_resource(&intel_private
.ifp_resource
);
1184 intel_private
.ifp_resource
.start
= 0;
1185 intel_private
.resource_valid
= 0;
1186 iounmap(intel_private
.gtt
);
1187 iounmap(intel_private
.registers
);
1190 static void intel_i915_chipset_flush(struct agp_bridge_data
*bridge
)
1192 if (intel_private
.i9xx_flush_page
)
1193 writel(1, intel_private
.i9xx_flush_page
);
1196 static int intel_i915_insert_entries(struct agp_memory
*mem
, off_t pg_start
,
1204 if (mem
->page_count
== 0)
1207 temp
= agp_bridge
->current_size
;
1208 num_entries
= A_SIZE_FIX(temp
)->num_entries
;
1210 if (pg_start
< intel_private
.base
.gtt_stolen_entries
) {
1211 dev_printk(KERN_DEBUG
, &intel_private
.pcidev
->dev
,
1212 "pg_start == 0x%.8lx, gtt_stolen_entries == 0x%.8x\n",
1213 pg_start
, intel_private
.base
.gtt_stolen_entries
);
1215 dev_info(&intel_private
.pcidev
->dev
,
1216 "trying to insert into local/stolen memory\n");
1220 if ((pg_start
+ mem
->page_count
) > num_entries
)
1223 /* The i915 can't check the GTT for entries since it's read only;
1224 * depend on the caller to make the correct offset decisions.
1227 if (type
!= mem
->type
)
1230 mask_type
= agp_bridge
->driver
->agp_type_to_mask_type(agp_bridge
, type
);
1232 if (INTEL_GTT_GEN
!= 6 && mask_type
!= 0 &&
1233 mask_type
!= AGP_PHYS_MEMORY
&&
1234 mask_type
!= INTEL_AGP_CACHED_MEMORY
)
1237 if (!mem
->is_flushed
)
1238 global_cache_flush();
1240 intel_agp_insert_sg_entries(mem
, pg_start
, mask_type
);
1245 mem
->is_flushed
= true;
1249 static int intel_i915_remove_entries(struct agp_memory
*mem
, off_t pg_start
,
1254 if (mem
->page_count
== 0)
1257 if (pg_start
< intel_private
.base
.gtt_stolen_entries
) {
1258 dev_info(&intel_private
.pcidev
->dev
,
1259 "trying to disable local/stolen memory\n");
1263 for (i
= pg_start
; i
< (mem
->page_count
+ pg_start
); i
++)
1264 writel(agp_bridge
->scratch_page
, intel_private
.gtt
+i
);
1266 readl(intel_private
.gtt
+i
-1);
1271 static int i9xx_setup(void)
1275 pci_read_config_dword(intel_private
.pcidev
, I915_MMADDR
, ®_addr
);
1277 reg_addr
&= 0xfff80000;
1279 intel_private
.registers
= ioremap(reg_addr
, 128 * 4096);
1280 if (!intel_private
.registers
)
1283 if (INTEL_GTT_GEN
== 3) {
1285 pci_read_config_dword(intel_private
.pcidev
,
1286 I915_PTEADDR
, >t_addr
);
1287 intel_private
.gtt_bus_addr
= gtt_addr
;
1291 switch (INTEL_GTT_GEN
) {
1298 gtt_offset
= KB(512);
1301 intel_private
.gtt_bus_addr
= reg_addr
+ gtt_offset
;
1304 intel_i9xx_setup_flush();
1310 * The i965 supports 36-bit physical addresses, but to keep
1311 * the format of the GTT the same, the bits that don't fit
1312 * in a 32-bit word are shifted down to bits 4..7.
1314 * Gcc is smart enough to notice that "(addr >> 28) & 0xf0"
1315 * is always zero on 32-bit architectures, so no need to make
1318 static unsigned long intel_i965_mask_memory(struct agp_bridge_data
*bridge
,
1319 dma_addr_t addr
, int type
)
1321 /* Shift high bits down */
1322 addr
|= (addr
>> 28) & 0xf0;
1324 /* Type checking must be done elsewhere */
1325 return addr
| bridge
->driver
->masks
[type
].mask
;
1328 static unsigned long intel_gen6_mask_memory(struct agp_bridge_data
*bridge
,
1329 dma_addr_t addr
, int type
)
1331 /* gen6 has bit11-4 for physical addr bit39-32 */
1332 addr
|= (addr
>> 28) & 0xff0;
1334 /* Type checking must be done elsewhere */
1335 return addr
| bridge
->driver
->masks
[type
].mask
;
1338 static const struct agp_bridge_driver intel_810_driver
= {
1339 .owner
= THIS_MODULE
,
1340 .aperture_sizes
= intel_i810_sizes
,
1341 .size_type
= FIXED_APER_SIZE
,
1342 .num_aperture_sizes
= 2,
1343 .needs_scratch_page
= true,
1344 .configure
= intel_i810_configure
,
1345 .fetch_size
= intel_i810_fetch_size
,
1346 .cleanup
= intel_i810_cleanup
,
1347 .mask_memory
= intel_i810_mask_memory
,
1348 .masks
= intel_i810_masks
,
1349 .agp_enable
= intel_fake_agp_enable
,
1350 .cache_flush
= global_cache_flush
,
1351 .create_gatt_table
= agp_generic_create_gatt_table
,
1352 .free_gatt_table
= agp_generic_free_gatt_table
,
1353 .insert_memory
= intel_i810_insert_entries
,
1354 .remove_memory
= intel_i810_remove_entries
,
1355 .alloc_by_type
= intel_i810_alloc_by_type
,
1356 .free_by_type
= intel_i810_free_by_type
,
1357 .agp_alloc_page
= agp_generic_alloc_page
,
1358 .agp_alloc_pages
= agp_generic_alloc_pages
,
1359 .agp_destroy_page
= agp_generic_destroy_page
,
1360 .agp_destroy_pages
= agp_generic_destroy_pages
,
1361 .agp_type_to_mask_type
= agp_generic_type_to_mask_type
,
1364 static const struct agp_bridge_driver intel_830_driver
= {
1365 .owner
= THIS_MODULE
,
1366 .aperture_sizes
= intel_fake_agp_sizes
,
1367 .size_type
= FIXED_APER_SIZE
,
1368 .num_aperture_sizes
= 4,
1369 .needs_scratch_page
= true,
1370 .configure
= intel_i830_configure
,
1371 .fetch_size
= intel_fake_agp_fetch_size
,
1372 .cleanup
= intel_gtt_cleanup
,
1373 .mask_memory
= intel_i810_mask_memory
,
1374 .masks
= intel_i810_masks
,
1375 .agp_enable
= intel_fake_agp_enable
,
1376 .cache_flush
= global_cache_flush
,
1377 .create_gatt_table
= intel_fake_agp_create_gatt_table
,
1378 .free_gatt_table
= intel_fake_agp_free_gatt_table
,
1379 .insert_memory
= intel_i830_insert_entries
,
1380 .remove_memory
= intel_i830_remove_entries
,
1381 .alloc_by_type
= intel_fake_agp_alloc_by_type
,
1382 .free_by_type
= intel_i810_free_by_type
,
1383 .agp_alloc_page
= agp_generic_alloc_page
,
1384 .agp_alloc_pages
= agp_generic_alloc_pages
,
1385 .agp_destroy_page
= agp_generic_destroy_page
,
1386 .agp_destroy_pages
= agp_generic_destroy_pages
,
1387 .agp_type_to_mask_type
= intel_i830_type_to_mask_type
,
1388 .chipset_flush
= intel_i830_chipset_flush
,
1391 static const struct agp_bridge_driver intel_915_driver
= {
1392 .owner
= THIS_MODULE
,
1393 .aperture_sizes
= intel_fake_agp_sizes
,
1394 .size_type
= FIXED_APER_SIZE
,
1395 .num_aperture_sizes
= 4,
1396 .needs_scratch_page
= true,
1397 .configure
= intel_i9xx_configure
,
1398 .fetch_size
= intel_fake_agp_fetch_size
,
1399 .cleanup
= intel_gtt_cleanup
,
1400 .mask_memory
= intel_i810_mask_memory
,
1401 .masks
= intel_i810_masks
,
1402 .agp_enable
= intel_fake_agp_enable
,
1403 .cache_flush
= global_cache_flush
,
1404 .create_gatt_table
= intel_fake_agp_create_gatt_table
,
1405 .free_gatt_table
= intel_fake_agp_free_gatt_table
,
1406 .insert_memory
= intel_i915_insert_entries
,
1407 .remove_memory
= intel_i915_remove_entries
,
1408 .alloc_by_type
= intel_fake_agp_alloc_by_type
,
1409 .free_by_type
= intel_i810_free_by_type
,
1410 .agp_alloc_page
= agp_generic_alloc_page
,
1411 .agp_alloc_pages
= agp_generic_alloc_pages
,
1412 .agp_destroy_page
= agp_generic_destroy_page
,
1413 .agp_destroy_pages
= agp_generic_destroy_pages
,
1414 .agp_type_to_mask_type
= intel_i830_type_to_mask_type
,
1415 .chipset_flush
= intel_i915_chipset_flush
,
1416 #ifdef USE_PCI_DMA_API
1417 .agp_map_page
= intel_agp_map_page
,
1418 .agp_unmap_page
= intel_agp_unmap_page
,
1419 .agp_map_memory
= intel_agp_map_memory
,
1420 .agp_unmap_memory
= intel_agp_unmap_memory
,
1424 static const struct agp_bridge_driver intel_i965_driver
= {
1425 .owner
= THIS_MODULE
,
1426 .aperture_sizes
= intel_fake_agp_sizes
,
1427 .size_type
= FIXED_APER_SIZE
,
1428 .num_aperture_sizes
= 4,
1429 .needs_scratch_page
= true,
1430 .configure
= intel_i9xx_configure
,
1431 .fetch_size
= intel_fake_agp_fetch_size
,
1432 .cleanup
= intel_gtt_cleanup
,
1433 .mask_memory
= intel_i965_mask_memory
,
1434 .masks
= intel_i810_masks
,
1435 .agp_enable
= intel_fake_agp_enable
,
1436 .cache_flush
= global_cache_flush
,
1437 .create_gatt_table
= intel_fake_agp_create_gatt_table
,
1438 .free_gatt_table
= intel_fake_agp_free_gatt_table
,
1439 .insert_memory
= intel_i915_insert_entries
,
1440 .remove_memory
= intel_i915_remove_entries
,
1441 .alloc_by_type
= intel_fake_agp_alloc_by_type
,
1442 .free_by_type
= intel_i810_free_by_type
,
1443 .agp_alloc_page
= agp_generic_alloc_page
,
1444 .agp_alloc_pages
= agp_generic_alloc_pages
,
1445 .agp_destroy_page
= agp_generic_destroy_page
,
1446 .agp_destroy_pages
= agp_generic_destroy_pages
,
1447 .agp_type_to_mask_type
= intel_i830_type_to_mask_type
,
1448 .chipset_flush
= intel_i915_chipset_flush
,
1449 #ifdef USE_PCI_DMA_API
1450 .agp_map_page
= intel_agp_map_page
,
1451 .agp_unmap_page
= intel_agp_unmap_page
,
1452 .agp_map_memory
= intel_agp_map_memory
,
1453 .agp_unmap_memory
= intel_agp_unmap_memory
,
1457 static const struct agp_bridge_driver intel_gen6_driver
= {
1458 .owner
= THIS_MODULE
,
1459 .aperture_sizes
= intel_fake_agp_sizes
,
1460 .size_type
= FIXED_APER_SIZE
,
1461 .num_aperture_sizes
= 4,
1462 .needs_scratch_page
= true,
1463 .configure
= intel_i9xx_configure
,
1464 .fetch_size
= intel_fake_agp_fetch_size
,
1465 .cleanup
= intel_gtt_cleanup
,
1466 .mask_memory
= intel_gen6_mask_memory
,
1467 .masks
= intel_gen6_masks
,
1468 .agp_enable
= intel_fake_agp_enable
,
1469 .cache_flush
= global_cache_flush
,
1470 .create_gatt_table
= intel_fake_agp_create_gatt_table
,
1471 .free_gatt_table
= intel_fake_agp_free_gatt_table
,
1472 .insert_memory
= intel_i915_insert_entries
,
1473 .remove_memory
= intel_i915_remove_entries
,
1474 .alloc_by_type
= intel_fake_agp_alloc_by_type
,
1475 .free_by_type
= intel_i810_free_by_type
,
1476 .agp_alloc_page
= agp_generic_alloc_page
,
1477 .agp_alloc_pages
= agp_generic_alloc_pages
,
1478 .agp_destroy_page
= agp_generic_destroy_page
,
1479 .agp_destroy_pages
= agp_generic_destroy_pages
,
1480 .agp_type_to_mask_type
= intel_gen6_type_to_mask_type
,
1481 .chipset_flush
= intel_i915_chipset_flush
,
1482 #ifdef USE_PCI_DMA_API
1483 .agp_map_page
= intel_agp_map_page
,
1484 .agp_unmap_page
= intel_agp_unmap_page
,
1485 .agp_map_memory
= intel_agp_map_memory
,
1486 .agp_unmap_memory
= intel_agp_unmap_memory
,
1490 static const struct agp_bridge_driver intel_g33_driver
= {
1491 .owner
= THIS_MODULE
,
1492 .aperture_sizes
= intel_fake_agp_sizes
,
1493 .size_type
= FIXED_APER_SIZE
,
1494 .num_aperture_sizes
= 4,
1495 .needs_scratch_page
= true,
1496 .configure
= intel_i9xx_configure
,
1497 .fetch_size
= intel_fake_agp_fetch_size
,
1498 .cleanup
= intel_gtt_cleanup
,
1499 .mask_memory
= intel_i965_mask_memory
,
1500 .masks
= intel_i810_masks
,
1501 .agp_enable
= intel_fake_agp_enable
,
1502 .cache_flush
= global_cache_flush
,
1503 .create_gatt_table
= intel_fake_agp_create_gatt_table
,
1504 .free_gatt_table
= intel_fake_agp_free_gatt_table
,
1505 .insert_memory
= intel_i915_insert_entries
,
1506 .remove_memory
= intel_i915_remove_entries
,
1507 .alloc_by_type
= intel_fake_agp_alloc_by_type
,
1508 .free_by_type
= intel_i810_free_by_type
,
1509 .agp_alloc_page
= agp_generic_alloc_page
,
1510 .agp_alloc_pages
= agp_generic_alloc_pages
,
1511 .agp_destroy_page
= agp_generic_destroy_page
,
1512 .agp_destroy_pages
= agp_generic_destroy_pages
,
1513 .agp_type_to_mask_type
= intel_i830_type_to_mask_type
,
1514 .chipset_flush
= intel_i915_chipset_flush
,
1515 #ifdef USE_PCI_DMA_API
1516 .agp_map_page
= intel_agp_map_page
,
1517 .agp_unmap_page
= intel_agp_unmap_page
,
1518 .agp_map_memory
= intel_agp_map_memory
,
1519 .agp_unmap_memory
= intel_agp_unmap_memory
,
1523 static const struct intel_gtt_driver i8xx_gtt_driver
= {
1525 .setup
= i830_setup
,
1527 static const struct intel_gtt_driver i915_gtt_driver
= {
1529 .setup
= i9xx_setup
,
1531 static const struct intel_gtt_driver g33_gtt_driver
= {
1534 .setup
= i9xx_setup
,
1536 static const struct intel_gtt_driver pineview_gtt_driver
= {
1538 .is_pineview
= 1, .is_g33
= 1,
1539 .setup
= i9xx_setup
,
1541 static const struct intel_gtt_driver i965_gtt_driver
= {
1543 .setup
= i9xx_setup
,
1545 static const struct intel_gtt_driver g4x_gtt_driver
= {
1547 .setup
= i9xx_setup
,
1549 static const struct intel_gtt_driver ironlake_gtt_driver
= {
1552 .setup
= i9xx_setup
,
1554 static const struct intel_gtt_driver sandybridge_gtt_driver
= {
1556 .setup
= i9xx_setup
,
1559 /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of
1560 * driver and gmch_driver must be non-null, and find_gmch will determine
1561 * which one should be used if a gmch_chip_id is present.
1563 static const struct intel_gtt_driver_description
{
1564 unsigned int gmch_chip_id
;
1566 const struct agp_bridge_driver
*gmch_driver
;
1567 const struct intel_gtt_driver
*gtt_driver
;
1568 } intel_gtt_chipsets
[] = {
1569 { PCI_DEVICE_ID_INTEL_82810_IG1
, "i810", &intel_810_driver
, NULL
},
1570 { PCI_DEVICE_ID_INTEL_82810_IG3
, "i810", &intel_810_driver
, NULL
},
1571 { PCI_DEVICE_ID_INTEL_82810E_IG
, "i810", &intel_810_driver
, NULL
},
1572 { PCI_DEVICE_ID_INTEL_82815_CGC
, "i815", &intel_810_driver
, NULL
},
1573 { PCI_DEVICE_ID_INTEL_82830_CGC
, "830M",
1574 &intel_830_driver
, &i8xx_gtt_driver
},
1575 { PCI_DEVICE_ID_INTEL_82845G_IG
, "830M",
1576 &intel_830_driver
, &i8xx_gtt_driver
},
1577 { PCI_DEVICE_ID_INTEL_82854_IG
, "854",
1578 &intel_830_driver
, &i8xx_gtt_driver
},
1579 { PCI_DEVICE_ID_INTEL_82855GM_IG
, "855GM",
1580 &intel_830_driver
, &i8xx_gtt_driver
},
1581 { PCI_DEVICE_ID_INTEL_82865_IG
, "865",
1582 &intel_830_driver
, &i8xx_gtt_driver
},
1583 { PCI_DEVICE_ID_INTEL_E7221_IG
, "E7221 (i915)",
1584 &intel_915_driver
, &i915_gtt_driver
},
1585 { PCI_DEVICE_ID_INTEL_82915G_IG
, "915G",
1586 &intel_915_driver
, &i915_gtt_driver
},
1587 { PCI_DEVICE_ID_INTEL_82915GM_IG
, "915GM",
1588 &intel_915_driver
, &i915_gtt_driver
},
1589 { PCI_DEVICE_ID_INTEL_82945G_IG
, "945G",
1590 &intel_915_driver
, &i915_gtt_driver
},
1591 { PCI_DEVICE_ID_INTEL_82945GM_IG
, "945GM",
1592 &intel_915_driver
, &i915_gtt_driver
},
1593 { PCI_DEVICE_ID_INTEL_82945GME_IG
, "945GME",
1594 &intel_915_driver
, &i915_gtt_driver
},
1595 { PCI_DEVICE_ID_INTEL_82946GZ_IG
, "946GZ",
1596 &intel_i965_driver
, &i965_gtt_driver
},
1597 { PCI_DEVICE_ID_INTEL_82G35_IG
, "G35",
1598 &intel_i965_driver
, &i965_gtt_driver
},
1599 { PCI_DEVICE_ID_INTEL_82965Q_IG
, "965Q",
1600 &intel_i965_driver
, &i965_gtt_driver
},
1601 { PCI_DEVICE_ID_INTEL_82965G_IG
, "965G",
1602 &intel_i965_driver
, &i965_gtt_driver
},
1603 { PCI_DEVICE_ID_INTEL_82965GM_IG
, "965GM",
1604 &intel_i965_driver
, &i965_gtt_driver
},
1605 { PCI_DEVICE_ID_INTEL_82965GME_IG
, "965GME/GLE",
1606 &intel_i965_driver
, &i965_gtt_driver
},
1607 { PCI_DEVICE_ID_INTEL_G33_IG
, "G33",
1608 &intel_g33_driver
, &g33_gtt_driver
},
1609 { PCI_DEVICE_ID_INTEL_Q35_IG
, "Q35",
1610 &intel_g33_driver
, &g33_gtt_driver
},
1611 { PCI_DEVICE_ID_INTEL_Q33_IG
, "Q33",
1612 &intel_g33_driver
, &g33_gtt_driver
},
1613 { PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG
, "GMA3150",
1614 &intel_g33_driver
, &pineview_gtt_driver
},
1615 { PCI_DEVICE_ID_INTEL_PINEVIEW_IG
, "GMA3150",
1616 &intel_g33_driver
, &pineview_gtt_driver
},
1617 { PCI_DEVICE_ID_INTEL_GM45_IG
, "GM45",
1618 &intel_i965_driver
, &g4x_gtt_driver
},
1619 { PCI_DEVICE_ID_INTEL_EAGLELAKE_IG
, "Eaglelake",
1620 &intel_i965_driver
, &g4x_gtt_driver
},
1621 { PCI_DEVICE_ID_INTEL_Q45_IG
, "Q45/Q43",
1622 &intel_i965_driver
, &g4x_gtt_driver
},
1623 { PCI_DEVICE_ID_INTEL_G45_IG
, "G45/G43",
1624 &intel_i965_driver
, &g4x_gtt_driver
},
1625 { PCI_DEVICE_ID_INTEL_B43_IG
, "B43",
1626 &intel_i965_driver
, &g4x_gtt_driver
},
1627 { PCI_DEVICE_ID_INTEL_G41_IG
, "G41",
1628 &intel_i965_driver
, &g4x_gtt_driver
},
1629 { PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG
,
1630 "HD Graphics", &intel_i965_driver
, &ironlake_gtt_driver
},
1631 { PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG
,
1632 "HD Graphics", &intel_i965_driver
, &ironlake_gtt_driver
},
1633 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT1_IG
,
1634 "Sandybridge", &intel_gen6_driver
, &sandybridge_gtt_driver
},
1635 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_IG
,
1636 "Sandybridge", &intel_gen6_driver
, &sandybridge_gtt_driver
},
1637 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_PLUS_IG
,
1638 "Sandybridge", &intel_gen6_driver
, &sandybridge_gtt_driver
},
1639 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT1_IG
,
1640 "Sandybridge", &intel_gen6_driver
, &sandybridge_gtt_driver
},
1641 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_IG
,
1642 "Sandybridge", &intel_gen6_driver
, &sandybridge_gtt_driver
},
1643 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_PLUS_IG
,
1644 "Sandybridge", &intel_gen6_driver
, &sandybridge_gtt_driver
},
1645 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG
,
1646 "Sandybridge", &intel_gen6_driver
, &sandybridge_gtt_driver
},
1650 static int find_gmch(u16 device
)
1652 struct pci_dev
*gmch_device
;
1654 gmch_device
= pci_get_device(PCI_VENDOR_ID_INTEL
, device
, NULL
);
1655 if (gmch_device
&& PCI_FUNC(gmch_device
->devfn
) != 0) {
1656 gmch_device
= pci_get_device(PCI_VENDOR_ID_INTEL
,
1657 device
, gmch_device
);
1663 intel_private
.pcidev
= gmch_device
;
1667 int intel_gmch_probe(struct pci_dev
*pdev
,
1668 struct agp_bridge_data
*bridge
)
1671 bridge
->driver
= NULL
;
1673 for (i
= 0; intel_gtt_chipsets
[i
].name
!= NULL
; i
++) {
1674 if (find_gmch(intel_gtt_chipsets
[i
].gmch_chip_id
)) {
1676 intel_gtt_chipsets
[i
].gmch_driver
;
1677 intel_private
.driver
=
1678 intel_gtt_chipsets
[i
].gtt_driver
;
1683 if (!bridge
->driver
)
1686 bridge
->dev_private_data
= &intel_private
;
1689 intel_private
.bridge_dev
= pci_dev_get(pdev
);
1691 dev_info(&pdev
->dev
, "Intel %s Chipset\n", intel_gtt_chipsets
[i
].name
);
1693 if (bridge
->driver
->mask_memory
== intel_gen6_mask_memory
)
1695 else if (bridge
->driver
->mask_memory
== intel_i965_mask_memory
)
1700 if (pci_set_dma_mask(intel_private
.pcidev
, DMA_BIT_MASK(mask
)))
1701 dev_err(&intel_private
.pcidev
->dev
,
1702 "set gfx device dma mask %d-bit failed!\n", mask
);
1704 pci_set_consistent_dma_mask(intel_private
.pcidev
,
1705 DMA_BIT_MASK(mask
));
1707 if (bridge
->driver
== &intel_810_driver
)
1710 if (intel_gtt_init() != 0)
1715 EXPORT_SYMBOL(intel_gmch_probe
);
1717 void intel_gmch_remove(struct pci_dev
*pdev
)
1719 if (intel_private
.pcidev
)
1720 pci_dev_put(intel_private
.pcidev
);
1721 if (intel_private
.bridge_dev
)
1722 pci_dev_put(intel_private
.bridge_dev
);
1724 EXPORT_SYMBOL(intel_gmch_remove
);
1726 MODULE_AUTHOR("Dave Jones <davej@redhat.com>");
1727 MODULE_LICENSE("GPL and additional rights");