2 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
3 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
5 Based on the original rt2800pci.c and rt2800usb.c.
6 Copyright (C) 2009 Ivo van Doorn <IvDoorn@gmail.com>
7 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
8 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
9 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
10 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
11 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
12 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
13 <http://rt2x00.serialmonkey.com>
15 This program is free software; you can redistribute it and/or modify
16 it under the terms of the GNU General Public License as published by
17 the Free Software Foundation; either version 2 of the License, or
18 (at your option) any later version.
20 This program is distributed in the hope that it will be useful,
21 but WITHOUT ANY WARRANTY; without even the implied warranty of
22 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 GNU General Public License for more details.
25 You should have received a copy of the GNU General Public License
26 along with this program; if not, write to the
27 Free Software Foundation, Inc.,
28 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
33 Abstract: rt2800 generic device routines.
36 #include <linux/kernel.h>
37 #include <linux/module.h>
40 #if defined(CONFIG_RT2X00_LIB_USB) || defined(CONFIG_RT2X00_LIB_USB_MODULE)
41 #include "rt2x00usb.h"
43 #if defined(CONFIG_RT2X00_LIB_PCI) || defined(CONFIG_RT2X00_LIB_PCI_MODULE)
44 #include "rt2x00pci.h"
46 #include "rt2800lib.h"
48 #include "rt2800usb.h"
50 MODULE_AUTHOR("Bartlomiej Zolnierkiewicz");
51 MODULE_DESCRIPTION("rt2800 library");
52 MODULE_LICENSE("GPL");
56 * All access to the CSR registers will go through the methods
57 * rt2800_register_read and rt2800_register_write.
58 * BBP and RF register require indirect register access,
59 * and use the CSR registers BBPCSR and RFCSR to achieve this.
60 * These indirect registers work with busy bits,
61 * and we will try maximal REGISTER_BUSY_COUNT times to access
62 * the register while taking a REGISTER_BUSY_DELAY us delay
63 * between each attampt. When the busy bit is still set at that time,
64 * the access attempt is considered to have failed,
65 * and we will print an error.
66 * The _lock versions must be used if you already hold the csr_mutex
68 #define WAIT_FOR_BBP(__dev, __reg) \
69 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
70 #define WAIT_FOR_RFCSR(__dev, __reg) \
71 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
72 #define WAIT_FOR_RF(__dev, __reg) \
73 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
74 #define WAIT_FOR_MCU(__dev, __reg) \
75 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
76 H2M_MAILBOX_CSR_OWNER, (__reg))
78 static void rt2800_bbp_write(struct rt2x00_dev
*rt2x00dev
,
79 const unsigned int word
, const u8 value
)
83 mutex_lock(&rt2x00dev
->csr_mutex
);
86 * Wait until the BBP becomes available, afterwards we
87 * can safely write the new data into the register.
89 if (WAIT_FOR_BBP(rt2x00dev
, ®
)) {
91 rt2x00_set_field32(®
, BBP_CSR_CFG_VALUE
, value
);
92 rt2x00_set_field32(®
, BBP_CSR_CFG_REGNUM
, word
);
93 rt2x00_set_field32(®
, BBP_CSR_CFG_BUSY
, 1);
94 rt2x00_set_field32(®
, BBP_CSR_CFG_READ_CONTROL
, 0);
95 if (rt2x00_is_pci(rt2x00dev
) || rt2x00_is_soc(rt2x00dev
))
96 rt2x00_set_field32(®
, BBP_CSR_CFG_BBP_RW_MODE
, 1);
98 rt2800_register_write_lock(rt2x00dev
, BBP_CSR_CFG
, reg
);
101 mutex_unlock(&rt2x00dev
->csr_mutex
);
104 static void rt2800_bbp_read(struct rt2x00_dev
*rt2x00dev
,
105 const unsigned int word
, u8
*value
)
109 mutex_lock(&rt2x00dev
->csr_mutex
);
112 * Wait until the BBP becomes available, afterwards we
113 * can safely write the read request into the register.
114 * After the data has been written, we wait until hardware
115 * returns the correct value, if at any time the register
116 * doesn't become available in time, reg will be 0xffffffff
117 * which means we return 0xff to the caller.
119 if (WAIT_FOR_BBP(rt2x00dev
, ®
)) {
121 rt2x00_set_field32(®
, BBP_CSR_CFG_REGNUM
, word
);
122 rt2x00_set_field32(®
, BBP_CSR_CFG_BUSY
, 1);
123 rt2x00_set_field32(®
, BBP_CSR_CFG_READ_CONTROL
, 1);
124 if (rt2x00_is_pci(rt2x00dev
) || rt2x00_is_soc(rt2x00dev
))
125 rt2x00_set_field32(®
, BBP_CSR_CFG_BBP_RW_MODE
, 1);
127 rt2800_register_write_lock(rt2x00dev
, BBP_CSR_CFG
, reg
);
129 WAIT_FOR_BBP(rt2x00dev
, ®
);
132 *value
= rt2x00_get_field32(reg
, BBP_CSR_CFG_VALUE
);
134 mutex_unlock(&rt2x00dev
->csr_mutex
);
137 static void rt2800_rfcsr_write(struct rt2x00_dev
*rt2x00dev
,
138 const unsigned int word
, const u8 value
)
142 mutex_lock(&rt2x00dev
->csr_mutex
);
145 * Wait until the RFCSR becomes available, afterwards we
146 * can safely write the new data into the register.
148 if (WAIT_FOR_RFCSR(rt2x00dev
, ®
)) {
150 rt2x00_set_field32(®
, RF_CSR_CFG_DATA
, value
);
151 rt2x00_set_field32(®
, RF_CSR_CFG_REGNUM
, word
);
152 rt2x00_set_field32(®
, RF_CSR_CFG_WRITE
, 1);
153 rt2x00_set_field32(®
, RF_CSR_CFG_BUSY
, 1);
155 rt2800_register_write_lock(rt2x00dev
, RF_CSR_CFG
, reg
);
158 mutex_unlock(&rt2x00dev
->csr_mutex
);
161 static void rt2800_rfcsr_read(struct rt2x00_dev
*rt2x00dev
,
162 const unsigned int word
, u8
*value
)
166 mutex_lock(&rt2x00dev
->csr_mutex
);
169 * Wait until the RFCSR becomes available, afterwards we
170 * can safely write the read request into the register.
171 * After the data has been written, we wait until hardware
172 * returns the correct value, if at any time the register
173 * doesn't become available in time, reg will be 0xffffffff
174 * which means we return 0xff to the caller.
176 if (WAIT_FOR_RFCSR(rt2x00dev
, ®
)) {
178 rt2x00_set_field32(®
, RF_CSR_CFG_REGNUM
, word
);
179 rt2x00_set_field32(®
, RF_CSR_CFG_WRITE
, 0);
180 rt2x00_set_field32(®
, RF_CSR_CFG_BUSY
, 1);
182 rt2800_register_write_lock(rt2x00dev
, RF_CSR_CFG
, reg
);
184 WAIT_FOR_RFCSR(rt2x00dev
, ®
);
187 *value
= rt2x00_get_field32(reg
, RF_CSR_CFG_DATA
);
189 mutex_unlock(&rt2x00dev
->csr_mutex
);
192 static void rt2800_rf_write(struct rt2x00_dev
*rt2x00dev
,
193 const unsigned int word
, const u32 value
)
197 mutex_lock(&rt2x00dev
->csr_mutex
);
200 * Wait until the RF becomes available, afterwards we
201 * can safely write the new data into the register.
203 if (WAIT_FOR_RF(rt2x00dev
, ®
)) {
205 rt2x00_set_field32(®
, RF_CSR_CFG0_REG_VALUE_BW
, value
);
206 rt2x00_set_field32(®
, RF_CSR_CFG0_STANDBYMODE
, 0);
207 rt2x00_set_field32(®
, RF_CSR_CFG0_SEL
, 0);
208 rt2x00_set_field32(®
, RF_CSR_CFG0_BUSY
, 1);
210 rt2800_register_write_lock(rt2x00dev
, RF_CSR_CFG0
, reg
);
211 rt2x00_rf_write(rt2x00dev
, word
, value
);
214 mutex_unlock(&rt2x00dev
->csr_mutex
);
217 void rt2800_mcu_request(struct rt2x00_dev
*rt2x00dev
,
218 const u8 command
, const u8 token
,
219 const u8 arg0
, const u8 arg1
)
224 * SOC devices don't support MCU requests.
226 if (rt2x00_is_soc(rt2x00dev
))
229 mutex_lock(&rt2x00dev
->csr_mutex
);
232 * Wait until the MCU becomes available, afterwards we
233 * can safely write the new data into the register.
235 if (WAIT_FOR_MCU(rt2x00dev
, ®
)) {
236 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_OWNER
, 1);
237 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_CMD_TOKEN
, token
);
238 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_ARG0
, arg0
);
239 rt2x00_set_field32(®
, H2M_MAILBOX_CSR_ARG1
, arg1
);
240 rt2800_register_write_lock(rt2x00dev
, H2M_MAILBOX_CSR
, reg
);
243 rt2x00_set_field32(®
, HOST_CMD_CSR_HOST_COMMAND
, command
);
244 rt2800_register_write_lock(rt2x00dev
, HOST_CMD_CSR
, reg
);
247 mutex_unlock(&rt2x00dev
->csr_mutex
);
249 EXPORT_SYMBOL_GPL(rt2800_mcu_request
);
251 int rt2800_wait_wpdma_ready(struct rt2x00_dev
*rt2x00dev
)
256 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
257 rt2800_register_read(rt2x00dev
, WPDMA_GLO_CFG
, ®
);
258 if (!rt2x00_get_field32(reg
, WPDMA_GLO_CFG_TX_DMA_BUSY
) &&
259 !rt2x00_get_field32(reg
, WPDMA_GLO_CFG_RX_DMA_BUSY
))
265 ERROR(rt2x00dev
, "WPDMA TX/RX busy, aborting.\n");
268 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready
);
270 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
271 const struct rt2x00debug rt2800_rt2x00debug
= {
272 .owner
= THIS_MODULE
,
274 .read
= rt2800_register_read
,
275 .write
= rt2800_register_write
,
276 .flags
= RT2X00DEBUGFS_OFFSET
,
277 .word_base
= CSR_REG_BASE
,
278 .word_size
= sizeof(u32
),
279 .word_count
= CSR_REG_SIZE
/ sizeof(u32
),
282 .read
= rt2x00_eeprom_read
,
283 .write
= rt2x00_eeprom_write
,
284 .word_base
= EEPROM_BASE
,
285 .word_size
= sizeof(u16
),
286 .word_count
= EEPROM_SIZE
/ sizeof(u16
),
289 .read
= rt2800_bbp_read
,
290 .write
= rt2800_bbp_write
,
291 .word_base
= BBP_BASE
,
292 .word_size
= sizeof(u8
),
293 .word_count
= BBP_SIZE
/ sizeof(u8
),
296 .read
= rt2x00_rf_read
,
297 .write
= rt2800_rf_write
,
298 .word_base
= RF_BASE
,
299 .word_size
= sizeof(u32
),
300 .word_count
= RF_SIZE
/ sizeof(u32
),
303 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug
);
304 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
306 int rt2800_rfkill_poll(struct rt2x00_dev
*rt2x00dev
)
310 rt2800_register_read(rt2x00dev
, GPIO_CTRL_CFG
, ®
);
311 return rt2x00_get_field32(reg
, GPIO_CTRL_CFG_BIT2
);
313 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll
);
315 #ifdef CONFIG_RT2X00_LIB_LEDS
316 static void rt2800_brightness_set(struct led_classdev
*led_cdev
,
317 enum led_brightness brightness
)
319 struct rt2x00_led
*led
=
320 container_of(led_cdev
, struct rt2x00_led
, led_dev
);
321 unsigned int enabled
= brightness
!= LED_OFF
;
322 unsigned int bg_mode
=
323 (enabled
&& led
->rt2x00dev
->curr_band
== IEEE80211_BAND_2GHZ
);
324 unsigned int polarity
=
325 rt2x00_get_field16(led
->rt2x00dev
->led_mcu_reg
,
326 EEPROM_FREQ_LED_POLARITY
);
327 unsigned int ledmode
=
328 rt2x00_get_field16(led
->rt2x00dev
->led_mcu_reg
,
329 EEPROM_FREQ_LED_MODE
);
331 if (led
->type
== LED_TYPE_RADIO
) {
332 rt2800_mcu_request(led
->rt2x00dev
, MCU_LED
, 0xff, ledmode
,
334 } else if (led
->type
== LED_TYPE_ASSOC
) {
335 rt2800_mcu_request(led
->rt2x00dev
, MCU_LED
, 0xff, ledmode
,
336 enabled
? (bg_mode
? 0x60 : 0xa0) : 0x20);
337 } else if (led
->type
== LED_TYPE_QUALITY
) {
339 * The brightness is divided into 6 levels (0 - 5),
340 * The specs tell us the following levels:
342 * to determine the level in a simple way we can simply
343 * work with bitshifting:
346 rt2800_mcu_request(led
->rt2x00dev
, MCU_LED_STRENGTH
, 0xff,
347 (1 << brightness
/ (LED_FULL
/ 6)) - 1,
352 static int rt2800_blink_set(struct led_classdev
*led_cdev
,
353 unsigned long *delay_on
, unsigned long *delay_off
)
355 struct rt2x00_led
*led
=
356 container_of(led_cdev
, struct rt2x00_led
, led_dev
);
359 rt2800_register_read(led
->rt2x00dev
, LED_CFG
, ®
);
360 rt2x00_set_field32(®
, LED_CFG_ON_PERIOD
, *delay_on
);
361 rt2x00_set_field32(®
, LED_CFG_OFF_PERIOD
, *delay_off
);
362 rt2800_register_write(led
->rt2x00dev
, LED_CFG
, reg
);
367 static void rt2800_init_led(struct rt2x00_dev
*rt2x00dev
,
368 struct rt2x00_led
*led
, enum led_type type
)
370 led
->rt2x00dev
= rt2x00dev
;
372 led
->led_dev
.brightness_set
= rt2800_brightness_set
;
373 led
->led_dev
.blink_set
= rt2800_blink_set
;
374 led
->flags
= LED_INITIALIZED
;
376 #endif /* CONFIG_RT2X00_LIB_LEDS */
379 * Configuration handlers.
381 static void rt2800_config_wcid_attr(struct rt2x00_dev
*rt2x00dev
,
382 struct rt2x00lib_crypto
*crypto
,
383 struct ieee80211_key_conf
*key
)
385 struct mac_wcid_entry wcid_entry
;
386 struct mac_iveiv_entry iveiv_entry
;
390 offset
= MAC_WCID_ATTR_ENTRY(key
->hw_key_idx
);
392 rt2800_register_read(rt2x00dev
, offset
, ®
);
393 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_KEYTAB
,
394 !!(key
->flags
& IEEE80211_KEY_FLAG_PAIRWISE
));
395 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_CIPHER
,
396 (crypto
->cmd
== SET_KEY
) * crypto
->cipher
);
397 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_BSS_IDX
,
398 (crypto
->cmd
== SET_KEY
) * crypto
->bssidx
);
399 rt2x00_set_field32(®
, MAC_WCID_ATTRIBUTE_RX_WIUDF
, crypto
->cipher
);
400 rt2800_register_write(rt2x00dev
, offset
, reg
);
402 offset
= MAC_IVEIV_ENTRY(key
->hw_key_idx
);
404 memset(&iveiv_entry
, 0, sizeof(iveiv_entry
));
405 if ((crypto
->cipher
== CIPHER_TKIP
) ||
406 (crypto
->cipher
== CIPHER_TKIP_NO_MIC
) ||
407 (crypto
->cipher
== CIPHER_AES
))
408 iveiv_entry
.iv
[3] |= 0x20;
409 iveiv_entry
.iv
[3] |= key
->keyidx
<< 6;
410 rt2800_register_multiwrite(rt2x00dev
, offset
,
411 &iveiv_entry
, sizeof(iveiv_entry
));
413 offset
= MAC_WCID_ENTRY(key
->hw_key_idx
);
415 memset(&wcid_entry
, 0, sizeof(wcid_entry
));
416 if (crypto
->cmd
== SET_KEY
)
417 memcpy(&wcid_entry
, crypto
->address
, ETH_ALEN
);
418 rt2800_register_multiwrite(rt2x00dev
, offset
,
419 &wcid_entry
, sizeof(wcid_entry
));
422 int rt2800_config_shared_key(struct rt2x00_dev
*rt2x00dev
,
423 struct rt2x00lib_crypto
*crypto
,
424 struct ieee80211_key_conf
*key
)
426 struct hw_key_entry key_entry
;
427 struct rt2x00_field32 field
;
431 if (crypto
->cmd
== SET_KEY
) {
432 key
->hw_key_idx
= (4 * crypto
->bssidx
) + key
->keyidx
;
434 memcpy(key_entry
.key
, crypto
->key
,
435 sizeof(key_entry
.key
));
436 memcpy(key_entry
.tx_mic
, crypto
->tx_mic
,
437 sizeof(key_entry
.tx_mic
));
438 memcpy(key_entry
.rx_mic
, crypto
->rx_mic
,
439 sizeof(key_entry
.rx_mic
));
441 offset
= SHARED_KEY_ENTRY(key
->hw_key_idx
);
442 rt2800_register_multiwrite(rt2x00dev
, offset
,
443 &key_entry
, sizeof(key_entry
));
447 * The cipher types are stored over multiple registers
448 * starting with SHARED_KEY_MODE_BASE each word will have
449 * 32 bits and contains the cipher types for 2 bssidx each.
450 * Using the correct defines correctly will cause overhead,
451 * so just calculate the correct offset.
453 field
.bit_offset
= 4 * (key
->hw_key_idx
% 8);
454 field
.bit_mask
= 0x7 << field
.bit_offset
;
456 offset
= SHARED_KEY_MODE_ENTRY(key
->hw_key_idx
/ 8);
458 rt2800_register_read(rt2x00dev
, offset
, ®
);
459 rt2x00_set_field32(®
, field
,
460 (crypto
->cmd
== SET_KEY
) * crypto
->cipher
);
461 rt2800_register_write(rt2x00dev
, offset
, reg
);
464 * Update WCID information
466 rt2800_config_wcid_attr(rt2x00dev
, crypto
, key
);
470 EXPORT_SYMBOL_GPL(rt2800_config_shared_key
);
472 int rt2800_config_pairwise_key(struct rt2x00_dev
*rt2x00dev
,
473 struct rt2x00lib_crypto
*crypto
,
474 struct ieee80211_key_conf
*key
)
476 struct hw_key_entry key_entry
;
479 if (crypto
->cmd
== SET_KEY
) {
481 * 1 pairwise key is possible per AID, this means that the AID
482 * equals our hw_key_idx. Make sure the WCID starts _after_ the
483 * last possible shared key entry.
485 if (crypto
->aid
> (256 - 32))
488 key
->hw_key_idx
= 32 + crypto
->aid
;
490 memcpy(key_entry
.key
, crypto
->key
,
491 sizeof(key_entry
.key
));
492 memcpy(key_entry
.tx_mic
, crypto
->tx_mic
,
493 sizeof(key_entry
.tx_mic
));
494 memcpy(key_entry
.rx_mic
, crypto
->rx_mic
,
495 sizeof(key_entry
.rx_mic
));
497 offset
= PAIRWISE_KEY_ENTRY(key
->hw_key_idx
);
498 rt2800_register_multiwrite(rt2x00dev
, offset
,
499 &key_entry
, sizeof(key_entry
));
503 * Update WCID information
505 rt2800_config_wcid_attr(rt2x00dev
, crypto
, key
);
509 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key
);
511 void rt2800_config_filter(struct rt2x00_dev
*rt2x00dev
,
512 const unsigned int filter_flags
)
517 * Start configuration steps.
518 * Note that the version error will always be dropped
519 * and broadcast frames will always be accepted since
520 * there is no filter for it at this time.
522 rt2800_register_read(rt2x00dev
, RX_FILTER_CFG
, ®
);
523 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_CRC_ERROR
,
524 !(filter_flags
& FIF_FCSFAIL
));
525 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_PHY_ERROR
,
526 !(filter_flags
& FIF_PLCPFAIL
));
527 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_NOT_TO_ME
,
528 !(filter_flags
& FIF_PROMISC_IN_BSS
));
529 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_NOT_MY_BSSD
, 0);
530 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_VER_ERROR
, 1);
531 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_MULTICAST
,
532 !(filter_flags
& FIF_ALLMULTI
));
533 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_BROADCAST
, 0);
534 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_DUPLICATE
, 1);
535 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_CF_END_ACK
,
536 !(filter_flags
& FIF_CONTROL
));
537 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_CF_END
,
538 !(filter_flags
& FIF_CONTROL
));
539 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_ACK
,
540 !(filter_flags
& FIF_CONTROL
));
541 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_CTS
,
542 !(filter_flags
& FIF_CONTROL
));
543 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_RTS
,
544 !(filter_flags
& FIF_CONTROL
));
545 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_PSPOLL
,
546 !(filter_flags
& FIF_PSPOLL
));
547 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_BA
, 1);
548 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_BAR
, 0);
549 rt2x00_set_field32(®
, RX_FILTER_CFG_DROP_CNTL
,
550 !(filter_flags
& FIF_CONTROL
));
551 rt2800_register_write(rt2x00dev
, RX_FILTER_CFG
, reg
);
553 EXPORT_SYMBOL_GPL(rt2800_config_filter
);
555 void rt2800_config_intf(struct rt2x00_dev
*rt2x00dev
, struct rt2x00_intf
*intf
,
556 struct rt2x00intf_conf
*conf
, const unsigned int flags
)
558 unsigned int beacon_base
;
561 if (flags
& CONFIG_UPDATE_TYPE
) {
563 * Clear current synchronisation setup.
564 * For the Beacon base registers we only need to clear
565 * the first byte since that byte contains the VALID and OWNER
566 * bits which (when set to 0) will invalidate the entire beacon.
568 beacon_base
= HW_BEACON_OFFSET(intf
->beacon
->entry_idx
);
569 rt2800_register_write(rt2x00dev
, beacon_base
, 0);
572 * Enable synchronisation.
574 rt2800_register_read(rt2x00dev
, BCN_TIME_CFG
, ®
);
575 rt2x00_set_field32(®
, BCN_TIME_CFG_TSF_TICKING
, 1);
576 rt2x00_set_field32(®
, BCN_TIME_CFG_TSF_SYNC
, conf
->sync
);
577 rt2x00_set_field32(®
, BCN_TIME_CFG_TBTT_ENABLE
,
578 (conf
->sync
== TSF_SYNC_BEACON
));
579 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
582 if (flags
& CONFIG_UPDATE_MAC
) {
583 reg
= le32_to_cpu(conf
->mac
[1]);
584 rt2x00_set_field32(®
, MAC_ADDR_DW1_UNICAST_TO_ME_MASK
, 0xff);
585 conf
->mac
[1] = cpu_to_le32(reg
);
587 rt2800_register_multiwrite(rt2x00dev
, MAC_ADDR_DW0
,
588 conf
->mac
, sizeof(conf
->mac
));
591 if (flags
& CONFIG_UPDATE_BSSID
) {
592 reg
= le32_to_cpu(conf
->bssid
[1]);
593 rt2x00_set_field32(®
, MAC_BSSID_DW1_BSS_ID_MASK
, 0);
594 rt2x00_set_field32(®
, MAC_BSSID_DW1_BSS_BCN_NUM
, 0);
595 conf
->bssid
[1] = cpu_to_le32(reg
);
597 rt2800_register_multiwrite(rt2x00dev
, MAC_BSSID_DW0
,
598 conf
->bssid
, sizeof(conf
->bssid
));
601 EXPORT_SYMBOL_GPL(rt2800_config_intf
);
603 void rt2800_config_erp(struct rt2x00_dev
*rt2x00dev
, struct rt2x00lib_erp
*erp
)
607 rt2800_register_read(rt2x00dev
, AUTO_RSP_CFG
, ®
);
608 rt2x00_set_field32(®
, AUTO_RSP_CFG_BAC_ACK_POLICY
,
609 !!erp
->short_preamble
);
610 rt2x00_set_field32(®
, AUTO_RSP_CFG_AR_PREAMBLE
,
611 !!erp
->short_preamble
);
612 rt2800_register_write(rt2x00dev
, AUTO_RSP_CFG
, reg
);
614 rt2800_register_read(rt2x00dev
, OFDM_PROT_CFG
, ®
);
615 rt2x00_set_field32(®
, OFDM_PROT_CFG_PROTECT_CTRL
,
616 erp
->cts_protection
? 2 : 0);
617 rt2800_register_write(rt2x00dev
, OFDM_PROT_CFG
, reg
);
619 rt2800_register_write(rt2x00dev
, LEGACY_BASIC_RATE
,
621 rt2800_register_write(rt2x00dev
, HT_BASIC_RATE
, 0x00008003);
623 rt2800_register_read(rt2x00dev
, BKOFF_SLOT_CFG
, ®
);
624 rt2x00_set_field32(®
, BKOFF_SLOT_CFG_SLOT_TIME
, erp
->slot_time
);
625 rt2800_register_write(rt2x00dev
, BKOFF_SLOT_CFG
, reg
);
627 rt2800_register_read(rt2x00dev
, XIFS_TIME_CFG
, ®
);
628 rt2x00_set_field32(®
, XIFS_TIME_CFG_CCKM_SIFS_TIME
, erp
->sifs
);
629 rt2x00_set_field32(®
, XIFS_TIME_CFG_OFDM_SIFS_TIME
, erp
->sifs
);
630 rt2x00_set_field32(®
, XIFS_TIME_CFG_EIFS
, erp
->eifs
);
631 rt2800_register_write(rt2x00dev
, XIFS_TIME_CFG
, reg
);
633 rt2800_register_read(rt2x00dev
, BCN_TIME_CFG
, ®
);
634 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_INTERVAL
,
635 erp
->beacon_int
* 16);
636 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
638 EXPORT_SYMBOL_GPL(rt2800_config_erp
);
640 void rt2800_config_ant(struct rt2x00_dev
*rt2x00dev
, struct antenna_setup
*ant
)
645 rt2800_bbp_read(rt2x00dev
, 1, &r1
);
646 rt2800_bbp_read(rt2x00dev
, 3, &r3
);
649 * Configure the TX antenna.
651 switch ((int)ant
->tx
) {
653 rt2x00_set_field8(&r1
, BBP1_TX_ANTENNA
, 0);
654 if (rt2x00_is_pci(rt2x00dev
) || rt2x00_is_soc(rt2x00dev
))
655 rt2x00_set_field8(&r3
, BBP3_RX_ANTENNA
, 0);
658 rt2x00_set_field8(&r1
, BBP1_TX_ANTENNA
, 2);
666 * Configure the RX antenna.
668 switch ((int)ant
->rx
) {
670 rt2x00_set_field8(&r3
, BBP3_RX_ANTENNA
, 0);
673 rt2x00_set_field8(&r3
, BBP3_RX_ANTENNA
, 1);
676 rt2x00_set_field8(&r3
, BBP3_RX_ANTENNA
, 2);
680 rt2800_bbp_write(rt2x00dev
, 3, r3
);
681 rt2800_bbp_write(rt2x00dev
, 1, r1
);
683 EXPORT_SYMBOL_GPL(rt2800_config_ant
);
685 static void rt2800_config_lna_gain(struct rt2x00_dev
*rt2x00dev
,
686 struct rt2x00lib_conf
*libconf
)
691 if (libconf
->rf
.channel
<= 14) {
692 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LNA
, &eeprom
);
693 lna_gain
= rt2x00_get_field16(eeprom
, EEPROM_LNA_BG
);
694 } else if (libconf
->rf
.channel
<= 64) {
695 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LNA
, &eeprom
);
696 lna_gain
= rt2x00_get_field16(eeprom
, EEPROM_LNA_A0
);
697 } else if (libconf
->rf
.channel
<= 128) {
698 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_BG2
, &eeprom
);
699 lna_gain
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_BG2_LNA_A1
);
701 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_A2
, &eeprom
);
702 lna_gain
= rt2x00_get_field16(eeprom
, EEPROM_RSSI_A2_LNA_A2
);
705 rt2x00dev
->lna_gain
= lna_gain
;
708 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev
*rt2x00dev
,
709 struct ieee80211_conf
*conf
,
710 struct rf_channel
*rf
,
711 struct channel_info
*info
)
713 rt2x00_set_field32(&rf
->rf4
, RF4_FREQ_OFFSET
, rt2x00dev
->freq_offset
);
715 if (rt2x00dev
->default_ant
.tx
== 1)
716 rt2x00_set_field32(&rf
->rf2
, RF2_ANTENNA_TX1
, 1);
718 if (rt2x00dev
->default_ant
.rx
== 1) {
719 rt2x00_set_field32(&rf
->rf2
, RF2_ANTENNA_RX1
, 1);
720 rt2x00_set_field32(&rf
->rf2
, RF2_ANTENNA_RX2
, 1);
721 } else if (rt2x00dev
->default_ant
.rx
== 2)
722 rt2x00_set_field32(&rf
->rf2
, RF2_ANTENNA_RX2
, 1);
724 if (rf
->channel
> 14) {
726 * When TX power is below 0, we should increase it by 7 to
727 * make it a positive value (Minumum value is -7).
728 * However this means that values between 0 and 7 have
729 * double meaning, and we should set a 7DBm boost flag.
731 rt2x00_set_field32(&rf
->rf3
, RF3_TXPOWER_A_7DBM_BOOST
,
732 (info
->tx_power1
>= 0));
734 if (info
->tx_power1
< 0)
735 info
->tx_power1
+= 7;
737 rt2x00_set_field32(&rf
->rf3
, RF3_TXPOWER_A
,
738 TXPOWER_A_TO_DEV(info
->tx_power1
));
740 rt2x00_set_field32(&rf
->rf4
, RF4_TXPOWER_A_7DBM_BOOST
,
741 (info
->tx_power2
>= 0));
743 if (info
->tx_power2
< 0)
744 info
->tx_power2
+= 7;
746 rt2x00_set_field32(&rf
->rf4
, RF4_TXPOWER_A
,
747 TXPOWER_A_TO_DEV(info
->tx_power2
));
749 rt2x00_set_field32(&rf
->rf3
, RF3_TXPOWER_G
,
750 TXPOWER_G_TO_DEV(info
->tx_power1
));
751 rt2x00_set_field32(&rf
->rf4
, RF4_TXPOWER_G
,
752 TXPOWER_G_TO_DEV(info
->tx_power2
));
755 rt2x00_set_field32(&rf
->rf4
, RF4_HT40
, conf_is_ht40(conf
));
757 rt2800_rf_write(rt2x00dev
, 1, rf
->rf1
);
758 rt2800_rf_write(rt2x00dev
, 2, rf
->rf2
);
759 rt2800_rf_write(rt2x00dev
, 3, rf
->rf3
& ~0x00000004);
760 rt2800_rf_write(rt2x00dev
, 4, rf
->rf4
);
764 rt2800_rf_write(rt2x00dev
, 1, rf
->rf1
);
765 rt2800_rf_write(rt2x00dev
, 2, rf
->rf2
);
766 rt2800_rf_write(rt2x00dev
, 3, rf
->rf3
| 0x00000004);
767 rt2800_rf_write(rt2x00dev
, 4, rf
->rf4
);
771 rt2800_rf_write(rt2x00dev
, 1, rf
->rf1
);
772 rt2800_rf_write(rt2x00dev
, 2, rf
->rf2
);
773 rt2800_rf_write(rt2x00dev
, 3, rf
->rf3
& ~0x00000004);
774 rt2800_rf_write(rt2x00dev
, 4, rf
->rf4
);
777 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev
*rt2x00dev
,
778 struct ieee80211_conf
*conf
,
779 struct rf_channel
*rf
,
780 struct channel_info
*info
)
784 rt2800_rfcsr_write(rt2x00dev
, 2, rf
->rf1
);
785 rt2800_rfcsr_write(rt2x00dev
, 3, rf
->rf3
);
787 rt2800_rfcsr_read(rt2x00dev
, 6, &rfcsr
);
788 rt2x00_set_field8(&rfcsr
, RFCSR6_R1
, rf
->rf2
);
789 rt2800_rfcsr_write(rt2x00dev
, 6, rfcsr
);
791 rt2800_rfcsr_read(rt2x00dev
, 12, &rfcsr
);
792 rt2x00_set_field8(&rfcsr
, RFCSR12_TX_POWER
,
793 TXPOWER_G_TO_DEV(info
->tx_power1
));
794 rt2800_rfcsr_write(rt2x00dev
, 12, rfcsr
);
796 rt2800_rfcsr_read(rt2x00dev
, 13, &rfcsr
);
797 rt2x00_set_field8(&rfcsr
, RFCSR13_TX_POWER
,
798 TXPOWER_G_TO_DEV(info
->tx_power2
));
799 rt2800_rfcsr_write(rt2x00dev
, 13, rfcsr
);
801 rt2800_rfcsr_read(rt2x00dev
, 23, &rfcsr
);
802 rt2x00_set_field8(&rfcsr
, RFCSR23_FREQ_OFFSET
, rt2x00dev
->freq_offset
);
803 rt2800_rfcsr_write(rt2x00dev
, 23, rfcsr
);
805 rt2800_rfcsr_write(rt2x00dev
, 24,
806 rt2x00dev
->calibration
[conf_is_ht40(conf
)]);
808 rt2800_rfcsr_read(rt2x00dev
, 7, &rfcsr
);
809 rt2x00_set_field8(&rfcsr
, RFCSR7_RF_TUNING
, 1);
810 rt2800_rfcsr_write(rt2x00dev
, 7, rfcsr
);
813 static void rt2800_config_channel(struct rt2x00_dev
*rt2x00dev
,
814 struct ieee80211_conf
*conf
,
815 struct rf_channel
*rf
,
816 struct channel_info
*info
)
822 if (rt2x00_rf(rt2x00dev
, RF2020
) ||
823 rt2x00_rf(rt2x00dev
, RF3020
) ||
824 rt2x00_rf(rt2x00dev
, RF3021
) ||
825 rt2x00_rf(rt2x00dev
, RF3022
))
826 rt2800_config_channel_rf3xxx(rt2x00dev
, conf
, rf
, info
);
828 rt2800_config_channel_rf2xxx(rt2x00dev
, conf
, rf
, info
);
831 * Change BBP settings
833 rt2800_bbp_write(rt2x00dev
, 62, 0x37 - rt2x00dev
->lna_gain
);
834 rt2800_bbp_write(rt2x00dev
, 63, 0x37 - rt2x00dev
->lna_gain
);
835 rt2800_bbp_write(rt2x00dev
, 64, 0x37 - rt2x00dev
->lna_gain
);
836 rt2800_bbp_write(rt2x00dev
, 86, 0);
838 if (rf
->channel
<= 14) {
839 if (test_bit(CONFIG_EXTERNAL_LNA_BG
, &rt2x00dev
->flags
)) {
840 rt2800_bbp_write(rt2x00dev
, 82, 0x62);
841 rt2800_bbp_write(rt2x00dev
, 75, 0x46);
843 rt2800_bbp_write(rt2x00dev
, 82, 0x84);
844 rt2800_bbp_write(rt2x00dev
, 75, 0x50);
847 rt2800_bbp_write(rt2x00dev
, 82, 0xf2);
849 if (test_bit(CONFIG_EXTERNAL_LNA_A
, &rt2x00dev
->flags
))
850 rt2800_bbp_write(rt2x00dev
, 75, 0x46);
852 rt2800_bbp_write(rt2x00dev
, 75, 0x50);
855 rt2800_register_read(rt2x00dev
, TX_BAND_CFG
, ®
);
856 rt2x00_set_field32(®
, TX_BAND_CFG_HT40_PLUS
, conf_is_ht40_plus(conf
));
857 rt2x00_set_field32(®
, TX_BAND_CFG_A
, rf
->channel
> 14);
858 rt2x00_set_field32(®
, TX_BAND_CFG_BG
, rf
->channel
<= 14);
859 rt2800_register_write(rt2x00dev
, TX_BAND_CFG
, reg
);
863 /* Turn on unused PA or LNA when not using 1T or 1R */
864 if (rt2x00dev
->default_ant
.tx
!= 1) {
865 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_A1_EN
, 1);
866 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_G1_EN
, 1);
869 /* Turn on unused PA or LNA when not using 1T or 1R */
870 if (rt2x00dev
->default_ant
.rx
!= 1) {
871 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_LNA_PE_A1_EN
, 1);
872 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_LNA_PE_G1_EN
, 1);
875 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_LNA_PE_A0_EN
, 1);
876 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_LNA_PE_G0_EN
, 1);
877 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_RFTR_EN
, 1);
878 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_TRSW_EN
, 1);
879 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_G0_EN
, rf
->channel
<= 14);
880 rt2x00_set_field32(&tx_pin
, TX_PIN_CFG_PA_PE_A0_EN
, rf
->channel
> 14);
882 rt2800_register_write(rt2x00dev
, TX_PIN_CFG
, tx_pin
);
884 rt2800_bbp_read(rt2x00dev
, 4, &bbp
);
885 rt2x00_set_field8(&bbp
, BBP4_BANDWIDTH
, 2 * conf_is_ht40(conf
));
886 rt2800_bbp_write(rt2x00dev
, 4, bbp
);
888 rt2800_bbp_read(rt2x00dev
, 3, &bbp
);
889 rt2x00_set_field8(&bbp
, BBP3_HT40_PLUS
, conf_is_ht40_plus(conf
));
890 rt2800_bbp_write(rt2x00dev
, 3, bbp
);
892 if (rt2x00_rt_rev(rt2x00dev
, RT2860
, REV_RT2860C
)) {
893 if (conf_is_ht40(conf
)) {
894 rt2800_bbp_write(rt2x00dev
, 69, 0x1a);
895 rt2800_bbp_write(rt2x00dev
, 70, 0x0a);
896 rt2800_bbp_write(rt2x00dev
, 73, 0x16);
898 rt2800_bbp_write(rt2x00dev
, 69, 0x16);
899 rt2800_bbp_write(rt2x00dev
, 70, 0x08);
900 rt2800_bbp_write(rt2x00dev
, 73, 0x11);
907 static void rt2800_config_txpower(struct rt2x00_dev
*rt2x00dev
,
911 u32 value
= TXPOWER_G_TO_DEV(txpower
);
914 rt2800_bbp_read(rt2x00dev
, 1, &r1
);
915 rt2x00_set_field8(®
, BBP1_TX_POWER
, 0);
916 rt2800_bbp_write(rt2x00dev
, 1, r1
);
918 rt2800_register_read(rt2x00dev
, TX_PWR_CFG_0
, ®
);
919 rt2x00_set_field32(®
, TX_PWR_CFG_0_1MBS
, value
);
920 rt2x00_set_field32(®
, TX_PWR_CFG_0_2MBS
, value
);
921 rt2x00_set_field32(®
, TX_PWR_CFG_0_55MBS
, value
);
922 rt2x00_set_field32(®
, TX_PWR_CFG_0_11MBS
, value
);
923 rt2x00_set_field32(®
, TX_PWR_CFG_0_6MBS
, value
);
924 rt2x00_set_field32(®
, TX_PWR_CFG_0_9MBS
, value
);
925 rt2x00_set_field32(®
, TX_PWR_CFG_0_12MBS
, value
);
926 rt2x00_set_field32(®
, TX_PWR_CFG_0_18MBS
, value
);
927 rt2800_register_write(rt2x00dev
, TX_PWR_CFG_0
, reg
);
929 rt2800_register_read(rt2x00dev
, TX_PWR_CFG_1
, ®
);
930 rt2x00_set_field32(®
, TX_PWR_CFG_1_24MBS
, value
);
931 rt2x00_set_field32(®
, TX_PWR_CFG_1_36MBS
, value
);
932 rt2x00_set_field32(®
, TX_PWR_CFG_1_48MBS
, value
);
933 rt2x00_set_field32(®
, TX_PWR_CFG_1_54MBS
, value
);
934 rt2x00_set_field32(®
, TX_PWR_CFG_1_MCS0
, value
);
935 rt2x00_set_field32(®
, TX_PWR_CFG_1_MCS1
, value
);
936 rt2x00_set_field32(®
, TX_PWR_CFG_1_MCS2
, value
);
937 rt2x00_set_field32(®
, TX_PWR_CFG_1_MCS3
, value
);
938 rt2800_register_write(rt2x00dev
, TX_PWR_CFG_1
, reg
);
940 rt2800_register_read(rt2x00dev
, TX_PWR_CFG_2
, ®
);
941 rt2x00_set_field32(®
, TX_PWR_CFG_2_MCS4
, value
);
942 rt2x00_set_field32(®
, TX_PWR_CFG_2_MCS5
, value
);
943 rt2x00_set_field32(®
, TX_PWR_CFG_2_MCS6
, value
);
944 rt2x00_set_field32(®
, TX_PWR_CFG_2_MCS7
, value
);
945 rt2x00_set_field32(®
, TX_PWR_CFG_2_MCS8
, value
);
946 rt2x00_set_field32(®
, TX_PWR_CFG_2_MCS9
, value
);
947 rt2x00_set_field32(®
, TX_PWR_CFG_2_MCS10
, value
);
948 rt2x00_set_field32(®
, TX_PWR_CFG_2_MCS11
, value
);
949 rt2800_register_write(rt2x00dev
, TX_PWR_CFG_2
, reg
);
951 rt2800_register_read(rt2x00dev
, TX_PWR_CFG_3
, ®
);
952 rt2x00_set_field32(®
, TX_PWR_CFG_3_MCS12
, value
);
953 rt2x00_set_field32(®
, TX_PWR_CFG_3_MCS13
, value
);
954 rt2x00_set_field32(®
, TX_PWR_CFG_3_MCS14
, value
);
955 rt2x00_set_field32(®
, TX_PWR_CFG_3_MCS15
, value
);
956 rt2x00_set_field32(®
, TX_PWR_CFG_3_UKNOWN1
, value
);
957 rt2x00_set_field32(®
, TX_PWR_CFG_3_UKNOWN2
, value
);
958 rt2x00_set_field32(®
, TX_PWR_CFG_3_UKNOWN3
, value
);
959 rt2x00_set_field32(®
, TX_PWR_CFG_3_UKNOWN4
, value
);
960 rt2800_register_write(rt2x00dev
, TX_PWR_CFG_3
, reg
);
962 rt2800_register_read(rt2x00dev
, TX_PWR_CFG_4
, ®
);
963 rt2x00_set_field32(®
, TX_PWR_CFG_4_UKNOWN5
, value
);
964 rt2x00_set_field32(®
, TX_PWR_CFG_4_UKNOWN6
, value
);
965 rt2x00_set_field32(®
, TX_PWR_CFG_4_UKNOWN7
, value
);
966 rt2x00_set_field32(®
, TX_PWR_CFG_4_UKNOWN8
, value
);
967 rt2800_register_write(rt2x00dev
, TX_PWR_CFG_4
, reg
);
970 static void rt2800_config_retry_limit(struct rt2x00_dev
*rt2x00dev
,
971 struct rt2x00lib_conf
*libconf
)
975 rt2800_register_read(rt2x00dev
, TX_RTY_CFG
, ®
);
976 rt2x00_set_field32(®
, TX_RTY_CFG_SHORT_RTY_LIMIT
,
977 libconf
->conf
->short_frame_max_tx_count
);
978 rt2x00_set_field32(®
, TX_RTY_CFG_LONG_RTY_LIMIT
,
979 libconf
->conf
->long_frame_max_tx_count
);
980 rt2800_register_write(rt2x00dev
, TX_RTY_CFG
, reg
);
983 static void rt2800_config_ps(struct rt2x00_dev
*rt2x00dev
,
984 struct rt2x00lib_conf
*libconf
)
986 enum dev_state state
=
987 (libconf
->conf
->flags
& IEEE80211_CONF_PS
) ?
988 STATE_SLEEP
: STATE_AWAKE
;
991 if (state
== STATE_SLEEP
) {
992 rt2800_register_write(rt2x00dev
, AUTOWAKEUP_CFG
, 0);
994 rt2800_register_read(rt2x00dev
, AUTOWAKEUP_CFG
, ®
);
995 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_AUTO_LEAD_TIME
, 5);
996 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE
,
997 libconf
->conf
->listen_interval
- 1);
998 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_AUTOWAKE
, 1);
999 rt2800_register_write(rt2x00dev
, AUTOWAKEUP_CFG
, reg
);
1001 rt2x00dev
->ops
->lib
->set_device_state(rt2x00dev
, state
);
1003 rt2800_register_read(rt2x00dev
, AUTOWAKEUP_CFG
, ®
);
1004 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_AUTO_LEAD_TIME
, 0);
1005 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE
, 0);
1006 rt2x00_set_field32(®
, AUTOWAKEUP_CFG_AUTOWAKE
, 0);
1007 rt2800_register_write(rt2x00dev
, AUTOWAKEUP_CFG
, reg
);
1009 rt2x00dev
->ops
->lib
->set_device_state(rt2x00dev
, state
);
1013 void rt2800_config(struct rt2x00_dev
*rt2x00dev
,
1014 struct rt2x00lib_conf
*libconf
,
1015 const unsigned int flags
)
1017 /* Always recalculate LNA gain before changing configuration */
1018 rt2800_config_lna_gain(rt2x00dev
, libconf
);
1020 if (flags
& IEEE80211_CONF_CHANGE_CHANNEL
)
1021 rt2800_config_channel(rt2x00dev
, libconf
->conf
,
1022 &libconf
->rf
, &libconf
->channel
);
1023 if (flags
& IEEE80211_CONF_CHANGE_POWER
)
1024 rt2800_config_txpower(rt2x00dev
, libconf
->conf
->power_level
);
1025 if (flags
& IEEE80211_CONF_CHANGE_RETRY_LIMITS
)
1026 rt2800_config_retry_limit(rt2x00dev
, libconf
);
1027 if (flags
& IEEE80211_CONF_CHANGE_PS
)
1028 rt2800_config_ps(rt2x00dev
, libconf
);
1030 EXPORT_SYMBOL_GPL(rt2800_config
);
1035 void rt2800_link_stats(struct rt2x00_dev
*rt2x00dev
, struct link_qual
*qual
)
1040 * Update FCS error count from register.
1042 rt2800_register_read(rt2x00dev
, RX_STA_CNT0
, ®
);
1043 qual
->rx_failed
= rt2x00_get_field32(reg
, RX_STA_CNT0_CRC_ERR
);
1045 EXPORT_SYMBOL_GPL(rt2800_link_stats
);
1047 static u8
rt2800_get_default_vgc(struct rt2x00_dev
*rt2x00dev
)
1049 if (rt2x00dev
->curr_band
== IEEE80211_BAND_2GHZ
) {
1050 if (rt2x00_rt(rt2x00dev
, RT3070
) ||
1051 rt2x00_rt(rt2x00dev
, RT3071
) ||
1052 rt2x00_rt(rt2x00dev
, RT3090
) ||
1053 rt2x00_rt(rt2x00dev
, RT3390
))
1054 return 0x1c + (2 * rt2x00dev
->lna_gain
);
1056 return 0x2e + rt2x00dev
->lna_gain
;
1059 if (!test_bit(CONFIG_CHANNEL_HT40
, &rt2x00dev
->flags
))
1060 return 0x32 + (rt2x00dev
->lna_gain
* 5) / 3;
1062 return 0x3a + (rt2x00dev
->lna_gain
* 5) / 3;
1065 static inline void rt2800_set_vgc(struct rt2x00_dev
*rt2x00dev
,
1066 struct link_qual
*qual
, u8 vgc_level
)
1068 if (qual
->vgc_level
!= vgc_level
) {
1069 rt2800_bbp_write(rt2x00dev
, 66, vgc_level
);
1070 qual
->vgc_level
= vgc_level
;
1071 qual
->vgc_level_reg
= vgc_level
;
1075 void rt2800_reset_tuner(struct rt2x00_dev
*rt2x00dev
, struct link_qual
*qual
)
1077 rt2800_set_vgc(rt2x00dev
, qual
, rt2800_get_default_vgc(rt2x00dev
));
1079 EXPORT_SYMBOL_GPL(rt2800_reset_tuner
);
1081 void rt2800_link_tuner(struct rt2x00_dev
*rt2x00dev
, struct link_qual
*qual
,
1084 if (rt2x00_rt_rev(rt2x00dev
, RT2860
, REV_RT2860C
))
1088 * When RSSI is better then -80 increase VGC level with 0x10
1090 rt2800_set_vgc(rt2x00dev
, qual
,
1091 rt2800_get_default_vgc(rt2x00dev
) +
1092 ((qual
->rssi
> -80) * 0x10));
1094 EXPORT_SYMBOL_GPL(rt2800_link_tuner
);
1097 * Initialization functions.
1099 int rt2800_init_registers(struct rt2x00_dev
*rt2x00dev
)
1105 rt2800_register_read(rt2x00dev
, WPDMA_GLO_CFG
, ®
);
1106 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_TX_DMA
, 0);
1107 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_DMA_BUSY
, 0);
1108 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_RX_DMA
, 0);
1109 rt2x00_set_field32(®
, WPDMA_GLO_CFG_RX_DMA_BUSY
, 0);
1110 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_WRITEBACK_DONE
, 1);
1111 rt2800_register_write(rt2x00dev
, WPDMA_GLO_CFG
, reg
);
1113 if (rt2x00_is_usb(rt2x00dev
)) {
1115 * Wait until BBP and RF are ready.
1117 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
1118 rt2800_register_read(rt2x00dev
, MAC_CSR0
, ®
);
1119 if (reg
&& reg
!= ~0)
1124 if (i
== REGISTER_BUSY_COUNT
) {
1125 ERROR(rt2x00dev
, "Unstable hardware.\n");
1129 rt2800_register_read(rt2x00dev
, PBF_SYS_CTRL
, ®
);
1130 rt2800_register_write(rt2x00dev
, PBF_SYS_CTRL
,
1132 } else if (rt2x00_is_pci(rt2x00dev
) || rt2x00_is_soc(rt2x00dev
)) {
1136 rt2800_register_read(rt2x00dev
, WPDMA_RST_IDX
, ®
);
1137 rt2x00_set_field32(®
, WPDMA_RST_IDX_DTX_IDX0
, 1);
1138 rt2x00_set_field32(®
, WPDMA_RST_IDX_DTX_IDX1
, 1);
1139 rt2x00_set_field32(®
, WPDMA_RST_IDX_DTX_IDX2
, 1);
1140 rt2x00_set_field32(®
, WPDMA_RST_IDX_DTX_IDX3
, 1);
1141 rt2x00_set_field32(®
, WPDMA_RST_IDX_DTX_IDX4
, 1);
1142 rt2x00_set_field32(®
, WPDMA_RST_IDX_DTX_IDX5
, 1);
1143 rt2x00_set_field32(®
, WPDMA_RST_IDX_DRX_IDX0
, 1);
1144 rt2800_register_write(rt2x00dev
, WPDMA_RST_IDX
, reg
);
1146 rt2800_register_write(rt2x00dev
, PBF_SYS_CTRL
, 0x00000e1f);
1147 rt2800_register_write(rt2x00dev
, PBF_SYS_CTRL
, 0x00000e00);
1149 rt2800_register_write(rt2x00dev
, PWR_PIN_CFG
, 0x00000003);
1152 rt2800_register_read(rt2x00dev
, MAC_SYS_CTRL
, ®
);
1153 rt2x00_set_field32(®
, MAC_SYS_CTRL_RESET_CSR
, 1);
1154 rt2x00_set_field32(®
, MAC_SYS_CTRL_RESET_BBP
, 1);
1155 rt2800_register_write(rt2x00dev
, MAC_SYS_CTRL
, reg
);
1157 if (rt2x00_is_usb(rt2x00dev
)) {
1158 rt2800_register_write(rt2x00dev
, USB_DMA_CFG
, 0x00000000);
1159 #if defined(CONFIG_RT2X00_LIB_USB) || defined(CONFIG_RT2X00_LIB_USB_MODULE)
1160 rt2x00usb_vendor_request_sw(rt2x00dev
, USB_DEVICE_MODE
, 0,
1161 USB_MODE_RESET
, REGISTER_TIMEOUT
);
1165 rt2800_register_write(rt2x00dev
, MAC_SYS_CTRL
, 0x00000000);
1167 rt2800_register_read(rt2x00dev
, BCN_OFFSET0
, ®
);
1168 rt2x00_set_field32(®
, BCN_OFFSET0_BCN0
, 0xe0); /* 0x3800 */
1169 rt2x00_set_field32(®
, BCN_OFFSET0_BCN1
, 0xe8); /* 0x3a00 */
1170 rt2x00_set_field32(®
, BCN_OFFSET0_BCN2
, 0xf0); /* 0x3c00 */
1171 rt2x00_set_field32(®
, BCN_OFFSET0_BCN3
, 0xf8); /* 0x3e00 */
1172 rt2800_register_write(rt2x00dev
, BCN_OFFSET0
, reg
);
1174 rt2800_register_read(rt2x00dev
, BCN_OFFSET1
, ®
);
1175 rt2x00_set_field32(®
, BCN_OFFSET1_BCN4
, 0xc8); /* 0x3200 */
1176 rt2x00_set_field32(®
, BCN_OFFSET1_BCN5
, 0xd0); /* 0x3400 */
1177 rt2x00_set_field32(®
, BCN_OFFSET1_BCN6
, 0x77); /* 0x1dc0 */
1178 rt2x00_set_field32(®
, BCN_OFFSET1_BCN7
, 0x6f); /* 0x1bc0 */
1179 rt2800_register_write(rt2x00dev
, BCN_OFFSET1
, reg
);
1181 rt2800_register_write(rt2x00dev
, LEGACY_BASIC_RATE
, 0x0000013f);
1182 rt2800_register_write(rt2x00dev
, HT_BASIC_RATE
, 0x00008003);
1184 rt2800_register_write(rt2x00dev
, MAC_SYS_CTRL
, 0x00000000);
1186 rt2800_register_read(rt2x00dev
, BCN_TIME_CFG
, ®
);
1187 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_INTERVAL
, 0);
1188 rt2x00_set_field32(®
, BCN_TIME_CFG_TSF_TICKING
, 0);
1189 rt2x00_set_field32(®
, BCN_TIME_CFG_TSF_SYNC
, 0);
1190 rt2x00_set_field32(®
, BCN_TIME_CFG_TBTT_ENABLE
, 0);
1191 rt2x00_set_field32(®
, BCN_TIME_CFG_BEACON_GEN
, 0);
1192 rt2x00_set_field32(®
, BCN_TIME_CFG_TX_TIME_COMPENSATE
, 0);
1193 rt2800_register_write(rt2x00dev
, BCN_TIME_CFG
, reg
);
1195 rt2800_config_filter(rt2x00dev
, FIF_ALLMULTI
);
1197 rt2800_register_read(rt2x00dev
, BKOFF_SLOT_CFG
, ®
);
1198 rt2x00_set_field32(®
, BKOFF_SLOT_CFG_SLOT_TIME
, 9);
1199 rt2x00_set_field32(®
, BKOFF_SLOT_CFG_CC_DELAY_TIME
, 2);
1200 rt2800_register_write(rt2x00dev
, BKOFF_SLOT_CFG
, reg
);
1202 if (rt2x00_rt(rt2x00dev
, RT3071
) ||
1203 rt2x00_rt(rt2x00dev
, RT3090
) ||
1204 rt2x00_rt(rt2x00dev
, RT3390
)) {
1205 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000400);
1206 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00000000);
1207 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3071
, REV_RT3071E
) ||
1208 rt2x00_rt_rev_lt(rt2x00dev
, RT3090
, REV_RT3090E
) ||
1209 rt2x00_rt_rev_lt(rt2x00dev
, RT3390
, REV_RT3390E
)) {
1210 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC
, &eeprom
);
1211 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_DAC_TEST
))
1212 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
,
1215 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
,
1218 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
, 0x00000000);
1220 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
, reg
);
1221 } else if (rt2x00_rt(rt2x00dev
, RT3070
)) {
1222 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000400);
1224 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3070
, REV_RT3070F
)) {
1225 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00000000);
1226 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
, 0x0000002c);
1228 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00080606);
1229 rt2800_register_write(rt2x00dev
, TX_SW_CFG2
, 0x00000000);
1232 rt2800_register_write(rt2x00dev
, TX_SW_CFG0
, 0x00000000);
1233 rt2800_register_write(rt2x00dev
, TX_SW_CFG1
, 0x00080606);
1236 rt2800_register_read(rt2x00dev
, TX_LINK_CFG
, ®
);
1237 rt2x00_set_field32(®
, TX_LINK_CFG_REMOTE_MFB_LIFETIME
, 32);
1238 rt2x00_set_field32(®
, TX_LINK_CFG_MFB_ENABLE
, 0);
1239 rt2x00_set_field32(®
, TX_LINK_CFG_REMOTE_UMFS_ENABLE
, 0);
1240 rt2x00_set_field32(®
, TX_LINK_CFG_TX_MRQ_EN
, 0);
1241 rt2x00_set_field32(®
, TX_LINK_CFG_TX_RDG_EN
, 0);
1242 rt2x00_set_field32(®
, TX_LINK_CFG_TX_CF_ACK_EN
, 1);
1243 rt2x00_set_field32(®
, TX_LINK_CFG_REMOTE_MFB
, 0);
1244 rt2x00_set_field32(®
, TX_LINK_CFG_REMOTE_MFS
, 0);
1245 rt2800_register_write(rt2x00dev
, TX_LINK_CFG
, reg
);
1247 rt2800_register_read(rt2x00dev
, TX_TIMEOUT_CFG
, ®
);
1248 rt2x00_set_field32(®
, TX_TIMEOUT_CFG_MPDU_LIFETIME
, 9);
1249 rt2x00_set_field32(®
, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT
, 32);
1250 rt2x00_set_field32(®
, TX_TIMEOUT_CFG_TX_OP_TIMEOUT
, 10);
1251 rt2800_register_write(rt2x00dev
, TX_TIMEOUT_CFG
, reg
);
1253 rt2800_register_read(rt2x00dev
, MAX_LEN_CFG
, ®
);
1254 rt2x00_set_field32(®
, MAX_LEN_CFG_MAX_MPDU
, AGGREGATION_SIZE
);
1255 if (rt2x00_rt_rev_gte(rt2x00dev
, RT2872
, REV_RT2872E
) ||
1256 rt2x00_rt(rt2x00dev
, RT2883
) ||
1257 rt2x00_rt_rev_lt(rt2x00dev
, RT3070
, REV_RT3070E
))
1258 rt2x00_set_field32(®
, MAX_LEN_CFG_MAX_PSDU
, 2);
1260 rt2x00_set_field32(®
, MAX_LEN_CFG_MAX_PSDU
, 1);
1261 rt2x00_set_field32(®
, MAX_LEN_CFG_MIN_PSDU
, 0);
1262 rt2x00_set_field32(®
, MAX_LEN_CFG_MIN_MPDU
, 0);
1263 rt2800_register_write(rt2x00dev
, MAX_LEN_CFG
, reg
);
1265 rt2800_register_read(rt2x00dev
, LED_CFG
, ®
);
1266 rt2x00_set_field32(®
, LED_CFG_ON_PERIOD
, 70);
1267 rt2x00_set_field32(®
, LED_CFG_OFF_PERIOD
, 30);
1268 rt2x00_set_field32(®
, LED_CFG_SLOW_BLINK_PERIOD
, 3);
1269 rt2x00_set_field32(®
, LED_CFG_R_LED_MODE
, 3);
1270 rt2x00_set_field32(®
, LED_CFG_G_LED_MODE
, 3);
1271 rt2x00_set_field32(®
, LED_CFG_Y_LED_MODE
, 3);
1272 rt2x00_set_field32(®
, LED_CFG_LED_POLAR
, 1);
1273 rt2800_register_write(rt2x00dev
, LED_CFG
, reg
);
1275 rt2800_register_write(rt2x00dev
, PBF_MAX_PCNT
, 0x1f3fbf9f);
1277 rt2800_register_read(rt2x00dev
, TX_RTY_CFG
, ®
);
1278 rt2x00_set_field32(®
, TX_RTY_CFG_SHORT_RTY_LIMIT
, 15);
1279 rt2x00_set_field32(®
, TX_RTY_CFG_LONG_RTY_LIMIT
, 31);
1280 rt2x00_set_field32(®
, TX_RTY_CFG_LONG_RTY_THRE
, 2000);
1281 rt2x00_set_field32(®
, TX_RTY_CFG_NON_AGG_RTY_MODE
, 0);
1282 rt2x00_set_field32(®
, TX_RTY_CFG_AGG_RTY_MODE
, 0);
1283 rt2x00_set_field32(®
, TX_RTY_CFG_TX_AUTO_FB_ENABLE
, 1);
1284 rt2800_register_write(rt2x00dev
, TX_RTY_CFG
, reg
);
1286 rt2800_register_read(rt2x00dev
, AUTO_RSP_CFG
, ®
);
1287 rt2x00_set_field32(®
, AUTO_RSP_CFG_AUTORESPONDER
, 1);
1288 rt2x00_set_field32(®
, AUTO_RSP_CFG_BAC_ACK_POLICY
, 1);
1289 rt2x00_set_field32(®
, AUTO_RSP_CFG_CTS_40_MMODE
, 0);
1290 rt2x00_set_field32(®
, AUTO_RSP_CFG_CTS_40_MREF
, 0);
1291 rt2x00_set_field32(®
, AUTO_RSP_CFG_AR_PREAMBLE
, 1);
1292 rt2x00_set_field32(®
, AUTO_RSP_CFG_DUAL_CTS_EN
, 0);
1293 rt2x00_set_field32(®
, AUTO_RSP_CFG_ACK_CTS_PSM_BIT
, 0);
1294 rt2800_register_write(rt2x00dev
, AUTO_RSP_CFG
, reg
);
1296 rt2800_register_read(rt2x00dev
, CCK_PROT_CFG
, ®
);
1297 rt2x00_set_field32(®
, CCK_PROT_CFG_PROTECT_RATE
, 3);
1298 rt2x00_set_field32(®
, CCK_PROT_CFG_PROTECT_CTRL
, 0);
1299 rt2x00_set_field32(®
, CCK_PROT_CFG_PROTECT_NAV
, 1);
1300 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
1301 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
1302 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
1303 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_MM40
, 0);
1304 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
1305 rt2x00_set_field32(®
, CCK_PROT_CFG_TX_OP_ALLOW_GF40
, 0);
1306 rt2x00_set_field32(®
, CCK_PROT_CFG_RTS_TH_EN
, 1);
1307 rt2800_register_write(rt2x00dev
, CCK_PROT_CFG
, reg
);
1309 rt2800_register_read(rt2x00dev
, OFDM_PROT_CFG
, ®
);
1310 rt2x00_set_field32(®
, OFDM_PROT_CFG_PROTECT_RATE
, 3);
1311 rt2x00_set_field32(®
, OFDM_PROT_CFG_PROTECT_CTRL
, 0);
1312 rt2x00_set_field32(®
, OFDM_PROT_CFG_PROTECT_NAV
, 1);
1313 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
1314 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
1315 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
1316 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_MM40
, 0);
1317 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
1318 rt2x00_set_field32(®
, OFDM_PROT_CFG_TX_OP_ALLOW_GF40
, 0);
1319 rt2x00_set_field32(®
, OFDM_PROT_CFG_RTS_TH_EN
, 1);
1320 rt2800_register_write(rt2x00dev
, OFDM_PROT_CFG
, reg
);
1322 rt2800_register_read(rt2x00dev
, MM20_PROT_CFG
, ®
);
1323 rt2x00_set_field32(®
, MM20_PROT_CFG_PROTECT_RATE
, 0x4004);
1324 rt2x00_set_field32(®
, MM20_PROT_CFG_PROTECT_CTRL
, 0);
1325 rt2x00_set_field32(®
, MM20_PROT_CFG_PROTECT_NAV
, 1);
1326 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
1327 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
1328 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
1329 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_MM40
, 0);
1330 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
1331 rt2x00_set_field32(®
, MM20_PROT_CFG_TX_OP_ALLOW_GF40
, 0);
1332 rt2x00_set_field32(®
, MM20_PROT_CFG_RTS_TH_EN
, 0);
1333 rt2800_register_write(rt2x00dev
, MM20_PROT_CFG
, reg
);
1335 rt2800_register_read(rt2x00dev
, MM40_PROT_CFG
, ®
);
1336 rt2x00_set_field32(®
, MM40_PROT_CFG_PROTECT_RATE
, 0x4084);
1337 rt2x00_set_field32(®
, MM40_PROT_CFG_PROTECT_CTRL
,
1338 !rt2x00_is_usb(rt2x00dev
));
1339 rt2x00_set_field32(®
, MM40_PROT_CFG_PROTECT_NAV
, 1);
1340 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
1341 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
1342 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
1343 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_MM40
, 1);
1344 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
1345 rt2x00_set_field32(®
, MM40_PROT_CFG_TX_OP_ALLOW_GF40
, 1);
1346 rt2x00_set_field32(®
, MM40_PROT_CFG_RTS_TH_EN
, 0);
1347 rt2800_register_write(rt2x00dev
, MM40_PROT_CFG
, reg
);
1349 rt2800_register_read(rt2x00dev
, GF20_PROT_CFG
, ®
);
1350 rt2x00_set_field32(®
, GF20_PROT_CFG_PROTECT_RATE
, 0x4004);
1351 rt2x00_set_field32(®
, GF20_PROT_CFG_PROTECT_CTRL
, 0);
1352 rt2x00_set_field32(®
, GF20_PROT_CFG_PROTECT_NAV
, 1);
1353 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
1354 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
1355 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
1356 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_MM40
, 0);
1357 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
1358 rt2x00_set_field32(®
, GF20_PROT_CFG_TX_OP_ALLOW_GF40
, 0);
1359 rt2x00_set_field32(®
, GF20_PROT_CFG_RTS_TH_EN
, 0);
1360 rt2800_register_write(rt2x00dev
, GF20_PROT_CFG
, reg
);
1362 rt2800_register_read(rt2x00dev
, GF40_PROT_CFG
, ®
);
1363 rt2x00_set_field32(®
, GF40_PROT_CFG_PROTECT_RATE
, 0x4084);
1364 rt2x00_set_field32(®
, GF40_PROT_CFG_PROTECT_CTRL
, 0);
1365 rt2x00_set_field32(®
, GF40_PROT_CFG_PROTECT_NAV
, 1);
1366 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_CCK
, 1);
1367 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_OFDM
, 1);
1368 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_MM20
, 1);
1369 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_MM40
, 1);
1370 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_GF20
, 1);
1371 rt2x00_set_field32(®
, GF40_PROT_CFG_TX_OP_ALLOW_GF40
, 1);
1372 rt2x00_set_field32(®
, GF40_PROT_CFG_RTS_TH_EN
, 0);
1373 rt2800_register_write(rt2x00dev
, GF40_PROT_CFG
, reg
);
1375 if (rt2x00_is_usb(rt2x00dev
)) {
1376 rt2800_register_write(rt2x00dev
, PBF_CFG
, 0xf40006);
1378 rt2800_register_read(rt2x00dev
, WPDMA_GLO_CFG
, ®
);
1379 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_TX_DMA
, 0);
1380 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_DMA_BUSY
, 0);
1381 rt2x00_set_field32(®
, WPDMA_GLO_CFG_ENABLE_RX_DMA
, 0);
1382 rt2x00_set_field32(®
, WPDMA_GLO_CFG_RX_DMA_BUSY
, 0);
1383 rt2x00_set_field32(®
, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE
, 3);
1384 rt2x00_set_field32(®
, WPDMA_GLO_CFG_TX_WRITEBACK_DONE
, 0);
1385 rt2x00_set_field32(®
, WPDMA_GLO_CFG_BIG_ENDIAN
, 0);
1386 rt2x00_set_field32(®
, WPDMA_GLO_CFG_RX_HDR_SCATTER
, 0);
1387 rt2x00_set_field32(®
, WPDMA_GLO_CFG_HDR_SEG_LEN
, 0);
1388 rt2800_register_write(rt2x00dev
, WPDMA_GLO_CFG
, reg
);
1391 rt2800_register_write(rt2x00dev
, TXOP_CTRL_CFG
, 0x0000583f);
1392 rt2800_register_write(rt2x00dev
, TXOP_HLDR_ET
, 0x00000002);
1394 rt2800_register_read(rt2x00dev
, TX_RTS_CFG
, ®
);
1395 rt2x00_set_field32(®
, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT
, 32);
1396 rt2x00_set_field32(®
, TX_RTS_CFG_RTS_THRES
,
1397 IEEE80211_MAX_RTS_THRESHOLD
);
1398 rt2x00_set_field32(®
, TX_RTS_CFG_RTS_FBK_EN
, 0);
1399 rt2800_register_write(rt2x00dev
, TX_RTS_CFG
, reg
);
1401 rt2800_register_write(rt2x00dev
, EXP_ACK_TIME
, 0x002400ca);
1403 rt2800_register_read(rt2x00dev
, XIFS_TIME_CFG
, ®
);
1404 rt2x00_set_field32(®
, XIFS_TIME_CFG_CCKM_SIFS_TIME
, 32);
1405 rt2x00_set_field32(®
, XIFS_TIME_CFG_OFDM_SIFS_TIME
, 32);
1406 rt2x00_set_field32(®
, XIFS_TIME_CFG_OFDM_XIFS_TIME
, 4);
1407 rt2x00_set_field32(®
, XIFS_TIME_CFG_EIFS
, 314);
1408 rt2x00_set_field32(®
, XIFS_TIME_CFG_BB_RXEND_ENABLE
, 1);
1409 rt2800_register_write(rt2x00dev
, XIFS_TIME_CFG
, reg
);
1411 rt2800_register_write(rt2x00dev
, PWR_PIN_CFG
, 0x00000003);
1414 * ASIC will keep garbage value after boot, clear encryption keys.
1416 for (i
= 0; i
< 4; i
++)
1417 rt2800_register_write(rt2x00dev
,
1418 SHARED_KEY_MODE_ENTRY(i
), 0);
1420 for (i
= 0; i
< 256; i
++) {
1421 u32 wcid
[2] = { 0xffffffff, 0x00ffffff };
1422 rt2800_register_multiwrite(rt2x00dev
, MAC_WCID_ENTRY(i
),
1423 wcid
, sizeof(wcid
));
1425 rt2800_register_write(rt2x00dev
, MAC_WCID_ATTR_ENTRY(i
), 1);
1426 rt2800_register_write(rt2x00dev
, MAC_IVEIV_ENTRY(i
), 0);
1431 * For the Beacon base registers we only need to clear
1432 * the first byte since that byte contains the VALID and OWNER
1433 * bits which (when set to 0) will invalidate the entire beacon.
1435 rt2800_register_write(rt2x00dev
, HW_BEACON_BASE0
, 0);
1436 rt2800_register_write(rt2x00dev
, HW_BEACON_BASE1
, 0);
1437 rt2800_register_write(rt2x00dev
, HW_BEACON_BASE2
, 0);
1438 rt2800_register_write(rt2x00dev
, HW_BEACON_BASE3
, 0);
1439 rt2800_register_write(rt2x00dev
, HW_BEACON_BASE4
, 0);
1440 rt2800_register_write(rt2x00dev
, HW_BEACON_BASE5
, 0);
1441 rt2800_register_write(rt2x00dev
, HW_BEACON_BASE6
, 0);
1442 rt2800_register_write(rt2x00dev
, HW_BEACON_BASE7
, 0);
1444 if (rt2x00_is_usb(rt2x00dev
)) {
1445 rt2800_register_read(rt2x00dev
, USB_CYC_CFG
, ®
);
1446 rt2x00_set_field32(®
, USB_CYC_CFG_CLOCK_CYCLE
, 30);
1447 rt2800_register_write(rt2x00dev
, USB_CYC_CFG
, reg
);
1450 rt2800_register_read(rt2x00dev
, HT_FBK_CFG0
, ®
);
1451 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS0FBK
, 0);
1452 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS1FBK
, 0);
1453 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS2FBK
, 1);
1454 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS3FBK
, 2);
1455 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS4FBK
, 3);
1456 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS5FBK
, 4);
1457 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS6FBK
, 5);
1458 rt2x00_set_field32(®
, HT_FBK_CFG0_HTMCS7FBK
, 6);
1459 rt2800_register_write(rt2x00dev
, HT_FBK_CFG0
, reg
);
1461 rt2800_register_read(rt2x00dev
, HT_FBK_CFG1
, ®
);
1462 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS8FBK
, 8);
1463 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS9FBK
, 8);
1464 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS10FBK
, 9);
1465 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS11FBK
, 10);
1466 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS12FBK
, 11);
1467 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS13FBK
, 12);
1468 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS14FBK
, 13);
1469 rt2x00_set_field32(®
, HT_FBK_CFG1_HTMCS15FBK
, 14);
1470 rt2800_register_write(rt2x00dev
, HT_FBK_CFG1
, reg
);
1472 rt2800_register_read(rt2x00dev
, LG_FBK_CFG0
, ®
);
1473 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS0FBK
, 8);
1474 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS1FBK
, 8);
1475 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS2FBK
, 9);
1476 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS3FBK
, 10);
1477 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS4FBK
, 11);
1478 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS5FBK
, 12);
1479 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS6FBK
, 13);
1480 rt2x00_set_field32(®
, LG_FBK_CFG0_OFDMMCS7FBK
, 14);
1481 rt2800_register_write(rt2x00dev
, LG_FBK_CFG0
, reg
);
1483 rt2800_register_read(rt2x00dev
, LG_FBK_CFG1
, ®
);
1484 rt2x00_set_field32(®
, LG_FBK_CFG0_CCKMCS0FBK
, 0);
1485 rt2x00_set_field32(®
, LG_FBK_CFG0_CCKMCS1FBK
, 0);
1486 rt2x00_set_field32(®
, LG_FBK_CFG0_CCKMCS2FBK
, 1);
1487 rt2x00_set_field32(®
, LG_FBK_CFG0_CCKMCS3FBK
, 2);
1488 rt2800_register_write(rt2x00dev
, LG_FBK_CFG1
, reg
);
1491 * We must clear the error counters.
1492 * These registers are cleared on read,
1493 * so we may pass a useless variable to store the value.
1495 rt2800_register_read(rt2x00dev
, RX_STA_CNT0
, ®
);
1496 rt2800_register_read(rt2x00dev
, RX_STA_CNT1
, ®
);
1497 rt2800_register_read(rt2x00dev
, RX_STA_CNT2
, ®
);
1498 rt2800_register_read(rt2x00dev
, TX_STA_CNT0
, ®
);
1499 rt2800_register_read(rt2x00dev
, TX_STA_CNT1
, ®
);
1500 rt2800_register_read(rt2x00dev
, TX_STA_CNT2
, ®
);
1504 EXPORT_SYMBOL_GPL(rt2800_init_registers
);
1506 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev
*rt2x00dev
)
1511 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
1512 rt2800_register_read(rt2x00dev
, MAC_STATUS_CFG
, ®
);
1513 if (!rt2x00_get_field32(reg
, MAC_STATUS_CFG_BBP_RF_BUSY
))
1516 udelay(REGISTER_BUSY_DELAY
);
1519 ERROR(rt2x00dev
, "BBP/RF register access failed, aborting.\n");
1523 static int rt2800_wait_bbp_ready(struct rt2x00_dev
*rt2x00dev
)
1529 * BBP was enabled after firmware was loaded,
1530 * but we need to reactivate it now.
1532 rt2800_register_write(rt2x00dev
, H2M_BBP_AGENT
, 0);
1533 rt2800_register_write(rt2x00dev
, H2M_MAILBOX_CSR
, 0);
1536 for (i
= 0; i
< REGISTER_BUSY_COUNT
; i
++) {
1537 rt2800_bbp_read(rt2x00dev
, 0, &value
);
1538 if ((value
!= 0xff) && (value
!= 0x00))
1540 udelay(REGISTER_BUSY_DELAY
);
1543 ERROR(rt2x00dev
, "BBP register access failed, aborting.\n");
1547 int rt2800_init_bbp(struct rt2x00_dev
*rt2x00dev
)
1554 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev
) ||
1555 rt2800_wait_bbp_ready(rt2x00dev
)))
1558 rt2800_bbp_write(rt2x00dev
, 65, 0x2c);
1559 rt2800_bbp_write(rt2x00dev
, 66, 0x38);
1561 if (rt2x00_rt_rev(rt2x00dev
, RT2860
, REV_RT2860C
)) {
1562 rt2800_bbp_write(rt2x00dev
, 69, 0x16);
1563 rt2800_bbp_write(rt2x00dev
, 73, 0x12);
1565 rt2800_bbp_write(rt2x00dev
, 69, 0x12);
1566 rt2800_bbp_write(rt2x00dev
, 73, 0x10);
1569 rt2800_bbp_write(rt2x00dev
, 70, 0x0a);
1571 if (rt2x00_rt(rt2x00dev
, RT3070
) ||
1572 rt2x00_rt(rt2x00dev
, RT3071
) ||
1573 rt2x00_rt(rt2x00dev
, RT3090
) ||
1574 rt2x00_rt(rt2x00dev
, RT3390
)) {
1575 rt2800_bbp_write(rt2x00dev
, 79, 0x13);
1576 rt2800_bbp_write(rt2x00dev
, 80, 0x05);
1577 rt2800_bbp_write(rt2x00dev
, 81, 0x33);
1579 rt2800_bbp_write(rt2x00dev
, 81, 0x37);
1582 rt2800_bbp_write(rt2x00dev
, 82, 0x62);
1583 rt2800_bbp_write(rt2x00dev
, 83, 0x6a);
1585 if (rt2x00_rt_rev(rt2x00dev
, RT2860
, REV_RT2860D
) ||
1586 rt2x00_rt_rev(rt2x00dev
, RT2870
, REV_RT2870D
))
1587 rt2800_bbp_write(rt2x00dev
, 84, 0x19);
1589 rt2800_bbp_write(rt2x00dev
, 84, 0x99);
1591 rt2800_bbp_write(rt2x00dev
, 86, 0x00);
1592 rt2800_bbp_write(rt2x00dev
, 91, 0x04);
1593 rt2800_bbp_write(rt2x00dev
, 92, 0x00);
1595 if (rt2x00_rt_rev_gte(rt2x00dev
, RT3070
, REV_RT3070F
) ||
1596 rt2x00_rt_rev_gte(rt2x00dev
, RT3071
, REV_RT3071E
) ||
1597 rt2x00_rt_rev_gte(rt2x00dev
, RT3090
, REV_RT3090E
) ||
1598 rt2x00_rt_rev_gte(rt2x00dev
, RT3390
, REV_RT3390E
))
1599 rt2800_bbp_write(rt2x00dev
, 103, 0xc0);
1601 rt2800_bbp_write(rt2x00dev
, 103, 0x00);
1603 rt2800_bbp_write(rt2x00dev
, 105, 0x05);
1604 rt2800_bbp_write(rt2x00dev
, 106, 0x35);
1606 if (rt2x00_rt(rt2x00dev
, RT3071
) ||
1607 rt2x00_rt(rt2x00dev
, RT3090
) ||
1608 rt2x00_rt(rt2x00dev
, RT3390
)) {
1609 rt2800_bbp_read(rt2x00dev
, 138, &value
);
1611 rt2x00_eeprom_read(rt2x00dev
, EEPROM_ANTENNA
, &eeprom
);
1612 if (rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_TXPATH
) == 1)
1614 if (rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_RXPATH
) == 1)
1617 rt2800_bbp_write(rt2x00dev
, 138, value
);
1620 if (rt2x00_rt(rt2x00dev
, RT2872
)) {
1621 rt2800_bbp_write(rt2x00dev
, 31, 0x08);
1622 rt2800_bbp_write(rt2x00dev
, 78, 0x0e);
1623 rt2800_bbp_write(rt2x00dev
, 80, 0x08);
1626 for (i
= 0; i
< EEPROM_BBP_SIZE
; i
++) {
1627 rt2x00_eeprom_read(rt2x00dev
, EEPROM_BBP_START
+ i
, &eeprom
);
1629 if (eeprom
!= 0xffff && eeprom
!= 0x0000) {
1630 reg_id
= rt2x00_get_field16(eeprom
, EEPROM_BBP_REG_ID
);
1631 value
= rt2x00_get_field16(eeprom
, EEPROM_BBP_VALUE
);
1632 rt2800_bbp_write(rt2x00dev
, reg_id
, value
);
1638 EXPORT_SYMBOL_GPL(rt2800_init_bbp
);
1640 static u8
rt2800_init_rx_filter(struct rt2x00_dev
*rt2x00dev
,
1641 bool bw40
, u8 rfcsr24
, u8 filter_target
)
1650 rt2800_rfcsr_write(rt2x00dev
, 24, rfcsr24
);
1652 rt2800_bbp_read(rt2x00dev
, 4, &bbp
);
1653 rt2x00_set_field8(&bbp
, BBP4_BANDWIDTH
, 2 * bw40
);
1654 rt2800_bbp_write(rt2x00dev
, 4, bbp
);
1656 rt2800_rfcsr_read(rt2x00dev
, 22, &rfcsr
);
1657 rt2x00_set_field8(&rfcsr
, RFCSR22_BASEBAND_LOOPBACK
, 1);
1658 rt2800_rfcsr_write(rt2x00dev
, 22, rfcsr
);
1661 * Set power & frequency of passband test tone
1663 rt2800_bbp_write(rt2x00dev
, 24, 0);
1665 for (i
= 0; i
< 100; i
++) {
1666 rt2800_bbp_write(rt2x00dev
, 25, 0x90);
1669 rt2800_bbp_read(rt2x00dev
, 55, &passband
);
1675 * Set power & frequency of stopband test tone
1677 rt2800_bbp_write(rt2x00dev
, 24, 0x06);
1679 for (i
= 0; i
< 100; i
++) {
1680 rt2800_bbp_write(rt2x00dev
, 25, 0x90);
1683 rt2800_bbp_read(rt2x00dev
, 55, &stopband
);
1685 if ((passband
- stopband
) <= filter_target
) {
1687 overtuned
+= ((passband
- stopband
) == filter_target
);
1691 rt2800_rfcsr_write(rt2x00dev
, 24, rfcsr24
);
1694 rfcsr24
-= !!overtuned
;
1696 rt2800_rfcsr_write(rt2x00dev
, 24, rfcsr24
);
1700 int rt2800_init_rfcsr(struct rt2x00_dev
*rt2x00dev
)
1707 if (!rt2x00_rt(rt2x00dev
, RT3070
) &&
1708 !rt2x00_rt(rt2x00dev
, RT3071
) &&
1709 !rt2x00_rt(rt2x00dev
, RT3090
) &&
1710 !rt2x00_rt(rt2x00dev
, RT3390
) &&
1711 !(rt2x00_is_soc(rt2x00dev
) && rt2x00_rt(rt2x00dev
, RT2872
)))
1715 * Init RF calibration.
1717 rt2800_rfcsr_read(rt2x00dev
, 30, &rfcsr
);
1718 rt2x00_set_field8(&rfcsr
, RFCSR30_RF_CALIBRATION
, 1);
1719 rt2800_rfcsr_write(rt2x00dev
, 30, rfcsr
);
1721 rt2x00_set_field8(&rfcsr
, RFCSR30_RF_CALIBRATION
, 0);
1722 rt2800_rfcsr_write(rt2x00dev
, 30, rfcsr
);
1724 if (rt2x00_rt(rt2x00dev
, RT3070
) ||
1725 rt2x00_rt(rt2x00dev
, RT3071
) ||
1726 rt2x00_rt(rt2x00dev
, RT3090
)) {
1727 rt2800_rfcsr_write(rt2x00dev
, 4, 0x40);
1728 rt2800_rfcsr_write(rt2x00dev
, 5, 0x03);
1729 rt2800_rfcsr_write(rt2x00dev
, 6, 0x02);
1730 rt2800_rfcsr_write(rt2x00dev
, 7, 0x70);
1731 rt2800_rfcsr_write(rt2x00dev
, 9, 0x0f);
1732 rt2800_rfcsr_write(rt2x00dev
, 10, 0x41);
1733 rt2800_rfcsr_write(rt2x00dev
, 11, 0x21);
1734 rt2800_rfcsr_write(rt2x00dev
, 12, 0x7b);
1735 rt2800_rfcsr_write(rt2x00dev
, 14, 0x90);
1736 rt2800_rfcsr_write(rt2x00dev
, 15, 0x58);
1737 rt2800_rfcsr_write(rt2x00dev
, 16, 0xb3);
1738 rt2800_rfcsr_write(rt2x00dev
, 17, 0x92);
1739 rt2800_rfcsr_write(rt2x00dev
, 18, 0x2c);
1740 rt2800_rfcsr_write(rt2x00dev
, 19, 0x02);
1741 rt2800_rfcsr_write(rt2x00dev
, 20, 0xba);
1742 rt2800_rfcsr_write(rt2x00dev
, 21, 0xdb);
1743 rt2800_rfcsr_write(rt2x00dev
, 24, 0x16);
1744 rt2800_rfcsr_write(rt2x00dev
, 25, 0x01);
1745 rt2800_rfcsr_write(rt2x00dev
, 29, 0x1f);
1746 } else if (rt2x00_rt(rt2x00dev
, RT3390
)) {
1747 rt2800_rfcsr_write(rt2x00dev
, 0, 0xa0);
1748 rt2800_rfcsr_write(rt2x00dev
, 1, 0xe1);
1749 rt2800_rfcsr_write(rt2x00dev
, 2, 0xf1);
1750 rt2800_rfcsr_write(rt2x00dev
, 3, 0x62);
1751 rt2800_rfcsr_write(rt2x00dev
, 4, 0x40);
1752 rt2800_rfcsr_write(rt2x00dev
, 5, 0x8b);
1753 rt2800_rfcsr_write(rt2x00dev
, 6, 0x42);
1754 rt2800_rfcsr_write(rt2x00dev
, 7, 0x34);
1755 rt2800_rfcsr_write(rt2x00dev
, 8, 0x00);
1756 rt2800_rfcsr_write(rt2x00dev
, 9, 0xc0);
1757 rt2800_rfcsr_write(rt2x00dev
, 10, 0x61);
1758 rt2800_rfcsr_write(rt2x00dev
, 11, 0x21);
1759 rt2800_rfcsr_write(rt2x00dev
, 12, 0x3b);
1760 rt2800_rfcsr_write(rt2x00dev
, 13, 0xe0);
1761 rt2800_rfcsr_write(rt2x00dev
, 14, 0x90);
1762 rt2800_rfcsr_write(rt2x00dev
, 15, 0x53);
1763 rt2800_rfcsr_write(rt2x00dev
, 16, 0xe0);
1764 rt2800_rfcsr_write(rt2x00dev
, 17, 0x94);
1765 rt2800_rfcsr_write(rt2x00dev
, 18, 0x5c);
1766 rt2800_rfcsr_write(rt2x00dev
, 19, 0x4a);
1767 rt2800_rfcsr_write(rt2x00dev
, 20, 0xb2);
1768 rt2800_rfcsr_write(rt2x00dev
, 21, 0xf6);
1769 rt2800_rfcsr_write(rt2x00dev
, 22, 0x00);
1770 rt2800_rfcsr_write(rt2x00dev
, 23, 0x14);
1771 rt2800_rfcsr_write(rt2x00dev
, 24, 0x08);
1772 rt2800_rfcsr_write(rt2x00dev
, 25, 0x3d);
1773 rt2800_rfcsr_write(rt2x00dev
, 26, 0x85);
1774 rt2800_rfcsr_write(rt2x00dev
, 27, 0x00);
1775 rt2800_rfcsr_write(rt2x00dev
, 28, 0x41);
1776 rt2800_rfcsr_write(rt2x00dev
, 29, 0x8f);
1777 rt2800_rfcsr_write(rt2x00dev
, 30, 0x20);
1778 rt2800_rfcsr_write(rt2x00dev
, 31, 0x0f);
1779 } else if (rt2x00_rt(rt2x00dev
, RT2872
)) {
1780 rt2800_rfcsr_write(rt2x00dev
, 0, 0x50);
1781 rt2800_rfcsr_write(rt2x00dev
, 1, 0x01);
1782 rt2800_rfcsr_write(rt2x00dev
, 2, 0xf7);
1783 rt2800_rfcsr_write(rt2x00dev
, 3, 0x75);
1784 rt2800_rfcsr_write(rt2x00dev
, 4, 0x40);
1785 rt2800_rfcsr_write(rt2x00dev
, 5, 0x03);
1786 rt2800_rfcsr_write(rt2x00dev
, 6, 0x02);
1787 rt2800_rfcsr_write(rt2x00dev
, 7, 0x50);
1788 rt2800_rfcsr_write(rt2x00dev
, 8, 0x39);
1789 rt2800_rfcsr_write(rt2x00dev
, 9, 0x0f);
1790 rt2800_rfcsr_write(rt2x00dev
, 10, 0x60);
1791 rt2800_rfcsr_write(rt2x00dev
, 11, 0x21);
1792 rt2800_rfcsr_write(rt2x00dev
, 12, 0x75);
1793 rt2800_rfcsr_write(rt2x00dev
, 13, 0x75);
1794 rt2800_rfcsr_write(rt2x00dev
, 14, 0x90);
1795 rt2800_rfcsr_write(rt2x00dev
, 15, 0x58);
1796 rt2800_rfcsr_write(rt2x00dev
, 16, 0xb3);
1797 rt2800_rfcsr_write(rt2x00dev
, 17, 0x92);
1798 rt2800_rfcsr_write(rt2x00dev
, 18, 0x2c);
1799 rt2800_rfcsr_write(rt2x00dev
, 19, 0x02);
1800 rt2800_rfcsr_write(rt2x00dev
, 20, 0xba);
1801 rt2800_rfcsr_write(rt2x00dev
, 21, 0xdb);
1802 rt2800_rfcsr_write(rt2x00dev
, 22, 0x00);
1803 rt2800_rfcsr_write(rt2x00dev
, 23, 0x31);
1804 rt2800_rfcsr_write(rt2x00dev
, 24, 0x08);
1805 rt2800_rfcsr_write(rt2x00dev
, 25, 0x01);
1806 rt2800_rfcsr_write(rt2x00dev
, 26, 0x25);
1807 rt2800_rfcsr_write(rt2x00dev
, 27, 0x23);
1808 rt2800_rfcsr_write(rt2x00dev
, 28, 0x13);
1809 rt2800_rfcsr_write(rt2x00dev
, 29, 0x83);
1812 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3070
, REV_RT3070F
)) {
1813 rt2800_register_read(rt2x00dev
, LDO_CFG0
, ®
);
1814 rt2x00_set_field32(®
, LDO_CFG0_BGSEL
, 1);
1815 rt2x00_set_field32(®
, LDO_CFG0_LDO_CORE_VLEVEL
, 3);
1816 rt2800_register_write(rt2x00dev
, LDO_CFG0
, reg
);
1817 } else if (rt2x00_rt(rt2x00dev
, RT3071
) ||
1818 rt2x00_rt(rt2x00dev
, RT3090
)) {
1819 rt2800_rfcsr_read(rt2x00dev
, 6, &rfcsr
);
1820 rt2x00_set_field8(&rfcsr
, RFCSR6_R2
, 1);
1821 rt2800_rfcsr_write(rt2x00dev
, 6, rfcsr
);
1823 rt2800_rfcsr_write(rt2x00dev
, 31, 0x14);
1825 rt2800_register_read(rt2x00dev
, LDO_CFG0
, ®
);
1826 rt2x00_set_field32(®
, LDO_CFG0_BGSEL
, 1);
1827 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3071
, REV_RT3071E
) ||
1828 rt2x00_rt_rev_lt(rt2x00dev
, RT3090
, REV_RT3090E
)) {
1829 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC
, &eeprom
);
1830 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_DAC_TEST
))
1831 rt2x00_set_field32(®
, LDO_CFG0_LDO_CORE_VLEVEL
, 3);
1833 rt2x00_set_field32(®
, LDO_CFG0_LDO_CORE_VLEVEL
, 0);
1835 rt2800_register_write(rt2x00dev
, LDO_CFG0
, reg
);
1836 } else if (rt2x00_rt(rt2x00dev
, RT3390
)) {
1837 rt2800_register_read(rt2x00dev
, GPIO_SWITCH
, ®
);
1838 rt2x00_set_field32(®
, GPIO_SWITCH_5
, 0);
1839 rt2800_register_write(rt2x00dev
, GPIO_SWITCH
, reg
);
1843 * Set RX Filter calibration for 20MHz and 40MHz
1845 if (rt2x00_rt(rt2x00dev
, RT3070
)) {
1846 rt2x00dev
->calibration
[0] =
1847 rt2800_init_rx_filter(rt2x00dev
, false, 0x07, 0x16);
1848 rt2x00dev
->calibration
[1] =
1849 rt2800_init_rx_filter(rt2x00dev
, true, 0x27, 0x19);
1850 } else if (rt2x00_rt(rt2x00dev
, RT3071
) ||
1851 rt2x00_rt(rt2x00dev
, RT3090
) ||
1852 rt2x00_rt(rt2x00dev
, RT3390
)) {
1853 rt2x00dev
->calibration
[0] =
1854 rt2800_init_rx_filter(rt2x00dev
, false, 0x07, 0x13);
1855 rt2x00dev
->calibration
[1] =
1856 rt2800_init_rx_filter(rt2x00dev
, true, 0x27, 0x15);
1860 * Set back to initial state
1862 rt2800_bbp_write(rt2x00dev
, 24, 0);
1864 rt2800_rfcsr_read(rt2x00dev
, 22, &rfcsr
);
1865 rt2x00_set_field8(&rfcsr
, RFCSR22_BASEBAND_LOOPBACK
, 0);
1866 rt2800_rfcsr_write(rt2x00dev
, 22, rfcsr
);
1869 * set BBP back to BW20
1871 rt2800_bbp_read(rt2x00dev
, 4, &bbp
);
1872 rt2x00_set_field8(&bbp
, BBP4_BANDWIDTH
, 0);
1873 rt2800_bbp_write(rt2x00dev
, 4, bbp
);
1875 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3070
, REV_RT3070F
) ||
1876 rt2x00_rt_rev_lt(rt2x00dev
, RT3071
, REV_RT3071E
) ||
1877 rt2x00_rt_rev_lt(rt2x00dev
, RT3090
, REV_RT3090E
) ||
1878 rt2x00_rt_rev_lt(rt2x00dev
, RT3390
, REV_RT3390E
))
1879 rt2800_rfcsr_write(rt2x00dev
, 27, 0x03);
1881 rt2800_register_read(rt2x00dev
, OPT_14_CSR
, ®
);
1882 rt2x00_set_field32(®
, OPT_14_CSR_BIT0
, 1);
1883 rt2800_register_write(rt2x00dev
, OPT_14_CSR
, reg
);
1885 rt2800_rfcsr_read(rt2x00dev
, 17, &rfcsr
);
1886 rt2x00_set_field8(&rfcsr
, RFCSR17_TX_LO1_EN
, 0);
1887 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3071
, REV_RT3071E
) ||
1888 rt2x00_rt_rev_lt(rt2x00dev
, RT3090
, REV_RT3090E
) ||
1889 rt2x00_rt_rev_lt(rt2x00dev
, RT3390
, REV_RT3390E
)) {
1890 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC
, &eeprom
);
1891 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_EXTERNAL_LNA_BG
))
1892 rt2x00_set_field8(&rfcsr
, RFCSR17_R
, 1);
1894 rt2x00_eeprom_read(rt2x00dev
, EEPROM_TXMIXER_GAIN_BG
, &eeprom
);
1895 if (rt2x00_get_field16(eeprom
, EEPROM_TXMIXER_GAIN_BG_VAL
) >= 1)
1896 rt2x00_set_field8(&rfcsr
, RFCSR17_TXMIXER_GAIN
,
1897 rt2x00_get_field16(eeprom
,
1898 EEPROM_TXMIXER_GAIN_BG_VAL
));
1899 rt2800_rfcsr_write(rt2x00dev
, 17, rfcsr
);
1901 if (rt2x00_rt(rt2x00dev
, RT3090
)) {
1902 rt2800_bbp_read(rt2x00dev
, 138, &bbp
);
1904 rt2x00_eeprom_read(rt2x00dev
, EEPROM_ANTENNA
, &eeprom
);
1905 if (rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_RXPATH
) == 1)
1906 rt2x00_set_field8(&bbp
, BBP138_RX_ADC1
, 0);
1907 if (rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_TXPATH
) == 1)
1908 rt2x00_set_field8(&bbp
, BBP138_TX_DAC1
, 1);
1910 rt2800_bbp_write(rt2x00dev
, 138, bbp
);
1913 if (rt2x00_rt(rt2x00dev
, RT3071
) ||
1914 rt2x00_rt(rt2x00dev
, RT3090
) ||
1915 rt2x00_rt(rt2x00dev
, RT3390
)) {
1916 rt2800_rfcsr_read(rt2x00dev
, 1, &rfcsr
);
1917 rt2x00_set_field8(&rfcsr
, RFCSR1_RF_BLOCK_EN
, 1);
1918 rt2x00_set_field8(&rfcsr
, RFCSR1_RX0_PD
, 0);
1919 rt2x00_set_field8(&rfcsr
, RFCSR1_TX0_PD
, 0);
1920 rt2x00_set_field8(&rfcsr
, RFCSR1_RX1_PD
, 1);
1921 rt2x00_set_field8(&rfcsr
, RFCSR1_TX1_PD
, 1);
1922 rt2800_rfcsr_write(rt2x00dev
, 1, rfcsr
);
1924 rt2800_rfcsr_read(rt2x00dev
, 15, &rfcsr
);
1925 rt2x00_set_field8(&rfcsr
, RFCSR15_TX_LO2_EN
, 0);
1926 rt2800_rfcsr_write(rt2x00dev
, 15, rfcsr
);
1928 rt2800_rfcsr_read(rt2x00dev
, 20, &rfcsr
);
1929 rt2x00_set_field8(&rfcsr
, RFCSR20_RX_LO1_EN
, 0);
1930 rt2800_rfcsr_write(rt2x00dev
, 20, rfcsr
);
1932 rt2800_rfcsr_read(rt2x00dev
, 21, &rfcsr
);
1933 rt2x00_set_field8(&rfcsr
, RFCSR21_RX_LO2_EN
, 0);
1934 rt2800_rfcsr_write(rt2x00dev
, 21, rfcsr
);
1937 if (rt2x00_rt(rt2x00dev
, RT3070
) || rt2x00_rt(rt2x00dev
, RT3071
)) {
1938 rt2800_rfcsr_read(rt2x00dev
, 27, &rfcsr
);
1939 if (rt2x00_rt_rev_lt(rt2x00dev
, RT3070
, REV_RT3070F
) ||
1940 rt2x00_rt_rev_lt(rt2x00dev
, RT3071
, REV_RT3071E
))
1941 rt2x00_set_field8(&rfcsr
, RFCSR27_R1
, 3);
1943 rt2x00_set_field8(&rfcsr
, RFCSR27_R1
, 0);
1944 rt2x00_set_field8(&rfcsr
, RFCSR27_R2
, 0);
1945 rt2x00_set_field8(&rfcsr
, RFCSR27_R3
, 0);
1946 rt2x00_set_field8(&rfcsr
, RFCSR27_R4
, 0);
1947 rt2800_rfcsr_write(rt2x00dev
, 27, rfcsr
);
1952 EXPORT_SYMBOL_GPL(rt2800_init_rfcsr
);
1954 int rt2800_efuse_detect(struct rt2x00_dev
*rt2x00dev
)
1958 rt2800_register_read(rt2x00dev
, EFUSE_CTRL
, ®
);
1960 return rt2x00_get_field32(reg
, EFUSE_CTRL_PRESENT
);
1962 EXPORT_SYMBOL_GPL(rt2800_efuse_detect
);
1964 static void rt2800_efuse_read(struct rt2x00_dev
*rt2x00dev
, unsigned int i
)
1968 mutex_lock(&rt2x00dev
->csr_mutex
);
1970 rt2800_register_read_lock(rt2x00dev
, EFUSE_CTRL
, ®
);
1971 rt2x00_set_field32(®
, EFUSE_CTRL_ADDRESS_IN
, i
);
1972 rt2x00_set_field32(®
, EFUSE_CTRL_MODE
, 0);
1973 rt2x00_set_field32(®
, EFUSE_CTRL_KICK
, 1);
1974 rt2800_register_write_lock(rt2x00dev
, EFUSE_CTRL
, reg
);
1976 /* Wait until the EEPROM has been loaded */
1977 rt2800_regbusy_read(rt2x00dev
, EFUSE_CTRL
, EFUSE_CTRL_KICK
, ®
);
1979 /* Apparently the data is read from end to start */
1980 rt2800_register_read_lock(rt2x00dev
, EFUSE_DATA3
,
1981 (u32
*)&rt2x00dev
->eeprom
[i
]);
1982 rt2800_register_read_lock(rt2x00dev
, EFUSE_DATA2
,
1983 (u32
*)&rt2x00dev
->eeprom
[i
+ 2]);
1984 rt2800_register_read_lock(rt2x00dev
, EFUSE_DATA1
,
1985 (u32
*)&rt2x00dev
->eeprom
[i
+ 4]);
1986 rt2800_register_read_lock(rt2x00dev
, EFUSE_DATA0
,
1987 (u32
*)&rt2x00dev
->eeprom
[i
+ 6]);
1989 mutex_unlock(&rt2x00dev
->csr_mutex
);
1992 void rt2800_read_eeprom_efuse(struct rt2x00_dev
*rt2x00dev
)
1996 for (i
= 0; i
< EEPROM_SIZE
/ sizeof(u16
); i
+= 8)
1997 rt2800_efuse_read(rt2x00dev
, i
);
1999 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse
);
2001 int rt2800_validate_eeprom(struct rt2x00_dev
*rt2x00dev
)
2005 u8 default_lna_gain
;
2008 * Start validation of the data that has been read.
2010 mac
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_MAC_ADDR_0
);
2011 if (!is_valid_ether_addr(mac
)) {
2012 random_ether_addr(mac
);
2013 EEPROM(rt2x00dev
, "MAC: %pM\n", mac
);
2016 rt2x00_eeprom_read(rt2x00dev
, EEPROM_ANTENNA
, &word
);
2017 if (word
== 0xffff) {
2018 rt2x00_set_field16(&word
, EEPROM_ANTENNA_RXPATH
, 2);
2019 rt2x00_set_field16(&word
, EEPROM_ANTENNA_TXPATH
, 1);
2020 rt2x00_set_field16(&word
, EEPROM_ANTENNA_RF_TYPE
, RF2820
);
2021 rt2x00_eeprom_write(rt2x00dev
, EEPROM_ANTENNA
, word
);
2022 EEPROM(rt2x00dev
, "Antenna: 0x%04x\n", word
);
2023 } else if (rt2x00_rt(rt2x00dev
, RT2860
) ||
2024 rt2x00_rt(rt2x00dev
, RT2870
) ||
2025 rt2x00_rt(rt2x00dev
, RT2872
) ||
2026 rt2x00_rt(rt2x00dev
, RT2872
)) {
2028 * There is a max of 2 RX streams for RT28x0 series
2030 if (rt2x00_get_field16(word
, EEPROM_ANTENNA_RXPATH
) > 2)
2031 rt2x00_set_field16(&word
, EEPROM_ANTENNA_RXPATH
, 2);
2032 rt2x00_eeprom_write(rt2x00dev
, EEPROM_ANTENNA
, word
);
2035 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC
, &word
);
2036 if (word
== 0xffff) {
2037 rt2x00_set_field16(&word
, EEPROM_NIC_HW_RADIO
, 0);
2038 rt2x00_set_field16(&word
, EEPROM_NIC_DYNAMIC_TX_AGC
, 0);
2039 rt2x00_set_field16(&word
, EEPROM_NIC_EXTERNAL_LNA_BG
, 0);
2040 rt2x00_set_field16(&word
, EEPROM_NIC_EXTERNAL_LNA_A
, 0);
2041 rt2x00_set_field16(&word
, EEPROM_NIC_CARDBUS_ACCEL
, 0);
2042 rt2x00_set_field16(&word
, EEPROM_NIC_BW40M_SB_BG
, 0);
2043 rt2x00_set_field16(&word
, EEPROM_NIC_BW40M_SB_A
, 0);
2044 rt2x00_set_field16(&word
, EEPROM_NIC_WPS_PBC
, 0);
2045 rt2x00_set_field16(&word
, EEPROM_NIC_BW40M_BG
, 0);
2046 rt2x00_set_field16(&word
, EEPROM_NIC_BW40M_A
, 0);
2047 rt2x00_eeprom_write(rt2x00dev
, EEPROM_NIC
, word
);
2048 EEPROM(rt2x00dev
, "NIC: 0x%04x\n", word
);
2051 rt2x00_eeprom_read(rt2x00dev
, EEPROM_FREQ
, &word
);
2052 if ((word
& 0x00ff) == 0x00ff) {
2053 rt2x00_set_field16(&word
, EEPROM_FREQ_OFFSET
, 0);
2054 rt2x00_set_field16(&word
, EEPROM_FREQ_LED_MODE
,
2055 LED_MODE_TXRX_ACTIVITY
);
2056 rt2x00_set_field16(&word
, EEPROM_FREQ_LED_POLARITY
, 0);
2057 rt2x00_eeprom_write(rt2x00dev
, EEPROM_FREQ
, word
);
2058 rt2x00_eeprom_write(rt2x00dev
, EEPROM_LED1
, 0x5555);
2059 rt2x00_eeprom_write(rt2x00dev
, EEPROM_LED2
, 0x2221);
2060 rt2x00_eeprom_write(rt2x00dev
, EEPROM_LED3
, 0xa9f8);
2061 EEPROM(rt2x00dev
, "Freq: 0x%04x\n", word
);
2065 * During the LNA validation we are going to use
2066 * lna0 as correct value. Note that EEPROM_LNA
2067 * is never validated.
2069 rt2x00_eeprom_read(rt2x00dev
, EEPROM_LNA
, &word
);
2070 default_lna_gain
= rt2x00_get_field16(word
, EEPROM_LNA_A0
);
2072 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_BG
, &word
);
2073 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_BG_OFFSET0
)) > 10)
2074 rt2x00_set_field16(&word
, EEPROM_RSSI_BG_OFFSET0
, 0);
2075 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_BG_OFFSET1
)) > 10)
2076 rt2x00_set_field16(&word
, EEPROM_RSSI_BG_OFFSET1
, 0);
2077 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_BG
, word
);
2079 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_BG2
, &word
);
2080 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_BG2_OFFSET2
)) > 10)
2081 rt2x00_set_field16(&word
, EEPROM_RSSI_BG2_OFFSET2
, 0);
2082 if (rt2x00_get_field16(word
, EEPROM_RSSI_BG2_LNA_A1
) == 0x00 ||
2083 rt2x00_get_field16(word
, EEPROM_RSSI_BG2_LNA_A1
) == 0xff)
2084 rt2x00_set_field16(&word
, EEPROM_RSSI_BG2_LNA_A1
,
2086 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_BG2
, word
);
2088 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_A
, &word
);
2089 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_A_OFFSET0
)) > 10)
2090 rt2x00_set_field16(&word
, EEPROM_RSSI_A_OFFSET0
, 0);
2091 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_A_OFFSET1
)) > 10)
2092 rt2x00_set_field16(&word
, EEPROM_RSSI_A_OFFSET1
, 0);
2093 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_A
, word
);
2095 rt2x00_eeprom_read(rt2x00dev
, EEPROM_RSSI_A2
, &word
);
2096 if (abs(rt2x00_get_field16(word
, EEPROM_RSSI_A2_OFFSET2
)) > 10)
2097 rt2x00_set_field16(&word
, EEPROM_RSSI_A2_OFFSET2
, 0);
2098 if (rt2x00_get_field16(word
, EEPROM_RSSI_A2_LNA_A2
) == 0x00 ||
2099 rt2x00_get_field16(word
, EEPROM_RSSI_A2_LNA_A2
) == 0xff)
2100 rt2x00_set_field16(&word
, EEPROM_RSSI_A2_LNA_A2
,
2102 rt2x00_eeprom_write(rt2x00dev
, EEPROM_RSSI_A2
, word
);
2106 EXPORT_SYMBOL_GPL(rt2800_validate_eeprom
);
2108 int rt2800_init_eeprom(struct rt2x00_dev
*rt2x00dev
)
2115 * Read EEPROM word for configuration.
2117 rt2x00_eeprom_read(rt2x00dev
, EEPROM_ANTENNA
, &eeprom
);
2120 * Identify RF chipset.
2122 value
= rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_RF_TYPE
);
2123 rt2800_register_read(rt2x00dev
, MAC_CSR0
, ®
);
2125 rt2x00_set_chip(rt2x00dev
, rt2x00_get_field32(reg
, MAC_CSR0_CHIPSET
),
2126 value
, rt2x00_get_field32(reg
, MAC_CSR0_REVISION
));
2128 if (!rt2x00_rt(rt2x00dev
, RT2860
) &&
2129 !rt2x00_rt(rt2x00dev
, RT2870
) &&
2130 !rt2x00_rt(rt2x00dev
, RT2872
) &&
2131 !rt2x00_rt(rt2x00dev
, RT2883
) &&
2132 !rt2x00_rt(rt2x00dev
, RT3070
) &&
2133 !rt2x00_rt(rt2x00dev
, RT3071
) &&
2134 !rt2x00_rt(rt2x00dev
, RT3090
) &&
2135 !rt2x00_rt(rt2x00dev
, RT3390
) &&
2136 !rt2x00_rt(rt2x00dev
, RT3572
)) {
2137 ERROR(rt2x00dev
, "Invalid RT chipset detected.\n");
2141 if (!rt2x00_rf(rt2x00dev
, RF2820
) &&
2142 !rt2x00_rf(rt2x00dev
, RF2850
) &&
2143 !rt2x00_rf(rt2x00dev
, RF2720
) &&
2144 !rt2x00_rf(rt2x00dev
, RF2750
) &&
2145 !rt2x00_rf(rt2x00dev
, RF3020
) &&
2146 !rt2x00_rf(rt2x00dev
, RF2020
) &&
2147 !rt2x00_rf(rt2x00dev
, RF3021
) &&
2148 !rt2x00_rf(rt2x00dev
, RF3022
) &&
2149 !rt2x00_rf(rt2x00dev
, RF3052
)) {
2150 ERROR(rt2x00dev
, "Invalid RF chipset detected.\n");
2155 * Identify default antenna configuration.
2157 rt2x00dev
->default_ant
.tx
=
2158 rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_TXPATH
);
2159 rt2x00dev
->default_ant
.rx
=
2160 rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_RXPATH
);
2163 * Read frequency offset and RF programming sequence.
2165 rt2x00_eeprom_read(rt2x00dev
, EEPROM_FREQ
, &eeprom
);
2166 rt2x00dev
->freq_offset
= rt2x00_get_field16(eeprom
, EEPROM_FREQ_OFFSET
);
2169 * Read external LNA informations.
2171 rt2x00_eeprom_read(rt2x00dev
, EEPROM_NIC
, &eeprom
);
2173 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_EXTERNAL_LNA_A
))
2174 __set_bit(CONFIG_EXTERNAL_LNA_A
, &rt2x00dev
->flags
);
2175 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_EXTERNAL_LNA_BG
))
2176 __set_bit(CONFIG_EXTERNAL_LNA_BG
, &rt2x00dev
->flags
);
2179 * Detect if this device has an hardware controlled radio.
2181 if (rt2x00_get_field16(eeprom
, EEPROM_NIC_HW_RADIO
))
2182 __set_bit(CONFIG_SUPPORT_HW_BUTTON
, &rt2x00dev
->flags
);
2185 * Store led settings, for correct led behaviour.
2187 #ifdef CONFIG_RT2X00_LIB_LEDS
2188 rt2800_init_led(rt2x00dev
, &rt2x00dev
->led_radio
, LED_TYPE_RADIO
);
2189 rt2800_init_led(rt2x00dev
, &rt2x00dev
->led_assoc
, LED_TYPE_ASSOC
);
2190 rt2800_init_led(rt2x00dev
, &rt2x00dev
->led_qual
, LED_TYPE_QUALITY
);
2192 rt2x00_eeprom_read(rt2x00dev
, EEPROM_FREQ
, &rt2x00dev
->led_mcu_reg
);
2193 #endif /* CONFIG_RT2X00_LIB_LEDS */
2197 EXPORT_SYMBOL_GPL(rt2800_init_eeprom
);
2200 * RF value list for rt28x0
2201 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
2203 static const struct rf_channel rf_vals
[] = {
2204 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
2205 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
2206 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
2207 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
2208 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
2209 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
2210 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
2211 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
2212 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
2213 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
2214 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
2215 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
2216 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
2217 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
2219 /* 802.11 UNI / HyperLan 2 */
2220 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
2221 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
2222 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
2223 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
2224 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
2225 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
2226 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
2227 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
2228 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
2229 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
2230 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
2231 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
2233 /* 802.11 HyperLan 2 */
2234 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
2235 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
2236 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
2237 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
2238 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
2239 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
2240 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
2241 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
2242 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
2243 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
2244 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
2245 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
2246 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
2247 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
2248 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
2249 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
2252 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
2253 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
2254 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
2255 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
2256 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
2257 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
2258 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
2259 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
2260 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
2261 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
2262 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
2265 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
2266 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
2267 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
2268 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
2269 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
2270 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
2271 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
2275 * RF value list for rt3070
2278 static const struct rf_channel rf_vals_302x
[] = {
2295 int rt2800_probe_hw_mode(struct rt2x00_dev
*rt2x00dev
)
2297 struct hw_mode_spec
*spec
= &rt2x00dev
->spec
;
2298 struct channel_info
*info
;
2305 * Disable powersaving as default on PCI devices.
2307 if (rt2x00_is_pci(rt2x00dev
) || rt2x00_is_soc(rt2x00dev
))
2308 rt2x00dev
->hw
->wiphy
->flags
&= ~WIPHY_FLAG_PS_ON_BY_DEFAULT
;
2311 * Initialize all hw fields.
2313 rt2x00dev
->hw
->flags
=
2314 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING
|
2315 IEEE80211_HW_SIGNAL_DBM
|
2316 IEEE80211_HW_SUPPORTS_PS
|
2317 IEEE80211_HW_PS_NULLFUNC_STACK
;
2319 SET_IEEE80211_DEV(rt2x00dev
->hw
, rt2x00dev
->dev
);
2320 SET_IEEE80211_PERM_ADDR(rt2x00dev
->hw
,
2321 rt2x00_eeprom_addr(rt2x00dev
,
2322 EEPROM_MAC_ADDR_0
));
2324 rt2x00_eeprom_read(rt2x00dev
, EEPROM_ANTENNA
, &eeprom
);
2327 * Initialize hw_mode information.
2329 spec
->supported_bands
= SUPPORT_BAND_2GHZ
;
2330 spec
->supported_rates
= SUPPORT_RATE_CCK
| SUPPORT_RATE_OFDM
;
2332 if (rt2x00_rf(rt2x00dev
, RF2820
) ||
2333 rt2x00_rf(rt2x00dev
, RF2720
) ||
2334 rt2x00_rf(rt2x00dev
, RF3052
)) {
2335 spec
->num_channels
= 14;
2336 spec
->channels
= rf_vals
;
2337 } else if (rt2x00_rf(rt2x00dev
, RF2850
) || rt2x00_rf(rt2x00dev
, RF2750
)) {
2338 spec
->supported_bands
|= SUPPORT_BAND_5GHZ
;
2339 spec
->num_channels
= ARRAY_SIZE(rf_vals
);
2340 spec
->channels
= rf_vals
;
2341 } else if (rt2x00_rf(rt2x00dev
, RF3020
) ||
2342 rt2x00_rf(rt2x00dev
, RF2020
) ||
2343 rt2x00_rf(rt2x00dev
, RF3021
) ||
2344 rt2x00_rf(rt2x00dev
, RF3022
)) {
2345 spec
->num_channels
= ARRAY_SIZE(rf_vals_302x
);
2346 spec
->channels
= rf_vals_302x
;
2350 * Initialize HT information.
2352 if (!rt2x00_rf(rt2x00dev
, RF2020
))
2353 spec
->ht
.ht_supported
= true;
2355 spec
->ht
.ht_supported
= false;
2358 * Don't set IEEE80211_HT_CAP_SUP_WIDTH_20_40 for now as it causes
2359 * reception problems with HT40 capable 11n APs
2362 IEEE80211_HT_CAP_GRN_FLD
|
2363 IEEE80211_HT_CAP_SGI_20
|
2364 IEEE80211_HT_CAP_SGI_40
|
2365 IEEE80211_HT_CAP_TX_STBC
|
2366 IEEE80211_HT_CAP_RX_STBC
;
2367 spec
->ht
.ampdu_factor
= 3;
2368 spec
->ht
.ampdu_density
= 4;
2369 spec
->ht
.mcs
.tx_params
=
2370 IEEE80211_HT_MCS_TX_DEFINED
|
2371 IEEE80211_HT_MCS_TX_RX_DIFF
|
2372 ((rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_TXPATH
) - 1) <<
2373 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT
);
2375 switch (rt2x00_get_field16(eeprom
, EEPROM_ANTENNA_RXPATH
)) {
2377 spec
->ht
.mcs
.rx_mask
[2] = 0xff;
2379 spec
->ht
.mcs
.rx_mask
[1] = 0xff;
2381 spec
->ht
.mcs
.rx_mask
[0] = 0xff;
2382 spec
->ht
.mcs
.rx_mask
[4] = 0x1; /* MCS32 */
2387 * Create channel information array
2389 info
= kzalloc(spec
->num_channels
* sizeof(*info
), GFP_KERNEL
);
2393 spec
->channels_info
= info
;
2395 tx_power1
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_BG1
);
2396 tx_power2
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_BG2
);
2398 for (i
= 0; i
< 14; i
++) {
2399 info
[i
].tx_power1
= TXPOWER_G_FROM_DEV(tx_power1
[i
]);
2400 info
[i
].tx_power2
= TXPOWER_G_FROM_DEV(tx_power2
[i
]);
2403 if (spec
->num_channels
> 14) {
2404 tx_power1
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_A1
);
2405 tx_power2
= rt2x00_eeprom_addr(rt2x00dev
, EEPROM_TXPOWER_A2
);
2407 for (i
= 14; i
< spec
->num_channels
; i
++) {
2408 info
[i
].tx_power1
= TXPOWER_A_FROM_DEV(tx_power1
[i
]);
2409 info
[i
].tx_power2
= TXPOWER_A_FROM_DEV(tx_power2
[i
]);
2415 EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode
);
2418 * IEEE80211 stack callback functions.
2420 static void rt2800_get_tkip_seq(struct ieee80211_hw
*hw
, u8 hw_key_idx
,
2421 u32
*iv32
, u16
*iv16
)
2423 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
2424 struct mac_iveiv_entry iveiv_entry
;
2427 offset
= MAC_IVEIV_ENTRY(hw_key_idx
);
2428 rt2800_register_multiread(rt2x00dev
, offset
,
2429 &iveiv_entry
, sizeof(iveiv_entry
));
2431 memcpy(iv16
, &iveiv_entry
.iv
[0], sizeof(*iv16
));
2432 memcpy(iv32
, &iveiv_entry
.iv
[4], sizeof(*iv32
));
2435 static int rt2800_set_rts_threshold(struct ieee80211_hw
*hw
, u32 value
)
2437 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
2439 bool enabled
= (value
< IEEE80211_MAX_RTS_THRESHOLD
);
2441 rt2800_register_read(rt2x00dev
, TX_RTS_CFG
, ®
);
2442 rt2x00_set_field32(®
, TX_RTS_CFG_RTS_THRES
, value
);
2443 rt2800_register_write(rt2x00dev
, TX_RTS_CFG
, reg
);
2445 rt2800_register_read(rt2x00dev
, CCK_PROT_CFG
, ®
);
2446 rt2x00_set_field32(®
, CCK_PROT_CFG_RTS_TH_EN
, enabled
);
2447 rt2800_register_write(rt2x00dev
, CCK_PROT_CFG
, reg
);
2449 rt2800_register_read(rt2x00dev
, OFDM_PROT_CFG
, ®
);
2450 rt2x00_set_field32(®
, OFDM_PROT_CFG_RTS_TH_EN
, enabled
);
2451 rt2800_register_write(rt2x00dev
, OFDM_PROT_CFG
, reg
);
2453 rt2800_register_read(rt2x00dev
, MM20_PROT_CFG
, ®
);
2454 rt2x00_set_field32(®
, MM20_PROT_CFG_RTS_TH_EN
, enabled
);
2455 rt2800_register_write(rt2x00dev
, MM20_PROT_CFG
, reg
);
2457 rt2800_register_read(rt2x00dev
, MM40_PROT_CFG
, ®
);
2458 rt2x00_set_field32(®
, MM40_PROT_CFG_RTS_TH_EN
, enabled
);
2459 rt2800_register_write(rt2x00dev
, MM40_PROT_CFG
, reg
);
2461 rt2800_register_read(rt2x00dev
, GF20_PROT_CFG
, ®
);
2462 rt2x00_set_field32(®
, GF20_PROT_CFG_RTS_TH_EN
, enabled
);
2463 rt2800_register_write(rt2x00dev
, GF20_PROT_CFG
, reg
);
2465 rt2800_register_read(rt2x00dev
, GF40_PROT_CFG
, ®
);
2466 rt2x00_set_field32(®
, GF40_PROT_CFG_RTS_TH_EN
, enabled
);
2467 rt2800_register_write(rt2x00dev
, GF40_PROT_CFG
, reg
);
2472 static int rt2800_conf_tx(struct ieee80211_hw
*hw
, u16 queue_idx
,
2473 const struct ieee80211_tx_queue_params
*params
)
2475 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
2476 struct data_queue
*queue
;
2477 struct rt2x00_field32 field
;
2483 * First pass the configuration through rt2x00lib, that will
2484 * update the queue settings and validate the input. After that
2485 * we are free to update the registers based on the value
2486 * in the queue parameter.
2488 retval
= rt2x00mac_conf_tx(hw
, queue_idx
, params
);
2493 * We only need to perform additional register initialization
2499 queue
= rt2x00queue_get_queue(rt2x00dev
, queue_idx
);
2501 /* Update WMM TXOP register */
2502 offset
= WMM_TXOP0_CFG
+ (sizeof(u32
) * (!!(queue_idx
& 2)));
2503 field
.bit_offset
= (queue_idx
& 1) * 16;
2504 field
.bit_mask
= 0xffff << field
.bit_offset
;
2506 rt2800_register_read(rt2x00dev
, offset
, ®
);
2507 rt2x00_set_field32(®
, field
, queue
->txop
);
2508 rt2800_register_write(rt2x00dev
, offset
, reg
);
2510 /* Update WMM registers */
2511 field
.bit_offset
= queue_idx
* 4;
2512 field
.bit_mask
= 0xf << field
.bit_offset
;
2514 rt2800_register_read(rt2x00dev
, WMM_AIFSN_CFG
, ®
);
2515 rt2x00_set_field32(®
, field
, queue
->aifs
);
2516 rt2800_register_write(rt2x00dev
, WMM_AIFSN_CFG
, reg
);
2518 rt2800_register_read(rt2x00dev
, WMM_CWMIN_CFG
, ®
);
2519 rt2x00_set_field32(®
, field
, queue
->cw_min
);
2520 rt2800_register_write(rt2x00dev
, WMM_CWMIN_CFG
, reg
);
2522 rt2800_register_read(rt2x00dev
, WMM_CWMAX_CFG
, ®
);
2523 rt2x00_set_field32(®
, field
, queue
->cw_max
);
2524 rt2800_register_write(rt2x00dev
, WMM_CWMAX_CFG
, reg
);
2526 /* Update EDCA registers */
2527 offset
= EDCA_AC0_CFG
+ (sizeof(u32
) * queue_idx
);
2529 rt2800_register_read(rt2x00dev
, offset
, ®
);
2530 rt2x00_set_field32(®
, EDCA_AC0_CFG_TX_OP
, queue
->txop
);
2531 rt2x00_set_field32(®
, EDCA_AC0_CFG_AIFSN
, queue
->aifs
);
2532 rt2x00_set_field32(®
, EDCA_AC0_CFG_CWMIN
, queue
->cw_min
);
2533 rt2x00_set_field32(®
, EDCA_AC0_CFG_CWMAX
, queue
->cw_max
);
2534 rt2800_register_write(rt2x00dev
, offset
, reg
);
2539 static u64
rt2800_get_tsf(struct ieee80211_hw
*hw
)
2541 struct rt2x00_dev
*rt2x00dev
= hw
->priv
;
2545 rt2800_register_read(rt2x00dev
, TSF_TIMER_DW1
, ®
);
2546 tsf
= (u64
) rt2x00_get_field32(reg
, TSF_TIMER_DW1_HIGH_WORD
) << 32;
2547 rt2800_register_read(rt2x00dev
, TSF_TIMER_DW0
, ®
);
2548 tsf
|= rt2x00_get_field32(reg
, TSF_TIMER_DW0_LOW_WORD
);
2553 const struct ieee80211_ops rt2800_mac80211_ops
= {
2555 .start
= rt2x00mac_start
,
2556 .stop
= rt2x00mac_stop
,
2557 .add_interface
= rt2x00mac_add_interface
,
2558 .remove_interface
= rt2x00mac_remove_interface
,
2559 .config
= rt2x00mac_config
,
2560 .configure_filter
= rt2x00mac_configure_filter
,
2561 .set_tim
= rt2x00mac_set_tim
,
2562 .set_key
= rt2x00mac_set_key
,
2563 .get_stats
= rt2x00mac_get_stats
,
2564 .get_tkip_seq
= rt2800_get_tkip_seq
,
2565 .set_rts_threshold
= rt2800_set_rts_threshold
,
2566 .bss_info_changed
= rt2x00mac_bss_info_changed
,
2567 .conf_tx
= rt2800_conf_tx
,
2568 .get_tsf
= rt2800_get_tsf
,
2569 .rfkill_poll
= rt2x00mac_rfkill_poll
,
2571 EXPORT_SYMBOL_GPL(rt2800_mac80211_ops
);