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[PATCH] savagefb: Allocate space for current and saved register states
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / video / savage / savagefb_driver.c
blob267d4e5c999131a8c0c3f5629394fa153d27c01b
1 /*
2 * linux/drivers/video/savagefb.c -- S3 Savage Framebuffer Driver
3 *
4 * Copyright (c) 2001-2002 Denis Oliver Kropp <dok@directfb.org>
5 * Sven Neumann <neo@directfb.org>
6 *
7 *
8 * Card specific code is based on XFree86's savage driver.
9 * Framebuffer framework code is based on code of cyber2000fb and tdfxfb.
10 *
11 * This file is subject to the terms and conditions of the GNU General
12 * Public License. See the file COPYING in the main directory of this
13 * archive for more details.
14 *
15 * 0.4.0 (neo)
16 * - hardware accelerated clear and move
17 *
18 * 0.3.2 (dok)
19 * - wait for vertical retrace before writing to cr67
20 * at the beginning of savagefb_set_par
21 * - use synchronization registers cr23 and cr26
22 *
23 * 0.3.1 (dok)
24 * - reset 3D engine
25 * - don't return alpha bits for 32bit format
26 *
27 * 0.3.0 (dok)
28 * - added WaitIdle functions for all Savage types
29 * - do WaitIdle before mode switching
30 * - code cleanup
31 *
32 * 0.2.0 (dok)
33 * - first working version
34 *
35 *
36 * TODO
37 * - clock validations in decode_var
38 *
39 * BUGS
40 * - white margin on bootup
41 *
42 */
43
44 #include <linux/config.h>
45 #include <linux/module.h>
46 #include <linux/kernel.h>
47 #include <linux/errno.h>
48 #include <linux/string.h>
49 #include <linux/mm.h>
50 #include <linux/tty.h>
51 #include <linux/slab.h>
52 #include <linux/delay.h>
53 #include <linux/fb.h>
54 #include <linux/pci.h>
55 #include <linux/init.h>
56 #include <linux/console.h>
57
58 #include <asm/io.h>
59 #include <asm/irq.h>
60 #include <asm/pgtable.h>
61 #include <asm/system.h>
62 #include <asm/uaccess.h>
63
64 #ifdef CONFIG_MTRR
65 #include <asm/mtrr.h>
66 #endif
67
68 #include "savagefb.h"
69
70
71 #define SAVAGEFB_VERSION "0.4.0_2.6"
72
73 /* --------------------------------------------------------------------- */
74
75
76 static char *mode_option __devinitdata = NULL;
77
78 #ifdef MODULE
79
80 MODULE_AUTHOR("(c) 2001-2002 Denis Oliver Kropp <dok@directfb.org>");
81 MODULE_LICENSE("GPL");
82 MODULE_DESCRIPTION("FBDev driver for S3 Savage PCI/AGP Chips");
83
84 #endif
85
86
87 /* --------------------------------------------------------------------- */
88
89 static void vgaHWSeqReset (struct savagefb_par *par, int start)
90 {
91 if (start)
92 VGAwSEQ (0x00, 0x01, par); /* Synchronous Reset */
93 else
94 VGAwSEQ (0x00, 0x03, par); /* End Reset */
95 }
96
97 static void vgaHWProtect (struct savagefb_par *par, int on)
98 {
99 unsigned char tmp;
100
101 if (on) {
102 /*
103 * Turn off screen and disable sequencer.
104 */
105 tmp = VGArSEQ (0x01, par);
106
107 vgaHWSeqReset (par, 1); /* start synchronous reset */
108 VGAwSEQ (0x01, tmp | 0x20, par);/* disable the display */
109
110 VGAenablePalette(par);
111 } else {
112 /*
113 * Reenable sequencer, then turn on screen.
114 */
115
116 tmp = VGArSEQ (0x01, par);
117
118 VGAwSEQ (0x01, tmp & ~0x20, par);/* reenable display */
119 vgaHWSeqReset (par, 0); /* clear synchronous reset */
120
121 VGAdisablePalette(par);
122 }
123 }
124
125 static void vgaHWRestore (struct savagefb_par *par, struct savage_reg *reg)
126 {
127 int i;
128
129 VGAwMISC (reg->MiscOutReg, par);
130
131 for (i = 1; i < 5; i++)
132 VGAwSEQ (i, reg->Sequencer[i], par);
133
134 /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 or
135 CRTC[17] */
136 VGAwCR (17, reg->CRTC[17] & ~0x80, par);
137
138 for (i = 0; i < 25; i++)
139 VGAwCR (i, reg->CRTC[i], par);
140
141 for (i = 0; i < 9; i++)
142 VGAwGR (i, reg->Graphics[i], par);
143
144 VGAenablePalette(par);
145
146 for (i = 0; i < 21; i++)
147 VGAwATTR (i, reg->Attribute[i], par);
148
149 VGAdisablePalette(par);
150 }
151
152 static void vgaHWInit (struct fb_var_screeninfo *var,
153 struct savagefb_par *par,
154 struct xtimings *timings,
155 struct savage_reg *reg)
156 {
157 reg->MiscOutReg = 0x23;
158
159 if (!(timings->sync & FB_SYNC_HOR_HIGH_ACT))
160 reg->MiscOutReg |= 0x40;
161
162 if (!(timings->sync & FB_SYNC_VERT_HIGH_ACT))
163 reg->MiscOutReg |= 0x80;
164
165 /*
166 * Time Sequencer
167 */
168 reg->Sequencer[0x00] = 0x00;
169 reg->Sequencer[0x01] = 0x01;
170 reg->Sequencer[0x02] = 0x0F;
171 reg->Sequencer[0x03] = 0x00; /* Font select */
172 reg->Sequencer[0x04] = 0x0E; /* Misc */
173
174 /*
175 * CRTC Controller
176 */
177 reg->CRTC[0x00] = (timings->HTotal >> 3) - 5;
178 reg->CRTC[0x01] = (timings->HDisplay >> 3) - 1;
179 reg->CRTC[0x02] = (timings->HSyncStart >> 3) - 1;
180 reg->CRTC[0x03] = (((timings->HSyncEnd >> 3) - 1) & 0x1f) | 0x80;
181 reg->CRTC[0x04] = (timings->HSyncStart >> 3);
182 reg->CRTC[0x05] = ((((timings->HSyncEnd >> 3) - 1) & 0x20) << 2) |
183 (((timings->HSyncEnd >> 3)) & 0x1f);
184 reg->CRTC[0x06] = (timings->VTotal - 2) & 0xFF;
185 reg->CRTC[0x07] = (((timings->VTotal - 2) & 0x100) >> 8) |
186 (((timings->VDisplay - 1) & 0x100) >> 7) |
187 ((timings->VSyncStart & 0x100) >> 6) |
188 (((timings->VSyncStart - 1) & 0x100) >> 5) |
189 0x10 |
190 (((timings->VTotal - 2) & 0x200) >> 4) |
191 (((timings->VDisplay - 1) & 0x200) >> 3) |
192 ((timings->VSyncStart & 0x200) >> 2);
193 reg->CRTC[0x08] = 0x00;
194 reg->CRTC[0x09] = (((timings->VSyncStart - 1) & 0x200) >> 4) | 0x40;
195
196 if (timings->dblscan)
197 reg->CRTC[0x09] |= 0x80;
198
199 reg->CRTC[0x0a] = 0x00;
200 reg->CRTC[0x0b] = 0x00;
201 reg->CRTC[0x0c] = 0x00;
202 reg->CRTC[0x0d] = 0x00;
203 reg->CRTC[0x0e] = 0x00;
204 reg->CRTC[0x0f] = 0x00;
205 reg->CRTC[0x10] = timings->VSyncStart & 0xff;
206 reg->CRTC[0x11] = (timings->VSyncEnd & 0x0f) | 0x20;
207 reg->CRTC[0x12] = (timings->VDisplay - 1) & 0xff;
208 reg->CRTC[0x13] = var->xres_virtual >> 4;
209 reg->CRTC[0x14] = 0x00;
210 reg->CRTC[0x15] = (timings->VSyncStart - 1) & 0xff;
211 reg->CRTC[0x16] = (timings->VSyncEnd - 1) & 0xff;
212 reg->CRTC[0x17] = 0xc3;
213 reg->CRTC[0x18] = 0xff;
214
215 /*
216 * are these unnecessary?
217 * vgaHWHBlankKGA(mode, regp, 0, KGA_FIX_OVERSCAN|KGA_ENABLE_ON_ZERO);
218 * vgaHWVBlankKGA(mode, regp, 0, KGA_FIX_OVERSCAN|KGA_ENABLE_ON_ZERO);
219 */
220
221 /*
222 * Graphics Display Controller
223 */
224 reg->Graphics[0x00] = 0x00;
225 reg->Graphics[0x01] = 0x00;
226 reg->Graphics[0x02] = 0x00;
227 reg->Graphics[0x03] = 0x00;
228 reg->Graphics[0x04] = 0x00;
229 reg->Graphics[0x05] = 0x40;
230 reg->Graphics[0x06] = 0x05; /* only map 64k VGA memory !!!! */
231 reg->Graphics[0x07] = 0x0F;
232 reg->Graphics[0x08] = 0xFF;
233
234
235 reg->Attribute[0x00] = 0x00; /* standard colormap translation */
236 reg->Attribute[0x01] = 0x01;
237 reg->Attribute[0x02] = 0x02;
238 reg->Attribute[0x03] = 0x03;
239 reg->Attribute[0x04] = 0x04;
240 reg->Attribute[0x05] = 0x05;
241 reg->Attribute[0x06] = 0x06;
242 reg->Attribute[0x07] = 0x07;
243 reg->Attribute[0x08] = 0x08;
244 reg->Attribute[0x09] = 0x09;
245 reg->Attribute[0x0a] = 0x0A;
246 reg->Attribute[0x0b] = 0x0B;
247 reg->Attribute[0x0c] = 0x0C;
248 reg->Attribute[0x0d] = 0x0D;
249 reg->Attribute[0x0e] = 0x0E;
250 reg->Attribute[0x0f] = 0x0F;
251 reg->Attribute[0x10] = 0x41;
252 reg->Attribute[0x11] = 0xFF;
253 reg->Attribute[0x12] = 0x0F;
254 reg->Attribute[0x13] = 0x00;
255 reg->Attribute[0x14] = 0x00;
256 }
257
258 /* -------------------- Hardware specific routines ------------------------- */
259
260 /*
261 * Hardware Acceleration for SavageFB
262 */
263
264 /* Wait for fifo space */
265 static void
266 savage3D_waitfifo(struct savagefb_par *par, int space)
267 {
268 int slots = MAXFIFO - space;
269
270 while ((savage_in32(0x48C00, par) & 0x0000ffff) > slots);
271 }
272
273 static void
274 savage4_waitfifo(struct savagefb_par *par, int space)
275 {
276 int slots = MAXFIFO - space;
277
278 while ((savage_in32(0x48C60, par) & 0x001fffff) > slots);
279 }
280
281 static void
282 savage2000_waitfifo(struct savagefb_par *par, int space)
283 {
284 int slots = MAXFIFO - space;
285
286 while ((savage_in32(0x48C60, par) & 0x0000ffff) > slots);
287 }
288
289 /* Wait for idle accelerator */
290 static void
291 savage3D_waitidle(struct savagefb_par *par)
292 {
293 while ((savage_in32(0x48C00, par) & 0x0008ffff) != 0x80000);
294 }
295
296 static void
297 savage4_waitidle(struct savagefb_par *par)
298 {
299 while ((savage_in32(0x48C60, par) & 0x00a00000) != 0x00a00000);
300 }
301
302 static void
303 savage2000_waitidle(struct savagefb_par *par)
304 {
305 while ((savage_in32(0x48C60, par) & 0x009fffff));
306 }
307
308
309 static void
310 SavageSetup2DEngine (struct savagefb_par *par)
311 {
312 unsigned long GlobalBitmapDescriptor;
313
314 GlobalBitmapDescriptor = 1 | 8 | BCI_BD_BW_DISABLE;
315 BCI_BD_SET_BPP (GlobalBitmapDescriptor, par->depth);
316 BCI_BD_SET_STRIDE (GlobalBitmapDescriptor, par->vwidth);
317
318 switch(par->chip) {
319 case S3_SAVAGE3D:
320 case S3_SAVAGE_MX:
321 /* Disable BCI */
322 savage_out32(0x48C18, savage_in32(0x48C18, par) & 0x3FF0, par);
323 /* Setup BCI command overflow buffer */
324 savage_out32(0x48C14,
325 (par->cob_offset >> 11) | (par->cob_index << 29),
326 par);
327 /* Program shadow status update. */
328 savage_out32(0x48C10, 0x78207220, par);
329 savage_out32(0x48C0C, 0, par);
330 /* Enable BCI and command overflow buffer */
331 savage_out32(0x48C18, savage_in32(0x48C18, par) | 0x0C, par);
332 break;
333 case S3_SAVAGE4:
334 case S3_PROSAVAGE:
335 case S3_SUPERSAVAGE:
336 /* Disable BCI */
337 savage_out32(0x48C18, savage_in32(0x48C18, par) & 0x3FF0, par);
338 /* Program shadow status update */
339 savage_out32(0x48C10, 0x00700040, par);
340 savage_out32(0x48C0C, 0, par);
341 /* Enable BCI without the COB */
342 savage_out32(0x48C18, savage_in32(0x48C18, par) | 0x08, par);
343 break;
344 case S3_SAVAGE2000:
345 /* Disable BCI */
346 savage_out32(0x48C18, 0, par);
347 /* Setup BCI command overflow buffer */
348 savage_out32(0x48C18,
349 (par->cob_offset >> 7) | (par->cob_index),
350 par);
351 /* Disable shadow status update */
352 savage_out32(0x48A30, 0, par);
353 /* Enable BCI and command overflow buffer */
354 savage_out32(0x48C18, savage_in32(0x48C18, par) | 0x00280000,
355 par);
356 break;
357 default:
358 break;
359 }
360 /* Turn on 16-bit register access. */
361 vga_out8(0x3d4, 0x31, par);
362 vga_out8(0x3d5, 0x0c, par);
363
364 /* Set stride to use GBD. */
365 vga_out8 (0x3d4, 0x50, par);
366 vga_out8 (0x3d5, vga_in8(0x3d5, par) | 0xC1, par);
367
368 /* Enable 2D engine. */
369 vga_out8 (0x3d4, 0x40, par);
370 vga_out8 (0x3d5, 0x01, par);
371
372 savage_out32 (MONO_PAT_0, ~0, par);
373 savage_out32 (MONO_PAT_1, ~0, par);
374
375 /* Setup plane masks */
376 savage_out32 (0x8128, ~0, par); /* enable all write planes */
377 savage_out32 (0x812C, ~0, par); /* enable all read planes */
378 savage_out16 (0x8134, 0x27, par);
379 savage_out16 (0x8136, 0x07, par);
380
381 /* Now set the GBD */
382 par->bci_ptr = 0;
383 par->SavageWaitFifo (par, 4);
384
385 BCI_SEND( BCI_CMD_SETREG | (1 << 16) | BCI_GBD1 );
386 BCI_SEND( 0 );
387 BCI_SEND( BCI_CMD_SETREG | (1 << 16) | BCI_GBD2 );
388 BCI_SEND( GlobalBitmapDescriptor );
389 }
390
391
392 static void SavageCalcClock(long freq, int min_m, int min_n1, int max_n1,
393 int min_n2, int max_n2, long freq_min,
394 long freq_max, unsigned int *mdiv,
395 unsigned int *ndiv, unsigned int *r)
396 {
397 long diff, best_diff;
398 unsigned int m;
399 unsigned char n1, n2, best_n1=16+2, best_n2=2, best_m=125+2;
400
401 if (freq < freq_min / (1 << max_n2)) {
402 printk (KERN_ERR "invalid frequency %ld Khz\n", freq);
403 freq = freq_min / (1 << max_n2);
404 }
405 if (freq > freq_max / (1 << min_n2)) {
406 printk (KERN_ERR "invalid frequency %ld Khz\n", freq);
407 freq = freq_max / (1 << min_n2);
408 }
409
410 /* work out suitable timings */
411 best_diff = freq;
412
413 for (n2=min_n2; n2<=max_n2; n2++) {
414 for (n1=min_n1+2; n1<=max_n1+2; n1++) {
415 m = (freq * n1 * (1 << n2) + HALF_BASE_FREQ) /
416 BASE_FREQ;
417 if (m < min_m+2 || m > 127+2)
418 continue;
419 if ((m * BASE_FREQ >= freq_min * n1) &&
420 (m * BASE_FREQ <= freq_max * n1)) {
421 diff = freq * (1 << n2) * n1 - BASE_FREQ * m;
422 if (diff < 0)
423 diff = -diff;
424 if (diff < best_diff) {
425 best_diff = diff;
426 best_m = m;
427 best_n1 = n1;
428 best_n2 = n2;
429 }
430 }
431 }
432 }
433
434 *ndiv = best_n1 - 2;
435 *r = best_n2;
436 *mdiv = best_m - 2;
437 }
438
439 static int common_calc_clock(long freq, int min_m, int min_n1, int max_n1,
440 int min_n2, int max_n2, long freq_min,
441 long freq_max, unsigned char *mdiv,
442 unsigned char *ndiv)
443 {
444 long diff, best_diff;
445 unsigned int m;
446 unsigned char n1, n2;
447 unsigned char best_n1 = 16+2, best_n2 = 2, best_m = 125+2;
448
449 best_diff = freq;
450
451 for (n2 = min_n2; n2 <= max_n2; n2++) {
452 for (n1 = min_n1+2; n1 <= max_n1+2; n1++) {
453 m = (freq * n1 * (1 << n2) + HALF_BASE_FREQ) /
454 BASE_FREQ;
455 if (m < min_m + 2 || m > 127+2)
456 continue;
457 if((m * BASE_FREQ >= freq_min * n1) &&
458 (m * BASE_FREQ <= freq_max * n1)) {
459 diff = freq * (1 << n2) * n1 - BASE_FREQ * m;
460 if(diff < 0)
461 diff = -diff;
462 if(diff < best_diff) {
463 best_diff = diff;
464 best_m = m;
465 best_n1 = n1;
466 best_n2 = n2;
467 }
468 }
469 }
470 }
471
472 if(max_n1 == 63)
473 *ndiv = (best_n1 - 2) | (best_n2 << 6);
474 else
475 *ndiv = (best_n1 - 2) | (best_n2 << 5);
476
477 *mdiv = best_m - 2;
478
479 return 0;
480 }
481
482 #ifdef SAVAGEFB_DEBUG
483 /* This function is used to debug, it prints out the contents of s3 regs */
484
485 static void SavagePrintRegs(void)
486 {
487 unsigned char i;
488 int vgaCRIndex = 0x3d4;
489 int vgaCRReg = 0x3d5;
490
491 printk(KERN_DEBUG "SR x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xA xB xC xD xE "
492 "xF" );
493
494 for( i = 0; i < 0x70; i++ ) {
495 if( !(i % 16) )
496 printk(KERN_DEBUG "\nSR%xx ", i >> 4 );
497 vga_out8( 0x3c4, i, par);
498 printk(KERN_DEBUG " %02x", vga_in8(0x3c5, par) );
499 }
500
501 printk(KERN_DEBUG "\n\nCR x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xA xB xC "
502 "xD xE xF" );
503
504 for( i = 0; i < 0xB7; i++ ) {
505 if( !(i % 16) )
506 printk(KERN_DEBUG "\nCR%xx ", i >> 4 );
507 vga_out8( vgaCRIndex, i, par);
508 printk(KERN_DEBUG " %02x", vga_in8(vgaCRReg, par) );
509 }
510
511 printk(KERN_DEBUG "\n\n");
512 }
513 #endif
514
515 /* --------------------------------------------------------------------- */
516
517 static void savage_get_default_par(struct savagefb_par *par, struct savage_reg *reg)
518 {
519 unsigned char cr3a, cr53, cr66;
520
521 vga_out16 (0x3d4, 0x4838, par);
522 vga_out16 (0x3d4, 0xa039, par);
523 vga_out16 (0x3c4, 0x0608, par);
524
525 vga_out8 (0x3d4, 0x66, par);
526 cr66 = vga_in8 (0x3d5, par);
527 vga_out8 (0x3d5, cr66 | 0x80, par);
528 vga_out8 (0x3d4, 0x3a, par);
529 cr3a = vga_in8 (0x3d5, par);
530 vga_out8 (0x3d5, cr3a | 0x80, par);
531 vga_out8 (0x3d4, 0x53, par);
532 cr53 = vga_in8 (0x3d5, par);
533 vga_out8 (0x3d5, cr53 & 0x7f, par);
534
535 vga_out8 (0x3d4, 0x66, par);
536 vga_out8 (0x3d5, cr66, par);
537 vga_out8 (0x3d4, 0x3a, par);
538 vga_out8 (0x3d5, cr3a, par);
539
540 vga_out8 (0x3d4, 0x66, par);
541 vga_out8 (0x3d5, cr66, par);
542 vga_out8 (0x3d4, 0x3a, par);
543 vga_out8 (0x3d5, cr3a, par);
544
545 /* unlock extended seq regs */
546 vga_out8 (0x3c4, 0x08, par);
547 reg->SR08 = vga_in8 (0x3c5, par);
548 vga_out8 (0x3c5, 0x06, par);
549
550 /* now save all the extended regs we need */
551 vga_out8 (0x3d4, 0x31, par);
552 reg->CR31 = vga_in8 (0x3d5, par);
553 vga_out8 (0x3d4, 0x32, par);
554 reg->CR32 = vga_in8 (0x3d5, par);
555 vga_out8 (0x3d4, 0x34, par);
556 reg->CR34 = vga_in8 (0x3d5, par);
557 vga_out8 (0x3d4, 0x36, par);
558 reg->CR36 = vga_in8 (0x3d5, par);
559 vga_out8 (0x3d4, 0x3a, par);
560 reg->CR3A = vga_in8 (0x3d5, par);
561 vga_out8 (0x3d4, 0x40, par);
562 reg->CR40 = vga_in8 (0x3d5, par);
563 vga_out8 (0x3d4, 0x42, par);
564 reg->CR42 = vga_in8 (0x3d5, par);
565 vga_out8 (0x3d4, 0x45, par);
566 reg->CR45 = vga_in8 (0x3d5, par);
567 vga_out8 (0x3d4, 0x50, par);
568 reg->CR50 = vga_in8 (0x3d5, par);
569 vga_out8 (0x3d4, 0x51, par);
570 reg->CR51 = vga_in8 (0x3d5, par);
571 vga_out8 (0x3d4, 0x53, par);
572 reg->CR53 = vga_in8 (0x3d5, par);
573 vga_out8 (0x3d4, 0x58, par);
574 reg->CR58 = vga_in8 (0x3d5, par);
575 vga_out8 (0x3d4, 0x60, par);
576 reg->CR60 = vga_in8 (0x3d5, par);
577 vga_out8 (0x3d4, 0x66, par);
578 reg->CR66 = vga_in8 (0x3d5, par);
579 vga_out8 (0x3d4, 0x67, par);
580 reg->CR67 = vga_in8 (0x3d5, par);
581 vga_out8 (0x3d4, 0x68, par);
582 reg->CR68 = vga_in8 (0x3d5, par);
583 vga_out8 (0x3d4, 0x69, par);
584 reg->CR69 = vga_in8 (0x3d5, par);
585 vga_out8 (0x3d4, 0x6f, par);
586 reg->CR6F = vga_in8 (0x3d5, par);
587
588 vga_out8 (0x3d4, 0x33, par);
589 reg->CR33 = vga_in8 (0x3d5, par);
590 vga_out8 (0x3d4, 0x86, par);
591 reg->CR86 = vga_in8 (0x3d5, par);
592 vga_out8 (0x3d4, 0x88, par);
593 reg->CR88 = vga_in8 (0x3d5, par);
594 vga_out8 (0x3d4, 0x90, par);
595 reg->CR90 = vga_in8 (0x3d5, par);
596 vga_out8 (0x3d4, 0x91, par);
597 reg->CR91 = vga_in8 (0x3d5, par);
598 vga_out8 (0x3d4, 0xb0, par);
599 reg->CRB0 = vga_in8 (0x3d5, par) | 0x80;
600
601 /* extended mode timing regs */
602 vga_out8 (0x3d4, 0x3b, par);
603 reg->CR3B = vga_in8 (0x3d5, par);
604 vga_out8 (0x3d4, 0x3c, par);
605 reg->CR3C = vga_in8 (0x3d5, par);
606 vga_out8 (0x3d4, 0x43, par);
607 reg->CR43 = vga_in8 (0x3d5, par);
608 vga_out8 (0x3d4, 0x5d, par);
609 reg->CR5D = vga_in8 (0x3d5, par);
610 vga_out8 (0x3d4, 0x5e, par);
611 reg->CR5E = vga_in8 (0x3d5, par);
612 vga_out8 (0x3d4, 0x65, par);
613 reg->CR65 = vga_in8 (0x3d5, par);
614
615 /* save seq extended regs for DCLK PLL programming */
616 vga_out8 (0x3c4, 0x0e, par);
617 reg->SR0E = vga_in8 (0x3c5, par);
618 vga_out8 (0x3c4, 0x0f, par);
619 reg->SR0F = vga_in8 (0x3c5, par);
620 vga_out8 (0x3c4, 0x10, par);
621 reg->SR10 = vga_in8 (0x3c5, par);
622 vga_out8 (0x3c4, 0x11, par);
623 reg->SR11 = vga_in8 (0x3c5, par);
624 vga_out8 (0x3c4, 0x12, par);
625 reg->SR12 = vga_in8 (0x3c5, par);
626 vga_out8 (0x3c4, 0x13, par);
627 reg->SR13 = vga_in8 (0x3c5, par);
628 vga_out8 (0x3c4, 0x29, par);
629 reg->SR29 = vga_in8 (0x3c5, par);
630
631 vga_out8 (0x3c4, 0x15, par);
632 reg->SR15 = vga_in8 (0x3c5, par);
633 vga_out8 (0x3c4, 0x30, par);
634 reg->SR30 = vga_in8 (0x3c5, par);
635 vga_out8 (0x3c4, 0x18, par);
636 reg->SR18 = vga_in8 (0x3c5, par);
637
638 /* Save flat panel expansion regsters. */
639 if (par->chip == S3_SAVAGE_MX) {
640 int i;
641
642 for (i = 0; i < 8; i++) {
643 vga_out8 (0x3c4, 0x54+i, par);
644 reg->SR54[i] = vga_in8 (0x3c5, par);
645 }
646 }
647
648 vga_out8 (0x3d4, 0x66, par);
649 cr66 = vga_in8 (0x3d5, par);
650 vga_out8 (0x3d5, cr66 | 0x80, par);
651 vga_out8 (0x3d4, 0x3a, par);
652 cr3a = vga_in8 (0x3d5, par);
653 vga_out8 (0x3d5, cr3a | 0x80, par);
654
655 /* now save MIU regs */
656 if (par->chip != S3_SAVAGE_MX) {
657 reg->MMPR0 = savage_in32(FIFO_CONTROL_REG, par);
658 reg->MMPR1 = savage_in32(MIU_CONTROL_REG, par);
659 reg->MMPR2 = savage_in32(STREAMS_TIMEOUT_REG, par);
660 reg->MMPR3 = savage_in32(MISC_TIMEOUT_REG, par);
661 }
662
663 vga_out8 (0x3d4, 0x3a, par);
664 vga_out8 (0x3d5, cr3a, par);
665 vga_out8 (0x3d4, 0x66, par);
666 vga_out8 (0x3d5, cr66, par);
667 }
668
669 static void savage_update_var(struct fb_var_screeninfo *var, struct fb_videomode *modedb)
670 {
671 var->xres = var->xres_virtual = modedb->xres;
672 var->yres = modedb->yres;
673 if (var->yres_virtual < var->yres)
674 var->yres_virtual = var->yres;
675 var->xoffset = var->yoffset = 0;
676 var->pixclock = modedb->pixclock;
677 var->left_margin = modedb->left_margin;
678 var->right_margin = modedb->right_margin;
679 var->upper_margin = modedb->upper_margin;
680 var->lower_margin = modedb->lower_margin;
681 var->hsync_len = modedb->hsync_len;
682 var->vsync_len = modedb->vsync_len;
683 var->sync = modedb->sync;
684 var->vmode = modedb->vmode;
685 }
686
687 static int savagefb_check_var (struct fb_var_screeninfo *var,
688 struct fb_info *info)
689 {
690 struct savagefb_par *par = info->par;
691 int memlen, vramlen, mode_valid = 0;
692
693 DBG("savagefb_check_var");
694
695 var->transp.offset = 0;
696 var->transp.length = 0;
697 switch (var->bits_per_pixel) {
698 case 8:
699 var->red.offset = var->green.offset =
700 var->blue.offset = 0;
701 var->red.length = var->green.length =
702 var->blue.length = var->bits_per_pixel;
703 break;
704 case 16:
705 var->red.offset = 11;
706 var->red.length = 5;
707 var->green.offset = 5;
708 var->green.length = 6;
709 var->blue.offset = 0;
710 var->blue.length = 5;
711 break;
712 case 32:
713 var->transp.offset = 24;
714 var->transp.length = 8;
715 var->red.offset = 16;
716 var->red.length = 8;
717 var->green.offset = 8;
718 var->green.length = 8;
719 var->blue.offset = 0;
720 var->blue.length = 8;
721 break;
722
723 default:
724 return -EINVAL;
725 }
726
727 if (!info->monspecs.hfmax || !info->monspecs.vfmax ||
728 !info->monspecs.dclkmax || !fb_validate_mode(var, info))
729 mode_valid = 1;
730
731 /* calculate modeline if supported by monitor */
732 if (!mode_valid && info->monspecs.gtf) {
733 if (!fb_get_mode(FB_MAXTIMINGS, 0, var, info))
734 mode_valid = 1;
735 }
736
737 if (!mode_valid) {
738 struct fb_videomode *mode;
739
740 mode = fb_find_best_mode(var, &info->modelist);
741 if (mode) {
742 savage_update_var(var, mode);
743 mode_valid = 1;
744 }
745 }
746
747 if (!mode_valid && info->monspecs.modedb_len)
748 return -EINVAL;
749
750 /* Is the mode larger than the LCD panel? */
751 if (par->SavagePanelWidth &&
752 (var->xres > par->SavagePanelWidth ||
753 var->yres > par->SavagePanelHeight)) {
754 printk (KERN_INFO "Mode (%dx%d) larger than the LCD panel "
755 "(%dx%d)\n", var->xres, var->yres,
756 par->SavagePanelWidth,
757 par->SavagePanelHeight);
758 return -1;
759 }
760
761 if (var->yres_virtual < var->yres)
762 var->yres_virtual = var->yres;
763 if (var->xres_virtual < var->xres)
764 var->xres_virtual = var->xres;
765
766 vramlen = info->fix.smem_len;
767
768 memlen = var->xres_virtual * var->bits_per_pixel *
769 var->yres_virtual / 8;
770 if (memlen > vramlen) {
771 var->yres_virtual = vramlen * 8 /
772 (var->xres_virtual * var->bits_per_pixel);
773 memlen = var->xres_virtual * var->bits_per_pixel *
774 var->yres_virtual / 8;
775 }
776
777 /* we must round yres/xres down, we already rounded y/xres_virtual up
778 if it was possible. We should return -EINVAL, but I disagree */
779 if (var->yres_virtual < var->yres)
780 var->yres = var->yres_virtual;
781 if (var->xres_virtual < var->xres)
782 var->xres = var->xres_virtual;
783 if (var->xoffset + var->xres > var->xres_virtual)
784 var->xoffset = var->xres_virtual - var->xres;
785 if (var->yoffset + var->yres > var->yres_virtual)
786 var->yoffset = var->yres_virtual - var->yres;
787
788 return 0;
789 }
790
791
792 static int savagefb_decode_var (struct fb_var_screeninfo *var,
793 struct savagefb_par *par,
794 struct savage_reg *reg)
795 {
796 struct xtimings timings;
797 int width, dclk, i, j; /*, refresh; */
798 unsigned int m, n, r;
799 unsigned char tmp = 0;
800 unsigned int pixclock = var->pixclock;
801
802 DBG("savagefb_decode_var");
803
804 memset (&timings, 0, sizeof(timings));
805
806 if (!pixclock) pixclock = 10000; /* 10ns = 100MHz */
807 timings.Clock = 1000000000 / pixclock;
808 if (timings.Clock < 1) timings.Clock = 1;
809 timings.dblscan = var->vmode & FB_VMODE_DOUBLE;
810 timings.interlaced = var->vmode & FB_VMODE_INTERLACED;
811 timings.HDisplay = var->xres;
812 timings.HSyncStart = timings.HDisplay + var->right_margin;
813 timings.HSyncEnd = timings.HSyncStart + var->hsync_len;
814 timings.HTotal = timings.HSyncEnd + var->left_margin;
815 timings.VDisplay = var->yres;
816 timings.VSyncStart = timings.VDisplay + var->lower_margin;
817 timings.VSyncEnd = timings.VSyncStart + var->vsync_len;
818 timings.VTotal = timings.VSyncEnd + var->upper_margin;
819 timings.sync = var->sync;
820
821
822 par->depth = var->bits_per_pixel;
823 par->vwidth = var->xres_virtual;
824
825 if (var->bits_per_pixel == 16 && par->chip == S3_SAVAGE3D) {
826 timings.HDisplay *= 2;
827 timings.HSyncStart *= 2;
828 timings.HSyncEnd *= 2;
829 timings.HTotal *= 2;
830 }
831
832 /*
833 * This will allocate the datastructure and initialize all of the
834 * generic VGA registers.
835 */
836 vgaHWInit (var, par, &timings, reg);
837
838 /* We need to set CR67 whether or not we use the BIOS. */
839
840 dclk = timings.Clock;
841 reg->CR67 = 0x00;
842
843 switch( var->bits_per_pixel ) {
844 case 8:
845 if( (par->chip == S3_SAVAGE2000) && (dclk >= 230000) )
846 reg->CR67 = 0x10; /* 8bpp, 2 pixels/clock */
847 else
848 reg->CR67 = 0x00; /* 8bpp, 1 pixel/clock */
849 break;
850 case 15:
851 if ( S3_SAVAGE_MOBILE_SERIES(par->chip) ||
852 ((par->chip == S3_SAVAGE2000) && (dclk >= 230000)) )
853 reg->CR67 = 0x30; /* 15bpp, 2 pixel/clock */
854 else
855 reg->CR67 = 0x20; /* 15bpp, 1 pixels/clock */
856 break;
857 case 16:
858 if( S3_SAVAGE_MOBILE_SERIES(par->chip) ||
859 ((par->chip == S3_SAVAGE2000) && (dclk >= 230000)) )
860 reg->CR67 = 0x50; /* 16bpp, 2 pixel/clock */
861 else
862 reg->CR67 = 0x40; /* 16bpp, 1 pixels/clock */
863 break;
864 case 24:
865 reg->CR67 = 0x70;
866 break;
867 case 32:
868 reg->CR67 = 0xd0;
869 break;
870 }
871
872 /*
873 * Either BIOS use is disabled, or we failed to find a suitable
874 * match. Fall back to traditional register-crunching.
875 */
876
877 vga_out8 (0x3d4, 0x3a, par);
878 tmp = vga_in8 (0x3d5, par);
879 if (1 /*FIXME:psav->pci_burst*/)
880 reg->CR3A = (tmp & 0x7f) | 0x15;
881 else
882 reg->CR3A = tmp | 0x95;
883
884 reg->CR53 = 0x00;
885 reg->CR31 = 0x8c;
886 reg->CR66 = 0x89;
887
888 vga_out8 (0x3d4, 0x58, par);
889 reg->CR58 = vga_in8 (0x3d5, par) & 0x80;
890 reg->CR58 |= 0x13;
891
892 reg->SR15 = 0x03 | 0x80;
893 reg->SR18 = 0x00;
894 reg->CR43 = reg->CR45 = reg->CR65 = 0x00;
895
896 vga_out8 (0x3d4, 0x40, par);
897 reg->CR40 = vga_in8 (0x3d5, par) & ~0x01;
898
899 reg->MMPR0 = 0x010400;
900 reg->MMPR1 = 0x00;
901 reg->MMPR2 = 0x0808;
902 reg->MMPR3 = 0x08080810;
903
904 SavageCalcClock (dclk, 1, 1, 127, 0, 4, 180000, 360000, &m, &n, &r);
905 /* m = 107; n = 4; r = 2; */
906
907 if (par->MCLK <= 0) {
908 reg->SR10 = 255;
909 reg->SR11 = 255;
910 } else {
911 common_calc_clock (par->MCLK, 1, 1, 31, 0, 3, 135000, 270000,
912 &reg->SR11, &reg->SR10);
913 /* reg->SR10 = 80; // MCLK == 286000 */
914 /* reg->SR11 = 125; */
915 }
916
917 reg->SR12 = (r << 6) | (n & 0x3f);
918 reg->SR13 = m & 0xff;
919 reg->SR29 = (r & 4) | (m & 0x100) >> 5 | (n & 0x40) >> 2;
920
921 if (var->bits_per_pixel < 24)
922 reg->MMPR0 -= 0x8000;
923 else
924 reg->MMPR0 -= 0x4000;
925
926 if (timings.interlaced)
927 reg->CR42 = 0x20;
928 else
929 reg->CR42 = 0x00;
930
931 reg->CR34 = 0x10; /* display fifo */
932
933 i = ((((timings.HTotal >> 3) - 5) & 0x100) >> 8) |
934 ((((timings.HDisplay >> 3) - 1) & 0x100) >> 7) |
935 ((((timings.HSyncStart >> 3) - 1) & 0x100) >> 6) |
936 ((timings.HSyncStart & 0x800) >> 7);
937
938 if ((timings.HSyncEnd >> 3) - (timings.HSyncStart >> 3) > 64)
939 i |= 0x08;
940 if ((timings.HSyncEnd >> 3) - (timings.HSyncStart >> 3) > 32)
941 i |= 0x20;
942
943 j = (reg->CRTC[0] + ((i & 0x01) << 8) +
944 reg->CRTC[4] + ((i & 0x10) << 4) + 1) / 2;
945
946 if (j - (reg->CRTC[4] + ((i & 0x10) << 4)) < 4) {
947 if (reg->CRTC[4] + ((i & 0x10) << 4) + 4 <=
948 reg->CRTC[0] + ((i & 0x01) << 8))
949 j = reg->CRTC[4] + ((i & 0x10) << 4) + 4;
950 else
951 j = reg->CRTC[0] + ((i & 0x01) << 8) + 1;
952 }
953
954 reg->CR3B = j & 0xff;
955 i |= (j & 0x100) >> 2;
956 reg->CR3C = (reg->CRTC[0] + ((i & 0x01) << 8)) / 2;
957 reg->CR5D = i;
958 reg->CR5E = (((timings.VTotal - 2) & 0x400) >> 10) |
959 (((timings.VDisplay - 1) & 0x400) >> 9) |
960 (((timings.VSyncStart) & 0x400) >> 8) |
961 (((timings.VSyncStart) & 0x400) >> 6) | 0x40;
962 width = (var->xres_virtual * ((var->bits_per_pixel+7) / 8)) >> 3;
963 reg->CR91 = reg->CRTC[19] = 0xff & width;
964 reg->CR51 = (0x300 & width) >> 4;
965 reg->CR90 = 0x80 | (width >> 8);
966 reg->MiscOutReg |= 0x0c;
967
968 /* Set frame buffer description. */
969
970 if (var->bits_per_pixel <= 8)
971 reg->CR50 = 0;
972 else if (var->bits_per_pixel <= 16)
973 reg->CR50 = 0x10;
974 else
975 reg->CR50 = 0x30;
976
977 if (var->xres_virtual <= 640)
978 reg->CR50 |= 0x40;
979 else if (var->xres_virtual == 800)
980 reg->CR50 |= 0x80;
981 else if (var->xres_virtual == 1024)
982 reg->CR50 |= 0x00;
983 else if (var->xres_virtual == 1152)
984 reg->CR50 |= 0x01;
985 else if (var->xres_virtual == 1280)
986 reg->CR50 |= 0xc0;
987 else if (var->xres_virtual == 1600)
988 reg->CR50 |= 0x81;
989 else
990 reg->CR50 |= 0xc1; /* Use GBD */
991
992 if( par->chip == S3_SAVAGE2000 )
993 reg->CR33 = 0x08;
994 else
995 reg->CR33 = 0x20;
996
997 reg->CRTC[0x17] = 0xeb;
998
999 reg->CR67 |= 1;
1000
1001 vga_out8(0x3d4, 0x36, par);
1002 reg->CR36 = vga_in8 (0x3d5, par);
1003 vga_out8 (0x3d4, 0x68, par);
1004 reg->CR68 = vga_in8 (0x3d5, par);
1005 reg->CR69 = 0;
1006 vga_out8 (0x3d4, 0x6f, par);
1007 reg->CR6F = vga_in8 (0x3d5, par);
1008 vga_out8 (0x3d4, 0x86, par);
1009 reg->CR86 = vga_in8 (0x3d5, par);
1010 vga_out8 (0x3d4, 0x88, par);
1011 reg->CR88 = vga_in8 (0x3d5, par) | 0x08;
1012 vga_out8 (0x3d4, 0xb0, par);
1013 reg->CRB0 = vga_in8 (0x3d5, par) | 0x80;
1014
1015 return 0;
1016 }
1017
1018 /* --------------------------------------------------------------------- */
1019
1020 /*
1021 * Set a single color register. Return != 0 for invalid regno.
1022 */
1023 static int savagefb_setcolreg(unsigned regno,
1024 unsigned red,
1025 unsigned green,
1026 unsigned blue,
1027 unsigned transp,
1028 struct fb_info *info)
1029 {
1030 struct savagefb_par *par = info->par;
1031
1032 if (regno >= NR_PALETTE)
1033 return -EINVAL;
1034
1035 par->palette[regno].red = red;
1036 par->palette[regno].green = green;
1037 par->palette[regno].blue = blue;
1038 par->palette[regno].transp = transp;
1039
1040 switch (info->var.bits_per_pixel) {
1041 case 8:
1042 vga_out8 (0x3c8, regno, par);
1043
1044 vga_out8 (0x3c9, red >> 10, par);
1045 vga_out8 (0x3c9, green >> 10, par);
1046 vga_out8 (0x3c9, blue >> 10, par);
1047 break;
1048
1049 case 16:
1050 if (regno < 16)
1051 ((u32 *)info->pseudo_palette)[regno] =
1052 ((red & 0xf800) ) |
1053 ((green & 0xfc00) >> 5) |
1054 ((blue & 0xf800) >> 11);
1055 break;
1056
1057 case 24:
1058 if (regno < 16)
1059 ((u32 *)info->pseudo_palette)[regno] =
1060 ((red & 0xff00) << 8) |
1061 ((green & 0xff00) ) |
1062 ((blue & 0xff00) >> 8);
1063 break;
1064 case 32:
1065 if (regno < 16)
1066 ((u32 *)info->pseudo_palette)[regno] =
1067 ((transp & 0xff00) << 16) |
1068 ((red & 0xff00) << 8) |
1069 ((green & 0xff00) ) |
1070 ((blue & 0xff00) >> 8);
1071 break;
1072
1073 default:
1074 return 1;
1075 }
1076
1077 return 0;
1078 }
1079
1080 static void savagefb_set_par_int (struct savagefb_par *par, struct savage_reg *reg)
1081 {
1082 unsigned char tmp, cr3a, cr66, cr67;
1083
1084 DBG ("savagefb_set_par_int");
1085
1086 par->SavageWaitIdle (par);
1087
1088 vga_out8 (0x3c2, 0x23, par);
1089
1090 vga_out16 (0x3d4, 0x4838, par);
1091 vga_out16 (0x3d4, 0xa539, par);
1092 vga_out16 (0x3c4, 0x0608, par);
1093
1094 vgaHWProtect (par, 1);
1095
1096 /*
1097 * Some Savage/MX and /IX systems go nuts when trying to exit the
1098 * server after WindowMaker has displayed a gradient background. I
1099 * haven't been able to find what causes it, but a non-destructive
1100 * switch to mode 3 here seems to eliminate the issue.
1101 */
1102
1103 VerticalRetraceWait(par);
1104 vga_out8 (0x3d4, 0x67, par);
1105 cr67 = vga_in8 (0x3d5, par);
1106 vga_out8 (0x3d5, cr67/*par->CR67*/ & ~0x0c, par); /* no STREAMS yet */
1107
1108 vga_out8 (0x3d4, 0x23, par);
1109 vga_out8 (0x3d5, 0x00, par);
1110 vga_out8 (0x3d4, 0x26, par);
1111 vga_out8 (0x3d5, 0x00, par);
1112
1113 /* restore extended regs */
1114 vga_out8 (0x3d4, 0x66, par);
1115 vga_out8 (0x3d5, reg->CR66, par);
1116 vga_out8 (0x3d4, 0x3a, par);
1117 vga_out8 (0x3d5, reg->CR3A, par);
1118 vga_out8 (0x3d4, 0x31, par);
1119 vga_out8 (0x3d5, reg->CR31, par);
1120 vga_out8 (0x3d4, 0x32, par);
1121 vga_out8 (0x3d5, reg->CR32, par);
1122 vga_out8 (0x3d4, 0x58, par);
1123 vga_out8 (0x3d5, reg->CR58, par);
1124 vga_out8 (0x3d4, 0x53, par);
1125 vga_out8 (0x3d5, reg->CR53 & 0x7f, par);
1126
1127 vga_out16 (0x3c4, 0x0608, par);
1128
1129 /* Restore DCLK registers. */
1130
1131 vga_out8 (0x3c4, 0x0e, par);
1132 vga_out8 (0x3c5, reg->SR0E, par);
1133 vga_out8 (0x3c4, 0x0f, par);
1134 vga_out8 (0x3c5, reg->SR0F, par);
1135 vga_out8 (0x3c4, 0x29, par);
1136 vga_out8 (0x3c5, reg->SR29, par);
1137 vga_out8 (0x3c4, 0x15, par);
1138 vga_out8 (0x3c5, reg->SR15, par);
1139
1140 /* Restore flat panel expansion regsters. */
1141 if( par->chip == S3_SAVAGE_MX ) {
1142 int i;
1143
1144 for( i = 0; i < 8; i++ ) {
1145 vga_out8 (0x3c4, 0x54+i, par);
1146 vga_out8 (0x3c5, reg->SR54[i], par);
1147 }
1148 }
1149
1150 vgaHWRestore (par, reg);
1151
1152 /* extended mode timing registers */
1153 vga_out8 (0x3d4, 0x53, par);
1154 vga_out8 (0x3d5, reg->CR53, par);
1155 vga_out8 (0x3d4, 0x5d, par);
1156 vga_out8 (0x3d5, reg->CR5D, par);
1157 vga_out8 (0x3d4, 0x5e, par);
1158 vga_out8 (0x3d5, reg->CR5E, par);
1159 vga_out8 (0x3d4, 0x3b, par);
1160 vga_out8 (0x3d5, reg->CR3B, par);
1161 vga_out8 (0x3d4, 0x3c, par);
1162 vga_out8 (0x3d5, reg->CR3C, par);
1163 vga_out8 (0x3d4, 0x43, par);
1164 vga_out8 (0x3d5, reg->CR43, par);
1165 vga_out8 (0x3d4, 0x65, par);
1166 vga_out8 (0x3d5, reg->CR65, par);
1167
1168 /* restore the desired video mode with cr67 */
1169 vga_out8 (0x3d4, 0x67, par);
1170 /* following part not present in X11 driver */
1171 cr67 = vga_in8 (0x3d5, par) & 0xf;
1172 vga_out8 (0x3d5, 0x50 | cr67, par);
1173 udelay (10000);
1174 vga_out8 (0x3d4, 0x67, par);
1175 /* end of part */
1176 vga_out8 (0x3d5, reg->CR67 & ~0x0c, par);
1177
1178 /* other mode timing and extended regs */
1179 vga_out8 (0x3d4, 0x34, par);
1180 vga_out8 (0x3d5, reg->CR34, par);
1181 vga_out8 (0x3d4, 0x40, par);
1182 vga_out8 (0x3d5, reg->CR40, par);
1183 vga_out8 (0x3d4, 0x42, par);
1184 vga_out8 (0x3d5, reg->CR42, par);
1185 vga_out8 (0x3d4, 0x45, par);
1186 vga_out8 (0x3d5, reg->CR45, par);
1187 vga_out8 (0x3d4, 0x50, par);
1188 vga_out8 (0x3d5, reg->CR50, par);
1189 vga_out8 (0x3d4, 0x51, par);
1190 vga_out8 (0x3d5, reg->CR51, par);
1191
1192 /* memory timings */
1193 vga_out8 (0x3d4, 0x36, par);
1194 vga_out8 (0x3d5, reg->CR36, par);
1195 vga_out8 (0x3d4, 0x60, par);
1196 vga_out8 (0x3d5, reg->CR60, par);
1197 vga_out8 (0x3d4, 0x68, par);
1198 vga_out8 (0x3d5, reg->CR68, par);
1199 vga_out8 (0x3d4, 0x69, par);
1200 vga_out8 (0x3d5, reg->CR69, par);
1201 vga_out8 (0x3d4, 0x6f, par);
1202 vga_out8 (0x3d5, reg->CR6F, par);
1203
1204 vga_out8 (0x3d4, 0x33, par);
1205 vga_out8 (0x3d5, reg->CR33, par);
1206 vga_out8 (0x3d4, 0x86, par);
1207 vga_out8 (0x3d5, reg->CR86, par);
1208 vga_out8 (0x3d4, 0x88, par);
1209 vga_out8 (0x3d5, reg->CR88, par);
1210 vga_out8 (0x3d4, 0x90, par);
1211 vga_out8 (0x3d5, reg->CR90, par);
1212 vga_out8 (0x3d4, 0x91, par);
1213 vga_out8 (0x3d5, reg->CR91, par);
1214
1215 if (par->chip == S3_SAVAGE4) {
1216 vga_out8 (0x3d4, 0xb0, par);
1217 vga_out8 (0x3d5, reg->CRB0, par);
1218 }
1219
1220 vga_out8 (0x3d4, 0x32, par);
1221 vga_out8 (0x3d5, reg->CR32, par);
1222
1223 /* unlock extended seq regs */
1224 vga_out8 (0x3c4, 0x08, par);
1225 vga_out8 (0x3c5, 0x06, par);
1226
1227 /* Restore extended sequencer regs for MCLK. SR10 == 255 indicates
1228 * that we should leave the default SR10 and SR11 values there.
1229 */
1230 if (reg->SR10 != 255) {
1231 vga_out8 (0x3c4, 0x10, par);
1232 vga_out8 (0x3c5, reg->SR10, par);
1233 vga_out8 (0x3c4, 0x11, par);
1234 vga_out8 (0x3c5, reg->SR11, par);
1235 }
1236
1237 /* restore extended seq regs for dclk */
1238 vga_out8 (0x3c4, 0x0e, par);
1239 vga_out8 (0x3c5, reg->SR0E, par);
1240 vga_out8 (0x3c4, 0x0f, par);
1241 vga_out8 (0x3c5, reg->SR0F, par);
1242 vga_out8 (0x3c4, 0x12, par);
1243 vga_out8 (0x3c5, reg->SR12, par);
1244 vga_out8 (0x3c4, 0x13, par);
1245 vga_out8 (0x3c5, reg->SR13, par);
1246 vga_out8 (0x3c4, 0x29, par);
1247 vga_out8 (0x3c5, reg->SR29, par);
1248
1249 vga_out8 (0x3c4, 0x18, par);
1250 vga_out8 (0x3c5, reg->SR18, par);
1251
1252 /* load new m, n pll values for dclk & mclk */
1253 vga_out8 (0x3c4, 0x15, par);
1254 tmp = vga_in8 (0x3c5, par) & ~0x21;
1255
1256 vga_out8 (0x3c5, tmp | 0x03, par);
1257 vga_out8 (0x3c5, tmp | 0x23, par);
1258 vga_out8 (0x3c5, tmp | 0x03, par);
1259 vga_out8 (0x3c5, reg->SR15, par);
1260 udelay (100);
1261
1262 vga_out8 (0x3c4, 0x30, par);
1263 vga_out8 (0x3c5, reg->SR30, par);
1264 vga_out8 (0x3c4, 0x08, par);
1265 vga_out8 (0x3c5, reg->SR08, par);
1266
1267 /* now write out cr67 in full, possibly starting STREAMS */
1268 VerticalRetraceWait(par);
1269 vga_out8 (0x3d4, 0x67, par);
1270 vga_out8 (0x3d5, reg->CR67, par);
1271
1272 vga_out8 (0x3d4, 0x66, par);
1273 cr66 = vga_in8 (0x3d5, par);
1274 vga_out8 (0x3d5, cr66 | 0x80, par);
1275 vga_out8 (0x3d4, 0x3a, par);
1276 cr3a = vga_in8 (0x3d5, par);
1277 vga_out8 (0x3d5, cr3a | 0x80, par);
1278
1279 if (par->chip != S3_SAVAGE_MX) {
1280 VerticalRetraceWait(par);
1281 savage_out32 (FIFO_CONTROL_REG, reg->MMPR0, par);
1282 par->SavageWaitIdle (par);
1283 savage_out32 (MIU_CONTROL_REG, reg->MMPR1, par);
1284 par->SavageWaitIdle (par);
1285 savage_out32 (STREAMS_TIMEOUT_REG, reg->MMPR2, par);
1286 par->SavageWaitIdle (par);
1287 savage_out32 (MISC_TIMEOUT_REG, reg->MMPR3, par);
1288 }
1289
1290 vga_out8 (0x3d4, 0x66, par);
1291 vga_out8 (0x3d5, cr66, par);
1292 vga_out8 (0x3d4, 0x3a, par);
1293 vga_out8 (0x3d5, cr3a, par);
1294
1295 SavageSetup2DEngine (par);
1296 vgaHWProtect (par, 0);
1297 }
1298
1299 static void savagefb_update_start (struct savagefb_par *par,
1300 struct fb_var_screeninfo *var)
1301 {
1302 int base;
1303
1304 base = ((var->yoffset * var->xres_virtual + (var->xoffset & ~1))
1305 * ((var->bits_per_pixel+7) / 8)) >> 2;
1306
1307 /* now program the start address registers */
1308 vga_out16(0x3d4, (base & 0x00ff00) | 0x0c, par);
1309 vga_out16(0x3d4, ((base & 0x00ff) << 8) | 0x0d, par);
1310 vga_out8 (0x3d4, 0x69, par);
1311 vga_out8 (0x3d5, (base & 0x7f0000) >> 16, par);
1312 }
1313
1314
1315 static void savagefb_set_fix(struct fb_info *info)
1316 {
1317 info->fix.line_length = info->var.xres_virtual *
1318 info->var.bits_per_pixel / 8;
1319
1320 if (info->var.bits_per_pixel == 8) {
1321 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
1322 info->fix.xpanstep = 4;
1323 } else {
1324 info->fix.visual = FB_VISUAL_TRUECOLOR;
1325 info->fix.xpanstep = 2;
1326 }
1327
1328 }
1329
1330 #if defined(CONFIG_FB_SAVAGE_ACCEL)
1331 static void savagefb_set_clip(struct fb_info *info)
1332 {
1333 struct savagefb_par *par = info->par;
1334 int cmd;
1335
1336 cmd = BCI_CMD_NOP | BCI_CMD_CLIP_NEW;
1337 par->bci_ptr = 0;
1338 par->SavageWaitFifo(par,3);
1339 BCI_SEND(cmd);
1340 BCI_SEND(BCI_CLIP_TL(0, 0));
1341 BCI_SEND(BCI_CLIP_BR(0xfff, 0xfff));
1342 }
1343 #endif
1344
1345 static int savagefb_set_par (struct fb_info *info)
1346 {
1347 struct savagefb_par *par = info->par;
1348 struct fb_var_screeninfo *var = &info->var;
1349 int err;
1350
1351 DBG("savagefb_set_par");
1352 err = savagefb_decode_var (var, par, &par->state);
1353 if (err)
1354 return err;
1355
1356 if (par->dacSpeedBpp <= 0) {
1357 if (var->bits_per_pixel > 24)
1358 par->dacSpeedBpp = par->clock[3];
1359 else if (var->bits_per_pixel >= 24)
1360 par->dacSpeedBpp = par->clock[2];
1361 else if ((var->bits_per_pixel > 8) && (var->bits_per_pixel < 24))
1362 par->dacSpeedBpp = par->clock[1];
1363 else if (var->bits_per_pixel <= 8)
1364 par->dacSpeedBpp = par->clock[0];
1365 }
1366
1367 /* Set ramdac limits */
1368 par->maxClock = par->dacSpeedBpp;
1369 par->minClock = 10000;
1370
1371 savagefb_set_par_int (par, &par->state);
1372 fb_set_cmap (&info->cmap, info);
1373 savagefb_set_fix(info);
1374 savagefb_set_clip(info);
1375
1376 SavagePrintRegs();
1377 return 0;
1378 }
1379
1380 /*
1381 * Pan or Wrap the Display
1382 */
1383 static int savagefb_pan_display (struct fb_var_screeninfo *var,
1384 struct fb_info *info)
1385 {
1386 struct savagefb_par *par = info->par;
1387
1388 savagefb_update_start (par, var);
1389 return 0;
1390 }
1391
1392 static int savagefb_blank(int blank, struct fb_info *info)
1393 {
1394 struct savagefb_par *par = info->par;
1395 u8 sr8 = 0, srd = 0;
1396
1397 if (par->display_type == DISP_CRT) {
1398 vga_out8(0x3c4, 0x08, par);
1399 sr8 = vga_in8(0x3c5, par);
1400 sr8 |= 0x06;
1401 vga_out8(0x3c5, sr8, par);
1402 vga_out8(0x3c4, 0x0d, par);
1403 srd = vga_in8(0x3c5, par);
1404 srd &= 0x03;
1405
1406 switch (blank) {
1407 case FB_BLANK_UNBLANK:
1408 case FB_BLANK_NORMAL:
1409 break;
1410 case FB_BLANK_VSYNC_SUSPEND:
1411 srd |= 0x10;
1412 break;
1413 case FB_BLANK_HSYNC_SUSPEND:
1414 srd |= 0x40;
1415 break;
1416 case FB_BLANK_POWERDOWN:
1417 srd |= 0x50;
1418 break;
1419 }
1420
1421 vga_out8(0x3c4, 0x0d, par);
1422 vga_out8(0x3c5, srd, par);
1423 }
1424
1425 if (par->display_type == DISP_LCD ||
1426 par->display_type == DISP_DFP) {
1427 switch(blank) {
1428 case FB_BLANK_UNBLANK:
1429 case FB_BLANK_NORMAL:
1430 vga_out8(0x3c4, 0x31, par); /* SR31 bit 4 - FP enable */
1431 vga_out8(0x3c5, vga_in8(0x3c5, par) | 0x10, par);
1432 break;
1433 case FB_BLANK_VSYNC_SUSPEND:
1434 case FB_BLANK_HSYNC_SUSPEND:
1435 case FB_BLANK_POWERDOWN:
1436 vga_out8(0x3c4, 0x31, par); /* SR31 bit 4 - FP enable */
1437 vga_out8(0x3c5, vga_in8(0x3c5, par) & ~0x10, par);
1438 break;
1439 }
1440 }
1441
1442 return (blank == FB_BLANK_NORMAL) ? 1 : 0;
1443 }
1444
1445 static struct fb_ops savagefb_ops = {
1446 .owner = THIS_MODULE,
1447 .fb_check_var = savagefb_check_var,
1448 .fb_set_par = savagefb_set_par,
1449 .fb_setcolreg = savagefb_setcolreg,
1450 .fb_pan_display = savagefb_pan_display,
1451 .fb_blank = savagefb_blank,
1452 #if defined(CONFIG_FB_SAVAGE_ACCEL)
1453 .fb_fillrect = savagefb_fillrect,
1454 .fb_copyarea = savagefb_copyarea,
1455 .fb_imageblit = savagefb_imageblit,
1456 .fb_sync = savagefb_sync,
1457 #else
1458 .fb_fillrect = cfb_fillrect,
1459 .fb_copyarea = cfb_copyarea,
1460 .fb_imageblit = cfb_imageblit,
1461 #endif
1462 };
1463
1464 /* --------------------------------------------------------------------- */
1465
1466 static struct fb_var_screeninfo __devinitdata savagefb_var800x600x8 = {
1467 .accel_flags = FB_ACCELF_TEXT,
1468 .xres = 800,
1469 .yres = 600,
1470 .xres_virtual = 800,
1471 .yres_virtual = 600,
1472 .bits_per_pixel = 8,
1473 .pixclock = 25000,
1474 .left_margin = 88,
1475 .right_margin = 40,
1476 .upper_margin = 23,
1477 .lower_margin = 1,
1478 .hsync_len = 128,
1479 .vsync_len = 4,
1480 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
1481 .vmode = FB_VMODE_NONINTERLACED
1482 };
1483
1484 static void savage_enable_mmio (struct savagefb_par *par)
1485 {
1486 unsigned char val;
1487
1488 DBG ("savage_enable_mmio\n");
1489
1490 val = vga_in8 (0x3c3, par);
1491 vga_out8 (0x3c3, val | 0x01, par);
1492 val = vga_in8 (0x3cc, par);
1493 vga_out8 (0x3c2, val | 0x01, par);
1494
1495 if (par->chip >= S3_SAVAGE4) {
1496 vga_out8 (0x3d4, 0x40, par);
1497 val = vga_in8 (0x3d5, par);
1498 vga_out8 (0x3d5, val | 1, par);
1499 }
1500 }
1501
1502
1503 static void savage_disable_mmio (struct savagefb_par *par)
1504 {
1505 unsigned char val;
1506
1507 DBG ("savage_disable_mmio\n");
1508
1509 if(par->chip >= S3_SAVAGE4 ) {
1510 vga_out8 (0x3d4, 0x40, par);
1511 val = vga_in8 (0x3d5, par);
1512 vga_out8 (0x3d5, val | 1, par);
1513 }
1514 }
1515
1516
1517 static int __devinit savage_map_mmio (struct fb_info *info)
1518 {
1519 struct savagefb_par *par = info->par;
1520 DBG ("savage_map_mmio");
1521
1522 if (S3_SAVAGE3D_SERIES (par->chip))
1523 par->mmio.pbase = pci_resource_start (par->pcidev, 0) +
1524 SAVAGE_NEWMMIO_REGBASE_S3;
1525 else
1526 par->mmio.pbase = pci_resource_start (par->pcidev, 0) +
1527 SAVAGE_NEWMMIO_REGBASE_S4;
1528
1529 par->mmio.len = SAVAGE_NEWMMIO_REGSIZE;
1530
1531 par->mmio.vbase = ioremap (par->mmio.pbase, par->mmio.len);
1532 if (!par->mmio.vbase) {
1533 printk ("savagefb: unable to map memory mapped IO\n");
1534 return -ENOMEM;
1535 } else
1536 printk (KERN_INFO "savagefb: mapped io at %p\n",
1537 par->mmio.vbase);
1538
1539 info->fix.mmio_start = par->mmio.pbase;
1540 info->fix.mmio_len = par->mmio.len;
1541
1542 par->bci_base = (u32 __iomem *)(par->mmio.vbase + BCI_BUFFER_OFFSET);
1543 par->bci_ptr = 0;
1544
1545 savage_enable_mmio (par);
1546
1547 return 0;
1548 }
1549
1550 static void savage_unmap_mmio (struct fb_info *info)
1551 {
1552 struct savagefb_par *par = info->par;
1553 DBG ("savage_unmap_mmio");
1554
1555 savage_disable_mmio(par);
1556
1557 if (par->mmio.vbase) {
1558 iounmap(par->mmio.vbase);
1559 par->mmio.vbase = NULL;
1560 }
1561 }
1562
1563 static int __devinit savage_map_video (struct fb_info *info,
1564 int video_len)
1565 {
1566 struct savagefb_par *par = info->par;
1567 int resource;
1568
1569 DBG("savage_map_video");
1570
1571 if (S3_SAVAGE3D_SERIES (par->chip))
1572 resource = 0;
1573 else
1574 resource = 1;
1575
1576 par->video.pbase = pci_resource_start (par->pcidev, resource);
1577 par->video.len = video_len;
1578 par->video.vbase = ioremap (par->video.pbase, par->video.len);
1579
1580 if (!par->video.vbase) {
1581 printk ("savagefb: unable to map screen memory\n");
1582 return -ENOMEM;
1583 } else
1584 printk (KERN_INFO "savagefb: mapped framebuffer at %p, "
1585 "pbase == %x\n", par->video.vbase, par->video.pbase);
1586
1587 info->fix.smem_start = par->video.pbase;
1588 info->fix.smem_len = par->video.len - par->cob_size;
1589 info->screen_base = par->video.vbase;
1590
1591 #ifdef CONFIG_MTRR
1592 par->video.mtrr = mtrr_add (par->video.pbase, video_len,
1593 MTRR_TYPE_WRCOMB, 1);
1594 #endif
1595
1596 /* Clear framebuffer, it's all white in memory after boot */
1597 memset_io (par->video.vbase, 0, par->video.len);
1598
1599 return 0;
1600 }
1601
1602 static void savage_unmap_video (struct fb_info *info)
1603 {
1604 struct savagefb_par *par = info->par;
1605
1606 DBG("savage_unmap_video");
1607
1608 if (par->video.vbase) {
1609 #ifdef CONFIG_MTRR
1610 mtrr_del (par->video.mtrr, par->video.pbase, par->video.len);
1611 #endif
1612
1613 iounmap (par->video.vbase);
1614 par->video.vbase = NULL;
1615 info->screen_base = NULL;
1616 }
1617 }
1618
1619 static int savage_init_hw (struct savagefb_par *par)
1620 {
1621 unsigned char config1, m, n, n1, n2, sr8, cr3f, cr66 = 0, tmp;
1622
1623 static unsigned char RamSavage3D[] = { 8, 4, 4, 2 };
1624 static unsigned char RamSavage4[] = { 2, 4, 8, 12, 16, 32, 64, 32 };
1625 static unsigned char RamSavageMX[] = { 2, 8, 4, 16, 8, 16, 4, 16 };
1626 static unsigned char RamSavageNB[] = { 0, 2, 4, 8, 16, 32, 2, 2 };
1627 int videoRam, videoRambytes, dvi;
1628
1629 DBG("savage_init_hw");
1630
1631 /* unprotect CRTC[0-7] */
1632 vga_out8(0x3d4, 0x11, par);
1633 tmp = vga_in8(0x3d5, par);
1634 vga_out8(0x3d5, tmp & 0x7f, par);
1635
1636 /* unlock extended regs */
1637 vga_out16(0x3d4, 0x4838, par);
1638 vga_out16(0x3d4, 0xa039, par);
1639 vga_out16(0x3c4, 0x0608, par);
1640
1641 vga_out8(0x3d4, 0x40, par);
1642 tmp = vga_in8(0x3d5, par);
1643 vga_out8(0x3d5, tmp & ~0x01, par);
1644
1645 /* unlock sys regs */
1646 vga_out8(0x3d4, 0x38, par);
1647 vga_out8(0x3d5, 0x48, par);
1648
1649 /* Unlock system registers. */
1650 vga_out16(0x3d4, 0x4838, par);
1651
1652 /* Next go on to detect amount of installed ram */
1653
1654 vga_out8(0x3d4, 0x36, par); /* for register CR36 (CONFG_REG1), */
1655 config1 = vga_in8(0x3d5, par); /* get amount of vram installed */
1656
1657 /* Compute the amount of video memory and offscreen memory. */
1658
1659 switch (par->chip) {
1660 case S3_SAVAGE3D:
1661 videoRam = RamSavage3D[ (config1 & 0xC0) >> 6 ] * 1024;
1662 break;
1663
1664 case S3_SAVAGE4:
1665 /*
1666 * The Savage4 has one ugly special case to consider. On
1667 * systems with 4 banks of 2Mx32 SDRAM, the BIOS says 4MB
1668 * when it really means 8MB. Why do it the same when you
1669 * can do it different...
1670 */
1671 vga_out8(0x3d4, 0x68, par); /* memory control 1 */
1672 if( (vga_in8(0x3d5, par) & 0xC0) == (0x01 << 6) )
1673 RamSavage4[1] = 8;
1674
1675 /*FALLTHROUGH*/
1676
1677 case S3_SAVAGE2000:
1678 videoRam = RamSavage4[ (config1 & 0xE0) >> 5 ] * 1024;
1679 break;
1680
1681 case S3_SAVAGE_MX:
1682 case S3_SUPERSAVAGE:
1683 videoRam = RamSavageMX[ (config1 & 0x0E) >> 1 ] * 1024;
1684 break;
1685
1686 case S3_PROSAVAGE:
1687 videoRam = RamSavageNB[ (config1 & 0xE0) >> 5 ] * 1024;
1688 break;
1689
1690 default:
1691 /* How did we get here? */
1692 videoRam = 0;
1693 break;
1694 }
1695
1696 videoRambytes = videoRam * 1024;
1697
1698 printk (KERN_INFO "savagefb: probed videoram: %dk\n", videoRam);
1699
1700 /* reset graphics engine to avoid memory corruption */
1701 vga_out8 (0x3d4, 0x66, par);
1702 cr66 = vga_in8 (0x3d5, par);
1703 vga_out8 (0x3d5, cr66 | 0x02, par);
1704 udelay (10000);
1705
1706 vga_out8 (0x3d4, 0x66, par);
1707 vga_out8 (0x3d5, cr66 & ~0x02, par); /* clear reset flag */
1708 udelay (10000);
1709
1710
1711 /*
1712 * reset memory interface, 3D engine, AGP master, PCI master,
1713 * master engine unit, motion compensation/LPB
1714 */
1715 vga_out8 (0x3d4, 0x3f, par);
1716 cr3f = vga_in8 (0x3d5, par);
1717 vga_out8 (0x3d5, cr3f | 0x08, par);
1718 udelay (10000);
1719
1720 vga_out8 (0x3d4, 0x3f, par);
1721 vga_out8 (0x3d5, cr3f & ~0x08, par); /* clear reset flags */
1722 udelay (10000);
1723
1724 /* Savage ramdac speeds */
1725 par->numClocks = 4;
1726 par->clock[0] = 250000;
1727 par->clock[1] = 250000;
1728 par->clock[2] = 220000;
1729 par->clock[3] = 220000;
1730
1731 /* detect current mclk */
1732 vga_out8(0x3c4, 0x08, par);
1733 sr8 = vga_in8(0x3c5, par);
1734 vga_out8(0x3c5, 0x06, par);
1735 vga_out8(0x3c4, 0x10, par);
1736 n = vga_in8(0x3c5, par);
1737 vga_out8(0x3c4, 0x11, par);
1738 m = vga_in8(0x3c5, par);
1739 vga_out8(0x3c4, 0x08, par);
1740 vga_out8(0x3c5, sr8, par);
1741 m &= 0x7f;
1742 n1 = n & 0x1f;
1743 n2 = (n >> 5) & 0x03;
1744 par->MCLK = ((1431818 * (m+2)) / (n1+2) / (1 << n2) + 50) / 100;
1745 printk (KERN_INFO "savagefb: Detected current MCLK value of %d kHz\n",
1746 par->MCLK);
1747
1748 /* check for DVI/flat panel */
1749 dvi = 0;
1750
1751 if (par->chip == S3_SAVAGE4) {
1752 unsigned char sr30 = 0x00;
1753
1754 vga_out8(0x3c4, 0x30, par);
1755 /* clear bit 1 */
1756 vga_out8(0x3c5, vga_in8(0x3c5, par) & ~0x02, par);
1757 sr30 = vga_in8(0x3c5, par);
1758 if (sr30 & 0x02 /*0x04 */) {
1759 dvi = 1;
1760 printk("savagefb: Digital Flat Panel Detected\n");
1761 }
1762 }
1763
1764 if (S3_SAVAGE_MOBILE_SERIES(par->chip) && !par->crtonly)
1765 par->display_type = DISP_LCD;
1766 else if (dvi || (par->chip == S3_SAVAGE4 && par->dvi))
1767 par->display_type = DISP_DFP;
1768 else
1769 par->display_type = DISP_CRT;
1770
1771 /* Check LCD panel parrmation */
1772
1773 if (par->display_type == DISP_LCD) {
1774 unsigned char cr6b = VGArCR( 0x6b, par);
1775
1776 int panelX = (VGArSEQ (0x61, par) +
1777 ((VGArSEQ (0x66, par) & 0x02) << 7) + 1) * 8;
1778 int panelY = (VGArSEQ (0x69, par) +
1779 ((VGArSEQ (0x6e, par) & 0x70) << 4) + 1);
1780
1781 char * sTechnology = "Unknown";
1782
1783 /* OK, I admit it. I don't know how to limit the max dot clock
1784 * for LCD panels of various sizes. I thought I copied the
1785 * formula from the BIOS, but many users have parrmed me of
1786 * my folly.
1787 *
1788 * Instead, I'll abandon any attempt to automatically limit the
1789 * clock, and add an LCDClock option to XF86Config. Some day,
1790 * I should come back to this.
1791 */
1792
1793 enum ACTIVE_DISPLAYS { /* These are the bits in CR6B */
1794 ActiveCRT = 0x01,
1795 ActiveLCD = 0x02,
1796 ActiveTV = 0x04,
1797 ActiveCRT2 = 0x20,
1798 ActiveDUO = 0x80
1799 };
1800
1801 if ((VGArSEQ (0x39, par) & 0x03) == 0) {
1802 sTechnology = "TFT";
1803 } else if ((VGArSEQ (0x30, par) & 0x01) == 0) {
1804 sTechnology = "DSTN";
1805 } else {
1806 sTechnology = "STN";
1807 }
1808
1809 printk (KERN_INFO "savagefb: %dx%d %s LCD panel detected %s\n",
1810 panelX, panelY, sTechnology,
1811 cr6b & ActiveLCD ? "and active" : "but not active");
1812
1813 if( cr6b & ActiveLCD ) {
1814 /*
1815 * If the LCD is active and panel expansion is enabled,
1816 * we probably want to kill the HW cursor.
1817 */
1818
1819 printk (KERN_INFO "savagefb: Limiting video mode to "
1820 "%dx%d\n", panelX, panelY );
1821
1822 par->SavagePanelWidth = panelX;
1823 par->SavagePanelHeight = panelY;
1824
1825 } else
1826 par->display_type = DISP_CRT;
1827 }
1828
1829 savage_get_default_par (par, &par->state);
1830 par->save = par->state;
1831
1832 if( S3_SAVAGE4_SERIES(par->chip) ) {
1833 /*
1834 * The Savage4 and ProSavage have COB coherency bugs which
1835 * render the buffer useless. We disable it.
1836 */
1837 par->cob_index = 2;
1838 par->cob_size = 0x8000 << par->cob_index;
1839 par->cob_offset = videoRambytes;
1840 } else {
1841 /* We use 128kB for the COB on all chips. */
1842
1843 par->cob_index = 7;
1844 par->cob_size = 0x400 << par->cob_index;
1845 par->cob_offset = videoRambytes - par->cob_size;
1846 }
1847
1848 return videoRambytes;
1849 }
1850
1851 static int __devinit savage_init_fb_info (struct fb_info *info,
1852 struct pci_dev *dev,
1853 const struct pci_device_id *id)
1854 {
1855 struct savagefb_par *par = info->par;
1856 int err = 0;
1857
1858 par->pcidev = dev;
1859
1860 info->fix.type = FB_TYPE_PACKED_PIXELS;
1861 info->fix.type_aux = 0;
1862 info->fix.ypanstep = 1;
1863 info->fix.ywrapstep = 0;
1864 info->fix.accel = id->driver_data;
1865
1866 switch (info->fix.accel) {
1867 case FB_ACCEL_SUPERSAVAGE:
1868 par->chip = S3_SUPERSAVAGE;
1869 snprintf (info->fix.id, 16, "SuperSavage");
1870 break;
1871 case FB_ACCEL_SAVAGE4:
1872 par->chip = S3_SAVAGE4;
1873 snprintf (info->fix.id, 16, "Savage4");
1874 break;
1875 case FB_ACCEL_SAVAGE3D:
1876 par->chip = S3_SAVAGE3D;
1877 snprintf (info->fix.id, 16, "Savage3D");
1878 break;
1879 case FB_ACCEL_SAVAGE3D_MV:
1880 par->chip = S3_SAVAGE3D;
1881 snprintf (info->fix.id, 16, "Savage3D-MV");
1882 break;
1883 case FB_ACCEL_SAVAGE2000:
1884 par->chip = S3_SAVAGE2000;
1885 snprintf (info->fix.id, 16, "Savage2000");
1886 break;
1887 case FB_ACCEL_SAVAGE_MX_MV:
1888 par->chip = S3_SAVAGE_MX;
1889 snprintf (info->fix.id, 16, "Savage/MX-MV");
1890 break;
1891 case FB_ACCEL_SAVAGE_MX:
1892 par->chip = S3_SAVAGE_MX;
1893 snprintf (info->fix.id, 16, "Savage/MX");
1894 break;
1895 case FB_ACCEL_SAVAGE_IX_MV:
1896 par->chip = S3_SAVAGE_MX;
1897 snprintf (info->fix.id, 16, "Savage/IX-MV");
1898 break;
1899 case FB_ACCEL_SAVAGE_IX:
1900 par->chip = S3_SAVAGE_MX;
1901 snprintf (info->fix.id, 16, "Savage/IX");
1902 break;
1903 case FB_ACCEL_PROSAVAGE_PM:
1904 par->chip = S3_PROSAVAGE;
1905 snprintf (info->fix.id, 16, "ProSavagePM");
1906 break;
1907 case FB_ACCEL_PROSAVAGE_KM:
1908 par->chip = S3_PROSAVAGE;
1909 snprintf (info->fix.id, 16, "ProSavageKM");
1910 break;
1911 case FB_ACCEL_S3TWISTER_P:
1912 par->chip = S3_PROSAVAGE;
1913 snprintf (info->fix.id, 16, "TwisterP");
1914 break;
1915 case FB_ACCEL_S3TWISTER_K:
1916 par->chip = S3_PROSAVAGE;
1917 snprintf (info->fix.id, 16, "TwisterK");
1918 break;
1919 case FB_ACCEL_PROSAVAGE_DDR:
1920 par->chip = S3_PROSAVAGE;
1921 snprintf (info->fix.id, 16, "ProSavageDDR");
1922 break;
1923 case FB_ACCEL_PROSAVAGE_DDRK:
1924 par->chip = S3_PROSAVAGE;
1925 snprintf (info->fix.id, 16, "ProSavage8");
1926 break;
1927 }
1928
1929 if (S3_SAVAGE3D_SERIES(par->chip)) {
1930 par->SavageWaitIdle = savage3D_waitidle;
1931 par->SavageWaitFifo = savage3D_waitfifo;
1932 } else if (S3_SAVAGE4_SERIES(par->chip) ||
1933 S3_SUPERSAVAGE == par->chip) {
1934 par->SavageWaitIdle = savage4_waitidle;
1935 par->SavageWaitFifo = savage4_waitfifo;
1936 } else {
1937 par->SavageWaitIdle = savage2000_waitidle;
1938 par->SavageWaitFifo = savage2000_waitfifo;
1939 }
1940
1941 info->var.nonstd = 0;
1942 info->var.activate = FB_ACTIVATE_NOW;
1943 info->var.width = -1;
1944 info->var.height = -1;
1945 info->var.accel_flags = 0;
1946
1947 info->fbops = &savagefb_ops;
1948 info->flags = FBINFO_DEFAULT |
1949 FBINFO_HWACCEL_YPAN |
1950 FBINFO_HWACCEL_XPAN;
1951
1952 info->pseudo_palette = par->pseudo_palette;
1953
1954 #if defined(CONFIG_FB_SAVAGE_ACCEL)
1955 /* FIFO size + padding for commands */
1956 info->pixmap.addr = kmalloc(8*1024, GFP_KERNEL);
1957
1958 err = -ENOMEM;
1959 if (info->pixmap.addr) {
1960 memset(info->pixmap.addr, 0, 8*1024);
1961 info->pixmap.size = 8*1024;
1962 info->pixmap.scan_align = 4;
1963 info->pixmap.buf_align = 4;
1964 info->pixmap.access_align = 32;
1965
1966 err = fb_alloc_cmap (&info->cmap, NR_PALETTE, 0);
1967 if (!err)
1968 info->flags |= FBINFO_HWACCEL_COPYAREA |
1969 FBINFO_HWACCEL_FILLRECT |
1970 FBINFO_HWACCEL_IMAGEBLIT;
1971 }
1972 #endif
1973 return err;
1974 }
1975
1976 /* --------------------------------------------------------------------- */
1977
1978 static int __devinit savagefb_probe (struct pci_dev* dev,
1979 const struct pci_device_id* id)
1980 {
1981 struct fb_info *info;
1982 struct savagefb_par *par;
1983 u_int h_sync, v_sync;
1984 int err, lpitch;
1985 int video_len;
1986
1987 DBG("savagefb_probe");
1988 SavagePrintRegs();
1989
1990 info = framebuffer_alloc(sizeof(struct savagefb_par), &dev->dev);
1991 if (!info)
1992 return -ENOMEM;
1993 par = info->par;
1994 err = pci_enable_device(dev);
1995 if (err)
1996 goto failed_enable;
1997
1998 if ((err = pci_request_regions(dev, "savagefb"))) {
1999 printk(KERN_ERR "cannot request PCI regions\n");
2000 goto failed_enable;
2001 }
2002
2003 err = -ENOMEM;
2004
2005 if ((err = savage_init_fb_info(info, dev, id)))
2006 goto failed_init;
2007
2008 err = savage_map_mmio(info);
2009 if (err)
2010 goto failed_mmio;
2011
2012 video_len = savage_init_hw(par);
2013 /* FIXME: cant be negative */
2014 if (video_len < 0) {
2015 err = video_len;
2016 goto failed_mmio;
2017 }
2018
2019 err = savage_map_video(info, video_len);
2020 if (err)
2021 goto failed_video;
2022
2023 INIT_LIST_HEAD(&info->modelist);
2024 #if defined(CONFIG_FB_SAVAGE_I2C)
2025 savagefb_create_i2c_busses(info);
2026 savagefb_probe_i2c_connector(info, &par->edid);
2027 fb_edid_to_monspecs(par->edid, &info->monspecs);
2028 kfree(par->edid);
2029 fb_videomode_to_modelist(info->monspecs.modedb,
2030 info->monspecs.modedb_len,
2031 &info->modelist);
2032 #endif
2033 info->var = savagefb_var800x600x8;
2034
2035 if (mode_option) {
2036 fb_find_mode(&info->var, info, mode_option,
2037 info->monspecs.modedb, info->monspecs.modedb_len,
2038 NULL, 8);
2039 } else if (info->monspecs.modedb != NULL) {
2040 struct fb_videomode *modedb;
2041
2042 modedb = fb_find_best_display(&info->monspecs,
2043 &info->modelist);
2044 savage_update_var(&info->var, modedb);
2045 }
2046
2047 /* maximize virtual vertical length */
2048 lpitch = info->var.xres_virtual*((info->var.bits_per_pixel + 7) >> 3);
2049 info->var.yres_virtual = info->fix.smem_len/lpitch;
2050
2051 if (info->var.yres_virtual < info->var.yres)
2052 goto failed;
2053
2054 #if defined(CONFIG_FB_SAVAGE_ACCEL)
2055 /*
2056 * The clipping coordinates are masked with 0xFFF, so limit our
2057 * virtual resolutions to these sizes.
2058 */
2059 if (info->var.yres_virtual > 0x1000)
2060 info->var.yres_virtual = 0x1000;
2061
2062 if (info->var.xres_virtual > 0x1000)
2063 info->var.xres_virtual = 0x1000;
2064 #endif
2065 savagefb_check_var(&info->var, info);
2066 savagefb_set_fix(info);
2067
2068 /*
2069 * Calculate the hsync and vsync frequencies. Note that
2070 * we split the 1e12 constant up so that we can preserve
2071 * the precision and fit the results into 32-bit registers.
2072 * (1953125000 * 512 = 1e12)
2073 */
2074 h_sync = 1953125000 / info->var.pixclock;
2075 h_sync = h_sync * 512 / (info->var.xres + info->var.left_margin +
2076 info->var.right_margin +
2077 info->var.hsync_len);
2078 v_sync = h_sync / (info->var.yres + info->var.upper_margin +
2079 info->var.lower_margin + info->var.vsync_len);
2080
2081 printk(KERN_INFO "savagefb v" SAVAGEFB_VERSION ": "
2082 "%dkB VRAM, using %dx%d, %d.%03dkHz, %dHz\n",
2083 info->fix.smem_len >> 10,
2084 info->var.xres, info->var.yres,
2085 h_sync / 1000, h_sync % 1000, v_sync);
2086
2087
2088 fb_destroy_modedb(info->monspecs.modedb);
2089 info->monspecs.modedb = NULL;
2090
2091 err = register_framebuffer (info);
2092 if (err < 0)
2093 goto failed;
2094
2095 printk (KERN_INFO "fb: S3 %s frame buffer device\n",
2096 info->fix.id);
2097
2098 /*
2099 * Our driver data
2100 */
2101 pci_set_drvdata(dev, info);
2102
2103 return 0;
2104
2105 failed:
2106 #ifdef CONFIG_FB_SAVAGE_I2C
2107 savagefb_delete_i2c_busses(info);
2108 #endif
2109 fb_alloc_cmap (&info->cmap, 0, 0);
2110 savage_unmap_video(info);
2111 failed_video:
2112 savage_unmap_mmio (info);
2113 failed_mmio:
2114 kfree(info->pixmap.addr);
2115 failed_init:
2116 pci_release_regions(dev);
2117 failed_enable:
2118 framebuffer_release(info);
2119
2120 return err;
2121 }
2122
2123 static void __devexit savagefb_remove (struct pci_dev *dev)
2124 {
2125 struct fb_info *info = pci_get_drvdata(dev);
2126
2127 DBG("savagefb_remove");
2128
2129 if (info) {
2130 /*
2131 * If unregister_framebuffer fails, then
2132 * we will be leaving hooks that could cause
2133 * oopsen laying around.
2134 */
2135 if (unregister_framebuffer (info))
2136 printk (KERN_WARNING "savagefb: danger danger! "
2137 "Oopsen imminent!\n");
2138
2139 #ifdef CONFIG_FB_SAVAGE_I2C
2140 savagefb_delete_i2c_busses(info);
2141 #endif
2142 fb_alloc_cmap (&info->cmap, 0, 0);
2143 savage_unmap_video (info);
2144 savage_unmap_mmio (info);
2145 kfree(info->pixmap.addr);
2146 pci_release_regions(dev);
2147 framebuffer_release(info);
2148
2149 /*
2150 * Ensure that the driver data is no longer
2151 * valid.
2152 */
2153 pci_set_drvdata(dev, NULL);
2154 }
2155 }
2156
2157 static int savagefb_suspend (struct pci_dev* dev, pm_message_t state)
2158 {
2159 struct fb_info *info = pci_get_drvdata(dev);
2160 struct savagefb_par *par = info->par;
2161
2162 DBG("savagefb_suspend");
2163
2164
2165 par->pm_state = state.event;
2166
2167 /*
2168 * For PM_EVENT_FREEZE, do not power down so the console
2169 * can remain active.
2170 */
2171 if (state.event == PM_EVENT_FREEZE) {
2172 dev->dev.power.power_state = state;
2173 return 0;
2174 }
2175
2176 acquire_console_sem();
2177 fb_set_suspend(info, 1);
2178
2179 if (info->fbops->fb_sync)
2180 info->fbops->fb_sync(info);
2181
2182 savagefb_blank(FB_BLANK_POWERDOWN, info);
2183 savage_disable_mmio(par);
2184 pci_save_state(dev);
2185 pci_disable_device(dev);
2186 pci_set_power_state(dev, pci_choose_state(dev, state));
2187 release_console_sem();
2188
2189 return 0;
2190 }
2191
2192 static int savagefb_resume (struct pci_dev* dev)
2193 {
2194 struct fb_info *info = pci_get_drvdata(dev);
2195 struct savagefb_par *par = info->par;
2196 int cur_state = par->pm_state;
2197
2198 DBG("savage_resume");
2199
2200 par->pm_state = PM_EVENT_ON;
2201
2202 /*
2203 * The adapter was not powered down coming back from a
2204 * PM_EVENT_FREEZE.
2205 */
2206 if (cur_state == PM_EVENT_FREEZE) {
2207 pci_set_power_state(dev, PCI_D0);
2208 return 0;
2209 }
2210
2211 acquire_console_sem();
2212
2213 pci_set_power_state(dev, PCI_D0);
2214 pci_restore_state(dev);
2215
2216 if(pci_enable_device(dev))
2217 DBG("err");
2218
2219 pci_set_master(dev);
2220 savage_enable_mmio(par);
2221 savage_init_hw(par);
2222 savagefb_set_par (info);
2223 savagefb_blank(FB_BLANK_UNBLANK, info);
2224 fb_set_suspend (info, 0);
2225 release_console_sem();
2226
2227 return 0;
2228 }
2229
2230
2231 static struct pci_device_id savagefb_devices[] __devinitdata = {
2232 {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_MX128,
2233 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2234
2235 {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_MX64,
2236 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2237
2238 {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_MX64C,
2239 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2240
2241 {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_IX128SDR,
2242 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2243
2244 {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_IX128DDR,
2245 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2246
2247 {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_IX64SDR,
2248 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2249
2250 {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_IX64DDR,
2251 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2252
2253 {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_IXCSDR,
2254 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2255
2256 {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_IXCDDR,
2257 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2258
2259 {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE4,
2260 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE4},
2261
2262 {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE3D,
2263 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE3D},
2264
2265 {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE3D_MV,
2266 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE3D_MV},
2267
2268 {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE2000,
2269 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE2000},
2270
2271 {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE_MX_MV,
2272 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE_MX_MV},
2273
2274 {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE_MX,
2275 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE_MX},
2276
2277 {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE_IX_MV,
2278 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE_IX_MV},
2279
2280 {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE_IX,
2281 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE_IX},
2282
2283 {PCI_VENDOR_ID_S3, PCI_CHIP_PROSAVAGE_PM,
2284 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_PROSAVAGE_PM},
2285
2286 {PCI_VENDOR_ID_S3, PCI_CHIP_PROSAVAGE_KM,
2287 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_PROSAVAGE_KM},
2288
2289 {PCI_VENDOR_ID_S3, PCI_CHIP_S3TWISTER_P,
2290 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_S3TWISTER_P},
2291
2292 {PCI_VENDOR_ID_S3, PCI_CHIP_S3TWISTER_K,
2293 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_S3TWISTER_K},
2294
2295 {PCI_VENDOR_ID_S3, PCI_CHIP_PROSAVAGE_DDR,
2296 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_PROSAVAGE_DDR},
2297
2298 {PCI_VENDOR_ID_S3, PCI_CHIP_PROSAVAGE_DDRK,
2299 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_PROSAVAGE_DDRK},
2300
2301 {0, 0, 0, 0, 0, 0, 0}
2302 };
2303
2304 MODULE_DEVICE_TABLE(pci, savagefb_devices);
2305
2306 static struct pci_driver savagefb_driver = {
2307 .name = "savagefb",
2308 .id_table = savagefb_devices,
2309 .probe = savagefb_probe,
2310 .suspend = savagefb_suspend,
2311 .resume = savagefb_resume,
2312 .remove = __devexit_p(savagefb_remove)
2313 };
2314
2315 /* **************************** exit-time only **************************** */
2316
2317 static void __exit savage_done (void)
2318 {
2319 DBG("savage_done");
2320 pci_unregister_driver (&savagefb_driver);
2321 }
2322
2323
2324 /* ************************* init in-kernel code ************************** */
2325
2326 static int __init savagefb_setup(char *options)
2327 {
2328 #ifndef MODULE
2329 char *this_opt;
2330
2331 if (!options || !*options)
2332 return 0;
2333
2334 while ((this_opt = strsep(&options, ",")) != NULL) {
2335 mode_option = this_opt;
2336 }
2337 #endif /* !MODULE */
2338 return 0;
2339 }
2340
2341 static int __init savagefb_init(void)
2342 {
2343 char *option;
2344
2345 DBG("savagefb_init");
2346
2347 if (fb_get_options("savagefb", &option))
2348 return -ENODEV;
2349
2350 savagefb_setup(option);
2351 return pci_register_driver (&savagefb_driver);
2352
2353 }
2354
2355 module_init(savagefb_init);
2356 module_exit(savage_done);
2357
2358 module_param(mode_option, charp, 0);
2359 MODULE_PARM_DESC(mode_option, "Specify initial video mode");
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree