arch/arm/mach-pxa/cm-x2xx-pci.c

   1 /*
   2  * linux/arch/arm/mach-pxa/cm-x2xx-pci.c
   3  *
   4  * PCI bios-type initialisation for PCI machines
   5  *
   6  * Bits taken from various places.
   7  *
   8  * Copyright (C) 2007, 2008 Compulab, Ltd.
   9  * Mike Rapoport <mike@compulab.co.il>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/pci.h>
  18 #include <linux/init.h>
  19 #include <linux/device.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/irq.h>
  22 #include <linux/gpio.h>
  23
  24 #include <asm/mach/pci.h>
  25 #include <asm/mach-types.h>
  26
  27 #include <asm/hardware/it8152.h>
  28
  29 unsigned long it8152_base_address;
  30 static int cmx2xx_it8152_irq_gpio;
  31
  32 /*
  33  * Only first 64MB of memory can be accessed via PCI.
  34  * We use GFP_DMA to allocate safe buffers to do map/unmap.
  35  * This is really ugly and we need a better way of specifying
  36  * DMA-capable regions of memory.
  37  */
  38 void __init cmx2xx_pci_adjust_zones(unsigned long *zone_size,
  39         unsigned long *zhole_size)
  40 {
  41         unsigned int sz = SZ_64M >> PAGE_SHIFT;
  42
  43         if (machine_is_armcore()) {
  44                 pr_info("Adjusting zones for CM-X2XX\n");
  45
  46                 /*
  47                  * Only adjust if > 64M on current system
  48                  */
  49                 if (zone_size[0] <= sz)
  50                         return;
  51
  52                 zone_size[1] = zone_size[0] - sz;
  53                 zone_size[0] = sz;
  54                 zhole_size[1] = zhole_size[0];
  55                 zhole_size[0] = 0;
  56         }
  57 }
  58
  59 static void cmx2xx_it8152_irq_demux(unsigned int irq, struct irq_desc *desc)
  60 {
  61         /* clear our parent irq */
  62         desc->irq_data.chip->irq_ack(&desc->irq_data);
  63
  64         it8152_irq_demux(irq, desc);
  65 }
  66
  67 void __cmx2xx_pci_init_irq(int irq_gpio)
  68 {
  69         it8152_init_irq();
  70
  71         cmx2xx_it8152_irq_gpio = irq_gpio;
  72
  73         irq_set_irq_type(gpio_to_irq(irq_gpio), IRQ_TYPE_EDGE_RISING);
  74
  75         irq_set_chained_handler(gpio_to_irq(irq_gpio),
  76                                 cmx2xx_it8152_irq_demux);
  77 }
  78
  79 #ifdef CONFIG_PM
  80 static unsigned long sleep_save_ite[10];
  81
  82 void __cmx2xx_pci_suspend(void)
  83 {
  84         /* save ITE state */
  85         sleep_save_ite[0] = __raw_readl(IT8152_INTC_PDCNIMR);
  86         sleep_save_ite[1] = __raw_readl(IT8152_INTC_LPCNIMR);
  87         sleep_save_ite[2] = __raw_readl(IT8152_INTC_LPNIAR);
  88
  89         /* Clear ITE IRQ's */
  90         __raw_writel((0), IT8152_INTC_PDCNIRR);
  91         __raw_writel((0), IT8152_INTC_LPCNIRR);
  92 }
  93
  94 void __cmx2xx_pci_resume(void)
  95 {
  96         /* restore IT8152 state */
  97         __raw_writel((sleep_save_ite[0]), IT8152_INTC_PDCNIMR);
  98         __raw_writel((sleep_save_ite[1]), IT8152_INTC_LPCNIMR);
  99         __raw_writel((sleep_save_ite[2]), IT8152_INTC_LPNIAR);
 100 }
 101 #else
 102 void cmx2xx_pci_suspend(void) {}
 103 void cmx2xx_pci_resume(void) {}
 104 #endif
 105
 106 /* PCI IRQ mapping*/
 107 static int __init cmx2xx_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 108 {
 109         int irq;
 110
 111         dev_dbg(&dev->dev, "%s: slot=%x, pin=%x\n", __func__, slot, pin);
 112
 113         irq = it8152_pci_map_irq(dev, slot, pin);
 114         if (irq)
 115                 return irq;
 116
 117         /*
 118           Here comes the ugly part. The routing is baseboard specific,
 119           but defining a platform for each possible base of CM-X2XX is
 120           unrealistic. Here we keep mapping for ATXBase and SB-X2XX.
 121         */
 122         /* ATXBASE PCI slot */
 123         if (slot == 7)
 124                 return IT8152_PCI_INTA;
 125
 126         /* ATXBase/SB-X2XX CardBus */
 127         if (slot == 8 || slot == 0)
 128                 return IT8152_PCI_INTB;
 129
 130         /* ATXBase Ethernet */
 131         if (slot == 9)
 132                 return IT8152_PCI_INTA;
 133
 134         /* CM-x255 Onboard Ethernet */
 135         if (slot == 15)
 136                 return IT8152_PCI_INTC;
 137
 138         /* SB-x2xx Ethernet */
 139         if (slot == 16)
 140                 return IT8152_PCI_INTA;
 141
 142         /* PC104+ interrupt routing */
 143         if ((slot == 17) || (slot == 19))
 144                 return IT8152_PCI_INTA;
 145         if ((slot == 18) || (slot == 20))
 146                 return IT8152_PCI_INTB;
 147
 148         return(0);
 149 }
 150
 151 static void cmx2xx_pci_preinit(void)
 152 {
 153         pr_info("Initializing CM-X2XX PCI subsystem\n");
 154
 155         __raw_writel(0x800, IT8152_PCI_CFG_ADDR);
 156         if (__raw_readl(IT8152_PCI_CFG_DATA) == 0x81521283) {
 157                 pr_info("PCI Bridge found.\n");
 158
 159                 /* set PCI I/O base at 0 */
 160                 writel(0x848, IT8152_PCI_CFG_ADDR);
 161                 writel(0, IT8152_PCI_CFG_DATA);
 162
 163                 /* set PCI memory base at 0 */
 164                 writel(0x840, IT8152_PCI_CFG_ADDR);
 165                 writel(0, IT8152_PCI_CFG_DATA);
 166
 167                 writel(0x20, IT8152_GPIO_GPDR);
 168
 169                 /* CardBus Controller on ATXbase baseboard */
 170                 writel(0x4000, IT8152_PCI_CFG_ADDR);
 171                 if (readl(IT8152_PCI_CFG_DATA) == 0xAC51104C) {
 172                         pr_info("CardBus Bridge found.\n");
 173
 174                         /* Configure socket 0 */
 175                         writel(0x408C, IT8152_PCI_CFG_ADDR);
 176                         writel(0x1022, IT8152_PCI_CFG_DATA);
 177
 178                         writel(0x4080, IT8152_PCI_CFG_ADDR);
 179                         writel(0x3844d060, IT8152_PCI_CFG_DATA);
 180
 181                         writel(0x4090, IT8152_PCI_CFG_ADDR);
 182                         writel(((readl(IT8152_PCI_CFG_DATA) & 0xffff) |
 183                                 0x60440000),
 184                                IT8152_PCI_CFG_DATA);
 185
 186                         writel(0x4018, IT8152_PCI_CFG_ADDR);
 187                         writel(0xb0000000, IT8152_PCI_CFG_DATA);
 188
 189                         /* Configure socket 1 */
 190                         writel(0x418C, IT8152_PCI_CFG_ADDR);
 191                         writel(0x1022, IT8152_PCI_CFG_DATA);
 192
 193                         writel(0x4180, IT8152_PCI_CFG_ADDR);
 194                         writel(0x3844d060, IT8152_PCI_CFG_DATA);
 195
 196                         writel(0x4190, IT8152_PCI_CFG_ADDR);
 197                         writel(((readl(IT8152_PCI_CFG_DATA) & 0xffff) |
 198                                 0x60440000),
 199                                IT8152_PCI_CFG_DATA);
 200
 201                         writel(0x4118, IT8152_PCI_CFG_ADDR);
 202                         writel(0xb0000000, IT8152_PCI_CFG_DATA);
 203                 }
 204         }
 205 }
 206
 207 static struct hw_pci cmx2xx_pci __initdata = {
 208         .swizzle        = pci_std_swizzle,
 209         .map_irq        = cmx2xx_pci_map_irq,
 210         .nr_controllers = 1,
 211         .setup          = it8152_pci_setup,
 212         .scan           = it8152_pci_scan_bus,
 213         .preinit        = cmx2xx_pci_preinit,
 214 };
 215
 216 static int __init cmx2xx_init_pci(void)
 217 {
 218         if (machine_is_armcore())
 219                 pci_common_init(&cmx2xx_pci);
 220
 221         return 0;
 222 }
 223
 224 subsys_initcall(cmx2xx_init_pci);