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ath9k: Determine btcoex scheme type based on chip version
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / wireless / ath / ath9k / main.c
blob8a2f000274b575be622623590f8f02ba2d7fa4b2
1 /*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/nl80211.h>
18 #include "ath9k.h"
19
20 static char *dev_info = "ath9k";
21
22 MODULE_AUTHOR("Atheros Communications");
23 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
24 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
25 MODULE_LICENSE("Dual BSD/GPL");
26
27 static int modparam_nohwcrypt;
28 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
29 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
30
31 /* We use the hw_value as an index into our private channel structure */
32
33 #define CHAN2G(_freq, _idx) { \
34 .center_freq = (_freq), \
35 .hw_value = (_idx), \
36 .max_power = 20, \
37 }
38
39 #define CHAN5G(_freq, _idx) { \
40 .band = IEEE80211_BAND_5GHZ, \
41 .center_freq = (_freq), \
42 .hw_value = (_idx), \
43 .max_power = 20, \
44 }
45
46 /* Some 2 GHz radios are actually tunable on 2312-2732
47 * on 5 MHz steps, we support the channels which we know
48 * we have calibration data for all cards though to make
49 * this static */
50 static struct ieee80211_channel ath9k_2ghz_chantable[] = {
51 CHAN2G(2412, 0), /* Channel 1 */
52 CHAN2G(2417, 1), /* Channel 2 */
53 CHAN2G(2422, 2), /* Channel 3 */
54 CHAN2G(2427, 3), /* Channel 4 */
55 CHAN2G(2432, 4), /* Channel 5 */
56 CHAN2G(2437, 5), /* Channel 6 */
57 CHAN2G(2442, 6), /* Channel 7 */
58 CHAN2G(2447, 7), /* Channel 8 */
59 CHAN2G(2452, 8), /* Channel 9 */
60 CHAN2G(2457, 9), /* Channel 10 */
61 CHAN2G(2462, 10), /* Channel 11 */
62 CHAN2G(2467, 11), /* Channel 12 */
63 CHAN2G(2472, 12), /* Channel 13 */
64 CHAN2G(2484, 13), /* Channel 14 */
65 };
66
67 /* Some 5 GHz radios are actually tunable on XXXX-YYYY
68 * on 5 MHz steps, we support the channels which we know
69 * we have calibration data for all cards though to make
70 * this static */
71 static struct ieee80211_channel ath9k_5ghz_chantable[] = {
72 /* _We_ call this UNII 1 */
73 CHAN5G(5180, 14), /* Channel 36 */
74 CHAN5G(5200, 15), /* Channel 40 */
75 CHAN5G(5220, 16), /* Channel 44 */
76 CHAN5G(5240, 17), /* Channel 48 */
77 /* _We_ call this UNII 2 */
78 CHAN5G(5260, 18), /* Channel 52 */
79 CHAN5G(5280, 19), /* Channel 56 */
80 CHAN5G(5300, 20), /* Channel 60 */
81 CHAN5G(5320, 21), /* Channel 64 */
82 /* _We_ call this "Middle band" */
83 CHAN5G(5500, 22), /* Channel 100 */
84 CHAN5G(5520, 23), /* Channel 104 */
85 CHAN5G(5540, 24), /* Channel 108 */
86 CHAN5G(5560, 25), /* Channel 112 */
87 CHAN5G(5580, 26), /* Channel 116 */
88 CHAN5G(5600, 27), /* Channel 120 */
89 CHAN5G(5620, 28), /* Channel 124 */
90 CHAN5G(5640, 29), /* Channel 128 */
91 CHAN5G(5660, 30), /* Channel 132 */
92 CHAN5G(5680, 31), /* Channel 136 */
93 CHAN5G(5700, 32), /* Channel 140 */
94 /* _We_ call this UNII 3 */
95 CHAN5G(5745, 33), /* Channel 149 */
96 CHAN5G(5765, 34), /* Channel 153 */
97 CHAN5G(5785, 35), /* Channel 157 */
98 CHAN5G(5805, 36), /* Channel 161 */
99 CHAN5G(5825, 37), /* Channel 165 */
100 };
101
102 static void ath_cache_conf_rate(struct ath_softc *sc,
103 struct ieee80211_conf *conf)
104 {
105 switch (conf->channel->band) {
106 case IEEE80211_BAND_2GHZ:
107 if (conf_is_ht20(conf))
108 sc->cur_rate_table =
109 sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
110 else if (conf_is_ht40_minus(conf))
111 sc->cur_rate_table =
112 sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
113 else if (conf_is_ht40_plus(conf))
114 sc->cur_rate_table =
115 sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
116 else
117 sc->cur_rate_table =
118 sc->hw_rate_table[ATH9K_MODE_11G];
119 break;
120 case IEEE80211_BAND_5GHZ:
121 if (conf_is_ht20(conf))
122 sc->cur_rate_table =
123 sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
124 else if (conf_is_ht40_minus(conf))
125 sc->cur_rate_table =
126 sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
127 else if (conf_is_ht40_plus(conf))
128 sc->cur_rate_table =
129 sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
130 else
131 sc->cur_rate_table =
132 sc->hw_rate_table[ATH9K_MODE_11A];
133 break;
134 default:
135 BUG_ON(1);
136 break;
137 }
138 }
139
140 static void ath_update_txpow(struct ath_softc *sc)
141 {
142 struct ath_hw *ah = sc->sc_ah;
143 u32 txpow;
144
145 if (sc->curtxpow != sc->config.txpowlimit) {
146 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
147 /* read back in case value is clamped */
148 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
149 sc->curtxpow = txpow;
150 }
151 }
152
153 static u8 parse_mpdudensity(u8 mpdudensity)
154 {
155 /*
156 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
157 * 0 for no restriction
158 * 1 for 1/4 us
159 * 2 for 1/2 us
160 * 3 for 1 us
161 * 4 for 2 us
162 * 5 for 4 us
163 * 6 for 8 us
164 * 7 for 16 us
165 */
166 switch (mpdudensity) {
167 case 0:
168 return 0;
169 case 1:
170 case 2:
171 case 3:
172 /* Our lower layer calculations limit our precision to
173 1 microsecond */
174 return 1;
175 case 4:
176 return 2;
177 case 5:
178 return 4;
179 case 6:
180 return 8;
181 case 7:
182 return 16;
183 default:
184 return 0;
185 }
186 }
187
188 static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
189 {
190 const struct ath_rate_table *rate_table = NULL;
191 struct ieee80211_supported_band *sband;
192 struct ieee80211_rate *rate;
193 int i, maxrates;
194
195 switch (band) {
196 case IEEE80211_BAND_2GHZ:
197 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
198 break;
199 case IEEE80211_BAND_5GHZ:
200 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
201 break;
202 default:
203 break;
204 }
205
206 if (rate_table == NULL)
207 return;
208
209 sband = &sc->sbands[band];
210 rate = sc->rates[band];
211
212 if (rate_table->rate_cnt > ATH_RATE_MAX)
213 maxrates = ATH_RATE_MAX;
214 else
215 maxrates = rate_table->rate_cnt;
216
217 for (i = 0; i < maxrates; i++) {
218 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
219 rate[i].hw_value = rate_table->info[i].ratecode;
220 if (rate_table->info[i].short_preamble) {
221 rate[i].hw_value_short = rate_table->info[i].ratecode |
222 rate_table->info[i].short_preamble;
223 rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
224 }
225 sband->n_bitrates++;
226
227 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
228 rate[i].bitrate / 10, rate[i].hw_value);
229 }
230 }
231
232 static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc,
233 struct ieee80211_hw *hw)
234 {
235 struct ieee80211_channel *curchan = hw->conf.channel;
236 struct ath9k_channel *channel;
237 u8 chan_idx;
238
239 chan_idx = curchan->hw_value;
240 channel = &sc->sc_ah->channels[chan_idx];
241 ath9k_update_ichannel(sc, hw, channel);
242 return channel;
243 }
244
245 /*
246 * Set/change channels. If the channel is really being changed, it's done
247 * by reseting the chip. To accomplish this we must first cleanup any pending
248 * DMA, then restart stuff.
249 */
250 int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
251 struct ath9k_channel *hchan)
252 {
253 struct ath_hw *ah = sc->sc_ah;
254 bool fastcc = true, stopped;
255 struct ieee80211_channel *channel = hw->conf.channel;
256 int r;
257
258 if (sc->sc_flags & SC_OP_INVALID)
259 return -EIO;
260
261 ath9k_ps_wakeup(sc);
262
263 /*
264 * This is only performed if the channel settings have
265 * actually changed.
266 *
267 * To switch channels clear any pending DMA operations;
268 * wait long enough for the RX fifo to drain, reset the
269 * hardware at the new frequency, and then re-enable
270 * the relevant bits of the h/w.
271 */
272 ath9k_hw_set_interrupts(ah, 0);
273 ath_drain_all_txq(sc, false);
274 stopped = ath_stoprecv(sc);
275
276 /* XXX: do not flush receive queue here. We don't want
277 * to flush data frames already in queue because of
278 * changing channel. */
279
280 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
281 fastcc = false;
282
283 DPRINTF(sc, ATH_DBG_CONFIG,
284 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
285 sc->sc_ah->curchan->channel,
286 channel->center_freq, sc->tx_chan_width);
287
288 spin_lock_bh(&sc->sc_resetlock);
289
290 r = ath9k_hw_reset(ah, hchan, fastcc);
291 if (r) {
292 DPRINTF(sc, ATH_DBG_FATAL,
293 "Unable to reset channel (%u Mhz) "
294 "reset status %d\n",
295 channel->center_freq, r);
296 spin_unlock_bh(&sc->sc_resetlock);
297 goto ps_restore;
298 }
299 spin_unlock_bh(&sc->sc_resetlock);
300
301 sc->sc_flags &= ~SC_OP_FULL_RESET;
302
303 if (ath_startrecv(sc) != 0) {
304 DPRINTF(sc, ATH_DBG_FATAL,
305 "Unable to restart recv logic\n");
306 r = -EIO;
307 goto ps_restore;
308 }
309
310 ath_cache_conf_rate(sc, &hw->conf);
311 ath_update_txpow(sc);
312 ath9k_hw_set_interrupts(ah, sc->imask);
313
314 ps_restore:
315 ath9k_ps_restore(sc);
316 return r;
317 }
318
319 /*
320 * This routine performs the periodic noise floor calibration function
321 * that is used to adjust and optimize the chip performance. This
322 * takes environmental changes (location, temperature) into account.
323 * When the task is complete, it reschedules itself depending on the
324 * appropriate interval that was calculated.
325 */
326 static void ath_ani_calibrate(unsigned long data)
327 {
328 struct ath_softc *sc = (struct ath_softc *)data;
329 struct ath_hw *ah = sc->sc_ah;
330 bool longcal = false;
331 bool shortcal = false;
332 bool aniflag = false;
333 unsigned int timestamp = jiffies_to_msecs(jiffies);
334 u32 cal_interval, short_cal_interval;
335
336 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
337 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
338
339 /*
340 * don't calibrate when we're scanning.
341 * we are most likely not on our home channel.
342 */
343 spin_lock(&sc->ani_lock);
344 if (sc->sc_flags & SC_OP_SCANNING)
345 goto set_timer;
346
347 /* Only calibrate if awake */
348 if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
349 goto set_timer;
350
351 ath9k_ps_wakeup(sc);
352
353 /* Long calibration runs independently of short calibration. */
354 if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
355 longcal = true;
356 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
357 sc->ani.longcal_timer = timestamp;
358 }
359
360 /* Short calibration applies only while caldone is false */
361 if (!sc->ani.caldone) {
362 if ((timestamp - sc->ani.shortcal_timer) >= short_cal_interval) {
363 shortcal = true;
364 DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
365 sc->ani.shortcal_timer = timestamp;
366 sc->ani.resetcal_timer = timestamp;
367 }
368 } else {
369 if ((timestamp - sc->ani.resetcal_timer) >=
370 ATH_RESTART_CALINTERVAL) {
371 sc->ani.caldone = ath9k_hw_reset_calvalid(ah);
372 if (sc->ani.caldone)
373 sc->ani.resetcal_timer = timestamp;
374 }
375 }
376
377 /* Verify whether we must check ANI */
378 if ((timestamp - sc->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
379 aniflag = true;
380 sc->ani.checkani_timer = timestamp;
381 }
382
383 /* Skip all processing if there's nothing to do. */
384 if (longcal || shortcal || aniflag) {
385 /* Call ANI routine if necessary */
386 if (aniflag)
387 ath9k_hw_ani_monitor(ah, ah->curchan);
388
389 /* Perform calibration if necessary */
390 if (longcal || shortcal) {
391 sc->ani.caldone = ath9k_hw_calibrate(ah, ah->curchan,
392 sc->rx_chainmask, longcal);
393
394 if (longcal)
395 sc->ani.noise_floor = ath9k_hw_getchan_noise(ah,
396 ah->curchan);
397
398 DPRINTF(sc, ATH_DBG_ANI," calibrate chan %u/%x nf: %d\n",
399 ah->curchan->channel, ah->curchan->channelFlags,
400 sc->ani.noise_floor);
401 }
402 }
403
404 ath9k_ps_restore(sc);
405
406 set_timer:
407 spin_unlock(&sc->ani_lock);
408 /*
409 * Set timer interval based on previous results.
410 * The interval must be the shortest necessary to satisfy ANI,
411 * short calibration and long calibration.
412 */
413 cal_interval = ATH_LONG_CALINTERVAL;
414 if (sc->sc_ah->config.enable_ani)
415 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
416 if (!sc->ani.caldone)
417 cal_interval = min(cal_interval, (u32)short_cal_interval);
418
419 mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
420 }
421
422 static void ath_start_ani(struct ath_softc *sc)
423 {
424 unsigned long timestamp = jiffies_to_msecs(jiffies);
425
426 sc->ani.longcal_timer = timestamp;
427 sc->ani.shortcal_timer = timestamp;
428 sc->ani.checkani_timer = timestamp;
429
430 mod_timer(&sc->ani.timer,
431 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
432 }
433
434 /*
435 * Update tx/rx chainmask. For legacy association,
436 * hard code chainmask to 1x1, for 11n association, use
437 * the chainmask configuration, for bt coexistence, use
438 * the chainmask configuration even in legacy mode.
439 */
440 void ath_update_chainmask(struct ath_softc *sc, int is_ht)
441 {
442 if ((sc->sc_flags & SC_OP_SCANNING) || is_ht ||
443 (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) {
444 sc->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
445 sc->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
446 } else {
447 sc->tx_chainmask = 1;
448 sc->rx_chainmask = 1;
449 }
450
451 DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
452 sc->tx_chainmask, sc->rx_chainmask);
453 }
454
455 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
456 {
457 struct ath_node *an;
458
459 an = (struct ath_node *)sta->drv_priv;
460
461 if (sc->sc_flags & SC_OP_TXAGGR) {
462 ath_tx_node_init(sc, an);
463 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
464 sta->ht_cap.ampdu_factor);
465 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
466 an->last_rssi = ATH_RSSI_DUMMY_MARKER;
467 }
468 }
469
470 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
471 {
472 struct ath_node *an = (struct ath_node *)sta->drv_priv;
473
474 if (sc->sc_flags & SC_OP_TXAGGR)
475 ath_tx_node_cleanup(sc, an);
476 }
477
478 static void ath9k_tasklet(unsigned long data)
479 {
480 struct ath_softc *sc = (struct ath_softc *)data;
481 u32 status = sc->intrstatus;
482
483 ath9k_ps_wakeup(sc);
484
485 if (status & ATH9K_INT_FATAL) {
486 ath_reset(sc, false);
487 ath9k_ps_restore(sc);
488 return;
489 }
490
491 if (status & (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
492 spin_lock_bh(&sc->rx.rxflushlock);
493 ath_rx_tasklet(sc, 0);
494 spin_unlock_bh(&sc->rx.rxflushlock);
495 }
496
497 if (status & ATH9K_INT_TX)
498 ath_tx_tasklet(sc);
499
500 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
501 /*
502 * TSF sync does not look correct; remain awake to sync with
503 * the next Beacon.
504 */
505 DPRINTF(sc, ATH_DBG_PS, "TSFOOR - Sync with next Beacon\n");
506 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON | SC_OP_BEACON_SYNC;
507 }
508
509 /* re-enable hardware interrupt */
510 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
511 ath9k_ps_restore(sc);
512 }
513
514 irqreturn_t ath_isr(int irq, void *dev)
515 {
516 #define SCHED_INTR ( \
517 ATH9K_INT_FATAL | \
518 ATH9K_INT_RXORN | \
519 ATH9K_INT_RXEOL | \
520 ATH9K_INT_RX | \
521 ATH9K_INT_TX | \
522 ATH9K_INT_BMISS | \
523 ATH9K_INT_CST | \
524 ATH9K_INT_TSFOOR)
525
526 struct ath_softc *sc = dev;
527 struct ath_hw *ah = sc->sc_ah;
528 enum ath9k_int status;
529 bool sched = false;
530
531 /*
532 * The hardware is not ready/present, don't
533 * touch anything. Note this can happen early
534 * on if the IRQ is shared.
535 */
536 if (sc->sc_flags & SC_OP_INVALID)
537 return IRQ_NONE;
538
539
540 /* shared irq, not for us */
541
542 if (!ath9k_hw_intrpend(ah))
543 return IRQ_NONE;
544
545 /*
546 * Figure out the reason(s) for the interrupt. Note
547 * that the hal returns a pseudo-ISR that may include
548 * bits we haven't explicitly enabled so we mask the
549 * value to insure we only process bits we requested.
550 */
551 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
552 status &= sc->imask; /* discard unasked-for bits */
553
554 /*
555 * If there are no status bits set, then this interrupt was not
556 * for me (should have been caught above).
557 */
558 if (!status)
559 return IRQ_NONE;
560
561 /* Cache the status */
562 sc->intrstatus = status;
563
564 if (status & SCHED_INTR)
565 sched = true;
566
567 /*
568 * If a FATAL or RXORN interrupt is received, we have to reset the
569 * chip immediately.
570 */
571 if (status & (ATH9K_INT_FATAL | ATH9K_INT_RXORN))
572 goto chip_reset;
573
574 if (status & ATH9K_INT_SWBA)
575 tasklet_schedule(&sc->bcon_tasklet);
576
577 if (status & ATH9K_INT_TXURN)
578 ath9k_hw_updatetxtriglevel(ah, true);
579
580 if (status & ATH9K_INT_MIB) {
581 /*
582 * Disable interrupts until we service the MIB
583 * interrupt; otherwise it will continue to
584 * fire.
585 */
586 ath9k_hw_set_interrupts(ah, 0);
587 /*
588 * Let the hal handle the event. We assume
589 * it will clear whatever condition caused
590 * the interrupt.
591 */
592 ath9k_hw_procmibevent(ah);
593 ath9k_hw_set_interrupts(ah, sc->imask);
594 }
595
596 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
597 if (status & ATH9K_INT_TIM_TIMER) {
598 /* Clear RxAbort bit so that we can
599 * receive frames */
600 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
601 ath9k_hw_setrxabort(sc->sc_ah, 0);
602 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
603 }
604
605 chip_reset:
606
607 ath_debug_stat_interrupt(sc, status);
608
609 if (sched) {
610 /* turn off every interrupt except SWBA */
611 ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
612 tasklet_schedule(&sc->intr_tq);
613 }
614
615 return IRQ_HANDLED;
616
617 #undef SCHED_INTR
618 }
619
620 static u32 ath_get_extchanmode(struct ath_softc *sc,
621 struct ieee80211_channel *chan,
622 enum nl80211_channel_type channel_type)
623 {
624 u32 chanmode = 0;
625
626 switch (chan->band) {
627 case IEEE80211_BAND_2GHZ:
628 switch(channel_type) {
629 case NL80211_CHAN_NO_HT:
630 case NL80211_CHAN_HT20:
631 chanmode = CHANNEL_G_HT20;
632 break;
633 case NL80211_CHAN_HT40PLUS:
634 chanmode = CHANNEL_G_HT40PLUS;
635 break;
636 case NL80211_CHAN_HT40MINUS:
637 chanmode = CHANNEL_G_HT40MINUS;
638 break;
639 }
640 break;
641 case IEEE80211_BAND_5GHZ:
642 switch(channel_type) {
643 case NL80211_CHAN_NO_HT:
644 case NL80211_CHAN_HT20:
645 chanmode = CHANNEL_A_HT20;
646 break;
647 case NL80211_CHAN_HT40PLUS:
648 chanmode = CHANNEL_A_HT40PLUS;
649 break;
650 case NL80211_CHAN_HT40MINUS:
651 chanmode = CHANNEL_A_HT40MINUS;
652 break;
653 }
654 break;
655 default:
656 break;
657 }
658
659 return chanmode;
660 }
661
662 static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
663 struct ath9k_keyval *hk, const u8 *addr,
664 bool authenticator)
665 {
666 const u8 *key_rxmic;
667 const u8 *key_txmic;
668
669 key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
670 key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
671
672 if (addr == NULL) {
673 /*
674 * Group key installation - only two key cache entries are used
675 * regardless of splitmic capability since group key is only
676 * used either for TX or RX.
677 */
678 if (authenticator) {
679 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
680 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
681 } else {
682 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
683 memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
684 }
685 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
686 }
687 if (!sc->splitmic) {
688 /* TX and RX keys share the same key cache entry. */
689 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
690 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
691 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
692 }
693
694 /* Separate key cache entries for TX and RX */
695
696 /* TX key goes at first index, RX key at +32. */
697 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
698 if (!ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, NULL)) {
699 /* TX MIC entry failed. No need to proceed further */
700 DPRINTF(sc, ATH_DBG_FATAL,
701 "Setting TX MIC Key Failed\n");
702 return 0;
703 }
704
705 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
706 /* XXX delete tx key on failure? */
707 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix + 32, hk, addr);
708 }
709
710 static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
711 {
712 int i;
713
714 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
715 if (test_bit(i, sc->keymap) ||
716 test_bit(i + 64, sc->keymap))
717 continue; /* At least one part of TKIP key allocated */
718 if (sc->splitmic &&
719 (test_bit(i + 32, sc->keymap) ||
720 test_bit(i + 64 + 32, sc->keymap)))
721 continue; /* At least one part of TKIP key allocated */
722
723 /* Found a free slot for a TKIP key */
724 return i;
725 }
726 return -1;
727 }
728
729 static int ath_reserve_key_cache_slot(struct ath_softc *sc)
730 {
731 int i;
732
733 /* First, try to find slots that would not be available for TKIP. */
734 if (sc->splitmic) {
735 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 4; i++) {
736 if (!test_bit(i, sc->keymap) &&
737 (test_bit(i + 32, sc->keymap) ||
738 test_bit(i + 64, sc->keymap) ||
739 test_bit(i + 64 + 32, sc->keymap)))
740 return i;
741 if (!test_bit(i + 32, sc->keymap) &&
742 (test_bit(i, sc->keymap) ||
743 test_bit(i + 64, sc->keymap) ||
744 test_bit(i + 64 + 32, sc->keymap)))
745 return i + 32;
746 if (!test_bit(i + 64, sc->keymap) &&
747 (test_bit(i , sc->keymap) ||
748 test_bit(i + 32, sc->keymap) ||
749 test_bit(i + 64 + 32, sc->keymap)))
750 return i + 64;
751 if (!test_bit(i + 64 + 32, sc->keymap) &&
752 (test_bit(i, sc->keymap) ||
753 test_bit(i + 32, sc->keymap) ||
754 test_bit(i + 64, sc->keymap)))
755 return i + 64 + 32;
756 }
757 } else {
758 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
759 if (!test_bit(i, sc->keymap) &&
760 test_bit(i + 64, sc->keymap))
761 return i;
762 if (test_bit(i, sc->keymap) &&
763 !test_bit(i + 64, sc->keymap))
764 return i + 64;
765 }
766 }
767
768 /* No partially used TKIP slots, pick any available slot */
769 for (i = IEEE80211_WEP_NKID; i < sc->keymax; i++) {
770 /* Do not allow slots that could be needed for TKIP group keys
771 * to be used. This limitation could be removed if we know that
772 * TKIP will not be used. */
773 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
774 continue;
775 if (sc->splitmic) {
776 if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
777 continue;
778 if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
779 continue;
780 }
781
782 if (!test_bit(i, sc->keymap))
783 return i; /* Found a free slot for a key */
784 }
785
786 /* No free slot found */
787 return -1;
788 }
789
790 static int ath_key_config(struct ath_softc *sc,
791 struct ieee80211_vif *vif,
792 struct ieee80211_sta *sta,
793 struct ieee80211_key_conf *key)
794 {
795 struct ath9k_keyval hk;
796 const u8 *mac = NULL;
797 int ret = 0;
798 int idx;
799
800 memset(&hk, 0, sizeof(hk));
801
802 switch (key->alg) {
803 case ALG_WEP:
804 hk.kv_type = ATH9K_CIPHER_WEP;
805 break;
806 case ALG_TKIP:
807 hk.kv_type = ATH9K_CIPHER_TKIP;
808 break;
809 case ALG_CCMP:
810 hk.kv_type = ATH9K_CIPHER_AES_CCM;
811 break;
812 default:
813 return -EOPNOTSUPP;
814 }
815
816 hk.kv_len = key->keylen;
817 memcpy(hk.kv_val, key->key, key->keylen);
818
819 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
820 /* For now, use the default keys for broadcast keys. This may
821 * need to change with virtual interfaces. */
822 idx = key->keyidx;
823 } else if (key->keyidx) {
824 if (WARN_ON(!sta))
825 return -EOPNOTSUPP;
826 mac = sta->addr;
827
828 if (vif->type != NL80211_IFTYPE_AP) {
829 /* Only keyidx 0 should be used with unicast key, but
830 * allow this for client mode for now. */
831 idx = key->keyidx;
832 } else
833 return -EIO;
834 } else {
835 if (WARN_ON(!sta))
836 return -EOPNOTSUPP;
837 mac = sta->addr;
838
839 if (key->alg == ALG_TKIP)
840 idx = ath_reserve_key_cache_slot_tkip(sc);
841 else
842 idx = ath_reserve_key_cache_slot(sc);
843 if (idx < 0)
844 return -ENOSPC; /* no free key cache entries */
845 }
846
847 if (key->alg == ALG_TKIP)
848 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac,
849 vif->type == NL80211_IFTYPE_AP);
850 else
851 ret = ath9k_hw_set_keycache_entry(sc->sc_ah, idx, &hk, mac);
852
853 if (!ret)
854 return -EIO;
855
856 set_bit(idx, sc->keymap);
857 if (key->alg == ALG_TKIP) {
858 set_bit(idx + 64, sc->keymap);
859 if (sc->splitmic) {
860 set_bit(idx + 32, sc->keymap);
861 set_bit(idx + 64 + 32, sc->keymap);
862 }
863 }
864
865 return idx;
866 }
867
868 static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
869 {
870 ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
871 if (key->hw_key_idx < IEEE80211_WEP_NKID)
872 return;
873
874 clear_bit(key->hw_key_idx, sc->keymap);
875 if (key->alg != ALG_TKIP)
876 return;
877
878 clear_bit(key->hw_key_idx + 64, sc->keymap);
879 if (sc->splitmic) {
880 clear_bit(key->hw_key_idx + 32, sc->keymap);
881 clear_bit(key->hw_key_idx + 64 + 32, sc->keymap);
882 }
883 }
884
885 static void setup_ht_cap(struct ath_softc *sc,
886 struct ieee80211_sta_ht_cap *ht_info)
887 {
888 u8 tx_streams, rx_streams;
889
890 ht_info->ht_supported = true;
891 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
892 IEEE80211_HT_CAP_SM_PS |
893 IEEE80211_HT_CAP_SGI_40 |
894 IEEE80211_HT_CAP_DSSSCCK40;
895
896 ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
897 ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
898
899 /* set up supported mcs set */
900 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
901 tx_streams = !(sc->tx_chainmask & (sc->tx_chainmask - 1)) ? 1 : 2;
902 rx_streams = !(sc->rx_chainmask & (sc->rx_chainmask - 1)) ? 1 : 2;
903
904 if (tx_streams != rx_streams) {
905 DPRINTF(sc, ATH_DBG_CONFIG, "TX streams %d, RX streams: %d\n",
906 tx_streams, rx_streams);
907 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
908 ht_info->mcs.tx_params |= ((tx_streams - 1) <<
909 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
910 }
911
912 ht_info->mcs.rx_mask[0] = 0xff;
913 if (rx_streams >= 2)
914 ht_info->mcs.rx_mask[1] = 0xff;
915
916 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
917 }
918
919 static void ath9k_bss_assoc_info(struct ath_softc *sc,
920 struct ieee80211_vif *vif,
921 struct ieee80211_bss_conf *bss_conf)
922 {
923
924 if (bss_conf->assoc) {
925 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
926 bss_conf->aid, sc->curbssid);
927
928 /* New association, store aid */
929 sc->curaid = bss_conf->aid;
930 ath9k_hw_write_associd(sc);
931
932 /*
933 * Request a re-configuration of Beacon related timers
934 * on the receipt of the first Beacon frame (i.e.,
935 * after time sync with the AP).
936 */
937 sc->sc_flags |= SC_OP_BEACON_SYNC;
938
939 /* Configure the beacon */
940 ath_beacon_config(sc, vif);
941
942 /* Reset rssi stats */
943 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
944
945 ath_start_ani(sc);
946 } else {
947 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
948 sc->curaid = 0;
949 /* Stop ANI */
950 del_timer_sync(&sc->ani.timer);
951 }
952 }
953
954 /********************************/
955 /* LED functions */
956 /********************************/
957
958 static void ath_led_blink_work(struct work_struct *work)
959 {
960 struct ath_softc *sc = container_of(work, struct ath_softc,
961 ath_led_blink_work.work);
962
963 if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
964 return;
965
966 if ((sc->led_on_duration == ATH_LED_ON_DURATION_IDLE) ||
967 (sc->led_off_duration == ATH_LED_OFF_DURATION_IDLE))
968 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 0);
969 else
970 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin,
971 (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
972
973 ieee80211_queue_delayed_work(sc->hw,
974 &sc->ath_led_blink_work,
975 (sc->sc_flags & SC_OP_LED_ON) ?
976 msecs_to_jiffies(sc->led_off_duration) :
977 msecs_to_jiffies(sc->led_on_duration));
978
979 sc->led_on_duration = sc->led_on_cnt ?
980 max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25) :
981 ATH_LED_ON_DURATION_IDLE;
982 sc->led_off_duration = sc->led_off_cnt ?
983 max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10) :
984 ATH_LED_OFF_DURATION_IDLE;
985 sc->led_on_cnt = sc->led_off_cnt = 0;
986 if (sc->sc_flags & SC_OP_LED_ON)
987 sc->sc_flags &= ~SC_OP_LED_ON;
988 else
989 sc->sc_flags |= SC_OP_LED_ON;
990 }
991
992 static void ath_led_brightness(struct led_classdev *led_cdev,
993 enum led_brightness brightness)
994 {
995 struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
996 struct ath_softc *sc = led->sc;
997
998 switch (brightness) {
999 case LED_OFF:
1000 if (led->led_type == ATH_LED_ASSOC ||
1001 led->led_type == ATH_LED_RADIO) {
1002 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin,
1003 (led->led_type == ATH_LED_RADIO));
1004 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1005 if (led->led_type == ATH_LED_RADIO)
1006 sc->sc_flags &= ~SC_OP_LED_ON;
1007 } else {
1008 sc->led_off_cnt++;
1009 }
1010 break;
1011 case LED_FULL:
1012 if (led->led_type == ATH_LED_ASSOC) {
1013 sc->sc_flags |= SC_OP_LED_ASSOCIATED;
1014 ieee80211_queue_delayed_work(sc->hw,
1015 &sc->ath_led_blink_work, 0);
1016 } else if (led->led_type == ATH_LED_RADIO) {
1017 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 0);
1018 sc->sc_flags |= SC_OP_LED_ON;
1019 } else {
1020 sc->led_on_cnt++;
1021 }
1022 break;
1023 default:
1024 break;
1025 }
1026 }
1027
1028 static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
1029 char *trigger)
1030 {
1031 int ret;
1032
1033 led->sc = sc;
1034 led->led_cdev.name = led->name;
1035 led->led_cdev.default_trigger = trigger;
1036 led->led_cdev.brightness_set = ath_led_brightness;
1037
1038 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1039 if (ret)
1040 DPRINTF(sc, ATH_DBG_FATAL,
1041 "Failed to register led:%s", led->name);
1042 else
1043 led->registered = 1;
1044 return ret;
1045 }
1046
1047 static void ath_unregister_led(struct ath_led *led)
1048 {
1049 if (led->registered) {
1050 led_classdev_unregister(&led->led_cdev);
1051 led->registered = 0;
1052 }
1053 }
1054
1055 static void ath_deinit_leds(struct ath_softc *sc)
1056 {
1057 ath_unregister_led(&sc->assoc_led);
1058 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1059 ath_unregister_led(&sc->tx_led);
1060 ath_unregister_led(&sc->rx_led);
1061 ath_unregister_led(&sc->radio_led);
1062 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
1063 }
1064
1065 static void ath_init_leds(struct ath_softc *sc)
1066 {
1067 char *trigger;
1068 int ret;
1069
1070 if (AR_SREV_9287(sc->sc_ah))
1071 sc->sc_ah->led_pin = ATH_LED_PIN_9287;
1072 else
1073 sc->sc_ah->led_pin = ATH_LED_PIN_DEF;
1074
1075 /* Configure gpio 1 for output */
1076 ath9k_hw_cfg_output(sc->sc_ah, sc->sc_ah->led_pin,
1077 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1078 /* LED off, active low */
1079 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
1080
1081 INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1082
1083 trigger = ieee80211_get_radio_led_name(sc->hw);
1084 snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
1085 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
1086 ret = ath_register_led(sc, &sc->radio_led, trigger);
1087 sc->radio_led.led_type = ATH_LED_RADIO;
1088 if (ret)
1089 goto fail;
1090
1091 trigger = ieee80211_get_assoc_led_name(sc->hw);
1092 snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
1093 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
1094 ret = ath_register_led(sc, &sc->assoc_led, trigger);
1095 sc->assoc_led.led_type = ATH_LED_ASSOC;
1096 if (ret)
1097 goto fail;
1098
1099 trigger = ieee80211_get_tx_led_name(sc->hw);
1100 snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
1101 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
1102 ret = ath_register_led(sc, &sc->tx_led, trigger);
1103 sc->tx_led.led_type = ATH_LED_TX;
1104 if (ret)
1105 goto fail;
1106
1107 trigger = ieee80211_get_rx_led_name(sc->hw);
1108 snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
1109 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
1110 ret = ath_register_led(sc, &sc->rx_led, trigger);
1111 sc->rx_led.led_type = ATH_LED_RX;
1112 if (ret)
1113 goto fail;
1114
1115 return;
1116
1117 fail:
1118 cancel_delayed_work_sync(&sc->ath_led_blink_work);
1119 ath_deinit_leds(sc);
1120 }
1121
1122 void ath_radio_enable(struct ath_softc *sc)
1123 {
1124 struct ath_hw *ah = sc->sc_ah;
1125 struct ieee80211_channel *channel = sc->hw->conf.channel;
1126 int r;
1127
1128 ath9k_ps_wakeup(sc);
1129 ath9k_hw_configpcipowersave(ah, 0);
1130
1131 if (!ah->curchan)
1132 ah->curchan = ath_get_curchannel(sc, sc->hw);
1133
1134 spin_lock_bh(&sc->sc_resetlock);
1135 r = ath9k_hw_reset(ah, ah->curchan, false);
1136 if (r) {
1137 DPRINTF(sc, ATH_DBG_FATAL,
1138 "Unable to reset channel %u (%uMhz) ",
1139 "reset status %d\n",
1140 channel->center_freq, r);
1141 }
1142 spin_unlock_bh(&sc->sc_resetlock);
1143
1144 ath_update_txpow(sc);
1145 if (ath_startrecv(sc) != 0) {
1146 DPRINTF(sc, ATH_DBG_FATAL,
1147 "Unable to restart recv logic\n");
1148 return;
1149 }
1150
1151 if (sc->sc_flags & SC_OP_BEACONS)
1152 ath_beacon_config(sc, NULL); /* restart beacons */
1153
1154 /* Re-Enable interrupts */
1155 ath9k_hw_set_interrupts(ah, sc->imask);
1156
1157 /* Enable LED */
1158 ath9k_hw_cfg_output(ah, ah->led_pin,
1159 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1160 ath9k_hw_set_gpio(ah, ah->led_pin, 0);
1161
1162 ieee80211_wake_queues(sc->hw);
1163 ath9k_ps_restore(sc);
1164 }
1165
1166 void ath_radio_disable(struct ath_softc *sc)
1167 {
1168 struct ath_hw *ah = sc->sc_ah;
1169 struct ieee80211_channel *channel = sc->hw->conf.channel;
1170 int r;
1171
1172 ath9k_ps_wakeup(sc);
1173 ieee80211_stop_queues(sc->hw);
1174
1175 /* Disable LED */
1176 ath9k_hw_set_gpio(ah, ah->led_pin, 1);
1177 ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
1178
1179 /* Disable interrupts */
1180 ath9k_hw_set_interrupts(ah, 0);
1181
1182 ath_drain_all_txq(sc, false); /* clear pending tx frames */
1183 ath_stoprecv(sc); /* turn off frame recv */
1184 ath_flushrecv(sc); /* flush recv queue */
1185
1186 if (!ah->curchan)
1187 ah->curchan = ath_get_curchannel(sc, sc->hw);
1188
1189 spin_lock_bh(&sc->sc_resetlock);
1190 r = ath9k_hw_reset(ah, ah->curchan, false);
1191 if (r) {
1192 DPRINTF(sc, ATH_DBG_FATAL,
1193 "Unable to reset channel %u (%uMhz) "
1194 "reset status %d\n",
1195 channel->center_freq, r);
1196 }
1197 spin_unlock_bh(&sc->sc_resetlock);
1198
1199 ath9k_hw_phy_disable(ah);
1200 ath9k_hw_configpcipowersave(ah, 1);
1201 ath9k_ps_restore(sc);
1202 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1203 }
1204
1205 /*******************/
1206 /* Rfkill */
1207 /*******************/
1208
1209 static bool ath_is_rfkill_set(struct ath_softc *sc)
1210 {
1211 struct ath_hw *ah = sc->sc_ah;
1212
1213 return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
1214 ah->rfkill_polarity;
1215 }
1216
1217 static void ath9k_rfkill_poll_state(struct ieee80211_hw *hw)
1218 {
1219 struct ath_wiphy *aphy = hw->priv;
1220 struct ath_softc *sc = aphy->sc;
1221 bool blocked = !!ath_is_rfkill_set(sc);
1222
1223 wiphy_rfkill_set_hw_state(hw->wiphy, blocked);
1224
1225 if (blocked)
1226 ath_radio_disable(sc);
1227 else
1228 ath_radio_enable(sc);
1229 }
1230
1231 static void ath_start_rfkill_poll(struct ath_softc *sc)
1232 {
1233 struct ath_hw *ah = sc->sc_ah;
1234
1235 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1236 wiphy_rfkill_start_polling(sc->hw->wiphy);
1237 }
1238
1239 void ath_cleanup(struct ath_softc *sc)
1240 {
1241 ath_detach(sc);
1242 free_irq(sc->irq, sc);
1243 ath_bus_cleanup(sc);
1244 kfree(sc->sec_wiphy);
1245 ieee80211_free_hw(sc->hw);
1246 }
1247
1248 void ath_detach(struct ath_softc *sc)
1249 {
1250 struct ieee80211_hw *hw = sc->hw;
1251 int i = 0;
1252
1253 ath9k_ps_wakeup(sc);
1254
1255 DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
1256
1257 ath_deinit_leds(sc);
1258
1259 for (i = 0; i < sc->num_sec_wiphy; i++) {
1260 struct ath_wiphy *aphy = sc->sec_wiphy[i];
1261 if (aphy == NULL)
1262 continue;
1263 sc->sec_wiphy[i] = NULL;
1264 ieee80211_unregister_hw(aphy->hw);
1265 ieee80211_free_hw(aphy->hw);
1266 }
1267 ieee80211_unregister_hw(hw);
1268 ath_rx_cleanup(sc);
1269 ath_tx_cleanup(sc);
1270
1271 tasklet_kill(&sc->intr_tq);
1272 tasklet_kill(&sc->bcon_tasklet);
1273
1274 if (!(sc->sc_flags & SC_OP_INVALID))
1275 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
1276
1277 /* cleanup tx queues */
1278 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1279 if (ATH_TXQ_SETUP(sc, i))
1280 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1281
1282 ath9k_hw_detach(sc->sc_ah);
1283 sc->sc_ah = NULL;
1284 ath9k_exit_debug(sc);
1285 }
1286
1287 static int ath9k_reg_notifier(struct wiphy *wiphy,
1288 struct regulatory_request *request)
1289 {
1290 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
1291 struct ath_wiphy *aphy = hw->priv;
1292 struct ath_softc *sc = aphy->sc;
1293 struct ath_regulatory *reg = &sc->common.regulatory;
1294
1295 return ath_reg_notifier_apply(wiphy, request, reg);
1296 }
1297
1298 /*
1299 * Initialize and fill ath_softc, ath_sofct is the
1300 * "Software Carrier" struct. Historically it has existed
1301 * to allow the separation between hardware specific
1302 * variables (now in ath_hw) and driver specific variables.
1303 */
1304 static int ath_init_softc(u16 devid, struct ath_softc *sc)
1305 {
1306 struct ath_hw *ah = NULL;
1307 int r = 0, i;
1308 int csz = 0;
1309
1310 /* XXX: hardware will not be ready until ath_open() being called */
1311 sc->sc_flags |= SC_OP_INVALID;
1312
1313 if (ath9k_init_debug(sc) < 0)
1314 printk(KERN_ERR "Unable to create debugfs files\n");
1315
1316 spin_lock_init(&sc->wiphy_lock);
1317 spin_lock_init(&sc->sc_resetlock);
1318 spin_lock_init(&sc->sc_serial_rw);
1319 spin_lock_init(&sc->ani_lock);
1320 spin_lock_init(&sc->sc_pm_lock);
1321 mutex_init(&sc->mutex);
1322 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1323 tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
1324 (unsigned long)sc);
1325
1326 /*
1327 * Cache line size is used to size and align various
1328 * structures used to communicate with the hardware.
1329 */
1330 ath_read_cachesize(sc, &csz);
1331 /* XXX assert csz is non-zero */
1332 sc->common.cachelsz = csz << 2; /* convert to bytes */
1333
1334 ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
1335 if (!ah) {
1336 r = -ENOMEM;
1337 goto bad_no_ah;
1338 }
1339
1340 ah->ah_sc = sc;
1341 ah->hw_version.devid = devid;
1342 sc->sc_ah = ah;
1343
1344 r = ath9k_hw_init(ah);
1345 if (r) {
1346 DPRINTF(sc, ATH_DBG_FATAL,
1347 "Unable to initialize hardware; "
1348 "initialization status: %d\n", r);
1349 goto bad;
1350 }
1351
1352 /* Get the hardware key cache size. */
1353 sc->keymax = ah->caps.keycache_size;
1354 if (sc->keymax > ATH_KEYMAX) {
1355 DPRINTF(sc, ATH_DBG_ANY,
1356 "Warning, using only %u entries in %u key cache\n",
1357 ATH_KEYMAX, sc->keymax);
1358 sc->keymax = ATH_KEYMAX;
1359 }
1360
1361 /*
1362 * Reset the key cache since some parts do not
1363 * reset the contents on initial power up.
1364 */
1365 for (i = 0; i < sc->keymax; i++)
1366 ath9k_hw_keyreset(ah, (u16) i);
1367
1368 /* default to MONITOR mode */
1369 sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
1370
1371 /* Setup rate tables */
1372
1373 ath_rate_attach(sc);
1374 ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1375 ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1376
1377 /*
1378 * Allocate hardware transmit queues: one queue for
1379 * beacon frames and one data queue for each QoS
1380 * priority. Note that the hal handles reseting
1381 * these queues at the needed time.
1382 */
1383 sc->beacon.beaconq = ath_beaconq_setup(ah);
1384 if (sc->beacon.beaconq == -1) {
1385 DPRINTF(sc, ATH_DBG_FATAL,
1386 "Unable to setup a beacon xmit queue\n");
1387 r = -EIO;
1388 goto bad2;
1389 }
1390 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1391 if (sc->beacon.cabq == NULL) {
1392 DPRINTF(sc, ATH_DBG_FATAL,
1393 "Unable to setup CAB xmit queue\n");
1394 r = -EIO;
1395 goto bad2;
1396 }
1397
1398 sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
1399 ath_cabq_update(sc);
1400
1401 for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1402 sc->tx.hwq_map[i] = -1;
1403
1404 /* Setup data queues */
1405 /* NB: ensure BK queue is the lowest priority h/w queue */
1406 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1407 DPRINTF(sc, ATH_DBG_FATAL,
1408 "Unable to setup xmit queue for BK traffic\n");
1409 r = -EIO;
1410 goto bad2;
1411 }
1412
1413 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1414 DPRINTF(sc, ATH_DBG_FATAL,
1415 "Unable to setup xmit queue for BE traffic\n");
1416 r = -EIO;
1417 goto bad2;
1418 }
1419 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1420 DPRINTF(sc, ATH_DBG_FATAL,
1421 "Unable to setup xmit queue for VI traffic\n");
1422 r = -EIO;
1423 goto bad2;
1424 }
1425 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1426 DPRINTF(sc, ATH_DBG_FATAL,
1427 "Unable to setup xmit queue for VO traffic\n");
1428 r = -EIO;
1429 goto bad2;
1430 }
1431
1432 /* Initializes the noise floor to a reasonable default value.
1433 * Later on this will be updated during ANI processing. */
1434
1435 sc->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1436 setup_timer(&sc->ani.timer, ath_ani_calibrate, (unsigned long)sc);
1437
1438 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1439 ATH9K_CIPHER_TKIP, NULL)) {
1440 /*
1441 * Whether we should enable h/w TKIP MIC.
1442 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1443 * report WMM capable, so it's always safe to turn on
1444 * TKIP MIC in this case.
1445 */
1446 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1447 0, 1, NULL);
1448 }
1449
1450 /*
1451 * Check whether the separate key cache entries
1452 * are required to handle both tx+rx MIC keys.
1453 * With split mic keys the number of stations is limited
1454 * to 27 otherwise 59.
1455 */
1456 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1457 ATH9K_CIPHER_TKIP, NULL)
1458 && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1459 ATH9K_CIPHER_MIC, NULL)
1460 && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1461 0, NULL))
1462 sc->splitmic = 1;
1463
1464 /* turn on mcast key search if possible */
1465 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1466 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1467 1, NULL);
1468
1469 sc->config.txpowlimit = ATH_TXPOWER_MAX;
1470
1471 /* 11n Capabilities */
1472 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1473 sc->sc_flags |= SC_OP_TXAGGR;
1474 sc->sc_flags |= SC_OP_RXAGGR;
1475 }
1476
1477 sc->tx_chainmask = ah->caps.tx_chainmask;
1478 sc->rx_chainmask = ah->caps.rx_chainmask;
1479
1480 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
1481 sc->rx.defant = ath9k_hw_getdefantenna(ah);
1482
1483 if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
1484 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
1485
1486 sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
1487
1488 /* initialize beacon slots */
1489 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
1490 sc->beacon.bslot[i] = NULL;
1491 sc->beacon.bslot_aphy[i] = NULL;
1492 }
1493
1494 /* setup channels and rates */
1495
1496 sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
1497 sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1498 sc->rates[IEEE80211_BAND_2GHZ];
1499 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1500 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1501 ARRAY_SIZE(ath9k_2ghz_chantable);
1502
1503 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
1504 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
1505 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1506 sc->rates[IEEE80211_BAND_5GHZ];
1507 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
1508 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1509 ARRAY_SIZE(ath9k_5ghz_chantable);
1510 }
1511
1512 if ((ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX) &&
1513 (sc->btcoex_info.btcoex_scheme == ATH_BTCOEX_CFG_2WIRE))
1514 ath9k_hw_btcoex_init(ah);
1515
1516 return 0;
1517 bad2:
1518 /* cleanup tx queues */
1519 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1520 if (ATH_TXQ_SETUP(sc, i))
1521 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1522 bad:
1523 ath9k_hw_detach(ah);
1524 sc->sc_ah = NULL;
1525 bad_no_ah:
1526 ath9k_exit_debug(sc);
1527
1528 return r;
1529 }
1530
1531 void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
1532 {
1533 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1534 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1535 IEEE80211_HW_SIGNAL_DBM |
1536 IEEE80211_HW_AMPDU_AGGREGATION |
1537 IEEE80211_HW_SUPPORTS_PS |
1538 IEEE80211_HW_PS_NULLFUNC_STACK |
1539 IEEE80211_HW_SPECTRUM_MGMT;
1540
1541 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
1542 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1543
1544 hw->wiphy->interface_modes =
1545 BIT(NL80211_IFTYPE_AP) |
1546 BIT(NL80211_IFTYPE_STATION) |
1547 BIT(NL80211_IFTYPE_ADHOC) |
1548 BIT(NL80211_IFTYPE_MESH_POINT);
1549
1550 hw->queues = 4;
1551 hw->max_rates = 4;
1552 hw->channel_change_time = 5000;
1553 hw->max_listen_interval = 10;
1554 /* Hardware supports 10 but we use 4 */
1555 hw->max_rate_tries = 4;
1556 hw->sta_data_size = sizeof(struct ath_node);
1557 hw->vif_data_size = sizeof(struct ath_vif);
1558
1559 hw->rate_control_algorithm = "ath9k_rate_control";
1560
1561 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
1562 &sc->sbands[IEEE80211_BAND_2GHZ];
1563 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1564 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1565 &sc->sbands[IEEE80211_BAND_5GHZ];
1566 }
1567
1568 /* Device driver core initialization */
1569 int ath_init_device(u16 devid, struct ath_softc *sc)
1570 {
1571 struct ieee80211_hw *hw = sc->hw;
1572 int error = 0, i;
1573 struct ath_regulatory *reg;
1574
1575 DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
1576
1577 error = ath_init_softc(devid, sc);
1578 if (error != 0)
1579 return error;
1580
1581 /* get mac address from hardware and set in mac80211 */
1582
1583 SET_IEEE80211_PERM_ADDR(hw, sc->sc_ah->macaddr);
1584
1585 ath_set_hw_capab(sc, hw);
1586
1587 error = ath_regd_init(&sc->common.regulatory, sc->hw->wiphy,
1588 ath9k_reg_notifier);
1589 if (error)
1590 return error;
1591
1592 reg = &sc->common.regulatory;
1593
1594 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1595 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1596 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1597 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
1598 }
1599
1600 /* initialize tx/rx engine */
1601 error = ath_tx_init(sc, ATH_TXBUF);
1602 if (error != 0)
1603 goto error_attach;
1604
1605 error = ath_rx_init(sc, ATH_RXBUF);
1606 if (error != 0)
1607 goto error_attach;
1608
1609 INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
1610 INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
1611 sc->wiphy_scheduler_int = msecs_to_jiffies(500);
1612
1613 error = ieee80211_register_hw(hw);
1614
1615 if (!ath_is_world_regd(reg)) {
1616 error = regulatory_hint(hw->wiphy, reg->alpha2);
1617 if (error)
1618 goto error_attach;
1619 }
1620
1621 /* Initialize LED control */
1622 ath_init_leds(sc);
1623
1624 ath_start_rfkill_poll(sc);
1625
1626 return 0;
1627
1628 error_attach:
1629 /* cleanup tx queues */
1630 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1631 if (ATH_TXQ_SETUP(sc, i))
1632 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1633
1634 ath9k_hw_detach(sc->sc_ah);
1635 sc->sc_ah = NULL;
1636 ath9k_exit_debug(sc);
1637
1638 return error;
1639 }
1640
1641 int ath_reset(struct ath_softc *sc, bool retry_tx)
1642 {
1643 struct ath_hw *ah = sc->sc_ah;
1644 struct ieee80211_hw *hw = sc->hw;
1645 int r;
1646
1647 ath9k_hw_set_interrupts(ah, 0);
1648 ath_drain_all_txq(sc, retry_tx);
1649 ath_stoprecv(sc);
1650 ath_flushrecv(sc);
1651
1652 spin_lock_bh(&sc->sc_resetlock);
1653 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
1654 if (r)
1655 DPRINTF(sc, ATH_DBG_FATAL,
1656 "Unable to reset hardware; reset status %d\n", r);
1657 spin_unlock_bh(&sc->sc_resetlock);
1658
1659 if (ath_startrecv(sc) != 0)
1660 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
1661
1662 /*
1663 * We may be doing a reset in response to a request
1664 * that changes the channel so update any state that
1665 * might change as a result.
1666 */
1667 ath_cache_conf_rate(sc, &hw->conf);
1668
1669 ath_update_txpow(sc);
1670
1671 if (sc->sc_flags & SC_OP_BEACONS)
1672 ath_beacon_config(sc, NULL); /* restart beacons */
1673
1674 ath9k_hw_set_interrupts(ah, sc->imask);
1675
1676 if (retry_tx) {
1677 int i;
1678 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1679 if (ATH_TXQ_SETUP(sc, i)) {
1680 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1681 ath_txq_schedule(sc, &sc->tx.txq[i]);
1682 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
1683 }
1684 }
1685 }
1686
1687 return r;
1688 }
1689
1690 /*
1691 * This function will allocate both the DMA descriptor structure, and the
1692 * buffers it contains. These are used to contain the descriptors used
1693 * by the system.
1694 */
1695 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1696 struct list_head *head, const char *name,
1697 int nbuf, int ndesc)
1698 {
1699 #define DS2PHYS(_dd, _ds) \
1700 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1701 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1702 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1703
1704 struct ath_desc *ds;
1705 struct ath_buf *bf;
1706 int i, bsize, error;
1707
1708 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1709 name, nbuf, ndesc);
1710
1711 INIT_LIST_HEAD(head);
1712 /* ath_desc must be a multiple of DWORDs */
1713 if ((sizeof(struct ath_desc) % 4) != 0) {
1714 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
1715 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1716 error = -ENOMEM;
1717 goto fail;
1718 }
1719
1720 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1721
1722 /*
1723 * Need additional DMA memory because we can't use
1724 * descriptors that cross the 4K page boundary. Assume
1725 * one skipped descriptor per 4K page.
1726 */
1727 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1728 u32 ndesc_skipped =
1729 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1730 u32 dma_len;
1731
1732 while (ndesc_skipped) {
1733 dma_len = ndesc_skipped * sizeof(struct ath_desc);
1734 dd->dd_desc_len += dma_len;
1735
1736 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1737 };
1738 }
1739
1740 /* allocate descriptors */
1741 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
1742 &dd->dd_desc_paddr, GFP_KERNEL);
1743 if (dd->dd_desc == NULL) {
1744 error = -ENOMEM;
1745 goto fail;
1746 }
1747 ds = dd->dd_desc;
1748 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
1749 name, ds, (u32) dd->dd_desc_len,
1750 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1751
1752 /* allocate buffers */
1753 bsize = sizeof(struct ath_buf) * nbuf;
1754 bf = kzalloc(bsize, GFP_KERNEL);
1755 if (bf == NULL) {
1756 error = -ENOMEM;
1757 goto fail2;
1758 }
1759 dd->dd_bufptr = bf;
1760
1761 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1762 bf->bf_desc = ds;
1763 bf->bf_daddr = DS2PHYS(dd, ds);
1764
1765 if (!(sc->sc_ah->caps.hw_caps &
1766 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1767 /*
1768 * Skip descriptor addresses which can cause 4KB
1769 * boundary crossing (addr + length) with a 32 dword
1770 * descriptor fetch.
1771 */
1772 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1773 ASSERT((caddr_t) bf->bf_desc <
1774 ((caddr_t) dd->dd_desc +
1775 dd->dd_desc_len));
1776
1777 ds += ndesc;
1778 bf->bf_desc = ds;
1779 bf->bf_daddr = DS2PHYS(dd, ds);
1780 }
1781 }
1782 list_add_tail(&bf->list, head);
1783 }
1784 return 0;
1785 fail2:
1786 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1787 dd->dd_desc_paddr);
1788 fail:
1789 memset(dd, 0, sizeof(*dd));
1790 return error;
1791 #undef ATH_DESC_4KB_BOUND_CHECK
1792 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1793 #undef DS2PHYS
1794 }
1795
1796 void ath_descdma_cleanup(struct ath_softc *sc,
1797 struct ath_descdma *dd,
1798 struct list_head *head)
1799 {
1800 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1801 dd->dd_desc_paddr);
1802
1803 INIT_LIST_HEAD(head);
1804 kfree(dd->dd_bufptr);
1805 memset(dd, 0, sizeof(*dd));
1806 }
1807
1808 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1809 {
1810 int qnum;
1811
1812 switch (queue) {
1813 case 0:
1814 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
1815 break;
1816 case 1:
1817 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
1818 break;
1819 case 2:
1820 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1821 break;
1822 case 3:
1823 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
1824 break;
1825 default:
1826 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1827 break;
1828 }
1829
1830 return qnum;
1831 }
1832
1833 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1834 {
1835 int qnum;
1836
1837 switch (queue) {
1838 case ATH9K_WME_AC_VO:
1839 qnum = 0;
1840 break;
1841 case ATH9K_WME_AC_VI:
1842 qnum = 1;
1843 break;
1844 case ATH9K_WME_AC_BE:
1845 qnum = 2;
1846 break;
1847 case ATH9K_WME_AC_BK:
1848 qnum = 3;
1849 break;
1850 default:
1851 qnum = -1;
1852 break;
1853 }
1854
1855 return qnum;
1856 }
1857
1858 /* XXX: Remove me once we don't depend on ath9k_channel for all
1859 * this redundant data */
1860 void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
1861 struct ath9k_channel *ichan)
1862 {
1863 struct ieee80211_channel *chan = hw->conf.channel;
1864 struct ieee80211_conf *conf = &hw->conf;
1865
1866 ichan->channel = chan->center_freq;
1867 ichan->chan = chan;
1868
1869 if (chan->band == IEEE80211_BAND_2GHZ) {
1870 ichan->chanmode = CHANNEL_G;
1871 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM;
1872 } else {
1873 ichan->chanmode = CHANNEL_A;
1874 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
1875 }
1876
1877 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1878
1879 if (conf_is_ht(conf)) {
1880 if (conf_is_ht40(conf))
1881 sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
1882
1883 ichan->chanmode = ath_get_extchanmode(sc, chan,
1884 conf->channel_type);
1885 }
1886 }
1887
1888 /**********************/
1889 /* mac80211 callbacks */
1890 /**********************/
1891
1892 static int ath9k_start(struct ieee80211_hw *hw)
1893 {
1894 struct ath_wiphy *aphy = hw->priv;
1895 struct ath_softc *sc = aphy->sc;
1896 struct ieee80211_channel *curchan = hw->conf.channel;
1897 struct ath9k_channel *init_channel;
1898 int r;
1899
1900 DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1901 "initial channel: %d MHz\n", curchan->center_freq);
1902
1903 mutex_lock(&sc->mutex);
1904
1905 if (ath9k_wiphy_started(sc)) {
1906 if (sc->chan_idx == curchan->hw_value) {
1907 /*
1908 * Already on the operational channel, the new wiphy
1909 * can be marked active.
1910 */
1911 aphy->state = ATH_WIPHY_ACTIVE;
1912 ieee80211_wake_queues(hw);
1913 } else {
1914 /*
1915 * Another wiphy is on another channel, start the new
1916 * wiphy in paused state.
1917 */
1918 aphy->state = ATH_WIPHY_PAUSED;
1919 ieee80211_stop_queues(hw);
1920 }
1921 mutex_unlock(&sc->mutex);
1922 return 0;
1923 }
1924 aphy->state = ATH_WIPHY_ACTIVE;
1925
1926 /* setup initial channel */
1927
1928 sc->chan_idx = curchan->hw_value;
1929
1930 init_channel = ath_get_curchannel(sc, hw);
1931
1932 /* Reset SERDES registers */
1933 ath9k_hw_configpcipowersave(sc->sc_ah, 0);
1934
1935 /*
1936 * The basic interface to setting the hardware in a good
1937 * state is ``reset''. On return the hardware is known to
1938 * be powered up and with interrupts disabled. This must
1939 * be followed by initialization of the appropriate bits
1940 * and then setup of the interrupt mask.
1941 */
1942 spin_lock_bh(&sc->sc_resetlock);
1943 r = ath9k_hw_reset(sc->sc_ah, init_channel, false);
1944 if (r) {
1945 DPRINTF(sc, ATH_DBG_FATAL,
1946 "Unable to reset hardware; reset status %d "
1947 "(freq %u MHz)\n", r,
1948 curchan->center_freq);
1949 spin_unlock_bh(&sc->sc_resetlock);
1950 goto mutex_unlock;
1951 }
1952 spin_unlock_bh(&sc->sc_resetlock);
1953
1954 /*
1955 * This is needed only to setup initial state
1956 * but it's best done after a reset.
1957 */
1958 ath_update_txpow(sc);
1959
1960 /*
1961 * Setup the hardware after reset:
1962 * The receive engine is set going.
1963 * Frame transmit is handled entirely
1964 * in the frame output path; there's nothing to do
1965 * here except setup the interrupt mask.
1966 */
1967 if (ath_startrecv(sc) != 0) {
1968 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
1969 r = -EIO;
1970 goto mutex_unlock;
1971 }
1972
1973 /* Setup our intr mask. */
1974 sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
1975 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
1976 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
1977
1978 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
1979 sc->imask |= ATH9K_INT_GTT;
1980
1981 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
1982 sc->imask |= ATH9K_INT_CST;
1983
1984 ath_cache_conf_rate(sc, &hw->conf);
1985
1986 sc->sc_flags &= ~SC_OP_INVALID;
1987
1988 /* Disable BMISS interrupt when we're not associated */
1989 sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
1990 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
1991
1992 ieee80211_wake_queues(hw);
1993
1994 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
1995
1996 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX) &&
1997 (sc->btcoex_info.btcoex_scheme == ATH_BTCOEX_CFG_2WIRE) &&
1998 !(sc->sc_flags & SC_OP_BTCOEX_ENABLED))
1999 ath9k_hw_btcoex_enable(sc->sc_ah);
2000
2001 mutex_unlock:
2002 mutex_unlock(&sc->mutex);
2003
2004 return r;
2005 }
2006
2007 static int ath9k_tx(struct ieee80211_hw *hw,
2008 struct sk_buff *skb)
2009 {
2010 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2011 struct ath_wiphy *aphy = hw->priv;
2012 struct ath_softc *sc = aphy->sc;
2013 struct ath_tx_control txctl;
2014 int hdrlen, padsize;
2015
2016 if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
2017 printk(KERN_DEBUG "ath9k: %s: TX in unexpected wiphy state "
2018 "%d\n", wiphy_name(hw->wiphy), aphy->state);
2019 goto exit;
2020 }
2021
2022 if (sc->ps_enabled) {
2023 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2024 /*
2025 * mac80211 does not set PM field for normal data frames, so we
2026 * need to update that based on the current PS mode.
2027 */
2028 if (ieee80211_is_data(hdr->frame_control) &&
2029 !ieee80211_is_nullfunc(hdr->frame_control) &&
2030 !ieee80211_has_pm(hdr->frame_control)) {
2031 DPRINTF(sc, ATH_DBG_PS, "Add PM=1 for a TX frame "
2032 "while in PS mode\n");
2033 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
2034 }
2035 }
2036
2037 if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
2038 /*
2039 * We are using PS-Poll and mac80211 can request TX while in
2040 * power save mode. Need to wake up hardware for the TX to be
2041 * completed and if needed, also for RX of buffered frames.
2042 */
2043 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2044 ath9k_ps_wakeup(sc);
2045 ath9k_hw_setrxabort(sc->sc_ah, 0);
2046 if (ieee80211_is_pspoll(hdr->frame_control)) {
2047 DPRINTF(sc, ATH_DBG_PS, "Sending PS-Poll to pick a "
2048 "buffered frame\n");
2049 sc->sc_flags |= SC_OP_WAIT_FOR_PSPOLL_DATA;
2050 } else {
2051 DPRINTF(sc, ATH_DBG_PS, "Wake up to complete TX\n");
2052 sc->sc_flags |= SC_OP_WAIT_FOR_TX_ACK;
2053 }
2054 /*
2055 * The actual restore operation will happen only after
2056 * the sc_flags bit is cleared. We are just dropping
2057 * the ps_usecount here.
2058 */
2059 ath9k_ps_restore(sc);
2060 }
2061
2062 memset(&txctl, 0, sizeof(struct ath_tx_control));
2063
2064 /*
2065 * As a temporary workaround, assign seq# here; this will likely need
2066 * to be cleaned up to work better with Beacon transmission and virtual
2067 * BSSes.
2068 */
2069 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2070 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2071 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2072 sc->tx.seq_no += 0x10;
2073 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2074 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
2075 }
2076
2077 /* Add the padding after the header if this is not already done */
2078 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2079 if (hdrlen & 3) {
2080 padsize = hdrlen % 4;
2081 if (skb_headroom(skb) < padsize)
2082 return -1;
2083 skb_push(skb, padsize);
2084 memmove(skb->data, skb->data + padsize, hdrlen);
2085 }
2086
2087 /* Check if a tx queue is available */
2088
2089 txctl.txq = ath_test_get_txq(sc, skb);
2090 if (!txctl.txq)
2091 goto exit;
2092
2093 DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
2094
2095 if (ath_tx_start(hw, skb, &txctl) != 0) {
2096 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
2097 goto exit;
2098 }
2099
2100 return 0;
2101 exit:
2102 dev_kfree_skb_any(skb);
2103 return 0;
2104 }
2105
2106 static void ath9k_stop(struct ieee80211_hw *hw)
2107 {
2108 struct ath_wiphy *aphy = hw->priv;
2109 struct ath_softc *sc = aphy->sc;
2110
2111 mutex_lock(&sc->mutex);
2112
2113 aphy->state = ATH_WIPHY_INACTIVE;
2114
2115 cancel_delayed_work_sync(&sc->ath_led_blink_work);
2116 cancel_delayed_work_sync(&sc->tx_complete_work);
2117
2118 if (!sc->num_sec_wiphy) {
2119 cancel_delayed_work_sync(&sc->wiphy_work);
2120 cancel_work_sync(&sc->chan_work);
2121 }
2122
2123 if (sc->sc_flags & SC_OP_INVALID) {
2124 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
2125 mutex_unlock(&sc->mutex);
2126 return;
2127 }
2128
2129 if (ath9k_wiphy_started(sc)) {
2130 mutex_unlock(&sc->mutex);
2131 return; /* another wiphy still in use */
2132 }
2133
2134 /* make sure h/w will not generate any interrupt
2135 * before setting the invalid flag. */
2136 ath9k_hw_set_interrupts(sc->sc_ah, 0);
2137
2138 if (!(sc->sc_flags & SC_OP_INVALID)) {
2139 ath_drain_all_txq(sc, false);
2140 ath_stoprecv(sc);
2141 ath9k_hw_phy_disable(sc->sc_ah);
2142 } else
2143 sc->rx.rxlink = NULL;
2144
2145 wiphy_rfkill_stop_polling(sc->hw->wiphy);
2146
2147 if (sc->sc_flags & SC_OP_BTCOEX_ENABLED)
2148 ath9k_hw_btcoex_disable(sc->sc_ah);
2149
2150 /* disable HAL and put h/w to sleep */
2151 ath9k_hw_disable(sc->sc_ah);
2152 ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2153 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
2154
2155 sc->sc_flags |= SC_OP_INVALID;
2156
2157 mutex_unlock(&sc->mutex);
2158
2159 DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
2160 }
2161
2162 static int ath9k_add_interface(struct ieee80211_hw *hw,
2163 struct ieee80211_if_init_conf *conf)
2164 {
2165 struct ath_wiphy *aphy = hw->priv;
2166 struct ath_softc *sc = aphy->sc;
2167 struct ath_vif *avp = (void *)conf->vif->drv_priv;
2168 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2169 int ret = 0;
2170
2171 mutex_lock(&sc->mutex);
2172
2173 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
2174 sc->nvifs > 0) {
2175 ret = -ENOBUFS;
2176 goto out;
2177 }
2178
2179 switch (conf->type) {
2180 case NL80211_IFTYPE_STATION:
2181 ic_opmode = NL80211_IFTYPE_STATION;
2182 break;
2183 case NL80211_IFTYPE_ADHOC:
2184 case NL80211_IFTYPE_AP:
2185 case NL80211_IFTYPE_MESH_POINT:
2186 if (sc->nbcnvifs >= ATH_BCBUF) {
2187 ret = -ENOBUFS;
2188 goto out;
2189 }
2190 ic_opmode = conf->type;
2191 break;
2192 default:
2193 DPRINTF(sc, ATH_DBG_FATAL,
2194 "Interface type %d not yet supported\n", conf->type);
2195 ret = -EOPNOTSUPP;
2196 goto out;
2197 }
2198
2199 DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VIF of type: %d\n", ic_opmode);
2200
2201 /* Set the VIF opmode */
2202 avp->av_opmode = ic_opmode;
2203 avp->av_bslot = -1;
2204
2205 sc->nvifs++;
2206
2207 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
2208 ath9k_set_bssid_mask(hw);
2209
2210 if (sc->nvifs > 1)
2211 goto out; /* skip global settings for secondary vif */
2212
2213 if (ic_opmode == NL80211_IFTYPE_AP) {
2214 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2215 sc->sc_flags |= SC_OP_TSF_RESET;
2216 }
2217
2218 /* Set the device opmode */
2219 sc->sc_ah->opmode = ic_opmode;
2220
2221 /*
2222 * Enable MIB interrupts when there are hardware phy counters.
2223 * Note we only do this (at the moment) for station mode.
2224 */
2225 if ((conf->type == NL80211_IFTYPE_STATION) ||
2226 (conf->type == NL80211_IFTYPE_ADHOC) ||
2227 (conf->type == NL80211_IFTYPE_MESH_POINT)) {
2228 sc->imask |= ATH9K_INT_MIB;
2229 sc->imask |= ATH9K_INT_TSFOOR;
2230 }
2231
2232 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
2233
2234 if (conf->type == NL80211_IFTYPE_AP ||
2235 conf->type == NL80211_IFTYPE_ADHOC ||
2236 conf->type == NL80211_IFTYPE_MONITOR)
2237 ath_start_ani(sc);
2238
2239 out:
2240 mutex_unlock(&sc->mutex);
2241 return ret;
2242 }
2243
2244 static void ath9k_remove_interface(struct ieee80211_hw *hw,
2245 struct ieee80211_if_init_conf *conf)
2246 {
2247 struct ath_wiphy *aphy = hw->priv;
2248 struct ath_softc *sc = aphy->sc;
2249 struct ath_vif *avp = (void *)conf->vif->drv_priv;
2250 int i;
2251
2252 DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
2253
2254 mutex_lock(&sc->mutex);
2255
2256 /* Stop ANI */
2257 del_timer_sync(&sc->ani.timer);
2258
2259 /* Reclaim beacon resources */
2260 if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
2261 (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
2262 (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
2263 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2264 ath_beacon_return(sc, avp);
2265 }
2266
2267 sc->sc_flags &= ~SC_OP_BEACONS;
2268
2269 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2270 if (sc->beacon.bslot[i] == conf->vif) {
2271 printk(KERN_DEBUG "%s: vif had allocated beacon "
2272 "slot\n", __func__);
2273 sc->beacon.bslot[i] = NULL;
2274 sc->beacon.bslot_aphy[i] = NULL;
2275 }
2276 }
2277
2278 sc->nvifs--;
2279
2280 mutex_unlock(&sc->mutex);
2281 }
2282
2283 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2284 {
2285 struct ath_wiphy *aphy = hw->priv;
2286 struct ath_softc *sc = aphy->sc;
2287 struct ieee80211_conf *conf = &hw->conf;
2288 struct ath_hw *ah = sc->sc_ah;
2289 bool all_wiphys_idle = false, disable_radio = false;
2290
2291 mutex_lock(&sc->mutex);
2292
2293 /* Leave this as the first check */
2294 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
2295
2296 spin_lock_bh(&sc->wiphy_lock);
2297 all_wiphys_idle = ath9k_all_wiphys_idle(sc);
2298 spin_unlock_bh(&sc->wiphy_lock);
2299
2300 if (conf->flags & IEEE80211_CONF_IDLE){
2301 if (all_wiphys_idle)
2302 disable_radio = true;
2303 }
2304 else if (all_wiphys_idle) {
2305 ath_radio_enable(sc);
2306 DPRINTF(sc, ATH_DBG_CONFIG,
2307 "not-idle: enabling radio\n");
2308 }
2309 }
2310
2311 if (changed & IEEE80211_CONF_CHANGE_PS) {
2312 if (conf->flags & IEEE80211_CONF_PS) {
2313 if (!(ah->caps.hw_caps &
2314 ATH9K_HW_CAP_AUTOSLEEP)) {
2315 if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
2316 sc->imask |= ATH9K_INT_TIM_TIMER;
2317 ath9k_hw_set_interrupts(sc->sc_ah,
2318 sc->imask);
2319 }
2320 ath9k_hw_setrxabort(sc->sc_ah, 1);
2321 }
2322 sc->ps_enabled = true;
2323 } else {
2324 sc->ps_enabled = false;
2325 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
2326 if (!(ah->caps.hw_caps &
2327 ATH9K_HW_CAP_AUTOSLEEP)) {
2328 ath9k_hw_setrxabort(sc->sc_ah, 0);
2329 sc->sc_flags &= ~(SC_OP_WAIT_FOR_BEACON |
2330 SC_OP_WAIT_FOR_CAB |
2331 SC_OP_WAIT_FOR_PSPOLL_DATA |
2332 SC_OP_WAIT_FOR_TX_ACK);
2333 if (sc->imask & ATH9K_INT_TIM_TIMER) {
2334 sc->imask &= ~ATH9K_INT_TIM_TIMER;
2335 ath9k_hw_set_interrupts(sc->sc_ah,
2336 sc->imask);
2337 }
2338 }
2339 }
2340 }
2341
2342 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2343 struct ieee80211_channel *curchan = hw->conf.channel;
2344 int pos = curchan->hw_value;
2345
2346 aphy->chan_idx = pos;
2347 aphy->chan_is_ht = conf_is_ht(conf);
2348
2349 if (aphy->state == ATH_WIPHY_SCAN ||
2350 aphy->state == ATH_WIPHY_ACTIVE)
2351 ath9k_wiphy_pause_all_forced(sc, aphy);
2352 else {
2353 /*
2354 * Do not change operational channel based on a paused
2355 * wiphy changes.
2356 */
2357 goto skip_chan_change;
2358 }
2359
2360 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2361 curchan->center_freq);
2362
2363 /* XXX: remove me eventualy */
2364 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
2365
2366 ath_update_chainmask(sc, conf_is_ht(conf));
2367
2368 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
2369 DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
2370 mutex_unlock(&sc->mutex);
2371 return -EINVAL;
2372 }
2373 }
2374
2375 skip_chan_change:
2376 if (changed & IEEE80211_CONF_CHANGE_POWER)
2377 sc->config.txpowlimit = 2 * conf->power_level;
2378
2379 if (disable_radio) {
2380 DPRINTF(sc, ATH_DBG_CONFIG, "idle: disabling radio\n");
2381 ath_radio_disable(sc);
2382 }
2383
2384 mutex_unlock(&sc->mutex);
2385
2386 return 0;
2387 }
2388
2389 #define SUPPORTED_FILTERS \
2390 (FIF_PROMISC_IN_BSS | \
2391 FIF_ALLMULTI | \
2392 FIF_CONTROL | \
2393 FIF_PSPOLL | \
2394 FIF_OTHER_BSS | \
2395 FIF_BCN_PRBRESP_PROMISC | \
2396 FIF_FCSFAIL)
2397
2398 /* FIXME: sc->sc_full_reset ? */
2399 static void ath9k_configure_filter(struct ieee80211_hw *hw,
2400 unsigned int changed_flags,
2401 unsigned int *total_flags,
2402 u64 multicast)
2403 {
2404 struct ath_wiphy *aphy = hw->priv;
2405 struct ath_softc *sc = aphy->sc;
2406 u32 rfilt;
2407
2408 changed_flags &= SUPPORTED_FILTERS;
2409 *total_flags &= SUPPORTED_FILTERS;
2410
2411 sc->rx.rxfilter = *total_flags;
2412 ath9k_ps_wakeup(sc);
2413 rfilt = ath_calcrxfilter(sc);
2414 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
2415 ath9k_ps_restore(sc);
2416
2417 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
2418 }
2419
2420 static void ath9k_sta_notify(struct ieee80211_hw *hw,
2421 struct ieee80211_vif *vif,
2422 enum sta_notify_cmd cmd,
2423 struct ieee80211_sta *sta)
2424 {
2425 struct ath_wiphy *aphy = hw->priv;
2426 struct ath_softc *sc = aphy->sc;
2427
2428 switch (cmd) {
2429 case STA_NOTIFY_ADD:
2430 ath_node_attach(sc, sta);
2431 break;
2432 case STA_NOTIFY_REMOVE:
2433 ath_node_detach(sc, sta);
2434 break;
2435 default:
2436 break;
2437 }
2438 }
2439
2440 static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
2441 const struct ieee80211_tx_queue_params *params)
2442 {
2443 struct ath_wiphy *aphy = hw->priv;
2444 struct ath_softc *sc = aphy->sc;
2445 struct ath9k_tx_queue_info qi;
2446 int ret = 0, qnum;
2447
2448 if (queue >= WME_NUM_AC)
2449 return 0;
2450
2451 mutex_lock(&sc->mutex);
2452
2453 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
2454
2455 qi.tqi_aifs = params->aifs;
2456 qi.tqi_cwmin = params->cw_min;
2457 qi.tqi_cwmax = params->cw_max;
2458 qi.tqi_burstTime = params->txop;
2459 qnum = ath_get_hal_qnum(queue, sc);
2460
2461 DPRINTF(sc, ATH_DBG_CONFIG,
2462 "Configure tx [queue/halq] [%d/%d], "
2463 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2464 queue, qnum, params->aifs, params->cw_min,
2465 params->cw_max, params->txop);
2466
2467 ret = ath_txq_update(sc, qnum, &qi);
2468 if (ret)
2469 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
2470
2471 mutex_unlock(&sc->mutex);
2472
2473 return ret;
2474 }
2475
2476 static int ath9k_set_key(struct ieee80211_hw *hw,
2477 enum set_key_cmd cmd,
2478 struct ieee80211_vif *vif,
2479 struct ieee80211_sta *sta,
2480 struct ieee80211_key_conf *key)
2481 {
2482 struct ath_wiphy *aphy = hw->priv;
2483 struct ath_softc *sc = aphy->sc;
2484 int ret = 0;
2485
2486 if (modparam_nohwcrypt)
2487 return -ENOSPC;
2488
2489 mutex_lock(&sc->mutex);
2490 ath9k_ps_wakeup(sc);
2491 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW Key\n");
2492
2493 switch (cmd) {
2494 case SET_KEY:
2495 ret = ath_key_config(sc, vif, sta, key);
2496 if (ret >= 0) {
2497 key->hw_key_idx = ret;
2498 /* push IV and Michael MIC generation to stack */
2499 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2500 if (key->alg == ALG_TKIP)
2501 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
2502 if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2503 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
2504 ret = 0;
2505 }
2506 break;
2507 case DISABLE_KEY:
2508 ath_key_delete(sc, key);
2509 break;
2510 default:
2511 ret = -EINVAL;
2512 }
2513
2514 ath9k_ps_restore(sc);
2515 mutex_unlock(&sc->mutex);
2516
2517 return ret;
2518 }
2519
2520 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2521 struct ieee80211_vif *vif,
2522 struct ieee80211_bss_conf *bss_conf,
2523 u32 changed)
2524 {
2525 struct ath_wiphy *aphy = hw->priv;
2526 struct ath_softc *sc = aphy->sc;
2527 struct ath_hw *ah = sc->sc_ah;
2528 struct ath_vif *avp = (void *)vif->drv_priv;
2529 u32 rfilt = 0;
2530 int error, i;
2531
2532 mutex_lock(&sc->mutex);
2533
2534 /*
2535 * TODO: Need to decide which hw opmode to use for
2536 * multi-interface cases
2537 * XXX: This belongs into add_interface!
2538 */
2539 if (vif->type == NL80211_IFTYPE_AP &&
2540 ah->opmode != NL80211_IFTYPE_AP) {
2541 ah->opmode = NL80211_IFTYPE_STATION;
2542 ath9k_hw_setopmode(ah);
2543 memcpy(sc->curbssid, sc->sc_ah->macaddr, ETH_ALEN);
2544 sc->curaid = 0;
2545 ath9k_hw_write_associd(sc);
2546 /* Request full reset to get hw opmode changed properly */
2547 sc->sc_flags |= SC_OP_FULL_RESET;
2548 }
2549
2550 if ((changed & BSS_CHANGED_BSSID) &&
2551 !is_zero_ether_addr(bss_conf->bssid)) {
2552 switch (vif->type) {
2553 case NL80211_IFTYPE_STATION:
2554 case NL80211_IFTYPE_ADHOC:
2555 case NL80211_IFTYPE_MESH_POINT:
2556 /* Set BSSID */
2557 memcpy(sc->curbssid, bss_conf->bssid, ETH_ALEN);
2558 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
2559 sc->curaid = 0;
2560 ath9k_hw_write_associd(sc);
2561
2562 /* Set aggregation protection mode parameters */
2563 sc->config.ath_aggr_prot = 0;
2564
2565 DPRINTF(sc, ATH_DBG_CONFIG,
2566 "RX filter 0x%x bssid %pM aid 0x%x\n",
2567 rfilt, sc->curbssid, sc->curaid);
2568
2569 /* need to reconfigure the beacon */
2570 sc->sc_flags &= ~SC_OP_BEACONS ;
2571
2572 break;
2573 default:
2574 break;
2575 }
2576 }
2577
2578 if ((vif->type == NL80211_IFTYPE_ADHOC) ||
2579 (vif->type == NL80211_IFTYPE_AP) ||
2580 (vif->type == NL80211_IFTYPE_MESH_POINT)) {
2581 if ((changed & BSS_CHANGED_BEACON) ||
2582 (changed & BSS_CHANGED_BEACON_ENABLED &&
2583 bss_conf->enable_beacon)) {
2584 /*
2585 * Allocate and setup the beacon frame.
2586 *
2587 * Stop any previous beacon DMA. This may be
2588 * necessary, for example, when an ibss merge
2589 * causes reconfiguration; we may be called
2590 * with beacon transmission active.
2591 */
2592 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2593
2594 error = ath_beacon_alloc(aphy, vif);
2595 if (!error)
2596 ath_beacon_config(sc, vif);
2597 }
2598 }
2599
2600 /* Check for WLAN_CAPABILITY_PRIVACY ? */
2601 if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
2602 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2603 if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2604 ath9k_hw_keysetmac(sc->sc_ah,
2605 (u16)i,
2606 sc->curbssid);
2607 }
2608
2609 /* Only legacy IBSS for now */
2610 if (vif->type == NL80211_IFTYPE_ADHOC)
2611 ath_update_chainmask(sc, 0);
2612
2613 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
2614 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
2615 bss_conf->use_short_preamble);
2616 if (bss_conf->use_short_preamble)
2617 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2618 else
2619 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2620 }
2621
2622 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
2623 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
2624 bss_conf->use_cts_prot);
2625 if (bss_conf->use_cts_prot &&
2626 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2627 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2628 else
2629 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2630 }
2631
2632 if (changed & BSS_CHANGED_ASSOC) {
2633 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
2634 bss_conf->assoc);
2635 ath9k_bss_assoc_info(sc, vif, bss_conf);
2636 }
2637
2638 /*
2639 * The HW TSF has to be reset when the beacon interval changes.
2640 * We set the flag here, and ath_beacon_config_ap() would take this
2641 * into account when it gets called through the subsequent
2642 * config_interface() call - with IFCC_BEACON in the changed field.
2643 */
2644
2645 if (changed & BSS_CHANGED_BEACON_INT) {
2646 sc->sc_flags |= SC_OP_TSF_RESET;
2647 sc->beacon_interval = bss_conf->beacon_int;
2648 }
2649
2650 mutex_unlock(&sc->mutex);
2651 }
2652
2653 static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2654 {
2655 u64 tsf;
2656 struct ath_wiphy *aphy = hw->priv;
2657 struct ath_softc *sc = aphy->sc;
2658
2659 mutex_lock(&sc->mutex);
2660 tsf = ath9k_hw_gettsf64(sc->sc_ah);
2661 mutex_unlock(&sc->mutex);
2662
2663 return tsf;
2664 }
2665
2666 static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2667 {
2668 struct ath_wiphy *aphy = hw->priv;
2669 struct ath_softc *sc = aphy->sc;
2670
2671 mutex_lock(&sc->mutex);
2672 ath9k_hw_settsf64(sc->sc_ah, tsf);
2673 mutex_unlock(&sc->mutex);
2674 }
2675
2676 static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2677 {
2678 struct ath_wiphy *aphy = hw->priv;
2679 struct ath_softc *sc = aphy->sc;
2680
2681 mutex_lock(&sc->mutex);
2682 ath9k_hw_reset_tsf(sc->sc_ah);
2683 mutex_unlock(&sc->mutex);
2684 }
2685
2686 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2687 enum ieee80211_ampdu_mlme_action action,
2688 struct ieee80211_sta *sta,
2689 u16 tid, u16 *ssn)
2690 {
2691 struct ath_wiphy *aphy = hw->priv;
2692 struct ath_softc *sc = aphy->sc;
2693 int ret = 0;
2694
2695 switch (action) {
2696 case IEEE80211_AMPDU_RX_START:
2697 if (!(sc->sc_flags & SC_OP_RXAGGR))
2698 ret = -ENOTSUPP;
2699 break;
2700 case IEEE80211_AMPDU_RX_STOP:
2701 break;
2702 case IEEE80211_AMPDU_TX_START:
2703 ath_tx_aggr_start(sc, sta, tid, ssn);
2704 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2705 break;
2706 case IEEE80211_AMPDU_TX_STOP:
2707 ath_tx_aggr_stop(sc, sta, tid);
2708 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2709 break;
2710 case IEEE80211_AMPDU_TX_OPERATIONAL:
2711 ath_tx_aggr_resume(sc, sta, tid);
2712 break;
2713 default:
2714 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
2715 }
2716
2717 return ret;
2718 }
2719
2720 static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
2721 {
2722 struct ath_wiphy *aphy = hw->priv;
2723 struct ath_softc *sc = aphy->sc;
2724
2725 mutex_lock(&sc->mutex);
2726 if (ath9k_wiphy_scanning(sc)) {
2727 printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the "
2728 "same time\n");
2729 /*
2730 * Do not allow the concurrent scanning state for now. This
2731 * could be improved with scanning control moved into ath9k.
2732 */
2733 mutex_unlock(&sc->mutex);
2734 return;
2735 }
2736
2737 aphy->state = ATH_WIPHY_SCAN;
2738 ath9k_wiphy_pause_all_forced(sc, aphy);
2739
2740 spin_lock_bh(&sc->ani_lock);
2741 sc->sc_flags |= SC_OP_SCANNING;
2742 spin_unlock_bh(&sc->ani_lock);
2743 mutex_unlock(&sc->mutex);
2744 }
2745
2746 static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
2747 {
2748 struct ath_wiphy *aphy = hw->priv;
2749 struct ath_softc *sc = aphy->sc;
2750
2751 mutex_lock(&sc->mutex);
2752 spin_lock_bh(&sc->ani_lock);
2753 aphy->state = ATH_WIPHY_ACTIVE;
2754 sc->sc_flags &= ~SC_OP_SCANNING;
2755 sc->sc_flags |= SC_OP_FULL_RESET;
2756 spin_unlock_bh(&sc->ani_lock);
2757 mutex_unlock(&sc->mutex);
2758 }
2759
2760 struct ieee80211_ops ath9k_ops = {
2761 .tx = ath9k_tx,
2762 .start = ath9k_start,
2763 .stop = ath9k_stop,
2764 .add_interface = ath9k_add_interface,
2765 .remove_interface = ath9k_remove_interface,
2766 .config = ath9k_config,
2767 .configure_filter = ath9k_configure_filter,
2768 .sta_notify = ath9k_sta_notify,
2769 .conf_tx = ath9k_conf_tx,
2770 .bss_info_changed = ath9k_bss_info_changed,
2771 .set_key = ath9k_set_key,
2772 .get_tsf = ath9k_get_tsf,
2773 .set_tsf = ath9k_set_tsf,
2774 .reset_tsf = ath9k_reset_tsf,
2775 .ampdu_action = ath9k_ampdu_action,
2776 .sw_scan_start = ath9k_sw_scan_start,
2777 .sw_scan_complete = ath9k_sw_scan_complete,
2778 .rfkill_poll = ath9k_rfkill_poll_state,
2779 };
2780
2781 static struct {
2782 u32 version;
2783 const char * name;
2784 } ath_mac_bb_names[] = {
2785 { AR_SREV_VERSION_5416_PCI, "5416" },
2786 { AR_SREV_VERSION_5416_PCIE, "5418" },
2787 { AR_SREV_VERSION_9100, "9100" },
2788 { AR_SREV_VERSION_9160, "9160" },
2789 { AR_SREV_VERSION_9280, "9280" },
2790 { AR_SREV_VERSION_9285, "9285" },
2791 { AR_SREV_VERSION_9287, "9287" }
2792 };
2793
2794 static struct {
2795 u16 version;
2796 const char * name;
2797 } ath_rf_names[] = {
2798 { 0, "5133" },
2799 { AR_RAD5133_SREV_MAJOR, "5133" },
2800 { AR_RAD5122_SREV_MAJOR, "5122" },
2801 { AR_RAD2133_SREV_MAJOR, "2133" },
2802 { AR_RAD2122_SREV_MAJOR, "2122" }
2803 };
2804
2805 /*
2806 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2807 */
2808 const char *
2809 ath_mac_bb_name(u32 mac_bb_version)
2810 {
2811 int i;
2812
2813 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2814 if (ath_mac_bb_names[i].version == mac_bb_version) {
2815 return ath_mac_bb_names[i].name;
2816 }
2817 }
2818
2819 return "????";
2820 }
2821
2822 /*
2823 * Return the RF name. "????" is returned if the RF is unknown.
2824 */
2825 const char *
2826 ath_rf_name(u16 rf_version)
2827 {
2828 int i;
2829
2830 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2831 if (ath_rf_names[i].version == rf_version) {
2832 return ath_rf_names[i].name;
2833 }
2834 }
2835
2836 return "????";
2837 }
2838
2839 static int __init ath9k_init(void)
2840 {
2841 int error;
2842
2843 /* Register rate control algorithm */
2844 error = ath_rate_control_register();
2845 if (error != 0) {
2846 printk(KERN_ERR
2847 "ath9k: Unable to register rate control "
2848 "algorithm: %d\n",
2849 error);
2850 goto err_out;
2851 }
2852
2853 error = ath9k_debug_create_root();
2854 if (error) {
2855 printk(KERN_ERR
2856 "ath9k: Unable to create debugfs root: %d\n",
2857 error);
2858 goto err_rate_unregister;
2859 }
2860
2861 error = ath_pci_init();
2862 if (error < 0) {
2863 printk(KERN_ERR
2864 "ath9k: No PCI devices found, driver not installed.\n");
2865 error = -ENODEV;
2866 goto err_remove_root;
2867 }
2868
2869 error = ath_ahb_init();
2870 if (error < 0) {
2871 error = -ENODEV;
2872 goto err_pci_exit;
2873 }
2874
2875 return 0;
2876
2877 err_pci_exit:
2878 ath_pci_exit();
2879
2880 err_remove_root:
2881 ath9k_debug_remove_root();
2882 err_rate_unregister:
2883 ath_rate_control_unregister();
2884 err_out:
2885 return error;
2886 }
2887 module_init(ath9k_init);
2888
2889 static void __exit ath9k_exit(void)
2890 {
2891 ath_ahb_exit();
2892 ath_pci_exit();
2893 ath9k_debug_remove_root();
2894 ath_rate_control_unregister();
2895 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
2896 }
2897 module_exit(ath9k_exit);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree