2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include <linux/usb.h>
24 #include <linux/pci.h>
25 #include <linux/slab.h>
26 #include <linux/dmapool.h>
31 * Allocates a generic ring segment from the ring pool, sets the dma address,
32 * initializes the segment to zero, and sets the private next pointer to NULL.
35 * "All components of all Command and Transfer TRBs shall be initialized to '0'"
37 static struct xhci_segment
*xhci_segment_alloc(struct xhci_hcd
*xhci
, gfp_t flags
)
39 struct xhci_segment
*seg
;
42 seg
= kzalloc(sizeof *seg
, flags
);
45 xhci_dbg(xhci
, "Allocating priv segment structure at %p\n", seg
);
47 seg
->trbs
= dma_pool_alloc(xhci
->segment_pool
, flags
, &dma
);
52 xhci_dbg(xhci
, "// Allocating segment at %p (virtual) 0x%llx (DMA)\n",
53 seg
->trbs
, (unsigned long long)dma
);
55 memset(seg
->trbs
, 0, SEGMENT_SIZE
);
62 static void xhci_segment_free(struct xhci_hcd
*xhci
, struct xhci_segment
*seg
)
67 xhci_dbg(xhci
, "Freeing DMA segment at %p (virtual) 0x%llx (DMA)\n",
68 seg
->trbs
, (unsigned long long)seg
->dma
);
69 dma_pool_free(xhci
->segment_pool
, seg
->trbs
, seg
->dma
);
72 xhci_dbg(xhci
, "Freeing priv segment structure at %p\n", seg
);
77 * Make the prev segment point to the next segment.
79 * Change the last TRB in the prev segment to be a Link TRB which points to the
80 * DMA address of the next segment. The caller needs to set any Link TRB
81 * related flags, such as End TRB, Toggle Cycle, and no snoop.
83 static void xhci_link_segments(struct xhci_hcd
*xhci
, struct xhci_segment
*prev
,
84 struct xhci_segment
*next
, bool link_trbs
)
92 prev
->trbs
[TRBS_PER_SEGMENT
-1].link
.segment_ptr
= next
->dma
;
94 /* Set the last TRB in the segment to have a TRB type ID of Link TRB */
95 val
= prev
->trbs
[TRBS_PER_SEGMENT
-1].link
.control
;
96 val
&= ~TRB_TYPE_BITMASK
;
97 val
|= TRB_TYPE(TRB_LINK
);
98 /* Always set the chain bit with 0.95 hardware */
99 if (xhci_link_trb_quirk(xhci
))
101 prev
->trbs
[TRBS_PER_SEGMENT
-1].link
.control
= val
;
103 xhci_dbg(xhci
, "Linking segment 0x%llx to segment 0x%llx (DMA)\n",
104 (unsigned long long)prev
->dma
,
105 (unsigned long long)next
->dma
);
108 /* XXX: Do we need the hcd structure in all these functions? */
109 void xhci_ring_free(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
)
111 struct xhci_segment
*seg
;
112 struct xhci_segment
*first_seg
;
114 if (!ring
|| !ring
->first_seg
)
116 first_seg
= ring
->first_seg
;
117 seg
= first_seg
->next
;
118 xhci_dbg(xhci
, "Freeing ring at %p\n", ring
);
119 while (seg
!= first_seg
) {
120 struct xhci_segment
*next
= seg
->next
;
121 xhci_segment_free(xhci
, seg
);
124 xhci_segment_free(xhci
, first_seg
);
125 ring
->first_seg
= NULL
;
129 static void xhci_initialize_ring_info(struct xhci_ring
*ring
)
131 /* The ring is empty, so the enqueue pointer == dequeue pointer */
132 ring
->enqueue
= ring
->first_seg
->trbs
;
133 ring
->enq_seg
= ring
->first_seg
;
134 ring
->dequeue
= ring
->enqueue
;
135 ring
->deq_seg
= ring
->first_seg
;
136 /* The ring is initialized to 0. The producer must write 1 to the cycle
137 * bit to handover ownership of the TRB, so PCS = 1. The consumer must
138 * compare CCS to the cycle bit to check ownership, so CCS = 1.
140 ring
->cycle_state
= 1;
141 /* Not necessary for new rings, but needed for re-initialized rings */
142 ring
->enq_updates
= 0;
143 ring
->deq_updates
= 0;
147 * Create a new ring with zero or more segments.
149 * Link each segment together into a ring.
150 * Set the end flag and the cycle toggle bit on the last segment.
151 * See section 4.9.1 and figures 15 and 16.
153 static struct xhci_ring
*xhci_ring_alloc(struct xhci_hcd
*xhci
,
154 unsigned int num_segs
, bool link_trbs
, gfp_t flags
)
156 struct xhci_ring
*ring
;
157 struct xhci_segment
*prev
;
159 ring
= kzalloc(sizeof *(ring
), flags
);
160 xhci_dbg(xhci
, "Allocating ring at %p\n", ring
);
164 INIT_LIST_HEAD(&ring
->td_list
);
168 ring
->first_seg
= xhci_segment_alloc(xhci
, flags
);
169 if (!ring
->first_seg
)
173 prev
= ring
->first_seg
;
174 while (num_segs
> 0) {
175 struct xhci_segment
*next
;
177 next
= xhci_segment_alloc(xhci
, flags
);
180 xhci_link_segments(xhci
, prev
, next
, link_trbs
);
185 xhci_link_segments(xhci
, prev
, ring
->first_seg
, link_trbs
);
188 /* See section 4.9.2.1 and 6.4.4.1 */
189 prev
->trbs
[TRBS_PER_SEGMENT
-1].link
.control
|= (LINK_TOGGLE
);
190 xhci_dbg(xhci
, "Wrote link toggle flag to"
191 " segment %p (virtual), 0x%llx (DMA)\n",
192 prev
, (unsigned long long)prev
->dma
);
194 xhci_initialize_ring_info(ring
);
198 xhci_ring_free(xhci
, ring
);
202 void xhci_free_or_cache_endpoint_ring(struct xhci_hcd
*xhci
,
203 struct xhci_virt_device
*virt_dev
,
204 unsigned int ep_index
)
208 rings_cached
= virt_dev
->num_rings_cached
;
209 if (rings_cached
< XHCI_MAX_RINGS_CACHED
) {
210 virt_dev
->num_rings_cached
++;
211 rings_cached
= virt_dev
->num_rings_cached
;
212 virt_dev
->ring_cache
[rings_cached
] =
213 virt_dev
->eps
[ep_index
].ring
;
214 xhci_dbg(xhci
, "Cached old ring, "
215 "%d ring%s cached\n",
217 (rings_cached
> 1) ? "s" : "");
219 xhci_ring_free(xhci
, virt_dev
->eps
[ep_index
].ring
);
220 xhci_dbg(xhci
, "Ring cache full (%d rings), "
222 virt_dev
->num_rings_cached
);
224 virt_dev
->eps
[ep_index
].ring
= NULL
;
227 /* Zero an endpoint ring (except for link TRBs) and move the enqueue and dequeue
228 * pointers to the beginning of the ring.
230 static void xhci_reinit_cached_ring(struct xhci_hcd
*xhci
,
231 struct xhci_ring
*ring
)
233 struct xhci_segment
*seg
= ring
->first_seg
;
236 sizeof(union xhci_trb
)*TRBS_PER_SEGMENT
);
237 /* All endpoint rings have link TRBs */
238 xhci_link_segments(xhci
, seg
, seg
->next
, 1);
240 } while (seg
!= ring
->first_seg
);
241 xhci_initialize_ring_info(ring
);
242 /* td list should be empty since all URBs have been cancelled,
243 * but just in case...
245 INIT_LIST_HEAD(&ring
->td_list
);
248 #define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32)
250 static struct xhci_container_ctx
*xhci_alloc_container_ctx(struct xhci_hcd
*xhci
,
251 int type
, gfp_t flags
)
253 struct xhci_container_ctx
*ctx
= kzalloc(sizeof(*ctx
), flags
);
257 BUG_ON((type
!= XHCI_CTX_TYPE_DEVICE
) && (type
!= XHCI_CTX_TYPE_INPUT
));
259 ctx
->size
= HCC_64BYTE_CONTEXT(xhci
->hcc_params
) ? 2048 : 1024;
260 if (type
== XHCI_CTX_TYPE_INPUT
)
261 ctx
->size
+= CTX_SIZE(xhci
->hcc_params
);
263 ctx
->bytes
= dma_pool_alloc(xhci
->device_pool
, flags
, &ctx
->dma
);
264 memset(ctx
->bytes
, 0, ctx
->size
);
268 static void xhci_free_container_ctx(struct xhci_hcd
*xhci
,
269 struct xhci_container_ctx
*ctx
)
273 dma_pool_free(xhci
->device_pool
, ctx
->bytes
, ctx
->dma
);
277 struct xhci_input_control_ctx
*xhci_get_input_control_ctx(struct xhci_hcd
*xhci
,
278 struct xhci_container_ctx
*ctx
)
280 BUG_ON(ctx
->type
!= XHCI_CTX_TYPE_INPUT
);
281 return (struct xhci_input_control_ctx
*)ctx
->bytes
;
284 struct xhci_slot_ctx
*xhci_get_slot_ctx(struct xhci_hcd
*xhci
,
285 struct xhci_container_ctx
*ctx
)
287 if (ctx
->type
== XHCI_CTX_TYPE_DEVICE
)
288 return (struct xhci_slot_ctx
*)ctx
->bytes
;
290 return (struct xhci_slot_ctx
*)
291 (ctx
->bytes
+ CTX_SIZE(xhci
->hcc_params
));
294 struct xhci_ep_ctx
*xhci_get_ep_ctx(struct xhci_hcd
*xhci
,
295 struct xhci_container_ctx
*ctx
,
296 unsigned int ep_index
)
298 /* increment ep index by offset of start of ep ctx array */
300 if (ctx
->type
== XHCI_CTX_TYPE_INPUT
)
303 return (struct xhci_ep_ctx
*)
304 (ctx
->bytes
+ (ep_index
* CTX_SIZE(xhci
->hcc_params
)));
308 /***************** Streams structures manipulation *************************/
310 static void xhci_free_stream_ctx(struct xhci_hcd
*xhci
,
311 unsigned int num_stream_ctxs
,
312 struct xhci_stream_ctx
*stream_ctx
, dma_addr_t dma
)
314 struct pci_dev
*pdev
= to_pci_dev(xhci_to_hcd(xhci
)->self
.controller
);
316 if (num_stream_ctxs
> MEDIUM_STREAM_ARRAY_SIZE
)
317 pci_free_consistent(pdev
,
318 sizeof(struct xhci_stream_ctx
)*num_stream_ctxs
,
320 else if (num_stream_ctxs
<= SMALL_STREAM_ARRAY_SIZE
)
321 return dma_pool_free(xhci
->small_streams_pool
,
324 return dma_pool_free(xhci
->medium_streams_pool
,
329 * The stream context array for each endpoint with bulk streams enabled can
330 * vary in size, based on:
331 * - how many streams the endpoint supports,
332 * - the maximum primary stream array size the host controller supports,
333 * - and how many streams the device driver asks for.
335 * The stream context array must be a power of 2, and can be as small as
336 * 64 bytes or as large as 1MB.
338 static struct xhci_stream_ctx
*xhci_alloc_stream_ctx(struct xhci_hcd
*xhci
,
339 unsigned int num_stream_ctxs
, dma_addr_t
*dma
,
342 struct pci_dev
*pdev
= to_pci_dev(xhci_to_hcd(xhci
)->self
.controller
);
344 if (num_stream_ctxs
> MEDIUM_STREAM_ARRAY_SIZE
)
345 return pci_alloc_consistent(pdev
,
346 sizeof(struct xhci_stream_ctx
)*num_stream_ctxs
,
348 else if (num_stream_ctxs
<= SMALL_STREAM_ARRAY_SIZE
)
349 return dma_pool_alloc(xhci
->small_streams_pool
,
352 return dma_pool_alloc(xhci
->medium_streams_pool
,
356 struct xhci_ring
*xhci_dma_to_transfer_ring(
357 struct xhci_virt_ep
*ep
,
360 if (ep
->ep_state
& EP_HAS_STREAMS
)
361 return radix_tree_lookup(&ep
->stream_info
->trb_address_map
,
362 address
>> SEGMENT_SHIFT
);
366 /* Only use this when you know stream_info is valid */
367 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
368 static struct xhci_ring
*dma_to_stream_ring(
369 struct xhci_stream_info
*stream_info
,
372 return radix_tree_lookup(&stream_info
->trb_address_map
,
373 address
>> SEGMENT_SHIFT
);
375 #endif /* CONFIG_USB_XHCI_HCD_DEBUGGING */
377 struct xhci_ring
*xhci_stream_id_to_ring(
378 struct xhci_virt_device
*dev
,
379 unsigned int ep_index
,
380 unsigned int stream_id
)
382 struct xhci_virt_ep
*ep
= &dev
->eps
[ep_index
];
386 if (!ep
->stream_info
)
389 if (stream_id
> ep
->stream_info
->num_streams
)
391 return ep
->stream_info
->stream_rings
[stream_id
];
394 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
395 static int xhci_test_radix_tree(struct xhci_hcd
*xhci
,
396 unsigned int num_streams
,
397 struct xhci_stream_info
*stream_info
)
400 struct xhci_ring
*cur_ring
;
403 for (cur_stream
= 1; cur_stream
< num_streams
; cur_stream
++) {
404 struct xhci_ring
*mapped_ring
;
405 int trb_size
= sizeof(union xhci_trb
);
407 cur_ring
= stream_info
->stream_rings
[cur_stream
];
408 for (addr
= cur_ring
->first_seg
->dma
;
409 addr
< cur_ring
->first_seg
->dma
+ SEGMENT_SIZE
;
411 mapped_ring
= dma_to_stream_ring(stream_info
, addr
);
412 if (cur_ring
!= mapped_ring
) {
413 xhci_warn(xhci
, "WARN: DMA address 0x%08llx "
414 "didn't map to stream ID %u; "
415 "mapped to ring %p\n",
416 (unsigned long long) addr
,
422 /* One TRB after the end of the ring segment shouldn't return a
423 * pointer to the current ring (although it may be a part of a
426 mapped_ring
= dma_to_stream_ring(stream_info
, addr
);
427 if (mapped_ring
!= cur_ring
) {
428 /* One TRB before should also fail */
429 addr
= cur_ring
->first_seg
->dma
- trb_size
;
430 mapped_ring
= dma_to_stream_ring(stream_info
, addr
);
432 if (mapped_ring
== cur_ring
) {
433 xhci_warn(xhci
, "WARN: Bad DMA address 0x%08llx "
434 "mapped to valid stream ID %u; "
435 "mapped ring = %p\n",
436 (unsigned long long) addr
,
444 #endif /* CONFIG_USB_XHCI_HCD_DEBUGGING */
447 * Change an endpoint's internal structure so it supports stream IDs. The
448 * number of requested streams includes stream 0, which cannot be used by device
451 * The number of stream contexts in the stream context array may be bigger than
452 * the number of streams the driver wants to use. This is because the number of
453 * stream context array entries must be a power of two.
455 * We need a radix tree for mapping physical addresses of TRBs to which stream
456 * ID they belong to. We need to do this because the host controller won't tell
457 * us which stream ring the TRB came from. We could store the stream ID in an
458 * event data TRB, but that doesn't help us for the cancellation case, since the
459 * endpoint may stop before it reaches that event data TRB.
461 * The radix tree maps the upper portion of the TRB DMA address to a ring
462 * segment that has the same upper portion of DMA addresses. For example, say I
463 * have segments of size 1KB, that are always 64-byte aligned. A segment may
464 * start at 0x10c91000 and end at 0x10c913f0. If I use the upper 10 bits, the
465 * key to the stream ID is 0x43244. I can use the DMA address of the TRB to
466 * pass the radix tree a key to get the right stream ID:
468 * 0x10c90fff >> 10 = 0x43243
469 * 0x10c912c0 >> 10 = 0x43244
470 * 0x10c91400 >> 10 = 0x43245
472 * Obviously, only those TRBs with DMA addresses that are within the segment
473 * will make the radix tree return the stream ID for that ring.
475 * Caveats for the radix tree:
477 * The radix tree uses an unsigned long as a key pair. On 32-bit systems, an
478 * unsigned long will be 32-bits; on a 64-bit system an unsigned long will be
479 * 64-bits. Since we only request 32-bit DMA addresses, we can use that as the
480 * key on 32-bit or 64-bit systems (it would also be fine if we asked for 64-bit
481 * PCI DMA addresses on a 64-bit system). There might be a problem on 32-bit
482 * extended systems (where the DMA address can be bigger than 32-bits),
483 * if we allow the PCI dma mask to be bigger than 32-bits. So don't do that.
485 struct xhci_stream_info
*xhci_alloc_stream_info(struct xhci_hcd
*xhci
,
486 unsigned int num_stream_ctxs
,
487 unsigned int num_streams
, gfp_t mem_flags
)
489 struct xhci_stream_info
*stream_info
;
491 struct xhci_ring
*cur_ring
;
496 xhci_dbg(xhci
, "Allocating %u streams and %u "
497 "stream context array entries.\n",
498 num_streams
, num_stream_ctxs
);
499 if (xhci
->cmd_ring_reserved_trbs
== MAX_RSVD_CMD_TRBS
) {
500 xhci_dbg(xhci
, "Command ring has no reserved TRBs available\n");
503 xhci
->cmd_ring_reserved_trbs
++;
505 stream_info
= kzalloc(sizeof(struct xhci_stream_info
), mem_flags
);
509 stream_info
->num_streams
= num_streams
;
510 stream_info
->num_stream_ctxs
= num_stream_ctxs
;
512 /* Initialize the array of virtual pointers to stream rings. */
513 stream_info
->stream_rings
= kzalloc(
514 sizeof(struct xhci_ring
*)*num_streams
,
516 if (!stream_info
->stream_rings
)
519 /* Initialize the array of DMA addresses for stream rings for the HW. */
520 stream_info
->stream_ctx_array
= xhci_alloc_stream_ctx(xhci
,
521 num_stream_ctxs
, &stream_info
->ctx_array_dma
,
523 if (!stream_info
->stream_ctx_array
)
525 memset(stream_info
->stream_ctx_array
, 0,
526 sizeof(struct xhci_stream_ctx
)*num_stream_ctxs
);
528 /* Allocate everything needed to free the stream rings later */
529 stream_info
->free_streams_command
=
530 xhci_alloc_command(xhci
, true, true, mem_flags
);
531 if (!stream_info
->free_streams_command
)
534 INIT_RADIX_TREE(&stream_info
->trb_address_map
, GFP_ATOMIC
);
536 /* Allocate rings for all the streams that the driver will use,
537 * and add their segment DMA addresses to the radix tree.
538 * Stream 0 is reserved.
540 for (cur_stream
= 1; cur_stream
< num_streams
; cur_stream
++) {
541 stream_info
->stream_rings
[cur_stream
] =
542 xhci_ring_alloc(xhci
, 1, true, mem_flags
);
543 cur_ring
= stream_info
->stream_rings
[cur_stream
];
546 cur_ring
->stream_id
= cur_stream
;
547 /* Set deq ptr, cycle bit, and stream context type */
548 addr
= cur_ring
->first_seg
->dma
|
549 SCT_FOR_CTX(SCT_PRI_TR
) |
550 cur_ring
->cycle_state
;
551 stream_info
->stream_ctx_array
[cur_stream
].stream_ring
= addr
;
552 xhci_dbg(xhci
, "Setting stream %d ring ptr to 0x%08llx\n",
553 cur_stream
, (unsigned long long) addr
);
555 key
= (unsigned long)
556 (cur_ring
->first_seg
->dma
>> SEGMENT_SHIFT
);
557 ret
= radix_tree_insert(&stream_info
->trb_address_map
,
560 xhci_ring_free(xhci
, cur_ring
);
561 stream_info
->stream_rings
[cur_stream
] = NULL
;
565 /* Leave the other unused stream ring pointers in the stream context
566 * array initialized to zero. This will cause the xHC to give us an
567 * error if the device asks for a stream ID we don't have setup (if it
568 * was any other way, the host controller would assume the ring is
569 * "empty" and wait forever for data to be queued to that stream ID).
572 /* Do a little test on the radix tree to make sure it returns the
575 if (xhci_test_radix_tree(xhci
, num_streams
, stream_info
))
582 for (cur_stream
= 1; cur_stream
< num_streams
; cur_stream
++) {
583 cur_ring
= stream_info
->stream_rings
[cur_stream
];
585 addr
= cur_ring
->first_seg
->dma
;
586 radix_tree_delete(&stream_info
->trb_address_map
,
587 addr
>> SEGMENT_SHIFT
);
588 xhci_ring_free(xhci
, cur_ring
);
589 stream_info
->stream_rings
[cur_stream
] = NULL
;
592 xhci_free_command(xhci
, stream_info
->free_streams_command
);
594 kfree(stream_info
->stream_rings
);
598 xhci
->cmd_ring_reserved_trbs
--;
602 * Sets the MaxPStreams field and the Linear Stream Array field.
603 * Sets the dequeue pointer to the stream context array.
605 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd
*xhci
,
606 struct xhci_ep_ctx
*ep_ctx
,
607 struct xhci_stream_info
*stream_info
)
609 u32 max_primary_streams
;
610 /* MaxPStreams is the number of stream context array entries, not the
611 * number we're actually using. Must be in 2^(MaxPstreams + 1) format.
612 * fls(0) = 0, fls(0x1) = 1, fls(0x10) = 2, fls(0x100) = 3, etc.
614 max_primary_streams
= fls(stream_info
->num_stream_ctxs
) - 2;
615 xhci_dbg(xhci
, "Setting number of stream ctx array entries to %u\n",
616 1 << (max_primary_streams
+ 1));
617 ep_ctx
->ep_info
&= ~EP_MAXPSTREAMS_MASK
;
618 ep_ctx
->ep_info
|= EP_MAXPSTREAMS(max_primary_streams
);
619 ep_ctx
->ep_info
|= EP_HAS_LSA
;
620 ep_ctx
->deq
= stream_info
->ctx_array_dma
;
624 * Sets the MaxPStreams field and the Linear Stream Array field to 0.
625 * Reinstalls the "normal" endpoint ring (at its previous dequeue mark,
626 * not at the beginning of the ring).
628 void xhci_setup_no_streams_ep_input_ctx(struct xhci_hcd
*xhci
,
629 struct xhci_ep_ctx
*ep_ctx
,
630 struct xhci_virt_ep
*ep
)
633 ep_ctx
->ep_info
&= ~EP_MAXPSTREAMS_MASK
;
634 ep_ctx
->ep_info
&= ~EP_HAS_LSA
;
635 addr
= xhci_trb_virt_to_dma(ep
->ring
->deq_seg
, ep
->ring
->dequeue
);
636 ep_ctx
->deq
= addr
| ep
->ring
->cycle_state
;
639 /* Frees all stream contexts associated with the endpoint,
641 * Caller should fix the endpoint context streams fields.
643 void xhci_free_stream_info(struct xhci_hcd
*xhci
,
644 struct xhci_stream_info
*stream_info
)
647 struct xhci_ring
*cur_ring
;
653 for (cur_stream
= 1; cur_stream
< stream_info
->num_streams
;
655 cur_ring
= stream_info
->stream_rings
[cur_stream
];
657 addr
= cur_ring
->first_seg
->dma
;
658 radix_tree_delete(&stream_info
->trb_address_map
,
659 addr
>> SEGMENT_SHIFT
);
660 xhci_ring_free(xhci
, cur_ring
);
661 stream_info
->stream_rings
[cur_stream
] = NULL
;
664 xhci_free_command(xhci
, stream_info
->free_streams_command
);
665 xhci
->cmd_ring_reserved_trbs
--;
666 if (stream_info
->stream_ctx_array
)
667 xhci_free_stream_ctx(xhci
,
668 stream_info
->num_stream_ctxs
,
669 stream_info
->stream_ctx_array
,
670 stream_info
->ctx_array_dma
);
673 kfree(stream_info
->stream_rings
);
678 /***************** Device context manipulation *************************/
680 static void xhci_init_endpoint_timer(struct xhci_hcd
*xhci
,
681 struct xhci_virt_ep
*ep
)
683 init_timer(&ep
->stop_cmd_timer
);
684 ep
->stop_cmd_timer
.data
= (unsigned long) ep
;
685 ep
->stop_cmd_timer
.function
= xhci_stop_endpoint_command_watchdog
;
689 /* All the xhci_tds in the ring's TD list should be freed at this point */
690 void xhci_free_virt_device(struct xhci_hcd
*xhci
, int slot_id
)
692 struct xhci_virt_device
*dev
;
695 /* Slot ID 0 is reserved */
696 if (slot_id
== 0 || !xhci
->devs
[slot_id
])
699 dev
= xhci
->devs
[slot_id
];
700 xhci
->dcbaa
->dev_context_ptrs
[slot_id
] = 0;
704 for (i
= 0; i
< 31; ++i
) {
705 if (dev
->eps
[i
].ring
)
706 xhci_ring_free(xhci
, dev
->eps
[i
].ring
);
707 if (dev
->eps
[i
].stream_info
)
708 xhci_free_stream_info(xhci
,
709 dev
->eps
[i
].stream_info
);
712 if (dev
->ring_cache
) {
713 for (i
= 0; i
< dev
->num_rings_cached
; i
++)
714 xhci_ring_free(xhci
, dev
->ring_cache
[i
]);
715 kfree(dev
->ring_cache
);
719 xhci_free_container_ctx(xhci
, dev
->in_ctx
);
721 xhci_free_container_ctx(xhci
, dev
->out_ctx
);
723 kfree(xhci
->devs
[slot_id
]);
724 xhci
->devs
[slot_id
] = NULL
;
727 int xhci_alloc_virt_device(struct xhci_hcd
*xhci
, int slot_id
,
728 struct usb_device
*udev
, gfp_t flags
)
730 struct xhci_virt_device
*dev
;
733 /* Slot ID 0 is reserved */
734 if (slot_id
== 0 || xhci
->devs
[slot_id
]) {
735 xhci_warn(xhci
, "Bad Slot ID %d\n", slot_id
);
739 xhci
->devs
[slot_id
] = kzalloc(sizeof(*xhci
->devs
[slot_id
]), flags
);
740 if (!xhci
->devs
[slot_id
])
742 dev
= xhci
->devs
[slot_id
];
744 /* Allocate the (output) device context that will be used in the HC. */
745 dev
->out_ctx
= xhci_alloc_container_ctx(xhci
, XHCI_CTX_TYPE_DEVICE
, flags
);
749 xhci_dbg(xhci
, "Slot %d output ctx = 0x%llx (dma)\n", slot_id
,
750 (unsigned long long)dev
->out_ctx
->dma
);
752 /* Allocate the (input) device context for address device command */
753 dev
->in_ctx
= xhci_alloc_container_ctx(xhci
, XHCI_CTX_TYPE_INPUT
, flags
);
757 xhci_dbg(xhci
, "Slot %d input ctx = 0x%llx (dma)\n", slot_id
,
758 (unsigned long long)dev
->in_ctx
->dma
);
760 /* Initialize the cancellation list and watchdog timers for each ep */
761 for (i
= 0; i
< 31; i
++) {
762 xhci_init_endpoint_timer(xhci
, &dev
->eps
[i
]);
763 INIT_LIST_HEAD(&dev
->eps
[i
].cancelled_td_list
);
766 /* Allocate endpoint 0 ring */
767 dev
->eps
[0].ring
= xhci_ring_alloc(xhci
, 1, true, flags
);
768 if (!dev
->eps
[0].ring
)
771 /* Allocate pointers to the ring cache */
772 dev
->ring_cache
= kzalloc(
773 sizeof(struct xhci_ring
*)*XHCI_MAX_RINGS_CACHED
,
775 if (!dev
->ring_cache
)
777 dev
->num_rings_cached
= 0;
779 init_completion(&dev
->cmd_completion
);
780 INIT_LIST_HEAD(&dev
->cmd_list
);
783 /* Point to output device context in dcbaa. */
784 xhci
->dcbaa
->dev_context_ptrs
[slot_id
] = dev
->out_ctx
->dma
;
785 xhci_dbg(xhci
, "Set slot id %d dcbaa entry %p to 0x%llx\n",
787 &xhci
->dcbaa
->dev_context_ptrs
[slot_id
],
788 (unsigned long long) xhci
->dcbaa
->dev_context_ptrs
[slot_id
]);
792 xhci_free_virt_device(xhci
, slot_id
);
796 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd
*xhci
,
797 struct usb_device
*udev
)
799 struct xhci_virt_device
*virt_dev
;
800 struct xhci_ep_ctx
*ep0_ctx
;
801 struct xhci_ring
*ep_ring
;
803 virt_dev
= xhci
->devs
[udev
->slot_id
];
804 ep0_ctx
= xhci_get_ep_ctx(xhci
, virt_dev
->in_ctx
, 0);
805 ep_ring
= virt_dev
->eps
[0].ring
;
807 * FIXME we don't keep track of the dequeue pointer very well after a
808 * Set TR dequeue pointer, so we're setting the dequeue pointer of the
809 * host to our enqueue pointer. This should only be called after a
810 * configured device has reset, so all control transfers should have
811 * been completed or cancelled before the reset.
813 ep0_ctx
->deq
= xhci_trb_virt_to_dma(ep_ring
->enq_seg
, ep_ring
->enqueue
);
814 ep0_ctx
->deq
|= ep_ring
->cycle_state
;
818 * The xHCI roothub may have ports of differing speeds in any order in the port
819 * status registers. xhci->port_array provides an array of the port speed for
820 * each offset into the port status registers.
822 * The xHCI hardware wants to know the roothub port number that the USB device
823 * is attached to (or the roothub port its ancestor hub is attached to). All we
824 * know is the index of that port under either the USB 2.0 or the USB 3.0
825 * roothub, but that doesn't give us the real index into the HW port status
826 * registers. Scan through the xHCI roothub port array, looking for the Nth
827 * entry of the correct port speed. Return the port number of that entry.
829 static u32
xhci_find_real_port_number(struct xhci_hcd
*xhci
,
830 struct usb_device
*udev
)
832 struct usb_device
*top_dev
;
833 unsigned int num_similar_speed_ports
;
834 unsigned int faked_port_num
;
837 for (top_dev
= udev
; top_dev
->parent
&& top_dev
->parent
->parent
;
838 top_dev
= top_dev
->parent
)
839 /* Found device below root hub */;
840 faked_port_num
= top_dev
->portnum
;
841 for (i
= 0, num_similar_speed_ports
= 0;
842 i
< HCS_MAX_PORTS(xhci
->hcs_params1
); i
++) {
843 u8 port_speed
= xhci
->port_array
[i
];
846 * Skip ports that don't have known speeds, or have duplicate
847 * Extended Capabilities port speed entries.
849 if (port_speed
== 0 || port_speed
== DUPLICATE_ENTRY
)
853 * USB 3.0 ports are always under a USB 3.0 hub. USB 2.0 and
854 * 1.1 ports are under the USB 2.0 hub. If the port speed
855 * matches the device speed, it's a similar speed port.
857 if ((port_speed
== 0x03) == (udev
->speed
== USB_SPEED_SUPER
))
858 num_similar_speed_ports
++;
859 if (num_similar_speed_ports
== faked_port_num
)
860 /* Roothub ports are numbered from 1 to N */
866 /* Setup an xHCI virtual device for a Set Address command */
867 int xhci_setup_addressable_virt_dev(struct xhci_hcd
*xhci
, struct usb_device
*udev
)
869 struct xhci_virt_device
*dev
;
870 struct xhci_ep_ctx
*ep0_ctx
;
871 struct xhci_slot_ctx
*slot_ctx
;
872 struct xhci_input_control_ctx
*ctrl_ctx
;
874 struct usb_device
*top_dev
;
876 dev
= xhci
->devs
[udev
->slot_id
];
877 /* Slot ID 0 is reserved */
878 if (udev
->slot_id
== 0 || !dev
) {
879 xhci_warn(xhci
, "Slot ID %d is not assigned to this device\n",
883 ep0_ctx
= xhci_get_ep_ctx(xhci
, dev
->in_ctx
, 0);
884 ctrl_ctx
= xhci_get_input_control_ctx(xhci
, dev
->in_ctx
);
885 slot_ctx
= xhci_get_slot_ctx(xhci
, dev
->in_ctx
);
887 /* 2) New slot context and endpoint 0 context are valid*/
888 ctrl_ctx
->add_flags
= SLOT_FLAG
| EP0_FLAG
;
890 /* 3) Only the control endpoint is valid - one endpoint context */
891 slot_ctx
->dev_info
|= LAST_CTX(1);
893 slot_ctx
->dev_info
|= (u32
) udev
->route
;
894 switch (udev
->speed
) {
895 case USB_SPEED_SUPER
:
896 slot_ctx
->dev_info
|= (u32
) SLOT_SPEED_SS
;
899 slot_ctx
->dev_info
|= (u32
) SLOT_SPEED_HS
;
902 slot_ctx
->dev_info
|= (u32
) SLOT_SPEED_FS
;
905 slot_ctx
->dev_info
|= (u32
) SLOT_SPEED_LS
;
907 case USB_SPEED_WIRELESS
:
908 xhci_dbg(xhci
, "FIXME xHCI doesn't support wireless speeds\n");
912 /* Speed was set earlier, this shouldn't happen. */
915 /* Find the root hub port this device is under */
916 port_num
= xhci_find_real_port_number(xhci
, udev
);
919 slot_ctx
->dev_info2
|= (u32
) ROOT_HUB_PORT(port_num
);
920 /* Set the port number in the virtual_device to the faked port number */
921 for (top_dev
= udev
; top_dev
->parent
&& top_dev
->parent
->parent
;
922 top_dev
= top_dev
->parent
)
923 /* Found device below root hub */;
924 dev
->port
= top_dev
->portnum
;
925 xhci_dbg(xhci
, "Set root hub portnum to %d\n", port_num
);
926 xhci_dbg(xhci
, "Set fake root hub portnum to %d\n", dev
->port
);
928 /* Is this a LS/FS device under an external HS hub? */
929 if (udev
->tt
&& udev
->tt
->hub
->parent
) {
930 slot_ctx
->tt_info
= udev
->tt
->hub
->slot_id
;
931 slot_ctx
->tt_info
|= udev
->ttport
<< 8;
933 slot_ctx
->dev_info
|= DEV_MTT
;
935 xhci_dbg(xhci
, "udev->tt = %p\n", udev
->tt
);
936 xhci_dbg(xhci
, "udev->ttport = 0x%x\n", udev
->ttport
);
938 /* Step 4 - ring already allocated */
940 ep0_ctx
->ep_info2
= EP_TYPE(CTRL_EP
);
942 * XXX: Not sure about wireless USB devices.
944 switch (udev
->speed
) {
945 case USB_SPEED_SUPER
:
946 ep0_ctx
->ep_info2
|= MAX_PACKET(512);
949 /* USB core guesses at a 64-byte max packet first for FS devices */
951 ep0_ctx
->ep_info2
|= MAX_PACKET(64);
954 ep0_ctx
->ep_info2
|= MAX_PACKET(8);
956 case USB_SPEED_WIRELESS
:
957 xhci_dbg(xhci
, "FIXME xHCI doesn't support wireless speeds\n");
964 /* EP 0 can handle "burst" sizes of 1, so Max Burst Size field is 0 */
965 ep0_ctx
->ep_info2
|= MAX_BURST(0);
966 ep0_ctx
->ep_info2
|= ERROR_COUNT(3);
969 dev
->eps
[0].ring
->first_seg
->dma
;
970 ep0_ctx
->deq
|= dev
->eps
[0].ring
->cycle_state
;
972 /* Steps 7 and 8 were done in xhci_alloc_virt_device() */
977 /* Return the polling or NAK interval.
979 * The polling interval is expressed in "microframes". If xHCI's Interval field
980 * is set to N, it will service the endpoint every 2^(Interval)*125us.
982 * The NAK interval is one NAK per 1 to 255 microframes, or no NAKs if interval
985 static inline unsigned int xhci_get_endpoint_interval(struct usb_device
*udev
,
986 struct usb_host_endpoint
*ep
)
988 unsigned int interval
= 0;
990 switch (udev
->speed
) {
993 if (usb_endpoint_xfer_control(&ep
->desc
) ||
994 usb_endpoint_xfer_bulk(&ep
->desc
))
995 interval
= ep
->desc
.bInterval
;
996 /* Fall through - SS and HS isoc/int have same decoding */
997 case USB_SPEED_SUPER
:
998 if (usb_endpoint_xfer_int(&ep
->desc
) ||
999 usb_endpoint_xfer_isoc(&ep
->desc
)) {
1000 if (ep
->desc
.bInterval
== 0)
1003 interval
= ep
->desc
.bInterval
- 1;
1006 if (interval
!= ep
->desc
.bInterval
+ 1)
1007 dev_warn(&udev
->dev
, "ep %#x - rounding interval to %d microframes\n",
1008 ep
->desc
.bEndpointAddress
, 1 << interval
);
1011 /* Convert bInterval (in 1-255 frames) to microframes and round down to
1012 * nearest power of 2.
1014 case USB_SPEED_FULL
:
1016 if (usb_endpoint_xfer_int(&ep
->desc
) ||
1017 usb_endpoint_xfer_isoc(&ep
->desc
)) {
1018 interval
= fls(8*ep
->desc
.bInterval
) - 1;
1023 if ((1 << interval
) != 8*ep
->desc
.bInterval
)
1024 dev_warn(&udev
->dev
,
1025 "ep %#x - rounding interval"
1026 " to %d microframes, "
1027 "ep desc says %d microframes\n",
1028 ep
->desc
.bEndpointAddress
,
1030 8*ep
->desc
.bInterval
);
1036 return EP_INTERVAL(interval
);
1039 /* The "Mult" field in the endpoint context is only set for SuperSpeed isoc eps.
1040 * High speed endpoint descriptors can define "the number of additional
1041 * transaction opportunities per microframe", but that goes in the Max Burst
1042 * endpoint context field.
1044 static inline u32
xhci_get_endpoint_mult(struct usb_device
*udev
,
1045 struct usb_host_endpoint
*ep
)
1047 if (udev
->speed
!= USB_SPEED_SUPER
||
1048 !usb_endpoint_xfer_isoc(&ep
->desc
))
1050 return ep
->ss_ep_comp
.bmAttributes
;
1053 static inline u32
xhci_get_endpoint_type(struct usb_device
*udev
,
1054 struct usb_host_endpoint
*ep
)
1059 in
= usb_endpoint_dir_in(&ep
->desc
);
1060 if (usb_endpoint_xfer_control(&ep
->desc
)) {
1061 type
= EP_TYPE(CTRL_EP
);
1062 } else if (usb_endpoint_xfer_bulk(&ep
->desc
)) {
1064 type
= EP_TYPE(BULK_IN_EP
);
1066 type
= EP_TYPE(BULK_OUT_EP
);
1067 } else if (usb_endpoint_xfer_isoc(&ep
->desc
)) {
1069 type
= EP_TYPE(ISOC_IN_EP
);
1071 type
= EP_TYPE(ISOC_OUT_EP
);
1072 } else if (usb_endpoint_xfer_int(&ep
->desc
)) {
1074 type
= EP_TYPE(INT_IN_EP
);
1076 type
= EP_TYPE(INT_OUT_EP
);
1083 /* Return the maximum endpoint service interval time (ESIT) payload.
1084 * Basically, this is the maxpacket size, multiplied by the burst size
1087 static inline u32
xhci_get_max_esit_payload(struct xhci_hcd
*xhci
,
1088 struct usb_device
*udev
,
1089 struct usb_host_endpoint
*ep
)
1094 /* Only applies for interrupt or isochronous endpoints */
1095 if (usb_endpoint_xfer_control(&ep
->desc
) ||
1096 usb_endpoint_xfer_bulk(&ep
->desc
))
1099 if (udev
->speed
== USB_SPEED_SUPER
)
1100 return ep
->ss_ep_comp
.wBytesPerInterval
;
1102 max_packet
= GET_MAX_PACKET(ep
->desc
.wMaxPacketSize
);
1103 max_burst
= (ep
->desc
.wMaxPacketSize
& 0x1800) >> 11;
1104 /* A 0 in max burst means 1 transfer per ESIT */
1105 return max_packet
* (max_burst
+ 1);
1108 /* Set up an endpoint with one ring segment. Do not allocate stream rings.
1109 * Drivers will have to call usb_alloc_streams() to do that.
1111 int xhci_endpoint_init(struct xhci_hcd
*xhci
,
1112 struct xhci_virt_device
*virt_dev
,
1113 struct usb_device
*udev
,
1114 struct usb_host_endpoint
*ep
,
1117 unsigned int ep_index
;
1118 struct xhci_ep_ctx
*ep_ctx
;
1119 struct xhci_ring
*ep_ring
;
1120 unsigned int max_packet
;
1121 unsigned int max_burst
;
1122 u32 max_esit_payload
;
1124 ep_index
= xhci_get_endpoint_index(&ep
->desc
);
1125 ep_ctx
= xhci_get_ep_ctx(xhci
, virt_dev
->in_ctx
, ep_index
);
1127 /* Set up the endpoint ring */
1129 * Isochronous endpoint ring needs bigger size because one isoc URB
1130 * carries multiple packets and it will insert multiple tds to the
1132 * This should be replaced with dynamic ring resizing in the future.
1134 if (usb_endpoint_xfer_isoc(&ep
->desc
))
1135 virt_dev
->eps
[ep_index
].new_ring
=
1136 xhci_ring_alloc(xhci
, 8, true, mem_flags
);
1138 virt_dev
->eps
[ep_index
].new_ring
=
1139 xhci_ring_alloc(xhci
, 1, true, mem_flags
);
1140 if (!virt_dev
->eps
[ep_index
].new_ring
) {
1141 /* Attempt to use the ring cache */
1142 if (virt_dev
->num_rings_cached
== 0)
1144 virt_dev
->eps
[ep_index
].new_ring
=
1145 virt_dev
->ring_cache
[virt_dev
->num_rings_cached
];
1146 virt_dev
->ring_cache
[virt_dev
->num_rings_cached
] = NULL
;
1147 virt_dev
->num_rings_cached
--;
1148 xhci_reinit_cached_ring(xhci
, virt_dev
->eps
[ep_index
].new_ring
);
1150 virt_dev
->eps
[ep_index
].skip
= false;
1151 ep_ring
= virt_dev
->eps
[ep_index
].new_ring
;
1152 ep_ctx
->deq
= ep_ring
->first_seg
->dma
| ep_ring
->cycle_state
;
1154 ep_ctx
->ep_info
= xhci_get_endpoint_interval(udev
, ep
);
1155 ep_ctx
->ep_info
|= EP_MULT(xhci_get_endpoint_mult(udev
, ep
));
1157 /* FIXME dig Mult and streams info out of ep companion desc */
1159 /* Allow 3 retries for everything but isoc;
1160 * error count = 0 means infinite retries.
1162 if (!usb_endpoint_xfer_isoc(&ep
->desc
))
1163 ep_ctx
->ep_info2
= ERROR_COUNT(3);
1165 ep_ctx
->ep_info2
= ERROR_COUNT(1);
1167 ep_ctx
->ep_info2
|= xhci_get_endpoint_type(udev
, ep
);
1169 /* Set the max packet size and max burst */
1170 switch (udev
->speed
) {
1171 case USB_SPEED_SUPER
:
1172 max_packet
= ep
->desc
.wMaxPacketSize
;
1173 ep_ctx
->ep_info2
|= MAX_PACKET(max_packet
);
1174 /* dig out max burst from ep companion desc */
1175 max_packet
= ep
->ss_ep_comp
.bMaxBurst
;
1177 xhci_warn(xhci
, "WARN no SS endpoint bMaxBurst\n");
1178 ep_ctx
->ep_info2
|= MAX_BURST(max_packet
);
1180 case USB_SPEED_HIGH
:
1181 /* bits 11:12 specify the number of additional transaction
1182 * opportunities per microframe (USB 2.0, section 9.6.6)
1184 if (usb_endpoint_xfer_isoc(&ep
->desc
) ||
1185 usb_endpoint_xfer_int(&ep
->desc
)) {
1186 max_burst
= (ep
->desc
.wMaxPacketSize
& 0x1800) >> 11;
1187 ep_ctx
->ep_info2
|= MAX_BURST(max_burst
);
1190 case USB_SPEED_FULL
:
1192 max_packet
= GET_MAX_PACKET(ep
->desc
.wMaxPacketSize
);
1193 ep_ctx
->ep_info2
|= MAX_PACKET(max_packet
);
1198 max_esit_payload
= xhci_get_max_esit_payload(xhci
, udev
, ep
);
1199 ep_ctx
->tx_info
= MAX_ESIT_PAYLOAD_FOR_EP(max_esit_payload
);
1202 * XXX no idea how to calculate the average TRB buffer length for bulk
1203 * endpoints, as the driver gives us no clue how big each scatter gather
1204 * list entry (or buffer) is going to be.
1206 * For isochronous and interrupt endpoints, we set it to the max
1207 * available, until we have new API in the USB core to allow drivers to
1208 * declare how much bandwidth they actually need.
1210 * Normally, it would be calculated by taking the total of the buffer
1211 * lengths in the TD and then dividing by the number of TRBs in a TD,
1212 * including link TRBs, No-op TRBs, and Event data TRBs. Since we don't
1213 * use Event Data TRBs, and we don't chain in a link TRB on short
1214 * transfers, we're basically dividing by 1.
1216 ep_ctx
->tx_info
|= AVG_TRB_LENGTH_FOR_EP(max_esit_payload
);
1218 /* FIXME Debug endpoint context */
1222 void xhci_endpoint_zero(struct xhci_hcd
*xhci
,
1223 struct xhci_virt_device
*virt_dev
,
1224 struct usb_host_endpoint
*ep
)
1226 unsigned int ep_index
;
1227 struct xhci_ep_ctx
*ep_ctx
;
1229 ep_index
= xhci_get_endpoint_index(&ep
->desc
);
1230 ep_ctx
= xhci_get_ep_ctx(xhci
, virt_dev
->in_ctx
, ep_index
);
1232 ep_ctx
->ep_info
= 0;
1233 ep_ctx
->ep_info2
= 0;
1235 ep_ctx
->tx_info
= 0;
1236 /* Don't free the endpoint ring until the set interface or configuration
1241 /* Copy output xhci_ep_ctx to the input xhci_ep_ctx copy.
1242 * Useful when you want to change one particular aspect of the endpoint and then
1243 * issue a configure endpoint command.
1245 void xhci_endpoint_copy(struct xhci_hcd
*xhci
,
1246 struct xhci_container_ctx
*in_ctx
,
1247 struct xhci_container_ctx
*out_ctx
,
1248 unsigned int ep_index
)
1250 struct xhci_ep_ctx
*out_ep_ctx
;
1251 struct xhci_ep_ctx
*in_ep_ctx
;
1253 out_ep_ctx
= xhci_get_ep_ctx(xhci
, out_ctx
, ep_index
);
1254 in_ep_ctx
= xhci_get_ep_ctx(xhci
, in_ctx
, ep_index
);
1256 in_ep_ctx
->ep_info
= out_ep_ctx
->ep_info
;
1257 in_ep_ctx
->ep_info2
= out_ep_ctx
->ep_info2
;
1258 in_ep_ctx
->deq
= out_ep_ctx
->deq
;
1259 in_ep_ctx
->tx_info
= out_ep_ctx
->tx_info
;
1262 /* Copy output xhci_slot_ctx to the input xhci_slot_ctx.
1263 * Useful when you want to change one particular aspect of the endpoint and then
1264 * issue a configure endpoint command. Only the context entries field matters,
1265 * but we'll copy the whole thing anyway.
1267 void xhci_slot_copy(struct xhci_hcd
*xhci
,
1268 struct xhci_container_ctx
*in_ctx
,
1269 struct xhci_container_ctx
*out_ctx
)
1271 struct xhci_slot_ctx
*in_slot_ctx
;
1272 struct xhci_slot_ctx
*out_slot_ctx
;
1274 in_slot_ctx
= xhci_get_slot_ctx(xhci
, in_ctx
);
1275 out_slot_ctx
= xhci_get_slot_ctx(xhci
, out_ctx
);
1277 in_slot_ctx
->dev_info
= out_slot_ctx
->dev_info
;
1278 in_slot_ctx
->dev_info2
= out_slot_ctx
->dev_info2
;
1279 in_slot_ctx
->tt_info
= out_slot_ctx
->tt_info
;
1280 in_slot_ctx
->dev_state
= out_slot_ctx
->dev_state
;
1283 /* Set up the scratchpad buffer array and scratchpad buffers, if needed. */
1284 static int scratchpad_alloc(struct xhci_hcd
*xhci
, gfp_t flags
)
1287 struct device
*dev
= xhci_to_hcd(xhci
)->self
.controller
;
1288 int num_sp
= HCS_MAX_SCRATCHPAD(xhci
->hcs_params2
);
1290 xhci_dbg(xhci
, "Allocating %d scratchpad buffers\n", num_sp
);
1295 xhci
->scratchpad
= kzalloc(sizeof(*xhci
->scratchpad
), flags
);
1296 if (!xhci
->scratchpad
)
1299 xhci
->scratchpad
->sp_array
=
1300 pci_alloc_consistent(to_pci_dev(dev
),
1301 num_sp
* sizeof(u64
),
1302 &xhci
->scratchpad
->sp_dma
);
1303 if (!xhci
->scratchpad
->sp_array
)
1306 xhci
->scratchpad
->sp_buffers
= kzalloc(sizeof(void *) * num_sp
, flags
);
1307 if (!xhci
->scratchpad
->sp_buffers
)
1310 xhci
->scratchpad
->sp_dma_buffers
=
1311 kzalloc(sizeof(dma_addr_t
) * num_sp
, flags
);
1313 if (!xhci
->scratchpad
->sp_dma_buffers
)
1316 xhci
->dcbaa
->dev_context_ptrs
[0] = xhci
->scratchpad
->sp_dma
;
1317 for (i
= 0; i
< num_sp
; i
++) {
1319 void *buf
= pci_alloc_consistent(to_pci_dev(dev
),
1320 xhci
->page_size
, &dma
);
1324 xhci
->scratchpad
->sp_array
[i
] = dma
;
1325 xhci
->scratchpad
->sp_buffers
[i
] = buf
;
1326 xhci
->scratchpad
->sp_dma_buffers
[i
] = dma
;
1332 for (i
= i
- 1; i
>= 0; i
--) {
1333 pci_free_consistent(to_pci_dev(dev
), xhci
->page_size
,
1334 xhci
->scratchpad
->sp_buffers
[i
],
1335 xhci
->scratchpad
->sp_dma_buffers
[i
]);
1337 kfree(xhci
->scratchpad
->sp_dma_buffers
);
1340 kfree(xhci
->scratchpad
->sp_buffers
);
1343 pci_free_consistent(to_pci_dev(dev
), num_sp
* sizeof(u64
),
1344 xhci
->scratchpad
->sp_array
,
1345 xhci
->scratchpad
->sp_dma
);
1348 kfree(xhci
->scratchpad
);
1349 xhci
->scratchpad
= NULL
;
1355 static void scratchpad_free(struct xhci_hcd
*xhci
)
1359 struct pci_dev
*pdev
= to_pci_dev(xhci_to_hcd(xhci
)->self
.controller
);
1361 if (!xhci
->scratchpad
)
1364 num_sp
= HCS_MAX_SCRATCHPAD(xhci
->hcs_params2
);
1366 for (i
= 0; i
< num_sp
; i
++) {
1367 pci_free_consistent(pdev
, xhci
->page_size
,
1368 xhci
->scratchpad
->sp_buffers
[i
],
1369 xhci
->scratchpad
->sp_dma_buffers
[i
]);
1371 kfree(xhci
->scratchpad
->sp_dma_buffers
);
1372 kfree(xhci
->scratchpad
->sp_buffers
);
1373 pci_free_consistent(pdev
, num_sp
* sizeof(u64
),
1374 xhci
->scratchpad
->sp_array
,
1375 xhci
->scratchpad
->sp_dma
);
1376 kfree(xhci
->scratchpad
);
1377 xhci
->scratchpad
= NULL
;
1380 struct xhci_command
*xhci_alloc_command(struct xhci_hcd
*xhci
,
1381 bool allocate_in_ctx
, bool allocate_completion
,
1384 struct xhci_command
*command
;
1386 command
= kzalloc(sizeof(*command
), mem_flags
);
1390 if (allocate_in_ctx
) {
1392 xhci_alloc_container_ctx(xhci
, XHCI_CTX_TYPE_INPUT
,
1394 if (!command
->in_ctx
) {
1400 if (allocate_completion
) {
1401 command
->completion
=
1402 kzalloc(sizeof(struct completion
), mem_flags
);
1403 if (!command
->completion
) {
1404 xhci_free_container_ctx(xhci
, command
->in_ctx
);
1408 init_completion(command
->completion
);
1411 command
->status
= 0;
1412 INIT_LIST_HEAD(&command
->cmd_list
);
1416 void xhci_urb_free_priv(struct xhci_hcd
*xhci
, struct urb_priv
*urb_priv
)
1423 last
= urb_priv
->length
- 1;
1426 for (i
= 0; i
<= last
; i
++)
1427 kfree(urb_priv
->td
[i
]);
1432 void xhci_free_command(struct xhci_hcd
*xhci
,
1433 struct xhci_command
*command
)
1435 xhci_free_container_ctx(xhci
,
1437 kfree(command
->completion
);
1441 void xhci_mem_cleanup(struct xhci_hcd
*xhci
)
1443 struct pci_dev
*pdev
= to_pci_dev(xhci_to_hcd(xhci
)->self
.controller
);
1447 /* Free the Event Ring Segment Table and the actual Event Ring */
1449 xhci_writel(xhci
, 0, &xhci
->ir_set
->erst_size
);
1450 xhci_write_64(xhci
, 0, &xhci
->ir_set
->erst_base
);
1451 xhci_write_64(xhci
, 0, &xhci
->ir_set
->erst_dequeue
);
1453 size
= sizeof(struct xhci_erst_entry
)*(xhci
->erst
.num_entries
);
1454 if (xhci
->erst
.entries
)
1455 pci_free_consistent(pdev
, size
,
1456 xhci
->erst
.entries
, xhci
->erst
.erst_dma_addr
);
1457 xhci
->erst
.entries
= NULL
;
1458 xhci_dbg(xhci
, "Freed ERST\n");
1459 if (xhci
->event_ring
)
1460 xhci_ring_free(xhci
, xhci
->event_ring
);
1461 xhci
->event_ring
= NULL
;
1462 xhci_dbg(xhci
, "Freed event ring\n");
1464 xhci_write_64(xhci
, 0, &xhci
->op_regs
->cmd_ring
);
1466 xhci_ring_free(xhci
, xhci
->cmd_ring
);
1467 xhci
->cmd_ring
= NULL
;
1468 xhci_dbg(xhci
, "Freed command ring\n");
1470 for (i
= 1; i
< MAX_HC_SLOTS
; ++i
)
1471 xhci_free_virt_device(xhci
, i
);
1473 if (xhci
->segment_pool
)
1474 dma_pool_destroy(xhci
->segment_pool
);
1475 xhci
->segment_pool
= NULL
;
1476 xhci_dbg(xhci
, "Freed segment pool\n");
1478 if (xhci
->device_pool
)
1479 dma_pool_destroy(xhci
->device_pool
);
1480 xhci
->device_pool
= NULL
;
1481 xhci_dbg(xhci
, "Freed device context pool\n");
1483 if (xhci
->small_streams_pool
)
1484 dma_pool_destroy(xhci
->small_streams_pool
);
1485 xhci
->small_streams_pool
= NULL
;
1486 xhci_dbg(xhci
, "Freed small stream array pool\n");
1488 if (xhci
->medium_streams_pool
)
1489 dma_pool_destroy(xhci
->medium_streams_pool
);
1490 xhci
->medium_streams_pool
= NULL
;
1491 xhci_dbg(xhci
, "Freed medium stream array pool\n");
1493 xhci_write_64(xhci
, 0, &xhci
->op_regs
->dcbaa_ptr
);
1495 pci_free_consistent(pdev
, sizeof(*xhci
->dcbaa
),
1496 xhci
->dcbaa
, xhci
->dcbaa
->dma
);
1499 scratchpad_free(xhci
);
1501 xhci
->num_usb2_ports
= 0;
1502 xhci
->num_usb3_ports
= 0;
1503 kfree(xhci
->usb2_ports
);
1504 kfree(xhci
->usb3_ports
);
1505 kfree(xhci
->port_array
);
1507 xhci
->page_size
= 0;
1508 xhci
->page_shift
= 0;
1509 xhci
->bus_state
[0].bus_suspended
= 0;
1510 xhci
->bus_state
[1].bus_suspended
= 0;
1513 static int xhci_test_trb_in_td(struct xhci_hcd
*xhci
,
1514 struct xhci_segment
*input_seg
,
1515 union xhci_trb
*start_trb
,
1516 union xhci_trb
*end_trb
,
1517 dma_addr_t input_dma
,
1518 struct xhci_segment
*result_seg
,
1519 char *test_name
, int test_number
)
1521 unsigned long long start_dma
;
1522 unsigned long long end_dma
;
1523 struct xhci_segment
*seg
;
1525 start_dma
= xhci_trb_virt_to_dma(input_seg
, start_trb
);
1526 end_dma
= xhci_trb_virt_to_dma(input_seg
, end_trb
);
1528 seg
= trb_in_td(input_seg
, start_trb
, end_trb
, input_dma
);
1529 if (seg
!= result_seg
) {
1530 xhci_warn(xhci
, "WARN: %s TRB math test %d failed!\n",
1531 test_name
, test_number
);
1532 xhci_warn(xhci
, "Tested TRB math w/ seg %p and "
1533 "input DMA 0x%llx\n",
1535 (unsigned long long) input_dma
);
1536 xhci_warn(xhci
, "starting TRB %p (0x%llx DMA), "
1537 "ending TRB %p (0x%llx DMA)\n",
1538 start_trb
, start_dma
,
1540 xhci_warn(xhci
, "Expected seg %p, got seg %p\n",
1547 /* TRB math checks for xhci_trb_in_td(), using the command and event rings. */
1548 static int xhci_check_trb_in_td_math(struct xhci_hcd
*xhci
, gfp_t mem_flags
)
1551 dma_addr_t input_dma
;
1552 struct xhci_segment
*result_seg
;
1553 } simple_test_vector
[] = {
1554 /* A zeroed DMA field should fail */
1556 /* One TRB before the ring start should fail */
1557 { xhci
->event_ring
->first_seg
->dma
- 16, NULL
},
1558 /* One byte before the ring start should fail */
1559 { xhci
->event_ring
->first_seg
->dma
- 1, NULL
},
1560 /* Starting TRB should succeed */
1561 { xhci
->event_ring
->first_seg
->dma
, xhci
->event_ring
->first_seg
},
1562 /* Ending TRB should succeed */
1563 { xhci
->event_ring
->first_seg
->dma
+ (TRBS_PER_SEGMENT
- 1)*16,
1564 xhci
->event_ring
->first_seg
},
1565 /* One byte after the ring end should fail */
1566 { xhci
->event_ring
->first_seg
->dma
+ (TRBS_PER_SEGMENT
- 1)*16 + 1, NULL
},
1567 /* One TRB after the ring end should fail */
1568 { xhci
->event_ring
->first_seg
->dma
+ (TRBS_PER_SEGMENT
)*16, NULL
},
1569 /* An address of all ones should fail */
1570 { (dma_addr_t
) (~0), NULL
},
1573 struct xhci_segment
*input_seg
;
1574 union xhci_trb
*start_trb
;
1575 union xhci_trb
*end_trb
;
1576 dma_addr_t input_dma
;
1577 struct xhci_segment
*result_seg
;
1578 } complex_test_vector
[] = {
1579 /* Test feeding a valid DMA address from a different ring */
1580 { .input_seg
= xhci
->event_ring
->first_seg
,
1581 .start_trb
= xhci
->event_ring
->first_seg
->trbs
,
1582 .end_trb
= &xhci
->event_ring
->first_seg
->trbs
[TRBS_PER_SEGMENT
- 1],
1583 .input_dma
= xhci
->cmd_ring
->first_seg
->dma
,
1586 /* Test feeding a valid end TRB from a different ring */
1587 { .input_seg
= xhci
->event_ring
->first_seg
,
1588 .start_trb
= xhci
->event_ring
->first_seg
->trbs
,
1589 .end_trb
= &xhci
->cmd_ring
->first_seg
->trbs
[TRBS_PER_SEGMENT
- 1],
1590 .input_dma
= xhci
->cmd_ring
->first_seg
->dma
,
1593 /* Test feeding a valid start and end TRB from a different ring */
1594 { .input_seg
= xhci
->event_ring
->first_seg
,
1595 .start_trb
= xhci
->cmd_ring
->first_seg
->trbs
,
1596 .end_trb
= &xhci
->cmd_ring
->first_seg
->trbs
[TRBS_PER_SEGMENT
- 1],
1597 .input_dma
= xhci
->cmd_ring
->first_seg
->dma
,
1600 /* TRB in this ring, but after this TD */
1601 { .input_seg
= xhci
->event_ring
->first_seg
,
1602 .start_trb
= &xhci
->event_ring
->first_seg
->trbs
[0],
1603 .end_trb
= &xhci
->event_ring
->first_seg
->trbs
[3],
1604 .input_dma
= xhci
->event_ring
->first_seg
->dma
+ 4*16,
1607 /* TRB in this ring, but before this TD */
1608 { .input_seg
= xhci
->event_ring
->first_seg
,
1609 .start_trb
= &xhci
->event_ring
->first_seg
->trbs
[3],
1610 .end_trb
= &xhci
->event_ring
->first_seg
->trbs
[6],
1611 .input_dma
= xhci
->event_ring
->first_seg
->dma
+ 2*16,
1614 /* TRB in this ring, but after this wrapped TD */
1615 { .input_seg
= xhci
->event_ring
->first_seg
,
1616 .start_trb
= &xhci
->event_ring
->first_seg
->trbs
[TRBS_PER_SEGMENT
- 3],
1617 .end_trb
= &xhci
->event_ring
->first_seg
->trbs
[1],
1618 .input_dma
= xhci
->event_ring
->first_seg
->dma
+ 2*16,
1621 /* TRB in this ring, but before this wrapped TD */
1622 { .input_seg
= xhci
->event_ring
->first_seg
,
1623 .start_trb
= &xhci
->event_ring
->first_seg
->trbs
[TRBS_PER_SEGMENT
- 3],
1624 .end_trb
= &xhci
->event_ring
->first_seg
->trbs
[1],
1625 .input_dma
= xhci
->event_ring
->first_seg
->dma
+ (TRBS_PER_SEGMENT
- 4)*16,
1628 /* TRB not in this ring, and we have a wrapped TD */
1629 { .input_seg
= xhci
->event_ring
->first_seg
,
1630 .start_trb
= &xhci
->event_ring
->first_seg
->trbs
[TRBS_PER_SEGMENT
- 3],
1631 .end_trb
= &xhci
->event_ring
->first_seg
->trbs
[1],
1632 .input_dma
= xhci
->cmd_ring
->first_seg
->dma
+ 2*16,
1637 unsigned int num_tests
;
1640 num_tests
= ARRAY_SIZE(simple_test_vector
);
1641 for (i
= 0; i
< num_tests
; i
++) {
1642 ret
= xhci_test_trb_in_td(xhci
,
1643 xhci
->event_ring
->first_seg
,
1644 xhci
->event_ring
->first_seg
->trbs
,
1645 &xhci
->event_ring
->first_seg
->trbs
[TRBS_PER_SEGMENT
- 1],
1646 simple_test_vector
[i
].input_dma
,
1647 simple_test_vector
[i
].result_seg
,
1653 num_tests
= ARRAY_SIZE(complex_test_vector
);
1654 for (i
= 0; i
< num_tests
; i
++) {
1655 ret
= xhci_test_trb_in_td(xhci
,
1656 complex_test_vector
[i
].input_seg
,
1657 complex_test_vector
[i
].start_trb
,
1658 complex_test_vector
[i
].end_trb
,
1659 complex_test_vector
[i
].input_dma
,
1660 complex_test_vector
[i
].result_seg
,
1665 xhci_dbg(xhci
, "TRB math tests passed.\n");
1669 static void xhci_set_hc_event_deq(struct xhci_hcd
*xhci
)
1674 deq
= xhci_trb_virt_to_dma(xhci
->event_ring
->deq_seg
,
1675 xhci
->event_ring
->dequeue
);
1676 if (deq
== 0 && !in_interrupt())
1677 xhci_warn(xhci
, "WARN something wrong with SW event ring "
1679 /* Update HC event ring dequeue pointer */
1680 temp
= xhci_read_64(xhci
, &xhci
->ir_set
->erst_dequeue
);
1681 temp
&= ERST_PTR_MASK
;
1682 /* Don't clear the EHB bit (which is RW1C) because
1683 * there might be more events to service.
1686 xhci_dbg(xhci
, "// Write event ring dequeue pointer, "
1687 "preserving EHB bit\n");
1688 xhci_write_64(xhci
, ((u64
) deq
& (u64
) ~ERST_PTR_MASK
) | temp
,
1689 &xhci
->ir_set
->erst_dequeue
);
1692 static void xhci_add_in_port(struct xhci_hcd
*xhci
, unsigned int num_ports
,
1693 u32 __iomem
*addr
, u8 major_revision
)
1695 u32 temp
, port_offset
, port_count
;
1698 if (major_revision
> 0x03) {
1699 xhci_warn(xhci
, "Ignoring unknown port speed, "
1700 "Ext Cap %p, revision = 0x%x\n",
1701 addr
, major_revision
);
1702 /* Ignoring port protocol we can't understand. FIXME */
1706 /* Port offset and count in the third dword, see section 7.2 */
1707 temp
= xhci_readl(xhci
, addr
+ 2);
1708 port_offset
= XHCI_EXT_PORT_OFF(temp
);
1709 port_count
= XHCI_EXT_PORT_COUNT(temp
);
1710 xhci_dbg(xhci
, "Ext Cap %p, port offset = %u, "
1711 "count = %u, revision = 0x%x\n",
1712 addr
, port_offset
, port_count
, major_revision
);
1713 /* Port count includes the current port offset */
1714 if (port_offset
== 0 || (port_offset
+ port_count
- 1) > num_ports
)
1715 /* WTF? "Valid values are ‘1’ to MaxPorts" */
1718 for (i
= port_offset
; i
< (port_offset
+ port_count
); i
++) {
1719 /* Duplicate entry. Ignore the port if the revisions differ. */
1720 if (xhci
->port_array
[i
] != 0) {
1721 xhci_warn(xhci
, "Duplicate port entry, Ext Cap %p,"
1722 " port %u\n", addr
, i
);
1723 xhci_warn(xhci
, "Port was marked as USB %u, "
1724 "duplicated as USB %u\n",
1725 xhci
->port_array
[i
], major_revision
);
1726 /* Only adjust the roothub port counts if we haven't
1727 * found a similar duplicate.
1729 if (xhci
->port_array
[i
] != major_revision
&&
1730 xhci
->port_array
[i
] != DUPLICATE_ENTRY
) {
1731 if (xhci
->port_array
[i
] == 0x03)
1732 xhci
->num_usb3_ports
--;
1734 xhci
->num_usb2_ports
--;
1735 xhci
->port_array
[i
] = DUPLICATE_ENTRY
;
1737 /* FIXME: Should we disable the port? */
1740 xhci
->port_array
[i
] = major_revision
;
1741 if (major_revision
== 0x03)
1742 xhci
->num_usb3_ports
++;
1744 xhci
->num_usb2_ports
++;
1746 /* FIXME: Should we disable ports not in the Extended Capabilities? */
1750 * Scan the Extended Capabilities for the "Supported Protocol Capabilities" that
1751 * specify what speeds each port is supposed to be. We can't count on the port
1752 * speed bits in the PORTSC register being correct until a device is connected,
1753 * but we need to set up the two fake roothubs with the correct number of USB
1754 * 3.0 and USB 2.0 ports at host controller initialization time.
1756 static int xhci_setup_port_arrays(struct xhci_hcd
*xhci
, gfp_t flags
)
1760 unsigned int num_ports
;
1763 addr
= &xhci
->cap_regs
->hcc_params
;
1764 offset
= XHCI_HCC_EXT_CAPS(xhci_readl(xhci
, addr
));
1766 xhci_err(xhci
, "No Extended Capability registers, "
1767 "unable to set up roothub.\n");
1771 num_ports
= HCS_MAX_PORTS(xhci
->hcs_params1
);
1772 xhci
->port_array
= kzalloc(sizeof(*xhci
->port_array
)*num_ports
, flags
);
1773 if (!xhci
->port_array
)
1777 * For whatever reason, the first capability offset is from the
1778 * capability register base, not from the HCCPARAMS register.
1779 * See section 5.3.6 for offset calculation.
1781 addr
= &xhci
->cap_regs
->hc_capbase
+ offset
;
1785 cap_id
= xhci_readl(xhci
, addr
);
1786 if (XHCI_EXT_CAPS_ID(cap_id
) == XHCI_EXT_CAPS_PROTOCOL
)
1787 xhci_add_in_port(xhci
, num_ports
, addr
,
1788 (u8
) XHCI_EXT_PORT_MAJOR(cap_id
));
1789 offset
= XHCI_EXT_CAPS_NEXT(cap_id
);
1790 if (!offset
|| (xhci
->num_usb2_ports
+ xhci
->num_usb3_ports
)
1794 * Once you're into the Extended Capabilities, the offset is
1795 * always relative to the register holding the offset.
1800 if (xhci
->num_usb2_ports
== 0 && xhci
->num_usb3_ports
== 0) {
1801 xhci_warn(xhci
, "No ports on the roothubs?\n");
1804 xhci_dbg(xhci
, "Found %u USB 2.0 ports and %u USB 3.0 ports.\n",
1805 xhci
->num_usb2_ports
, xhci
->num_usb3_ports
);
1807 /* Place limits on the number of roothub ports so that the hub
1808 * descriptors aren't longer than the USB core will allocate.
1810 if (xhci
->num_usb3_ports
> 15) {
1811 xhci_dbg(xhci
, "Limiting USB 3.0 roothub ports to 15.\n");
1812 xhci
->num_usb3_ports
= 15;
1814 if (xhci
->num_usb2_ports
> USB_MAXCHILDREN
) {
1815 xhci_dbg(xhci
, "Limiting USB 2.0 roothub ports to %u.\n",
1817 xhci
->num_usb2_ports
= USB_MAXCHILDREN
;
1821 * Note we could have all USB 3.0 ports, or all USB 2.0 ports.
1822 * Not sure how the USB core will handle a hub with no ports...
1824 if (xhci
->num_usb2_ports
) {
1825 xhci
->usb2_ports
= kmalloc(sizeof(*xhci
->usb2_ports
)*
1826 xhci
->num_usb2_ports
, flags
);
1827 if (!xhci
->usb2_ports
)
1831 for (i
= 0; i
< num_ports
; i
++) {
1832 if (xhci
->port_array
[i
] == 0x03 ||
1833 xhci
->port_array
[i
] == 0 ||
1834 xhci
->port_array
[i
] == DUPLICATE_ENTRY
)
1837 xhci
->usb2_ports
[port_index
] =
1838 &xhci
->op_regs
->port_status_base
+
1840 xhci_dbg(xhci
, "USB 2.0 port at index %u, "
1842 xhci
->usb2_ports
[port_index
]);
1844 if (port_index
== xhci
->num_usb2_ports
)
1848 if (xhci
->num_usb3_ports
) {
1849 xhci
->usb3_ports
= kmalloc(sizeof(*xhci
->usb3_ports
)*
1850 xhci
->num_usb3_ports
, flags
);
1851 if (!xhci
->usb3_ports
)
1855 for (i
= 0; i
< num_ports
; i
++)
1856 if (xhci
->port_array
[i
] == 0x03) {
1857 xhci
->usb3_ports
[port_index
] =
1858 &xhci
->op_regs
->port_status_base
+
1860 xhci_dbg(xhci
, "USB 3.0 port at index %u, "
1862 xhci
->usb3_ports
[port_index
]);
1864 if (port_index
== xhci
->num_usb3_ports
)
1871 int xhci_mem_init(struct xhci_hcd
*xhci
, gfp_t flags
)
1874 struct device
*dev
= xhci_to_hcd(xhci
)->self
.controller
;
1875 unsigned int val
, val2
;
1877 struct xhci_segment
*seg
;
1881 page_size
= xhci_readl(xhci
, &xhci
->op_regs
->page_size
);
1882 xhci_dbg(xhci
, "Supported page size register = 0x%x\n", page_size
);
1883 for (i
= 0; i
< 16; i
++) {
1884 if ((0x1 & page_size
) != 0)
1886 page_size
= page_size
>> 1;
1889 xhci_dbg(xhci
, "Supported page size of %iK\n", (1 << (i
+12)) / 1024);
1891 xhci_warn(xhci
, "WARN: no supported page size\n");
1892 /* Use 4K pages, since that's common and the minimum the HC supports */
1893 xhci
->page_shift
= 12;
1894 xhci
->page_size
= 1 << xhci
->page_shift
;
1895 xhci_dbg(xhci
, "HCD page size set to %iK\n", xhci
->page_size
/ 1024);
1898 * Program the Number of Device Slots Enabled field in the CONFIG
1899 * register with the max value of slots the HC can handle.
1901 val
= HCS_MAX_SLOTS(xhci_readl(xhci
, &xhci
->cap_regs
->hcs_params1
));
1902 xhci_dbg(xhci
, "// xHC can handle at most %d device slots.\n",
1903 (unsigned int) val
);
1904 val2
= xhci_readl(xhci
, &xhci
->op_regs
->config_reg
);
1905 val
|= (val2
& ~HCS_SLOTS_MASK
);
1906 xhci_dbg(xhci
, "// Setting Max device slots reg = 0x%x.\n",
1907 (unsigned int) val
);
1908 xhci_writel(xhci
, val
, &xhci
->op_regs
->config_reg
);
1911 * Section 5.4.8 - doorbell array must be
1912 * "physically contiguous and 64-byte (cache line) aligned".
1914 xhci
->dcbaa
= pci_alloc_consistent(to_pci_dev(dev
),
1915 sizeof(*xhci
->dcbaa
), &dma
);
1918 memset(xhci
->dcbaa
, 0, sizeof *(xhci
->dcbaa
));
1919 xhci
->dcbaa
->dma
= dma
;
1920 xhci_dbg(xhci
, "// Device context base array address = 0x%llx (DMA), %p (virt)\n",
1921 (unsigned long long)xhci
->dcbaa
->dma
, xhci
->dcbaa
);
1922 xhci_write_64(xhci
, dma
, &xhci
->op_regs
->dcbaa_ptr
);
1925 * Initialize the ring segment pool. The ring must be a contiguous
1926 * structure comprised of TRBs. The TRBs must be 16 byte aligned,
1927 * however, the command ring segment needs 64-byte aligned segments,
1928 * so we pick the greater alignment need.
1930 xhci
->segment_pool
= dma_pool_create("xHCI ring segments", dev
,
1931 SEGMENT_SIZE
, 64, xhci
->page_size
);
1933 /* See Table 46 and Note on Figure 55 */
1934 xhci
->device_pool
= dma_pool_create("xHCI input/output contexts", dev
,
1935 2112, 64, xhci
->page_size
);
1936 if (!xhci
->segment_pool
|| !xhci
->device_pool
)
1939 /* Linear stream context arrays don't have any boundary restrictions,
1940 * and only need to be 16-byte aligned.
1942 xhci
->small_streams_pool
=
1943 dma_pool_create("xHCI 256 byte stream ctx arrays",
1944 dev
, SMALL_STREAM_ARRAY_SIZE
, 16, 0);
1945 xhci
->medium_streams_pool
=
1946 dma_pool_create("xHCI 1KB stream ctx arrays",
1947 dev
, MEDIUM_STREAM_ARRAY_SIZE
, 16, 0);
1948 /* Any stream context array bigger than MEDIUM_STREAM_ARRAY_SIZE
1949 * will be allocated with pci_alloc_consistent()
1952 if (!xhci
->small_streams_pool
|| !xhci
->medium_streams_pool
)
1955 /* Set up the command ring to have one segments for now. */
1956 xhci
->cmd_ring
= xhci_ring_alloc(xhci
, 1, true, flags
);
1957 if (!xhci
->cmd_ring
)
1959 xhci_dbg(xhci
, "Allocated command ring at %p\n", xhci
->cmd_ring
);
1960 xhci_dbg(xhci
, "First segment DMA is 0x%llx\n",
1961 (unsigned long long)xhci
->cmd_ring
->first_seg
->dma
);
1963 /* Set the address in the Command Ring Control register */
1964 val_64
= xhci_read_64(xhci
, &xhci
->op_regs
->cmd_ring
);
1965 val_64
= (val_64
& (u64
) CMD_RING_RSVD_BITS
) |
1966 (xhci
->cmd_ring
->first_seg
->dma
& (u64
) ~CMD_RING_RSVD_BITS
) |
1967 xhci
->cmd_ring
->cycle_state
;
1968 xhci_dbg(xhci
, "// Setting command ring address to 0x%x\n", val
);
1969 xhci_write_64(xhci
, val_64
, &xhci
->op_regs
->cmd_ring
);
1970 xhci_dbg_cmd_ptrs(xhci
);
1972 val
= xhci_readl(xhci
, &xhci
->cap_regs
->db_off
);
1974 xhci_dbg(xhci
, "// Doorbell array is located at offset 0x%x"
1975 " from cap regs base addr\n", val
);
1976 xhci
->dba
= (void __iomem
*) xhci
->cap_regs
+ val
;
1977 xhci_dbg_regs(xhci
);
1978 xhci_print_run_regs(xhci
);
1979 /* Set ir_set to interrupt register set 0 */
1980 xhci
->ir_set
= &xhci
->run_regs
->ir_set
[0];
1983 * Event ring setup: Allocate a normal ring, but also setup
1984 * the event ring segment table (ERST). Section 4.9.3.
1986 xhci_dbg(xhci
, "// Allocating event ring\n");
1987 xhci
->event_ring
= xhci_ring_alloc(xhci
, ERST_NUM_SEGS
, false, flags
);
1988 if (!xhci
->event_ring
)
1990 if (xhci_check_trb_in_td_math(xhci
, flags
) < 0)
1993 xhci
->erst
.entries
= pci_alloc_consistent(to_pci_dev(dev
),
1994 sizeof(struct xhci_erst_entry
)*ERST_NUM_SEGS
, &dma
);
1995 if (!xhci
->erst
.entries
)
1997 xhci_dbg(xhci
, "// Allocated event ring segment table at 0x%llx\n",
1998 (unsigned long long)dma
);
2000 memset(xhci
->erst
.entries
, 0, sizeof(struct xhci_erst_entry
)*ERST_NUM_SEGS
);
2001 xhci
->erst
.num_entries
= ERST_NUM_SEGS
;
2002 xhci
->erst
.erst_dma_addr
= dma
;
2003 xhci_dbg(xhci
, "Set ERST to 0; private num segs = %i, virt addr = %p, dma addr = 0x%llx\n",
2004 xhci
->erst
.num_entries
,
2006 (unsigned long long)xhci
->erst
.erst_dma_addr
);
2008 /* set ring base address and size for each segment table entry */
2009 for (val
= 0, seg
= xhci
->event_ring
->first_seg
; val
< ERST_NUM_SEGS
; val
++) {
2010 struct xhci_erst_entry
*entry
= &xhci
->erst
.entries
[val
];
2011 entry
->seg_addr
= seg
->dma
;
2012 entry
->seg_size
= TRBS_PER_SEGMENT
;
2017 /* set ERST count with the number of entries in the segment table */
2018 val
= xhci_readl(xhci
, &xhci
->ir_set
->erst_size
);
2019 val
&= ERST_SIZE_MASK
;
2020 val
|= ERST_NUM_SEGS
;
2021 xhci_dbg(xhci
, "// Write ERST size = %i to ir_set 0 (some bits preserved)\n",
2023 xhci_writel(xhci
, val
, &xhci
->ir_set
->erst_size
);
2025 xhci_dbg(xhci
, "// Set ERST entries to point to event ring.\n");
2026 /* set the segment table base address */
2027 xhci_dbg(xhci
, "// Set ERST base address for ir_set 0 = 0x%llx\n",
2028 (unsigned long long)xhci
->erst
.erst_dma_addr
);
2029 val_64
= xhci_read_64(xhci
, &xhci
->ir_set
->erst_base
);
2030 val_64
&= ERST_PTR_MASK
;
2031 val_64
|= (xhci
->erst
.erst_dma_addr
& (u64
) ~ERST_PTR_MASK
);
2032 xhci_write_64(xhci
, val_64
, &xhci
->ir_set
->erst_base
);
2034 /* Set the event ring dequeue address */
2035 xhci_set_hc_event_deq(xhci
);
2036 xhci_dbg(xhci
, "Wrote ERST address to ir_set 0.\n");
2037 xhci_print_ir_set(xhci
, 0);
2040 * XXX: Might need to set the Interrupter Moderation Register to
2041 * something other than the default (~1ms minimum between interrupts).
2042 * See section 5.5.1.2.
2044 init_completion(&xhci
->addr_dev
);
2045 for (i
= 0; i
< MAX_HC_SLOTS
; ++i
)
2046 xhci
->devs
[i
] = NULL
;
2047 for (i
= 0; i
< USB_MAXCHILDREN
; ++i
) {
2048 xhci
->bus_state
[0].resume_done
[i
] = 0;
2049 xhci
->bus_state
[1].resume_done
[i
] = 0;
2052 if (scratchpad_alloc(xhci
, flags
))
2054 if (xhci_setup_port_arrays(xhci
, flags
))
2060 xhci_warn(xhci
, "Couldn't initialize memory\n");
2061 xhci_mem_cleanup(xhci
);