2 * Copyright (C) 2000 Deep Blue Solutions Ltd
3 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
4 * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/platform_device.h>
18 #include <linux/mtd/mtd.h>
19 #include <linux/mtd/map.h>
20 #include <linux/mtd/partitions.h>
21 #include <linux/mtd/physmap.h>
22 #include <linux/i2c.h>
23 #include <linux/irq.h>
24 #include <mach/common.h>
25 #include <mach/hardware.h>
26 #include <asm/mach-types.h>
27 #include <asm/mach/arch.h>
28 #include <asm/mach/time.h>
29 #include <asm/mach/map.h>
30 #include <mach/gpio.h>
31 #include <mach/iomux-mx27.h>
32 #include <mach/mxc_nand.h>
33 #include <mach/imxfb.h>
36 #include "devices-imx27.h"
40 * Base address of PBC controller, CS4
42 #define PBC_BASE_ADDRESS 0xf4300000
43 #define PBC_REG_ADDR(offset) (void __force __iomem *) \
44 (PBC_BASE_ADDRESS + (offset))
46 /* When the PBC address connection is fixed in h/w, defined as 1 */
49 /* Offsets for the PBC Controller register */
51 * PBC Board version register offset
53 #define PBC_VERSION_REG PBC_REG_ADDR(0x00000 >> PBC_ADDR_SH)
55 * PBC Board control register 1 set address.
57 #define PBC_BCTRL1_SET_REG PBC_REG_ADDR(0x00008 >> PBC_ADDR_SH)
59 * PBC Board control register 1 clear address.
61 #define PBC_BCTRL1_CLEAR_REG PBC_REG_ADDR(0x0000C >> PBC_ADDR_SH)
63 /* PBC Board Control Register 1 bit definitions */
64 #define PBC_BCTRL1_LCDON 0x0800 /* Enable the LCD */
66 /* to determine the correct external crystal reference */
67 #define CKIH_27MHZ_BIT_SET (1 << 3)
69 static const int mx27ads_pins
[] __initconst
= {
112 PD11_AOUT_FEC_TX_CLK
,
115 PD14_AOUT_FEC_RX_CLK
,
168 static const struct mxc_nand_platform_data
169 mx27ads_nand_board_info __initconst
= {
174 /* ADS's NOR flash */
175 static struct physmap_flash_data mx27ads_flash_data
= {
179 static struct resource mx27ads_flash_resource
= {
181 .end
= 0xc0000000 + 0x02000000 - 1,
182 .flags
= IORESOURCE_MEM
,
186 static struct platform_device mx27ads_nor_mtd_device
= {
187 .name
= "physmap-flash",
190 .platform_data
= &mx27ads_flash_data
,
193 .resource
= &mx27ads_flash_resource
,
196 static const struct imxi2c_platform_data mx27ads_i2c1_data __initconst
= {
200 static struct i2c_board_info mx27ads_i2c_devices
[] = {
203 void lcd_power(int on
)
206 __raw_writew(PBC_BCTRL1_LCDON
, PBC_BCTRL1_SET_REG
);
208 __raw_writew(PBC_BCTRL1_LCDON
, PBC_BCTRL1_CLEAR_REG
);
211 static struct imx_fb_videomode mx27ads_modes
[] = {
214 .name
= "Sharp-LQ035Q7",
218 .pixclock
= 188679, /* in ps (5.3MHz) */
231 static struct imx_fb_platform_data mx27ads_fb_data
= {
232 .mode
= mx27ads_modes
,
233 .num_modes
= ARRAY_SIZE(mx27ads_modes
),
236 * - HSYNC active high
237 * - VSYNC active high
238 * - clk notenabled while idle
240 * - data not inverted
241 * - data enable low active
242 * - enable sharp mode
248 .lcd_power
= lcd_power
,
251 static int mx27ads_sdhc1_init(struct device
*dev
, irq_handler_t detect_irq
,
254 return request_irq(IRQ_GPIOE(21), detect_irq
, IRQF_TRIGGER_RISING
,
255 "sdhc1-card-detect", data
);
258 static int mx27ads_sdhc2_init(struct device
*dev
, irq_handler_t detect_irq
,
261 return request_irq(IRQ_GPIOB(7), detect_irq
, IRQF_TRIGGER_RISING
,
262 "sdhc2-card-detect", data
);
265 static void mx27ads_sdhc1_exit(struct device
*dev
, void *data
)
267 free_irq(IRQ_GPIOE(21), data
);
270 static void mx27ads_sdhc2_exit(struct device
*dev
, void *data
)
272 free_irq(IRQ_GPIOB(7), data
);
275 static struct imxmmc_platform_data sdhc1_pdata
= {
276 .init
= mx27ads_sdhc1_init
,
277 .exit
= mx27ads_sdhc1_exit
,
280 static struct imxmmc_platform_data sdhc2_pdata
= {
281 .init
= mx27ads_sdhc2_init
,
282 .exit
= mx27ads_sdhc2_exit
,
285 static struct platform_device
*platform_devices
[] __initdata
= {
286 &mx27ads_nor_mtd_device
,
287 &mxc_w1_master_device
,
290 static const struct imxuart_platform_data uart_pdata __initconst
= {
291 .flags
= IMXUART_HAVE_RTSCTS
,
294 static void __init
mx27ads_board_init(void)
296 mxc_gpio_setup_multiple_pins(mx27ads_pins
, ARRAY_SIZE(mx27ads_pins
),
299 imx27_add_imx_uart0(&uart_pdata
);
300 imx27_add_imx_uart1(&uart_pdata
);
301 imx27_add_imx_uart2(&uart_pdata
);
302 imx27_add_imx_uart3(&uart_pdata
);
303 imx27_add_imx_uart4(&uart_pdata
);
304 imx27_add_imx_uart5(&uart_pdata
);
305 imx27_add_mxc_nand(&mx27ads_nand_board_info
);
307 /* only the i2c master 1 is used on this CPU card */
308 i2c_register_board_info(1, mx27ads_i2c_devices
,
309 ARRAY_SIZE(mx27ads_i2c_devices
));
310 imx27_add_imx_i2c(1, &mx27ads_i2c1_data
);
311 mxc_register_device(&mxc_fb_device
, &mx27ads_fb_data
);
312 mxc_register_device(&mxc_sdhc_device0
, &sdhc1_pdata
);
313 mxc_register_device(&mxc_sdhc_device1
, &sdhc2_pdata
);
316 platform_add_devices(platform_devices
, ARRAY_SIZE(platform_devices
));
319 static void __init
mx27ads_timer_init(void)
321 unsigned long fref
= 26000000;
323 if ((__raw_readw(PBC_VERSION_REG
) & CKIH_27MHZ_BIT_SET
) == 0)
326 mx27_clocks_init(fref
);
329 static struct sys_timer mx27ads_timer
= {
330 .init
= mx27ads_timer_init
,
333 static struct map_desc mx27ads_io_desc
[] __initdata
= {
335 .virtual = PBC_BASE_ADDRESS
,
336 .pfn
= __phys_to_pfn(MX27_CS4_BASE_ADDR
),
342 static void __init
mx27ads_map_io(void)
345 iotable_init(mx27ads_io_desc
, ARRAY_SIZE(mx27ads_io_desc
));
348 MACHINE_START(MX27ADS
, "Freescale i.MX27ADS")
349 /* maintainer: Freescale Semiconductor, Inc. */
350 .boot_params
= MX27_PHYS_OFFSET
+ 0x100,
351 .map_io
= mx27ads_map_io
,
352 .init_irq
= mx27_init_irq
,
353 .init_machine
= mx27ads_board_init
,
354 .timer
= &mx27ads_timer
,