2 * Driver for the NXP ISP1760 chip
4 * However, the code might contain some bugs. What doesn't work for sure is:
7 e The interrupt line is configured as active low, level.
9 * (c) 2007 Sebastian Siewior <bigeasy@linutronix.de>
12 #include <linux/module.h>
13 #include <linux/kernel.h>
14 #include <linux/slab.h>
15 #include <linux/list.h>
16 #include <linux/usb.h>
17 #include <linux/usb/hcd.h>
18 #include <linux/debugfs.h>
19 #include <linux/uaccess.h>
22 #include <asm/unaligned.h>
23 #include <asm/cacheflush.h>
25 #include "isp1760-hcd.h"
27 static struct kmem_cache
*qtd_cachep
;
28 static struct kmem_cache
*qh_cachep
;
33 struct inter_packet_info atl_ints
[32];
34 struct inter_packet_info int_ints
[32];
35 struct memory_chunk memory_pool
[BLOCKS
];
38 /* periodic schedule support */
39 #define DEFAULT_I_TDPS 1024
40 unsigned periodic_size
;
42 unsigned long reset_done
;
43 unsigned long next_statechange
;
44 unsigned int devflags
;
47 static inline struct isp1760_hcd
*hcd_to_priv(struct usb_hcd
*hcd
)
49 return (struct isp1760_hcd
*) (hcd
->hcd_priv
);
52 /* Section 2.2 Host Controller Capability Registers */
53 #define HC_LENGTH(p) (((p)>>00)&0x00ff) /* bits 7:0 */
54 #define HC_VERSION(p) (((p)>>16)&0xffff) /* bits 31:16 */
55 #define HCS_INDICATOR(p) ((p)&(1 << 16)) /* true: has port indicators */
56 #define HCS_PPC(p) ((p)&(1 << 4)) /* true: port power control */
57 #define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */
58 #define HCC_ISOC_CACHE(p) ((p)&(1 << 7)) /* true: can cache isoc frame */
59 #define HCC_ISOC_THRES(p) (((p)>>4)&0x7) /* bits 6:4, uframes cached */
61 /* Section 2.3 Host Controller Operational Registers */
62 #define CMD_LRESET (1<<7) /* partial reset (no ports, etc) */
63 #define CMD_RESET (1<<1) /* reset HC not bus */
64 #define CMD_RUN (1<<0) /* start/stop HC */
65 #define STS_PCD (1<<2) /* port change detect */
66 #define FLAG_CF (1<<0) /* true: we'll support "high speed" */
68 #define PORT_OWNER (1<<13) /* true: companion hc owns this port */
69 #define PORT_POWER (1<<12) /* true: has power (see PPC) */
70 #define PORT_USB11(x) (((x) & (3 << 10)) == (1 << 10)) /* USB 1.1 device */
71 #define PORT_RESET (1<<8) /* reset port */
72 #define PORT_SUSPEND (1<<7) /* suspend port */
73 #define PORT_RESUME (1<<6) /* resume it */
74 #define PORT_PE (1<<2) /* port enable */
75 #define PORT_CSC (1<<1) /* connect status change */
76 #define PORT_CONNECT (1<<0) /* device connected */
77 #define PORT_RWC_BITS (PORT_CSC)
84 /* the rest is HCD-private */
85 struct list_head qtd_list
;
91 #define URB_ENQUEUED (1 << 1)
95 /* first part defined by EHCI spec */
96 struct list_head qtd_list
;
103 * Access functions for isp176x registers (addresses 0..0x03FF).
105 static u32
reg_read32(void __iomem
*base
, u32 reg
)
107 return readl(base
+ reg
);
110 static void reg_write32(void __iomem
*base
, u32 reg
, u32 val
)
112 writel(val
, base
+ reg
);
116 * Access functions for isp176x memory (offset >= 0x0400).
118 * bank_reads8() reads memory locations prefetched by an earlier write to
119 * HC_MEMORY_REG (see isp176x datasheet). Unless you want to do fancy multi-
120 * bank optimizations, you should use the more generic mem_reads8() below.
122 * For access to ptd memory, use the specialized ptd_read() and ptd_write()
125 * These functions copy via MMIO data to/from the device. memcpy_{to|from}io()
126 * doesn't quite work because some people have to enforce 32-bit access
128 static void bank_reads8(void __iomem
*src_base
, u32 src_offset
, u32 bank_addr
,
129 __u32
*dst
, u32 bytes
)
136 src
= src_base
+ (bank_addr
| src_offset
);
138 if (src_offset
< PAYLOAD_OFFSET
) {
140 *dst
= le32_to_cpu(__raw_readl(src
));
147 *dst
= __raw_readl(src
);
157 /* in case we have 3, 2 or 1 by left. The dst buffer may not be fully
160 if (src_offset
< PAYLOAD_OFFSET
)
161 val
= le32_to_cpu(__raw_readl(src
));
163 val
= __raw_readl(src
);
165 dst_byteptr
= (void *) dst
;
166 src_byteptr
= (void *) &val
;
168 *dst_byteptr
= *src_byteptr
;
175 static void mem_reads8(void __iomem
*src_base
, u32 src_offset
, void *dst
,
178 reg_write32(src_base
, HC_MEMORY_REG
, src_offset
+ ISP_BANK(0));
180 bank_reads8(src_base
, src_offset
, ISP_BANK(0), dst
, bytes
);
183 static void mem_writes8(void __iomem
*dst_base
, u32 dst_offset
,
184 __u32
const *src
, u32 bytes
)
188 dst
= dst_base
+ dst_offset
;
190 if (dst_offset
< PAYLOAD_OFFSET
) {
192 __raw_writel(cpu_to_le32(*src
), dst
);
199 __raw_writel(*src
, dst
);
208 /* in case we have 3, 2 or 1 bytes left. The buffer is allocated and the
209 * extra bytes should not be read by the HW.
212 if (dst_offset
< PAYLOAD_OFFSET
)
213 __raw_writel(cpu_to_le32(*src
), dst
);
215 __raw_writel(*src
, dst
);
219 * Read and write ptds. 'ptd_offset' should be one of ISO_PTD_OFFSET,
220 * INT_PTD_OFFSET, and ATL_PTD_OFFSET. 'slot' should be less than 32.
222 static void ptd_read(void __iomem
*base
, u32 ptd_offset
, u32 slot
,
225 reg_write32(base
, HC_MEMORY_REG
,
226 ISP_BANK(0) + ptd_offset
+ slot
*sizeof(*ptd
));
228 bank_reads8(base
, ptd_offset
+ slot
*sizeof(*ptd
), ISP_BANK(0),
229 (void *) ptd
, sizeof(*ptd
));
232 static void ptd_write(void __iomem
*base
, u32 ptd_offset
, u32 slot
,
235 mem_writes8(base
, ptd_offset
+ slot
*sizeof(*ptd
) + sizeof(ptd
->dw0
),
236 &ptd
->dw1
, 7*sizeof(ptd
->dw1
));
237 /* Make sure dw0 gets written last (after other dw's and after payload)
238 since it contains the enable bit */
240 mem_writes8(base
, ptd_offset
+ slot
*sizeof(*ptd
), &ptd
->dw0
,
245 /* memory management of the 60kb on the chip from 0x1000 to 0xffff */
246 static void init_memory(struct isp1760_hcd
*priv
)
251 payload_addr
= PAYLOAD_OFFSET
;
252 for (i
= 0; i
< BLOCK_1_NUM
; i
++) {
253 priv
->memory_pool
[i
].start
= payload_addr
;
254 priv
->memory_pool
[i
].size
= BLOCK_1_SIZE
;
255 priv
->memory_pool
[i
].free
= 1;
256 payload_addr
+= priv
->memory_pool
[i
].size
;
260 for (i
= 0; i
< BLOCK_2_NUM
; i
++) {
261 priv
->memory_pool
[curr
+ i
].start
= payload_addr
;
262 priv
->memory_pool
[curr
+ i
].size
= BLOCK_2_SIZE
;
263 priv
->memory_pool
[curr
+ i
].free
= 1;
264 payload_addr
+= priv
->memory_pool
[curr
+ i
].size
;
268 for (i
= 0; i
< BLOCK_3_NUM
; i
++) {
269 priv
->memory_pool
[curr
+ i
].start
= payload_addr
;
270 priv
->memory_pool
[curr
+ i
].size
= BLOCK_3_SIZE
;
271 priv
->memory_pool
[curr
+ i
].free
= 1;
272 payload_addr
+= priv
->memory_pool
[curr
+ i
].size
;
275 WARN_ON(payload_addr
- priv
->memory_pool
[0].start
> PAYLOAD_AREA_SIZE
);
278 static void alloc_mem(struct usb_hcd
*hcd
, struct isp1760_qtd
*qtd
)
280 struct isp1760_hcd
*priv
= hcd_to_priv(hcd
);
283 WARN_ON(qtd
->payload_addr
);
288 for (i
= 0; i
< BLOCKS
; i
++) {
289 if (priv
->memory_pool
[i
].size
>= qtd
->length
&&
290 priv
->memory_pool
[i
].free
) {
291 priv
->memory_pool
[i
].free
= 0;
292 qtd
->payload_addr
= priv
->memory_pool
[i
].start
;
297 dev_err(hcd
->self
.controller
,
298 "%s: Cannot allocate %zu bytes of memory\n"
299 "Current memory map:\n",
300 __func__
, qtd
->length
);
301 for (i
= 0; i
< BLOCKS
; i
++) {
302 dev_err(hcd
->self
.controller
, "Pool %2d size %4d status: %d\n",
303 i
, priv
->memory_pool
[i
].size
,
304 priv
->memory_pool
[i
].free
);
306 /* XXX maybe -ENOMEM could be possible */
311 static void free_mem(struct usb_hcd
*hcd
, struct isp1760_qtd
*qtd
)
313 struct isp1760_hcd
*priv
= hcd_to_priv(hcd
);
316 if (!qtd
->payload_addr
)
319 for (i
= 0; i
< BLOCKS
; i
++) {
320 if (priv
->memory_pool
[i
].start
== qtd
->payload_addr
) {
321 WARN_ON(priv
->memory_pool
[i
].free
);
322 priv
->memory_pool
[i
].free
= 1;
323 qtd
->payload_addr
= 0;
328 dev_err(hcd
->self
.controller
, "%s: Invalid pointer: %08x\n",
329 __func__
, qtd
->payload_addr
);
333 static void isp1760_init_regs(struct usb_hcd
*hcd
)
335 reg_write32(hcd
->regs
, HC_BUFFER_STATUS_REG
, 0);
336 reg_write32(hcd
->regs
, HC_ATL_PTD_SKIPMAP_REG
, NO_TRANSFER_ACTIVE
);
337 reg_write32(hcd
->regs
, HC_INT_PTD_SKIPMAP_REG
, NO_TRANSFER_ACTIVE
);
338 reg_write32(hcd
->regs
, HC_ISO_PTD_SKIPMAP_REG
, NO_TRANSFER_ACTIVE
);
341 static int handshake(struct usb_hcd
*hcd
, u32 reg
,
342 u32 mask
, u32 done
, int usec
)
347 result
= reg_read32(hcd
->regs
, reg
);
359 /* reset a non-running (STS_HALT == 1) controller */
360 static int ehci_reset(struct usb_hcd
*hcd
)
363 struct isp1760_hcd
*priv
= hcd_to_priv(hcd
);
365 u32 command
= reg_read32(hcd
->regs
, HC_USBCMD
);
367 command
|= CMD_RESET
;
368 reg_write32(hcd
->regs
, HC_USBCMD
, command
);
369 hcd
->state
= HC_STATE_HALT
;
370 priv
->next_statechange
= jiffies
;
371 retval
= handshake(hcd
, HC_USBCMD
,
372 CMD_RESET
, 0, 250 * 1000);
376 static void qh_destroy(struct isp1760_qh
*qh
)
378 WARN_ON(!list_empty(&qh
->qtd_list
));
379 kmem_cache_free(qh_cachep
, qh
);
382 static struct isp1760_qh
*isp1760_qh_alloc(gfp_t flags
)
384 struct isp1760_qh
*qh
;
386 qh
= kmem_cache_zalloc(qh_cachep
, flags
);
390 INIT_LIST_HEAD(&qh
->qtd_list
);
394 /* magic numbers that can affect system performance */
395 #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */
396 #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */
397 #define EHCI_TUNE_RL_TT 0
398 #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */
399 #define EHCI_TUNE_MULT_TT 1
400 #define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */
402 /* one-time init, only for memory state */
403 static int priv_init(struct usb_hcd
*hcd
)
405 struct isp1760_hcd
*priv
= hcd_to_priv(hcd
);
408 spin_lock_init(&priv
->lock
);
411 * hw default: 1K periodic list heads, one per frame.
412 * periodic_size can shrink by USBCMD update if hcc_params allows.
414 priv
->periodic_size
= DEFAULT_I_TDPS
;
416 /* controllers may cache some of the periodic schedule ... */
417 hcc_params
= reg_read32(hcd
->regs
, HC_HCCPARAMS
);
418 /* full frame cache */
419 if (HCC_ISOC_CACHE(hcc_params
))
421 else /* N microframes cached */
422 priv
->i_thresh
= 2 + HCC_ISOC_THRES(hcc_params
);
427 static int isp1760_hc_setup(struct usb_hcd
*hcd
)
429 struct isp1760_hcd
*priv
= hcd_to_priv(hcd
);
433 /* Setup HW Mode Control: This assumes a level active-low interrupt */
434 hwmode
= HW_DATA_BUS_32BIT
;
436 if (priv
->devflags
& ISP1760_FLAG_BUS_WIDTH_16
)
437 hwmode
&= ~HW_DATA_BUS_32BIT
;
438 if (priv
->devflags
& ISP1760_FLAG_ANALOG_OC
)
439 hwmode
|= HW_ANA_DIGI_OC
;
440 if (priv
->devflags
& ISP1760_FLAG_DACK_POL_HIGH
)
441 hwmode
|= HW_DACK_POL_HIGH
;
442 if (priv
->devflags
& ISP1760_FLAG_DREQ_POL_HIGH
)
443 hwmode
|= HW_DREQ_POL_HIGH
;
444 if (priv
->devflags
& ISP1760_FLAG_INTR_POL_HIGH
)
445 hwmode
|= HW_INTR_HIGH_ACT
;
446 if (priv
->devflags
& ISP1760_FLAG_INTR_EDGE_TRIG
)
447 hwmode
|= HW_INTR_EDGE_TRIG
;
450 * We have to set this first in case we're in 16-bit mode.
451 * Write it twice to ensure correct upper bits if switching
454 reg_write32(hcd
->regs
, HC_HW_MODE_CTRL
, hwmode
);
455 reg_write32(hcd
->regs
, HC_HW_MODE_CTRL
, hwmode
);
457 reg_write32(hcd
->regs
, HC_SCRATCH_REG
, 0xdeadbabe);
458 /* Change bus pattern */
459 scratch
= reg_read32(hcd
->regs
, HC_CHIP_ID_REG
);
460 scratch
= reg_read32(hcd
->regs
, HC_SCRATCH_REG
);
461 if (scratch
!= 0xdeadbabe) {
462 dev_err(hcd
->self
.controller
, "Scratch test failed.\n");
467 isp1760_init_regs(hcd
);
470 reg_write32(hcd
->regs
, HC_RESET_REG
, SW_RESET_RESET_ALL
);
473 reg_write32(hcd
->regs
, HC_RESET_REG
, SW_RESET_RESET_HC
);
476 result
= ehci_reset(hcd
);
482 dev_info(hcd
->self
.controller
, "bus width: %d, oc: %s\n",
483 (priv
->devflags
& ISP1760_FLAG_BUS_WIDTH_16
) ?
484 16 : 32, (priv
->devflags
& ISP1760_FLAG_ANALOG_OC
) ?
485 "analog" : "digital");
488 reg_write32(hcd
->regs
, HC_HW_MODE_CTRL
, hwmode
| ALL_ATX_RESET
);
490 reg_write32(hcd
->regs
, HC_HW_MODE_CTRL
, hwmode
);
492 reg_write32(hcd
->regs
, HC_INTERRUPT_REG
, INTERRUPT_ENABLE_MASK
);
493 reg_write32(hcd
->regs
, HC_INTERRUPT_ENABLE
, INTERRUPT_ENABLE_MASK
);
496 * PORT 1 Control register of the ISP1760 is the OTG control
497 * register on ISP1761. Since there is no OTG or device controller
498 * support in this driver, we use port 1 as a "normal" USB host port on
501 reg_write32(hcd
->regs
, HC_PORT1_CTRL
, PORT1_POWER
| PORT1_INIT2
);
504 priv
->hcs_params
= reg_read32(hcd
->regs
, HC_HCSPARAMS
);
506 return priv_init(hcd
);
509 static void isp1760_init_maps(struct usb_hcd
*hcd
)
511 /*set last maps, for iso its only 1, else 32 tds bitmap*/
512 reg_write32(hcd
->regs
, HC_ATL_PTD_LASTPTD_REG
, 0x80000000);
513 reg_write32(hcd
->regs
, HC_INT_PTD_LASTPTD_REG
, 0x80000000);
514 reg_write32(hcd
->regs
, HC_ISO_PTD_LASTPTD_REG
, 0x00000001);
516 reg_write32(hcd
->regs
, HC_BUFFER_STATUS_REG
,
517 ATL_BUF_FILL
| INT_BUF_FILL
);
520 static void isp1760_enable_interrupts(struct usb_hcd
*hcd
)
522 reg_write32(hcd
->regs
, HC_ATL_IRQ_MASK_AND_REG
, 0);
523 reg_write32(hcd
->regs
, HC_ATL_IRQ_MASK_OR_REG
, 0xffffffff);
524 reg_write32(hcd
->regs
, HC_INT_IRQ_MASK_AND_REG
, 0);
525 reg_write32(hcd
->regs
, HC_INT_IRQ_MASK_OR_REG
, 0xffffffff);
526 reg_write32(hcd
->regs
, HC_ISO_IRQ_MASK_AND_REG
, 0);
527 reg_write32(hcd
->regs
, HC_ISO_IRQ_MASK_OR_REG
, 0xffffffff);
531 static int isp1760_run(struct usb_hcd
*hcd
)
538 hcd
->uses_new_polling
= 1;
540 hcd
->state
= HC_STATE_RUNNING
;
541 isp1760_enable_interrupts(hcd
);
542 temp
= reg_read32(hcd
->regs
, HC_HW_MODE_CTRL
);
543 reg_write32(hcd
->regs
, HC_HW_MODE_CTRL
, temp
| HW_GLOBAL_INTR_EN
);
545 command
= reg_read32(hcd
->regs
, HC_USBCMD
);
546 command
&= ~(CMD_LRESET
|CMD_RESET
);
548 reg_write32(hcd
->regs
, HC_USBCMD
, command
);
550 retval
= handshake(hcd
, HC_USBCMD
, CMD_RUN
, CMD_RUN
,
557 * Spec says to write FLAG_CF as last config action, priv code grabs
558 * the semaphore while doing so.
560 down_write(&ehci_cf_port_reset_rwsem
);
561 reg_write32(hcd
->regs
, HC_CONFIGFLAG
, FLAG_CF
);
563 retval
= handshake(hcd
, HC_CONFIGFLAG
, FLAG_CF
, FLAG_CF
, 250 * 1000);
564 up_write(&ehci_cf_port_reset_rwsem
);
568 chipid
= reg_read32(hcd
->regs
, HC_CHIP_ID_REG
);
569 dev_info(hcd
->self
.controller
, "USB ISP %04x HW rev. %d started\n",
570 chipid
& 0xffff, chipid
>> 16);
572 /* PTD Register Init Part 2, Step 28 */
574 isp1760_init_maps(hcd
);
576 /* GRR this is run-once init(), being done every time the HC starts.
577 * So long as they're part of class devices, we can't do it init()
578 * since the class device isn't created that early.
583 static u32
base_to_chip(u32 base
)
585 return ((base
- 0x400) >> 3);
588 static int last_qtd_of_urb(struct isp1760_qtd
*qtd
, struct isp1760_qh
*qh
)
592 if (list_is_last(&qtd
->qtd_list
, &qh
->qtd_list
))
596 qtd
= list_entry(qtd
->qtd_list
.next
, typeof(*qtd
), qtd_list
);
597 return (qtd
->urb
!= urb
);
600 static void transform_into_atl(struct isp1760_qh
*qh
,
601 struct isp1760_qtd
*qtd
, struct ptd
*ptd
)
607 u32 nak
= NAK_COUNTER
;
609 memset(ptd
, 0, sizeof(*ptd
));
611 /* according to 3.6.2, max packet len can not be > 0x400 */
612 maxpacket
= usb_maxpacket(qtd
->urb
->dev
, qtd
->urb
->pipe
,
613 usb_pipeout(qtd
->urb
->pipe
));
614 multi
= 1 + ((maxpacket
>> 11) & 0x3);
618 ptd
->dw0
= PTD_VALID
;
619 ptd
->dw0
|= PTD_LENGTH(qtd
->length
);
620 ptd
->dw0
|= PTD_MAXPACKET(maxpacket
);
621 ptd
->dw0
|= PTD_ENDPOINT(usb_pipeendpoint(qtd
->urb
->pipe
));
624 ptd
->dw1
= usb_pipeendpoint(qtd
->urb
->pipe
) >> 1;
625 ptd
->dw1
|= PTD_DEVICE_ADDR(usb_pipedevice(qtd
->urb
->pipe
));
627 pid_code
= qtd
->packet_type
;
628 ptd
->dw1
|= PTD_PID_TOKEN(pid_code
);
630 if (usb_pipebulk(qtd
->urb
->pipe
))
631 ptd
->dw1
|= PTD_TRANS_BULK
;
632 else if (usb_pipeint(qtd
->urb
->pipe
))
633 ptd
->dw1
|= PTD_TRANS_INT
;
635 if (qtd
->urb
->dev
->speed
!= USB_SPEED_HIGH
) {
636 /* split transaction */
638 ptd
->dw1
|= PTD_TRANS_SPLIT
;
639 if (qtd
->urb
->dev
->speed
== USB_SPEED_LOW
)
640 ptd
->dw1
|= PTD_SE_USB_LOSPEED
;
642 ptd
->dw1
|= PTD_PORT_NUM(qtd
->urb
->dev
->ttport
);
643 ptd
->dw1
|= PTD_HUB_NUM(qtd
->urb
->dev
->tt
->hub
->devnum
);
645 /* SE bit for Split INT transfers */
646 if (usb_pipeint(qtd
->urb
->pipe
) &&
647 (qtd
->urb
->dev
->speed
== USB_SPEED_LOW
))
654 ptd
->dw0
|= PTD_MULTI(multi
);
655 if (usb_pipecontrol(qtd
->urb
->pipe
) ||
656 usb_pipebulk(qtd
->urb
->pipe
))
663 ptd
->dw2
|= PTD_DATA_START_ADDR(base_to_chip(qtd
->payload_addr
));
664 ptd
->dw2
|= PTD_RL_CNT(rl
);
665 ptd
->dw3
|= PTD_NAC_CNT(nak
);
668 ptd
->dw3
|= qh
->toggle
;
669 if (usb_pipecontrol(qtd
->urb
->pipe
)) {
670 if (qtd
->data_buffer
== qtd
->urb
->setup_packet
)
671 ptd
->dw3
&= ~PTD_DATA_TOGGLE(1);
672 else if (last_qtd_of_urb(qtd
, qh
))
673 ptd
->dw3
|= PTD_DATA_TOGGLE(1);
676 ptd
->dw3
|= PTD_ACTIVE
;
678 ptd
->dw3
|= PTD_CERR(ERR_COUNTER
);
681 static void transform_add_int(struct isp1760_qh
*qh
,
682 struct isp1760_qtd
*qtd
, struct ptd
*ptd
)
688 * Most of this is guessing. ISP1761 datasheet is quite unclear, and
689 * the algorithm from the original Philips driver code, which was
690 * pretty much used in this driver before as well, is quite horrendous
691 * and, i believe, incorrect. The code below follows the datasheet and
692 * USB2.0 spec as far as I can tell, and plug/unplug seems to be much
693 * more reliable this way (fingers crossed...).
696 if (qtd
->urb
->dev
->speed
== USB_SPEED_HIGH
) {
697 /* urb->interval is in units of microframes (1/8 ms) */
698 period
= qtd
->urb
->interval
>> 3;
700 if (qtd
->urb
->interval
> 4)
701 usof
= 0x01; /* One bit set =>
702 interval 1 ms * uFrame-match */
703 else if (qtd
->urb
->interval
> 2)
704 usof
= 0x22; /* Two bits set => interval 1/2 ms */
705 else if (qtd
->urb
->interval
> 1)
706 usof
= 0x55; /* Four bits set => interval 1/4 ms */
708 usof
= 0xff; /* All bits set => interval 1/8 ms */
710 /* urb->interval is in units of frames (1 ms) */
711 period
= qtd
->urb
->interval
;
712 usof
= 0x0f; /* Execute Start Split on any of the
713 four first uFrames */
716 * First 8 bits in dw5 is uSCS and "specifies which uSOF the
717 * complete split needs to be sent. Valid only for IN." Also,
718 * "All bits can be set to one for every transfer." (p 82,
719 * ISP1761 data sheet.) 0x1c is from Philips driver. Where did
720 * that number come from? 0xff seems to work fine...
722 /* ptd->dw5 = 0x1c; */
723 ptd
->dw5
= 0xff; /* Execute Complete Split on any uFrame */
726 period
= period
>> 1;/* Ensure equal or shorter period than requested */
727 period
&= 0xf8; /* Mask off too large values and lowest unused 3 bits */
733 static void transform_into_int(struct isp1760_qh
*qh
,
734 struct isp1760_qtd
*qtd
, struct ptd
*ptd
)
736 transform_into_atl(qh
, qtd
, ptd
);
737 transform_add_int(qh
, qtd
, ptd
);
740 static int check_error(struct usb_hcd
*hcd
, struct ptd
*ptd
)
744 if (ptd
->dw3
& DW3_HALT_BIT
) {
747 if (ptd
->dw3
& DW3_ERROR_BIT
)
748 pr_err("error bit is set in DW3\n");
751 if (ptd
->dw3
& DW3_QTD_ACTIVE
) {
752 dev_err(hcd
->self
.controller
, "Transfer active bit is set DW3\n"
753 "nak counter: %d, rl: %d\n",
754 (ptd
->dw3
>> 19) & 0xf, (ptd
->dw2
>> 25) & 0xf);
760 static void check_int_err_status(struct usb_hcd
*hcd
, u32 dw4
)
766 for (i
= 0; i
< 8; i
++) {
769 dev_err(hcd
->self
.controller
, "Underrun (%d)\n", i
);
773 dev_err(hcd
->self
.controller
,
774 "Transaction error (%d)\n", i
);
778 dev_err(hcd
->self
.controller
, "Babble error (%d)\n", i
);
785 static void enqueue_one_qtd(struct usb_hcd
*hcd
, struct isp1760_qtd
*qtd
)
787 if (qtd
->length
&& (qtd
->length
<= MAX_PAYLOAD_SIZE
)) {
788 switch (qtd
->packet_type
) {
793 mem_writes8(hcd
->regs
, qtd
->payload_addr
,
794 qtd
->data_buffer
, qtd
->length
);
799 static void enqueue_one_atl_qtd(struct usb_hcd
*hcd
, struct isp1760_qh
*qh
,
800 u32 slot
, struct isp1760_qtd
*qtd
)
802 struct isp1760_hcd
*priv
= hcd_to_priv(hcd
);
806 transform_into_atl(qh
, qtd
, &ptd
);
807 ptd_write(hcd
->regs
, ATL_PTD_OFFSET
, slot
, &ptd
);
808 enqueue_one_qtd(hcd
, qtd
);
810 priv
->atl_ints
[slot
].qh
= qh
;
811 priv
->atl_ints
[slot
].qtd
= qtd
;
812 qtd
->status
|= URB_ENQUEUED
;
813 qtd
->status
|= slot
<< 16;
816 static void enqueue_one_int_qtd(struct usb_hcd
*hcd
, struct isp1760_qh
*qh
,
817 u32 slot
, struct isp1760_qtd
*qtd
)
819 struct isp1760_hcd
*priv
= hcd_to_priv(hcd
);
823 transform_into_int(qh
, qtd
, &ptd
);
824 ptd_write(hcd
->regs
, INT_PTD_OFFSET
, slot
, &ptd
);
825 enqueue_one_qtd(hcd
, qtd
);
827 priv
->int_ints
[slot
].qh
= qh
;
828 priv
->int_ints
[slot
].qtd
= qtd
;
829 qtd
->status
|= URB_ENQUEUED
;
830 qtd
->status
|= slot
<< 16;
833 static void enqueue_an_ATL_packet(struct usb_hcd
*hcd
, struct isp1760_qh
*qh
,
834 struct isp1760_qtd
*qtd
)
836 struct isp1760_hcd
*priv
= hcd_to_priv(hcd
);
841 * When this function is called from the interrupt handler to enqueue
842 * a follow-up packet, the SKIP register gets written and read back
843 * almost immediately. With ISP1761, this register requires a delay of
844 * 195ns between a write and subsequent read (see section 15.1.1.3).
848 skip_map
= reg_read32(hcd
->regs
, HC_ATL_PTD_SKIPMAP_REG
);
851 slot
= __ffs(skip_map
);
853 enqueue_one_atl_qtd(hcd
, qh
, slot
, qtd
);
855 skip_map
&= ~(1 << slot
);
856 reg_write32(hcd
->regs
, HC_ATL_PTD_SKIPMAP_REG
, skip_map
);
859 if (priv
->atl_queued
== 2)
860 reg_write32(hcd
->regs
, HC_INTERRUPT_ENABLE
,
861 INTERRUPT_ENABLE_SOT_MASK
);
864 static void enqueue_an_INT_packet(struct usb_hcd
*hcd
, struct isp1760_qh
*qh
,
865 struct isp1760_qtd
*qtd
)
871 * When this function is called from the interrupt handler to enqueue
872 * a follow-up packet, the SKIP register gets written and read back
873 * almost immediately. With ISP1761, this register requires a delay of
874 * 195ns between a write and subsequent read (see section 15.1.1.3).
878 skip_map
= reg_read32(hcd
->regs
, HC_INT_PTD_SKIPMAP_REG
);
881 slot
= __ffs(skip_map
);
883 enqueue_one_int_qtd(hcd
, qh
, slot
, qtd
);
885 skip_map
&= ~(1 << slot
);
886 reg_write32(hcd
->regs
, HC_INT_PTD_SKIPMAP_REG
, skip_map
);
889 static void isp1760_urb_done(struct usb_hcd
*hcd
, struct urb
*urb
)
890 __releases(priv
->lock
)
891 __acquires(priv
->lock
)
893 struct isp1760_hcd
*priv
= hcd_to_priv(hcd
);
895 if (!urb
->unlinked
) {
896 if (urb
->status
== -EINPROGRESS
)
900 if (usb_pipein(urb
->pipe
) && usb_pipetype(urb
->pipe
) != PIPE_CONTROL
) {
902 for (ptr
= urb
->transfer_buffer
;
903 ptr
< urb
->transfer_buffer
+ urb
->transfer_buffer_length
;
905 flush_dcache_page(virt_to_page(ptr
));
908 /* complete() can reenter this HCD */
909 usb_hcd_unlink_urb_from_ep(hcd
, urb
);
910 spin_unlock(&priv
->lock
);
911 usb_hcd_giveback_urb(hcd
, urb
, urb
->status
);
912 spin_lock(&priv
->lock
);
915 static struct isp1760_qtd
*qtd_alloc(gfp_t flags
, struct urb
*urb
,
918 struct isp1760_qtd
*qtd
;
920 qtd
= kmem_cache_zalloc(qtd_cachep
, flags
);
924 INIT_LIST_HEAD(&qtd
->qtd_list
);
926 qtd
->packet_type
= packet_type
;
931 static void qtd_free(struct isp1760_qtd
*qtd
)
933 WARN_ON(qtd
->payload_addr
);
934 kmem_cache_free(qtd_cachep
, qtd
);
937 static struct isp1760_qtd
*clean_this_qtd(struct isp1760_qtd
*qtd
,
938 struct isp1760_qh
*qh
)
940 struct isp1760_qtd
*tmp_qtd
;
942 if (list_is_last(&qtd
->qtd_list
, &qh
->qtd_list
))
945 tmp_qtd
= list_entry(qtd
->qtd_list
.next
, struct isp1760_qtd
,
947 list_del(&qtd
->qtd_list
);
953 * Remove this QTD from the QH list and free its memory. If this QTD
954 * isn't the last one than remove also his successor(s).
955 * Returns the QTD which is part of an new URB and should be enqueued.
957 static struct isp1760_qtd
*clean_up_qtdlist(struct isp1760_qtd
*qtd
,
958 struct isp1760_qh
*qh
)
964 qtd
= clean_this_qtd(qtd
, qh
);
965 } while (qtd
&& (qtd
->urb
== urb
));
970 static void do_atl_int(struct usb_hcd
*hcd
)
972 struct isp1760_hcd
*priv
= hcd_to_priv(hcd
);
973 u32 done_map
, skip_map
;
978 u32 status
= -EINVAL
;
980 struct isp1760_qtd
*qtd
;
981 struct isp1760_qh
*qh
;
985 done_map
= reg_read32(hcd
->regs
, HC_ATL_PTD_DONEMAP_REG
);
986 skip_map
= reg_read32(hcd
->regs
, HC_ATL_PTD_SKIPMAP_REG
);
992 slot
= __ffs(done_map
);
993 done_map
&= ~(1 << slot
);
994 skip_map
|= (1 << slot
);
996 qtd
= priv
->atl_ints
[slot
].qtd
;
997 qh
= priv
->atl_ints
[slot
].qh
;
1003 ptd_read(hcd
->regs
, ATL_PTD_OFFSET
, slot
, &ptd
);
1005 rl
= (ptd
.dw2
>> 25) & 0x0f;
1006 nakcount
= (ptd
.dw3
>> 19) & 0xf;
1008 /* Transfer Error, *but* active and no HALT -> reload */
1009 if ((ptd
.dw3
& DW3_ERROR_BIT
) && (ptd
.dw3
& DW3_QTD_ACTIVE
) &&
1010 !(ptd
.dw3
& DW3_HALT_BIT
)) {
1012 /* according to ppriv code, we have to
1013 * reload this one if trasfered bytes != requested bytes
1014 * else act like everything went smooth..
1015 * XXX This just doesn't feel right and hasn't
1019 length
= PTD_XFERRED_LENGTH(ptd
.dw3
);
1020 dev_err(hcd
->self
.controller
,
1021 "Should reload now... transferred %d "
1022 "of %zu\n", length
, qtd
->length
);
1026 if (!nakcount
&& (ptd
.dw3
& DW3_QTD_ACTIVE
)) {
1028 * NAKs are handled in HW by the chip. Usually if the
1029 * device is not able to send data fast enough.
1030 * This happens mostly on slower hardware.
1033 /* RL counter = ERR counter */
1034 ptd
.dw3
&= ~(0xf << 19);
1035 ptd
.dw3
|= rl
<< 19;
1036 ptd
.dw3
&= ~(3 << (55 - 32));
1037 ptd
.dw3
|= ERR_COUNTER
<< (55 - 32);
1040 * It is not needed to write skip map back because it
1041 * is unchanged. Just make sure that this entry is
1042 * unskipped once it gets written to the HW.
1044 skip_map
&= ~(1 << slot
);
1046 ptd
.dw0
|= PTD_VALID
;
1047 ptd_write(hcd
->regs
, ATL_PTD_OFFSET
, slot
, &ptd
);
1050 if (priv
->atl_queued
== 2)
1051 reg_write32(hcd
->regs
, HC_INTERRUPT_ENABLE
,
1052 INTERRUPT_ENABLE_SOT_MASK
);
1056 error
= check_error(hcd
, &ptd
);
1059 priv
->atl_ints
[slot
].qh
->toggle
= 0;
1060 priv
->atl_ints
[slot
].qh
->ping
= 0;
1061 qtd
->urb
->status
= -EPIPE
;
1064 printk(KERN_ERR
"Error in %s().\n", __func__
);
1065 printk(KERN_ERR
"IN dw0: %08x dw1: %08x dw2: %08x "
1066 "dw3: %08x dw4: %08x dw5: %08x dw6: "
1068 ptd
.dw0
, ptd
.dw1
, ptd
.dw2
, ptd
.dw3
,
1069 ptd
.dw4
, ptd
.dw5
, ptd
.dw6
, ptd
.dw7
);
1072 priv
->atl_ints
[slot
].qh
->toggle
= ptd
.dw3
& (1 << 25);
1073 priv
->atl_ints
[slot
].qh
->ping
= ptd
.dw3
& (1 << 26);
1076 length
= PTD_XFERRED_LENGTH(ptd
.dw3
);
1078 switch (DW1_GET_PID(ptd
.dw1
)) {
1080 mem_reads8(hcd
->regs
, qtd
->payload_addr
,
1081 qtd
->data_buffer
, length
);
1085 qtd
->urb
->actual_length
+= length
;
1092 priv
->atl_ints
[slot
].qtd
= NULL
;
1093 priv
->atl_ints
[slot
].qh
= NULL
;
1097 reg_write32(hcd
->regs
, HC_ATL_PTD_SKIPMAP_REG
, skip_map
);
1099 if (qtd
->urb
->status
== -EPIPE
) {
1100 /* HALT was received */
1103 qtd
= clean_up_qtdlist(qtd
, qh
);
1104 isp1760_urb_done(hcd
, urb
);
1106 } else if (usb_pipebulk(qtd
->urb
->pipe
) &&
1107 (length
< qtd
->length
)) {
1108 /* short BULK received */
1110 if (qtd
->urb
->transfer_flags
& URB_SHORT_NOT_OK
) {
1111 qtd
->urb
->status
= -EREMOTEIO
;
1112 dev_dbg(hcd
->self
.controller
,
1113 "short bulk, %d instead %zu "
1114 "with URB_SHORT_NOT_OK flag.\n",
1115 length
, qtd
->length
);
1118 if (qtd
->urb
->status
== -EINPROGRESS
)
1119 qtd
->urb
->status
= 0;
1122 qtd
= clean_up_qtdlist(qtd
, qh
);
1123 isp1760_urb_done(hcd
, urb
);
1125 } else if (last_qtd_of_urb(qtd
, qh
)) {
1126 /* that was the last qtd of that URB */
1128 if (qtd
->urb
->status
== -EINPROGRESS
)
1129 qtd
->urb
->status
= 0;
1132 qtd
= clean_up_qtdlist(qtd
, qh
);
1133 isp1760_urb_done(hcd
, urb
);
1136 /* next QTD of this URB */
1138 qtd
= clean_this_qtd(qtd
, qh
);
1143 enqueue_an_ATL_packet(hcd
, qh
, qtd
);
1145 skip_map
= reg_read32(hcd
->regs
, HC_ATL_PTD_SKIPMAP_REG
);
1147 if (priv
->atl_queued
<= 1)
1148 reg_write32(hcd
->regs
, HC_INTERRUPT_ENABLE
,
1149 INTERRUPT_ENABLE_MASK
);
1152 static void do_intl_int(struct usb_hcd
*hcd
)
1154 struct isp1760_hcd
*priv
= hcd_to_priv(hcd
);
1155 u32 done_map
, skip_map
;
1161 struct isp1760_qtd
*qtd
;
1162 struct isp1760_qh
*qh
;
1164 done_map
= reg_read32(hcd
->regs
, HC_INT_PTD_DONEMAP_REG
);
1165 skip_map
= reg_read32(hcd
->regs
, HC_INT_PTD_SKIPMAP_REG
);
1168 slot
= __ffs(done_map
);
1169 done_map
&= ~(1 << slot
);
1170 skip_map
|= (1 << slot
);
1172 qtd
= priv
->int_ints
[slot
].qtd
;
1173 qh
= priv
->int_ints
[slot
].qh
;
1179 ptd_read(hcd
->regs
, INT_PTD_OFFSET
, slot
, &ptd
);
1180 check_int_err_status(hcd
, ptd
.dw4
);
1182 error
= check_error(hcd
, &ptd
);
1185 printk(KERN_ERR
"Error in %s().\n", __func__
);
1186 printk(KERN_ERR
"IN dw0: %08x dw1: %08x dw2: %08x "
1187 "dw3: %08x dw4: %08x dw5: %08x dw6: "
1189 ptd
.dw0
, ptd
.dw1
, ptd
.dw2
, ptd
.dw3
,
1190 ptd
.dw4
, ptd
.dw5
, ptd
.dw6
, ptd
.dw7
);
1192 qtd
->urb
->status
= -EPIPE
;
1193 priv
->int_ints
[slot
].qh
->toggle
= 0;
1194 priv
->int_ints
[slot
].qh
->ping
= 0;
1197 priv
->int_ints
[slot
].qh
->toggle
= ptd
.dw3
& (1 << 25);
1198 priv
->int_ints
[slot
].qh
->ping
= ptd
.dw3
& (1 << 26);
1201 if (qtd
->urb
->dev
->speed
!= USB_SPEED_HIGH
)
1202 length
= PTD_XFERRED_LENGTH_LO(ptd
.dw3
);
1204 length
= PTD_XFERRED_LENGTH(ptd
.dw3
);
1207 switch (DW1_GET_PID(ptd
.dw1
)) {
1209 mem_reads8(hcd
->regs
, qtd
->payload_addr
,
1210 qtd
->data_buffer
, length
);
1213 qtd
->urb
->actual_length
+= length
;
1220 priv
->int_ints
[slot
].qtd
= NULL
;
1221 priv
->int_ints
[slot
].qh
= NULL
;
1223 reg_write32(hcd
->regs
, HC_INT_PTD_SKIPMAP_REG
, skip_map
);
1226 if (qtd
->urb
->status
== -EPIPE
) {
1230 qtd
= clean_up_qtdlist(qtd
, qh
);
1231 isp1760_urb_done(hcd
, urb
);
1233 } else if (last_qtd_of_urb(qtd
, qh
)) {
1235 if (qtd
->urb
->status
== -EINPROGRESS
)
1236 qtd
->urb
->status
= 0;
1239 qtd
= clean_up_qtdlist(qtd
, qh
);
1240 isp1760_urb_done(hcd
, urb
);
1243 /* next QTD of this URB */
1245 qtd
= clean_this_qtd(qtd
, qh
);
1250 enqueue_an_INT_packet(hcd
, qh
, qtd
);
1252 skip_map
= reg_read32(hcd
->regs
, HC_INT_PTD_SKIPMAP_REG
);
1256 static int qtd_fill(struct isp1760_qtd
*qtd
, void *databuffer
, size_t len
)
1258 qtd
->data_buffer
= databuffer
;
1260 if (len
> MAX_PAYLOAD_SIZE
)
1261 len
= MAX_PAYLOAD_SIZE
;
1267 static void qtd_list_free(struct list_head
*qtd_list
)
1269 struct isp1760_qtd
*qtd
, *qtd_next
;
1271 list_for_each_entry_safe(qtd
, qtd_next
, qtd_list
, qtd_list
) {
1272 list_del(&qtd
->qtd_list
);
1278 * Packetize urb->transfer_buffer into list of packets of size wMaxPacketSize.
1279 * Also calculate the PID type (SETUP/IN/OUT) for each packet.
1281 #define max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff)
1282 static void packetize_urb(struct usb_hcd
*hcd
,
1283 struct urb
*urb
, struct list_head
*head
, gfp_t flags
)
1285 struct isp1760_qtd
*qtd
;
1287 int len
, maxpacketsize
;
1291 * URBs map to sequences of QTDs: one logical transaction
1294 if (!urb
->transfer_buffer
&& urb
->transfer_buffer_length
) {
1295 /* XXX This looks like usb storage / SCSI bug */
1296 dev_err(hcd
->self
.controller
,
1297 "buf is null, dma is %08lx len is %d\n",
1298 (long unsigned)urb
->transfer_dma
,
1299 urb
->transfer_buffer_length
);
1303 if (usb_pipein(urb
->pipe
))
1304 packet_type
= IN_PID
;
1306 packet_type
= OUT_PID
;
1308 if (usb_pipecontrol(urb
->pipe
)) {
1309 qtd
= qtd_alloc(flags
, urb
, SETUP_PID
);
1312 qtd_fill(qtd
, urb
->setup_packet
, sizeof(struct usb_ctrlrequest
));
1313 list_add_tail(&qtd
->qtd_list
, head
);
1315 /* for zero length DATA stages, STATUS is always IN */
1316 if (urb
->transfer_buffer_length
== 0)
1317 packet_type
= IN_PID
;
1320 maxpacketsize
= max_packet(usb_maxpacket(urb
->dev
, urb
->pipe
,
1321 usb_pipeout(urb
->pipe
)));
1324 * buffer gets wrapped in one or more qtds;
1325 * last one may be "short" (including zero len)
1326 * and may serve as a control status ack
1328 buf
= urb
->transfer_buffer
;
1329 len
= urb
->transfer_buffer_length
;
1334 qtd
= qtd_alloc(flags
, urb
, packet_type
);
1337 this_qtd_len
= qtd_fill(qtd
, buf
, len
);
1338 list_add_tail(&qtd
->qtd_list
, head
);
1340 len
-= this_qtd_len
;
1341 buf
+= this_qtd_len
;
1348 * control requests may need a terminating data "status" ack;
1349 * bulk ones may need a terminating short packet (zero length).
1351 if (urb
->transfer_buffer_length
!= 0) {
1354 if (usb_pipecontrol(urb
->pipe
)) {
1356 if (packet_type
== IN_PID
)
1357 packet_type
= OUT_PID
;
1359 packet_type
= IN_PID
;
1360 } else if (usb_pipebulk(urb
->pipe
)
1361 && (urb
->transfer_flags
& URB_ZERO_PACKET
)
1362 && !(urb
->transfer_buffer_length
%
1367 qtd
= qtd_alloc(flags
, urb
, packet_type
);
1371 /* never any data in such packets */
1372 qtd_fill(qtd
, NULL
, 0);
1373 list_add_tail(&qtd
->qtd_list
, head
);
1380 qtd_list_free(head
);
1383 static int enqueue_qtdlist(struct usb_hcd
*hcd
, struct urb
*urb
,
1384 struct list_head
*qtd_list
, gfp_t mem_flags
, packet_enqueue
*p
)
1386 struct isp1760_hcd
*priv
= hcd_to_priv(hcd
);
1387 struct isp1760_qtd
*qtd
;
1388 struct isp1760_qh
*qh
= NULL
;
1389 unsigned long flags
;
1393 spin_lock_irqsave(&priv
->lock
, flags
);
1394 if (!HCD_HW_ACCESSIBLE(hcd
)) {
1398 rc
= usb_hcd_link_urb_to_ep(hcd
, urb
);
1402 qh
= urb
->ep
->hcpriv
;
1404 qh
= isp1760_qh_alloc(GFP_ATOMIC
);
1406 usb_hcd_unlink_urb_from_ep(hcd
, urb
);
1410 if (!usb_pipecontrol(urb
->pipe
))
1411 usb_settoggle(urb
->dev
, usb_pipeendpoint(urb
->pipe
),
1412 !usb_pipein(urb
->pipe
), 1);
1413 urb
->ep
->hcpriv
= qh
;
1416 qh_empty
= list_empty(&qh
->qtd_list
);
1417 list_splice_tail(qtd_list
, &qh
->qtd_list
);
1419 qtd
= list_entry(qtd_list
->next
, struct isp1760_qtd
, qtd_list
);
1424 spin_unlock_irqrestore(&priv
->lock
, flags
);
1426 qtd_list_free(qtd_list
);
1430 static int isp1760_urb_enqueue(struct usb_hcd
*hcd
, struct urb
*urb
,
1433 struct list_head qtd_list
;
1436 INIT_LIST_HEAD(&qtd_list
);
1438 switch (usb_pipetype(urb
->pipe
)) {
1441 pe
= enqueue_an_ATL_packet
;
1444 case PIPE_INTERRUPT
:
1445 pe
= enqueue_an_INT_packet
;
1448 case PIPE_ISOCHRONOUS
:
1449 dev_err(hcd
->self
.controller
, "PIPE_ISOCHRONOUS ain't supported\n");
1454 packetize_urb(hcd
, urb
, &qtd_list
, mem_flags
);
1455 if (list_empty(&qtd_list
))
1458 return enqueue_qtdlist(hcd
, urb
, &qtd_list
, mem_flags
, pe
);
1461 static int isp1760_urb_dequeue(struct usb_hcd
*hcd
, struct urb
*urb
, int status
)
1463 struct isp1760_hcd
*priv
= hcd_to_priv(hcd
);
1464 struct inter_packet_info
*ints
;
1466 u32 reg_base
, skip_reg
;
1467 unsigned long flags
;
1471 switch (usb_pipetype(urb
->pipe
)) {
1472 case PIPE_ISOCHRONOUS
:
1476 case PIPE_INTERRUPT
:
1477 ints
= priv
->int_ints
;
1478 reg_base
= INT_PTD_OFFSET
;
1479 skip_reg
= HC_INT_PTD_SKIPMAP_REG
;
1480 pe
= enqueue_an_INT_packet
;
1484 ints
= priv
->atl_ints
;
1485 reg_base
= ATL_PTD_OFFSET
;
1486 skip_reg
= HC_ATL_PTD_SKIPMAP_REG
;
1487 pe
= enqueue_an_ATL_packet
;
1491 memset(&ptd
, 0, sizeof(ptd
));
1492 spin_lock_irqsave(&priv
->lock
, flags
);
1494 for (i
= 0; i
< 32; i
++) {
1497 WARN_ON(!ints
[i
].qtd
);
1499 if (ints
[i
].qtd
->urb
== urb
) {
1501 struct isp1760_qtd
*qtd
;
1502 struct isp1760_qh
*qh
;
1504 skip_map
= reg_read32(hcd
->regs
, skip_reg
);
1506 reg_write32(hcd
->regs
, skip_reg
, skip_map
);
1508 ptd_write(hcd
->regs
, reg_base
, i
, &ptd
);
1514 qtd
= clean_up_qtdlist(qtd
, qh
);
1519 urb
->status
= status
;
1520 isp1760_urb_done(hcd
, urb
);
1526 struct isp1760_qtd
*qtd
;
1528 list_for_each_entry(qtd
, &ints
[i
].qtd
->qtd_list
,
1530 if (qtd
->urb
== urb
) {
1531 clean_up_qtdlist(qtd
, ints
[i
].qh
);
1532 isp1760_urb_done(hcd
, urb
);
1538 /* We found the urb before the last slot */
1544 spin_unlock_irqrestore(&priv
->lock
, flags
);
1548 static irqreturn_t
isp1760_irq(struct usb_hcd
*hcd
)
1550 struct isp1760_hcd
*priv
= hcd_to_priv(hcd
);
1552 irqreturn_t irqret
= IRQ_NONE
;
1554 spin_lock(&priv
->lock
);
1556 if (!(hcd
->state
& HC_STATE_RUNNING
))
1559 imask
= reg_read32(hcd
->regs
, HC_INTERRUPT_REG
);
1560 if (unlikely(!imask
))
1563 reg_write32(hcd
->regs
, HC_INTERRUPT_REG
, imask
);
1564 if (imask
& (HC_ATL_INT
| HC_SOT_INT
))
1567 if (imask
& HC_INTL_INT
)
1570 irqret
= IRQ_HANDLED
;
1572 spin_unlock(&priv
->lock
);
1576 static int isp1760_hub_status_data(struct usb_hcd
*hcd
, char *buf
)
1578 struct isp1760_hcd
*priv
= hcd_to_priv(hcd
);
1579 u32 temp
, status
= 0;
1582 unsigned long flags
;
1584 /* if !USB_SUSPEND, root hub timers won't get shut down ... */
1585 if (!HC_IS_RUNNING(hcd
->state
))
1588 /* init status to no-changes */
1592 spin_lock_irqsave(&priv
->lock
, flags
);
1593 temp
= reg_read32(hcd
->regs
, HC_PORTSC1
);
1595 if (temp
& PORT_OWNER
) {
1596 if (temp
& PORT_CSC
) {
1598 reg_write32(hcd
->regs
, HC_PORTSC1
, temp
);
1604 * Return status information even for ports with OWNER set.
1605 * Otherwise khubd wouldn't see the disconnect event when a
1606 * high-speed device is switched over to the companion
1607 * controller by the user.
1610 if ((temp
& mask
) != 0
1611 || ((temp
& PORT_RESUME
) != 0
1612 && time_after_eq(jiffies
,
1613 priv
->reset_done
))) {
1614 buf
[0] |= 1 << (0 + 1);
1617 /* FIXME autosuspend idle root hubs */
1619 spin_unlock_irqrestore(&priv
->lock
, flags
);
1620 return status
? retval
: 0;
1623 static void isp1760_hub_descriptor(struct isp1760_hcd
*priv
,
1624 struct usb_hub_descriptor
*desc
)
1626 int ports
= HCS_N_PORTS(priv
->hcs_params
);
1629 desc
->bDescriptorType
= 0x29;
1630 /* priv 1.0, 2.3.9 says 20ms max */
1631 desc
->bPwrOn2PwrGood
= 10;
1632 desc
->bHubContrCurrent
= 0;
1634 desc
->bNbrPorts
= ports
;
1635 temp
= 1 + (ports
/ 8);
1636 desc
->bDescLength
= 7 + 2 * temp
;
1638 /* ports removable, and usb 1.0 legacy PortPwrCtrlMask */
1639 memset(&desc
->u
.hs
.DeviceRemovable
[0], 0, temp
);
1640 memset(&desc
->u
.hs
.DeviceRemovable
[temp
], 0xff, temp
);
1642 /* per-port overcurrent reporting */
1644 if (HCS_PPC(priv
->hcs_params
))
1645 /* per-port power control */
1648 /* no power switching */
1650 desc
->wHubCharacteristics
= cpu_to_le16(temp
);
1653 #define PORT_WAKE_BITS (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E)
1655 static int check_reset_complete(struct usb_hcd
*hcd
, int index
,
1658 if (!(port_status
& PORT_CONNECT
))
1661 /* if reset finished and it's still not enabled -- handoff */
1662 if (!(port_status
& PORT_PE
)) {
1664 dev_err(hcd
->self
.controller
,
1665 "port %d full speed --> companion\n",
1668 port_status
|= PORT_OWNER
;
1669 port_status
&= ~PORT_RWC_BITS
;
1670 reg_write32(hcd
->regs
, HC_PORTSC1
, port_status
);
1673 dev_err(hcd
->self
.controller
, "port %d high speed\n",
1679 static int isp1760_hub_control(struct usb_hcd
*hcd
, u16 typeReq
,
1680 u16 wValue
, u16 wIndex
, char *buf
, u16 wLength
)
1682 struct isp1760_hcd
*priv
= hcd_to_priv(hcd
);
1683 int ports
= HCS_N_PORTS(priv
->hcs_params
);
1685 unsigned long flags
;
1690 * FIXME: support SetPortFeatures USB_PORT_FEAT_INDICATOR.
1691 * HCS_INDICATOR may say we can change LEDs to off/amber/green.
1692 * (track current state ourselves) ... blink for diagnostics,
1693 * power, "this is the one", etc. EHCI spec supports this.
1696 spin_lock_irqsave(&priv
->lock
, flags
);
1698 case ClearHubFeature
:
1700 case C_HUB_LOCAL_POWER
:
1701 case C_HUB_OVER_CURRENT
:
1702 /* no hub-wide feature/status flags */
1708 case ClearPortFeature
:
1709 if (!wIndex
|| wIndex
> ports
)
1712 temp
= reg_read32(hcd
->regs
, HC_PORTSC1
);
1715 * Even if OWNER is set, so the port is owned by the
1716 * companion controller, khubd needs to be able to clear
1717 * the port-change status bits (especially
1718 * USB_PORT_STAT_C_CONNECTION).
1722 case USB_PORT_FEAT_ENABLE
:
1723 reg_write32(hcd
->regs
, HC_PORTSC1
, temp
& ~PORT_PE
);
1725 case USB_PORT_FEAT_C_ENABLE
:
1728 case USB_PORT_FEAT_SUSPEND
:
1729 if (temp
& PORT_RESET
)
1732 if (temp
& PORT_SUSPEND
) {
1733 if ((temp
& PORT_PE
) == 0)
1735 /* resume signaling for 20 msec */
1736 temp
&= ~(PORT_RWC_BITS
);
1737 reg_write32(hcd
->regs
, HC_PORTSC1
,
1738 temp
| PORT_RESUME
);
1739 priv
->reset_done
= jiffies
+
1740 msecs_to_jiffies(20);
1743 case USB_PORT_FEAT_C_SUSPEND
:
1744 /* we auto-clear this feature */
1746 case USB_PORT_FEAT_POWER
:
1747 if (HCS_PPC(priv
->hcs_params
))
1748 reg_write32(hcd
->regs
, HC_PORTSC1
,
1749 temp
& ~PORT_POWER
);
1751 case USB_PORT_FEAT_C_CONNECTION
:
1752 reg_write32(hcd
->regs
, HC_PORTSC1
, temp
| PORT_CSC
);
1754 case USB_PORT_FEAT_C_OVER_CURRENT
:
1757 case USB_PORT_FEAT_C_RESET
:
1758 /* GetPortStatus clears reset */
1763 reg_read32(hcd
->regs
, HC_USBCMD
);
1765 case GetHubDescriptor
:
1766 isp1760_hub_descriptor(priv
, (struct usb_hub_descriptor
*)
1770 /* no hub-wide feature/status flags */
1774 if (!wIndex
|| wIndex
> ports
)
1778 temp
= reg_read32(hcd
->regs
, HC_PORTSC1
);
1780 /* wPortChange bits */
1781 if (temp
& PORT_CSC
)
1782 status
|= USB_PORT_STAT_C_CONNECTION
<< 16;
1785 /* whoever resumes must GetPortStatus to complete it!! */
1786 if (temp
& PORT_RESUME
) {
1787 dev_err(hcd
->self
.controller
, "Port resume should be skipped.\n");
1789 /* Remote Wakeup received? */
1790 if (!priv
->reset_done
) {
1791 /* resume signaling for 20 msec */
1792 priv
->reset_done
= jiffies
1793 + msecs_to_jiffies(20);
1794 /* check the port again */
1795 mod_timer(&hcd
->rh_timer
, priv
->reset_done
);
1798 /* resume completed? */
1799 else if (time_after_eq(jiffies
,
1800 priv
->reset_done
)) {
1801 status
|= USB_PORT_STAT_C_SUSPEND
<< 16;
1802 priv
->reset_done
= 0;
1804 /* stop resume signaling */
1805 temp
= reg_read32(hcd
->regs
, HC_PORTSC1
);
1806 reg_write32(hcd
->regs
, HC_PORTSC1
,
1807 temp
& ~(PORT_RWC_BITS
| PORT_RESUME
));
1808 retval
= handshake(hcd
, HC_PORTSC1
,
1809 PORT_RESUME
, 0, 2000 /* 2msec */);
1811 dev_err(hcd
->self
.controller
,
1812 "port %d resume error %d\n",
1813 wIndex
+ 1, retval
);
1816 temp
&= ~(PORT_SUSPEND
|PORT_RESUME
|(3<<10));
1820 /* whoever resets must GetPortStatus to complete it!! */
1821 if ((temp
& PORT_RESET
)
1822 && time_after_eq(jiffies
,
1823 priv
->reset_done
)) {
1824 status
|= USB_PORT_STAT_C_RESET
<< 16;
1825 priv
->reset_done
= 0;
1827 /* force reset to complete */
1828 reg_write32(hcd
->regs
, HC_PORTSC1
, temp
& ~PORT_RESET
);
1829 /* REVISIT: some hardware needs 550+ usec to clear
1830 * this bit; seems too long to spin routinely...
1832 retval
= handshake(hcd
, HC_PORTSC1
,
1833 PORT_RESET
, 0, 750);
1835 dev_err(hcd
->self
.controller
, "port %d reset error %d\n",
1836 wIndex
+ 1, retval
);
1840 /* see what we found out */
1841 temp
= check_reset_complete(hcd
, wIndex
,
1842 reg_read32(hcd
->regs
, HC_PORTSC1
));
1845 * Even if OWNER is set, there's no harm letting khubd
1846 * see the wPortStatus values (they should all be 0 except
1847 * for PORT_POWER anyway).
1850 if (temp
& PORT_OWNER
)
1851 dev_err(hcd
->self
.controller
, "PORT_OWNER is set\n");
1853 if (temp
& PORT_CONNECT
) {
1854 status
|= USB_PORT_STAT_CONNECTION
;
1855 /* status may be from integrated TT */
1856 status
|= USB_PORT_STAT_HIGH_SPEED
;
1859 status
|= USB_PORT_STAT_ENABLE
;
1860 if (temp
& (PORT_SUSPEND
|PORT_RESUME
))
1861 status
|= USB_PORT_STAT_SUSPEND
;
1862 if (temp
& PORT_RESET
)
1863 status
|= USB_PORT_STAT_RESET
;
1864 if (temp
& PORT_POWER
)
1865 status
|= USB_PORT_STAT_POWER
;
1867 put_unaligned(cpu_to_le32(status
), (__le32
*) buf
);
1871 case C_HUB_LOCAL_POWER
:
1872 case C_HUB_OVER_CURRENT
:
1873 /* no hub-wide feature/status flags */
1879 case SetPortFeature
:
1880 selector
= wIndex
>> 8;
1882 if (!wIndex
|| wIndex
> ports
)
1885 temp
= reg_read32(hcd
->regs
, HC_PORTSC1
);
1886 if (temp
& PORT_OWNER
)
1889 /* temp &= ~PORT_RWC_BITS; */
1891 case USB_PORT_FEAT_ENABLE
:
1892 reg_write32(hcd
->regs
, HC_PORTSC1
, temp
| PORT_PE
);
1895 case USB_PORT_FEAT_SUSPEND
:
1896 if ((temp
& PORT_PE
) == 0
1897 || (temp
& PORT_RESET
) != 0)
1900 reg_write32(hcd
->regs
, HC_PORTSC1
, temp
| PORT_SUSPEND
);
1902 case USB_PORT_FEAT_POWER
:
1903 if (HCS_PPC(priv
->hcs_params
))
1904 reg_write32(hcd
->regs
, HC_PORTSC1
,
1907 case USB_PORT_FEAT_RESET
:
1908 if (temp
& PORT_RESUME
)
1910 /* line status bits may report this as low speed,
1911 * which can be fine if this root hub has a
1912 * transaction translator built in.
1914 if ((temp
& (PORT_PE
|PORT_CONNECT
)) == PORT_CONNECT
1915 && PORT_USB11(temp
)) {
1922 * caller must wait, then call GetPortStatus
1923 * usb 2.0 spec says 50 ms resets on root
1925 priv
->reset_done
= jiffies
+
1926 msecs_to_jiffies(50);
1928 reg_write32(hcd
->regs
, HC_PORTSC1
, temp
);
1933 reg_read32(hcd
->regs
, HC_USBCMD
);
1938 /* "stall" on error */
1941 spin_unlock_irqrestore(&priv
->lock
, flags
);
1945 static void isp1760_endpoint_disable(struct usb_hcd
*hcd
,
1946 struct usb_host_endpoint
*ep
)
1948 struct isp1760_hcd
*priv
= hcd_to_priv(hcd
);
1949 struct isp1760_qh
*qh
;
1950 struct isp1760_qtd
*qtd
;
1951 unsigned long flags
;
1953 spin_lock_irqsave(&priv
->lock
, flags
);
1960 /* more than entry might get removed */
1961 if (list_empty(&qh
->qtd_list
))
1964 qtd
= list_first_entry(&qh
->qtd_list
, struct isp1760_qtd
,
1967 if (qtd
->status
& URB_ENQUEUED
) {
1968 spin_unlock_irqrestore(&priv
->lock
, flags
);
1969 isp1760_urb_dequeue(hcd
, qtd
->urb
, -ECONNRESET
);
1970 spin_lock_irqsave(&priv
->lock
, flags
);
1975 clean_up_qtdlist(qtd
, qh
);
1976 urb
->status
= -ECONNRESET
;
1977 isp1760_urb_done(hcd
, urb
);
1982 /* remove requests and leak them.
1983 * ATL are pretty fast done, INT could take a while...
1984 * The latter shoule be removed
1987 spin_unlock_irqrestore(&priv
->lock
, flags
);
1990 static int isp1760_get_frame(struct usb_hcd
*hcd
)
1992 struct isp1760_hcd
*priv
= hcd_to_priv(hcd
);
1995 fr
= reg_read32(hcd
->regs
, HC_FRINDEX
);
1996 return (fr
>> 3) % priv
->periodic_size
;
1999 static void isp1760_stop(struct usb_hcd
*hcd
)
2001 struct isp1760_hcd
*priv
= hcd_to_priv(hcd
);
2004 isp1760_hub_control(hcd
, ClearPortFeature
, USB_PORT_FEAT_POWER
, 1,
2008 spin_lock_irq(&priv
->lock
);
2011 temp
= reg_read32(hcd
->regs
, HC_HW_MODE_CTRL
);
2012 reg_write32(hcd
->regs
, HC_HW_MODE_CTRL
, temp
&= ~HW_GLOBAL_INTR_EN
);
2013 spin_unlock_irq(&priv
->lock
);
2015 reg_write32(hcd
->regs
, HC_CONFIGFLAG
, 0);
2018 static void isp1760_shutdown(struct usb_hcd
*hcd
)
2023 temp
= reg_read32(hcd
->regs
, HC_HW_MODE_CTRL
);
2024 reg_write32(hcd
->regs
, HC_HW_MODE_CTRL
, temp
&= ~HW_GLOBAL_INTR_EN
);
2026 command
= reg_read32(hcd
->regs
, HC_USBCMD
);
2027 command
&= ~CMD_RUN
;
2028 reg_write32(hcd
->regs
, HC_USBCMD
, command
);
2031 static const struct hc_driver isp1760_hc_driver
= {
2032 .description
= "isp1760-hcd",
2033 .product_desc
= "NXP ISP1760 USB Host Controller",
2034 .hcd_priv_size
= sizeof(struct isp1760_hcd
),
2036 .flags
= HCD_MEMORY
| HCD_USB2
,
2037 .reset
= isp1760_hc_setup
,
2038 .start
= isp1760_run
,
2039 .stop
= isp1760_stop
,
2040 .shutdown
= isp1760_shutdown
,
2041 .urb_enqueue
= isp1760_urb_enqueue
,
2042 .urb_dequeue
= isp1760_urb_dequeue
,
2043 .endpoint_disable
= isp1760_endpoint_disable
,
2044 .get_frame_number
= isp1760_get_frame
,
2045 .hub_status_data
= isp1760_hub_status_data
,
2046 .hub_control
= isp1760_hub_control
,
2049 int __init
init_kmem_once(void)
2051 qtd_cachep
= kmem_cache_create("isp1760_qtd",
2052 sizeof(struct isp1760_qtd
), 0, SLAB_TEMPORARY
|
2053 SLAB_MEM_SPREAD
, NULL
);
2058 qh_cachep
= kmem_cache_create("isp1760_qh", sizeof(struct isp1760_qh
),
2059 0, SLAB_TEMPORARY
| SLAB_MEM_SPREAD
, NULL
);
2062 kmem_cache_destroy(qtd_cachep
);
2069 void deinit_kmem_cache(void)
2071 kmem_cache_destroy(qtd_cachep
);
2072 kmem_cache_destroy(qh_cachep
);
2075 struct usb_hcd
*isp1760_register(phys_addr_t res_start
, resource_size_t res_len
,
2076 int irq
, unsigned long irqflags
,
2077 struct device
*dev
, const char *busname
,
2078 unsigned int devflags
)
2080 struct usb_hcd
*hcd
;
2081 struct isp1760_hcd
*priv
;
2085 return ERR_PTR(-ENODEV
);
2087 /* prevent usb-core allocating DMA pages */
2088 dev
->dma_mask
= NULL
;
2090 hcd
= usb_create_hcd(&isp1760_hc_driver
, dev
, dev_name(dev
));
2092 return ERR_PTR(-ENOMEM
);
2094 priv
= hcd_to_priv(hcd
);
2095 priv
->devflags
= devflags
;
2097 hcd
->regs
= ioremap(res_start
, res_len
);
2104 hcd
->rsrc_start
= res_start
;
2105 hcd
->rsrc_len
= res_len
;
2107 ret
= usb_add_hcd(hcd
, irq
, irqflags
);
2119 return ERR_PTR(ret
);
2122 MODULE_DESCRIPTION("Driver for the ISP1760 USB-controller from NXP");
2123 MODULE_AUTHOR("Sebastian Siewior <bigeasy@linuxtronix.de>");
2124 MODULE_LICENSE("GPL v2");