3 * Copyright (c) 2005-2006, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
16 * Place - Suite 330, Boston, MA 02111-1307 USA.
20 #include <linux/pci.h>
21 #include <linux/delay.h>
24 #include <asm/hardware.h>
25 #include <asm/sizes.h>
26 #include <asm/mach/pci.h>
27 #include <asm/arch/pci.h>
29 #define IOP13XX_PCI_DEBUG 0
30 #define PRINTK(x...) ((void)(IOP13XX_PCI_DEBUG && printk(x)))
32 u32 iop13xx_atux_pmmr_offset
; /* This offset can change based on strapping */
33 u32 iop13xx_atue_pmmr_offset
; /* This offset can change based on strapping */
34 static struct pci_bus
*pci_bus_atux
= 0;
35 static struct pci_bus
*pci_bus_atue
= 0;
36 u32 iop13xx_atue_mem_base
;
37 u32 iop13xx_atux_mem_base
;
38 size_t iop13xx_atue_mem_size
;
39 size_t iop13xx_atux_mem_size
;
40 unsigned long iop13xx_pcibios_min_io
= 0;
41 unsigned long iop13xx_pcibios_min_mem
= 0;
43 EXPORT_SYMBOL(iop13xx_atue_mem_base
);
44 EXPORT_SYMBOL(iop13xx_atux_mem_base
);
45 EXPORT_SYMBOL(iop13xx_atue_mem_size
);
46 EXPORT_SYMBOL(iop13xx_atux_mem_size
);
48 int init_atu
= 0; /* Flag to select which ATU(s) to initialize / disable */
49 static unsigned long atux_trhfa_timeout
= 0; /* Trhfa = RST# high to first
52 /* Scan the initialized busses and ioremap the requested memory range
54 void iop13xx_map_pci_memory(void)
59 resource_size_t end
= 0;
61 for (atu
= 0; atu
< 2; atu
++) {
62 bus
= atu
? pci_bus_atue
: pci_bus_atux
;
64 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
69 max
= DEVICE_COUNT_RESOURCE
;
71 for (i
= 0; i
< max
; i
++) {
72 struct resource
*res
= &dev
->resource
[i
];
73 if (res
->flags
& IORESOURCE_MEM
)
74 end
= max(res
->end
, end
);
80 iop13xx_atux_mem_size
=
81 (end
- IOP13XX_PCIX_LOWER_MEM_RA
) + 1;
83 /* 16MB align the request */
84 if (iop13xx_atux_mem_size
& (SZ_16M
- 1)) {
85 iop13xx_atux_mem_size
&= ~(SZ_16M
- 1);
86 iop13xx_atux_mem_size
+= SZ_16M
;
90 iop13xx_atux_mem_base
=
92 __phys_to_pfn(IOP13XX_PCIX_LOWER_MEM_PA
)
93 , 0, iop13xx_atux_mem_size
, 0);
94 if (!iop13xx_atux_mem_base
) {
95 printk("%s: atux allocation "
96 "failed\n", __FUNCTION__
);
100 iop13xx_atux_mem_size
= 0;
101 PRINTK("%s: atu: %d bus_size: %d mem_base: %x\n",
102 __FUNCTION__
, atu
, iop13xx_atux_mem_size
,
103 iop13xx_atux_mem_base
);
106 iop13xx_atue_mem_size
=
107 (end
- IOP13XX_PCIE_LOWER_MEM_RA
) + 1;
109 /* 16MB align the request */
110 if (iop13xx_atue_mem_size
& (SZ_16M
- 1)) {
111 iop13xx_atue_mem_size
&= ~(SZ_16M
- 1);
112 iop13xx_atue_mem_size
+= SZ_16M
;
116 iop13xx_atue_mem_base
=
118 __phys_to_pfn(IOP13XX_PCIE_LOWER_MEM_PA
)
119 , 0, iop13xx_atue_mem_size
, 0);
120 if (!iop13xx_atue_mem_base
) {
121 printk("%s: atue allocation "
122 "failed\n", __FUNCTION__
);
126 iop13xx_atue_mem_size
= 0;
127 PRINTK("%s: atu: %d bus_size: %d mem_base: %x\n",
128 __FUNCTION__
, atu
, iop13xx_atue_mem_size
,
129 iop13xx_atue_mem_base
);
133 printk("%s: Initialized (%uM @ resource/virtual: %08lx/%08x)\n",
134 atu
? "ATUE" : "ATUX",
135 (atu
? iop13xx_atue_mem_size
: iop13xx_atux_mem_size
) /
137 atu
? IOP13XX_PCIE_LOWER_MEM_RA
:
138 IOP13XX_PCIX_LOWER_MEM_RA
,
139 atu
? iop13xx_atue_mem_base
:
140 iop13xx_atux_mem_base
);
147 static inline int iop13xx_atu_function(int atu
)
150 /* the function number depends on the value of the
151 * IOP13XX_INTERFACE_SEL_PCIX reset strap
152 * see C-Spec section 3.17
155 case IOP13XX_INIT_ATU_ATUX
:
156 if (__raw_readl(IOP13XX_ESSR0
) & IOP13XX_INTERFACE_SEL_PCIX
)
161 case IOP13XX_INIT_ATU_ATUE
:
162 if (__raw_readl(IOP13XX_ESSR0
) & IOP13XX_INTERFACE_SEL_PCIX
)
174 /* iop13xx_atux_cfg_address - format a configuration address for atux
175 * @bus: Target bus to access
176 * @devfn: Combined device number and function number
177 * @where: Desired register's address offset
179 * Convert the parameters to a configuration address formatted
180 * according the PCI-X 2.0 specification
182 static u32
iop13xx_atux_cfg_address(struct pci_bus
*bus
, int devfn
, int where
)
184 struct pci_sys_data
*sys
= bus
->sysdata
;
187 if (sys
->busnr
== bus
->number
)
188 addr
= 1 << (PCI_SLOT(devfn
) + 16) | (PCI_SLOT(devfn
) << 11);
190 addr
= bus
->number
<< 16 | PCI_SLOT(devfn
) << 11 | 1;
192 addr
|= PCI_FUNC(devfn
) << 8 | ((where
& 0xff) & ~3);
193 addr
|= ((where
& 0xf00) >> 8) << 24; /* upper register number */
198 /* iop13xx_atue_cfg_address - format a configuration address for atue
199 * @bus: Target bus to access
200 * @devfn: Combined device number and function number
201 * @where: Desired register's address offset
203 * Convert the parameters to an address usable by the ATUE_OCCAR
205 static u32
iop13xx_atue_cfg_address(struct pci_bus
*bus
, int devfn
, int where
)
207 struct pci_sys_data
*sys
= bus
->sysdata
;
210 PRINTK("iop13xx_atue_cfg_address: bus: %d dev: %d func: %d",
211 bus
->number
, PCI_SLOT(devfn
), PCI_FUNC(devfn
));
212 addr
= ((u32
) bus
->number
) << IOP13XX_ATUE_OCCAR_BUS_NUM
|
213 ((u32
) PCI_SLOT(devfn
)) << IOP13XX_ATUE_OCCAR_DEV_NUM
|
214 ((u32
) PCI_FUNC(devfn
)) << IOP13XX_ATUE_OCCAR_FUNC_NUM
|
217 if (sys
->busnr
!= bus
->number
)
218 addr
|= 1; /* type 1 access */
223 /* This routine checks the status of the last configuration cycle. If an error
224 * was detected it returns >0, else it returns a 0. The errors being checked
225 * are parity, master abort, target abort (master and target). These types of
226 * errors occure during a config cycle where there is no device, like during
227 * the discovery stage.
229 static int iop13xx_atux_pci_status(int clear
)
235 * Check the status registers.
237 status
= __raw_readw(IOP13XX_ATUX_ATUSR
);
238 if (status
& IOP_PCI_STATUS_ERROR
)
240 PRINTK("\t\t\tPCI error: ATUSR %#08x", status
);
242 __raw_writew(status
& IOP_PCI_STATUS_ERROR
,
246 status
= __raw_readl(IOP13XX_ATUX_ATUISR
);
247 if (status
& IOP13XX_ATUX_ATUISR_ERROR
)
249 PRINTK("\t\t\tPCI error interrupt: ATUISR %#08x", status
);
251 __raw_writel(status
& IOP13XX_ATUX_ATUISR_ERROR
,
252 IOP13XX_ATUX_ATUISR
);
258 /* Simply write the address register and read the configuration
259 * data. Note that the data dependency on %0 encourages an abort
260 * to be detected before we return.
262 static inline u32
iop13xx_atux_read(unsigned long addr
)
266 __asm__
__volatile__(
271 : "r" (addr
), "r" (IOP13XX_ATUX_OCCAR
), "r" (IOP13XX_ATUX_OCCDR
));
276 /* The read routines must check the error status of the last configuration
277 * cycle. If there was an error, the routine returns all hex f's.
280 iop13xx_atux_read_config(struct pci_bus
*bus
, unsigned int devfn
, int where
,
281 int size
, u32
*value
)
283 unsigned long addr
= iop13xx_atux_cfg_address(bus
, devfn
, where
);
284 u32 val
= iop13xx_atux_read(addr
) >> ((where
& 3) * 8);
286 if (iop13xx_atux_pci_status(1) || is_atux_occdr_error()) {
287 __raw_writel(__raw_readl(IOP13XX_XBG_BECSR
) & 3,
294 return PCIBIOS_SUCCESSFUL
;
298 iop13xx_atux_write_config(struct pci_bus
*bus
, unsigned int devfn
, int where
,
301 unsigned long addr
= iop13xx_atux_cfg_address(bus
, devfn
, where
);
305 val
= iop13xx_atux_read(addr
);
306 if (!iop13xx_atux_pci_status(1) == 0)
307 return PCIBIOS_SUCCESSFUL
;
309 where
= (where
& 3) * 8;
312 val
&= ~(0xff << where
);
314 val
&= ~(0xffff << where
);
316 __raw_writel(val
| value
<< where
, IOP13XX_ATUX_OCCDR
);
318 __raw_writel(addr
, IOP13XX_ATUX_OCCAR
);
319 __raw_writel(value
, IOP13XX_ATUX_OCCDR
);
322 return PCIBIOS_SUCCESSFUL
;
325 static struct pci_ops iop13xx_atux_ops
= {
326 .read
= iop13xx_atux_read_config
,
327 .write
= iop13xx_atux_write_config
,
330 /* This routine checks the status of the last configuration cycle. If an error
331 * was detected it returns >0, else it returns a 0. The errors being checked
332 * are parity, master abort, target abort (master and target). These types of
333 * errors occure during a config cycle where there is no device, like during
334 * the discovery stage.
336 static int iop13xx_atue_pci_status(int clear
)
342 * Check the status registers.
345 /* standard pci status register */
346 status
= __raw_readw(IOP13XX_ATUE_ATUSR
);
347 if (status
& IOP_PCI_STATUS_ERROR
) {
348 PRINTK("\t\t\tPCI error: ATUSR %#08x", status
);
350 __raw_writew(status
& IOP_PCI_STATUS_ERROR
,
355 /* check the normal status bits in the ATUISR */
356 status
= __raw_readl(IOP13XX_ATUE_ATUISR
);
357 if (status
& IOP13XX_ATUE_ATUISR_ERROR
) {
358 PRINTK("\t\t\tPCI error: ATUISR %#08x", status
);
360 __raw_writew(status
& IOP13XX_ATUE_ATUISR_ERROR
,
361 IOP13XX_ATUE_ATUISR
);
364 /* check the PCI-E status if the ATUISR reports an interface error */
365 if (status
& IOP13XX_ATUE_STAT_PCI_IFACE_ERR
) {
366 /* get the unmasked errors */
367 status
= __raw_readl(IOP13XX_ATUE_PIE_STS
) &
368 ~(__raw_readl(IOP13XX_ATUE_PIE_MSK
));
371 PRINTK("\t\t\tPCI-E error: ATUE_PIE_STS %#08x",
372 __raw_readl(IOP13XX_ATUE_PIE_STS
));
375 PRINTK("\t\t\tPCI-E error: ATUE_PIE_STS %#08x",
376 __raw_readl(IOP13XX_ATUE_PIE_STS
));
377 PRINTK("\t\t\tPCI-E error: ATUE_PIE_MSK %#08x",
378 __raw_readl(IOP13XX_ATUE_PIE_MSK
));
383 __raw_writel(status
, IOP13XX_ATUE_PIE_STS
);
390 static inline int __init
391 iop13xx_pcie_map_irq(struct pci_dev
*dev
, u8 idsel
, u8 pin
)
396 case 1: return ATUE_INTA
;
397 case 2: return ATUE_INTB
;
398 case 3: return ATUE_INTC
;
399 case 4: return ATUE_INTD
;
404 static inline u32
iop13xx_atue_read(unsigned long addr
)
408 __raw_writel(addr
, IOP13XX_ATUE_OCCAR
);
409 val
= __raw_readl(IOP13XX_ATUE_OCCDR
);
416 /* The read routines must check the error status of the last configuration
417 * cycle. If there was an error, the routine returns all hex f's.
420 iop13xx_atue_read_config(struct pci_bus
*bus
, unsigned int devfn
, int where
,
421 int size
, u32
*value
)
424 unsigned long addr
= iop13xx_atue_cfg_address(bus
, devfn
, where
);
426 /* Hide device numbers > 0 on the local PCI-E bus (Type 0 access) */
427 if (!PCI_SLOT(devfn
) || (addr
& 1)) {
428 val
= iop13xx_atue_read(addr
) >> ((where
& 3) * 8);
429 if( iop13xx_atue_pci_status(1) || is_atue_occdr_error() ) {
430 __raw_writel(__raw_readl(IOP13XX_XBG_BECSR
) & 3,
435 PRINTK("addr=%#0lx, val=%#010x", addr
, val
);
441 return PCIBIOS_SUCCESSFUL
;
445 iop13xx_atue_write_config(struct pci_bus
*bus
, unsigned int devfn
, int where
,
448 unsigned long addr
= iop13xx_atue_cfg_address(bus
, devfn
, where
);
452 val
= iop13xx_atue_read(addr
);
453 if (!iop13xx_atue_pci_status(1) == 0)
454 return PCIBIOS_SUCCESSFUL
;
456 where
= (where
& 3) * 8;
459 val
&= ~(0xff << where
);
461 val
&= ~(0xffff << where
);
463 __raw_writel(val
| value
<< where
, IOP13XX_ATUE_OCCDR
);
465 __raw_writel(addr
, IOP13XX_ATUE_OCCAR
);
466 __raw_writel(value
, IOP13XX_ATUE_OCCDR
);
469 return PCIBIOS_SUCCESSFUL
;
472 static struct pci_ops iop13xx_atue_ops
= {
473 .read
= iop13xx_atue_read_config
,
474 .write
= iop13xx_atue_write_config
,
477 /* When a PCI device does not exist during config cycles, the XScale gets a
478 * bus error instead of returning 0xffffffff. We can't rely on the ATU status
479 * bits to tell us that it was indeed a configuration cycle that caused this
480 * error especially in the case when the ATUE link is down. Instead we rely
481 * on data from the south XSI bridge to validate the abort
484 iop13xx_pci_abort(unsigned long addr
, unsigned int fsr
, struct pt_regs
*regs
)
486 PRINTK("Data abort: address = 0x%08lx "
487 "fsr = 0x%03x PC = 0x%08lx LR = 0x%08lx",
488 addr
, fsr
, regs
->ARM_pc
, regs
->ARM_lr
);
490 PRINTK("IOP13XX_XBG_BECSR: %#10x", __raw_readl(IOP13XX_XBG_BECSR
));
491 PRINTK("IOP13XX_XBG_BERAR: %#10x", __raw_readl(IOP13XX_XBG_BERAR
));
492 PRINTK("IOP13XX_XBG_BERUAR: %#10x", __raw_readl(IOP13XX_XBG_BERUAR
));
494 /* If it was an imprecise abort, then we need to correct the
495 * return address to be _after_ the instruction.
500 if (is_atue_occdr_error() || is_atux_occdr_error())
506 /* Scan an IOP13XX PCI bus. nr selects which ATU we use.
508 struct pci_bus
*iop13xx_scan_bus(int nr
, struct pci_sys_data
*sys
)
511 struct pci_bus
*bus
= NULL
;
514 case IOP13XX_INIT_ATU_ATUX
:
515 which_atu
= nr
? 0 : IOP13XX_INIT_ATU_ATUX
;
517 case IOP13XX_INIT_ATU_ATUE
:
518 which_atu
= nr
? 0 : IOP13XX_INIT_ATU_ATUE
;
520 case (IOP13XX_INIT_ATU_ATUX
| IOP13XX_INIT_ATU_ATUE
):
521 which_atu
= nr
? IOP13XX_INIT_ATU_ATUE
: IOP13XX_INIT_ATU_ATUX
;
533 case IOP13XX_INIT_ATU_ATUX
:
534 if (time_after_eq(jiffies
+ msecs_to_jiffies(1000),
535 atux_trhfa_timeout
)) /* ensure not wrap */
536 while(time_before(jiffies
, atux_trhfa_timeout
))
539 bus
= pci_bus_atux
= pci_scan_bus(sys
->busnr
,
543 case IOP13XX_INIT_ATU_ATUE
:
544 bus
= pci_bus_atue
= pci_scan_bus(sys
->busnr
,
553 /* This function is called from iop13xx_pci_init() after assigning valid
554 * values to iop13xx_atue_pmmr_offset. This is the location for common
555 * setup of ATUE for all IOP13XX implementations.
557 void __init
iop13xx_atue_setup(void)
559 int func
= iop13xx_atu_function(IOP13XX_INIT_ATU_ATUE
);
562 /* BAR 1 (1:1 mapping with Physical RAM) */
563 /* Set limit and enable */
564 __raw_writel(~(IOP13XX_MAX_RAM_SIZE
- PHYS_OFFSET
- 1) & ~0x1,
566 __raw_writel(0x0, IOP13XX_ATUE_IAUBAR1
);
568 /* Set base at the top of the reserved address space */
569 __raw_writel(PHYS_OFFSET
| PCI_BASE_ADDRESS_MEM_TYPE_64
|
570 PCI_BASE_ADDRESS_MEM_PREFETCH
, IOP13XX_ATUE_IABAR1
);
572 /* 1:1 mapping with physical ram
573 * (leave big endian byte swap disabled)
575 __raw_writel(0x0, IOP13XX_ATUE_IAUTVR1
);
576 __raw_writel(PHYS_OFFSET
, IOP13XX_ATUE_IATVR1
);
578 /* Outbound window 1 (PCIX/PCIE memory window) */
579 /* 32 bit Address Space */
580 __raw_writel(0x0, IOP13XX_ATUE_OUMWTVR1
);
582 __raw_writel(IOP13XX_ATUE_OUMBAR_ENABLE
|
583 (IOP13XX_PCIE_MEM_PHYS_OFFSET
>> 32),
584 IOP13XX_ATUE_OUMBAR1
);
589 __raw_writel(((IOP13XX_PCIE_LOWER_IO_PA
>> 0x4) & 0xfffff000),
590 IOP13XX_ATUE_OIOBAR
);
591 __raw_writel(IOP13XX_PCIE_LOWER_IO_BA
, IOP13XX_ATUE_OIOWTVR
);
593 /* clear startup errors */
594 iop13xx_atue_pci_status(1);
596 /* OIOBAR function number
598 reg_val
= __raw_readl(IOP13XX_ATUE_OIOBAR
);
601 __raw_writel(reg_val
, IOP13XX_ATUE_OIOBAR
);
603 /* OUMBAR function numbers
605 reg_val
= __raw_readl(IOP13XX_ATUE_OUMBAR0
);
606 reg_val
&= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK
<<
607 IOP13XX_ATU_OUMBAR_FUNC_NUM
);
608 reg_val
|= func
<< IOP13XX_ATU_OUMBAR_FUNC_NUM
;
609 __raw_writel(reg_val
, IOP13XX_ATUE_OUMBAR0
);
611 reg_val
= __raw_readl(IOP13XX_ATUE_OUMBAR1
);
612 reg_val
&= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK
<<
613 IOP13XX_ATU_OUMBAR_FUNC_NUM
);
614 reg_val
|= func
<< IOP13XX_ATU_OUMBAR_FUNC_NUM
;
615 __raw_writel(reg_val
, IOP13XX_ATUE_OUMBAR1
);
617 reg_val
= __raw_readl(IOP13XX_ATUE_OUMBAR2
);
618 reg_val
&= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK
<<
619 IOP13XX_ATU_OUMBAR_FUNC_NUM
);
620 reg_val
|= func
<< IOP13XX_ATU_OUMBAR_FUNC_NUM
;
621 __raw_writel(reg_val
, IOP13XX_ATUE_OUMBAR2
);
623 reg_val
= __raw_readl(IOP13XX_ATUE_OUMBAR3
);
624 reg_val
&= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK
<<
625 IOP13XX_ATU_OUMBAR_FUNC_NUM
);
626 reg_val
|= func
<< IOP13XX_ATU_OUMBAR_FUNC_NUM
;
627 __raw_writel(reg_val
, IOP13XX_ATUE_OUMBAR3
);
629 /* Enable inbound and outbound cycles
631 reg_val
= __raw_readw(IOP13XX_ATUE_ATUCMD
);
632 reg_val
|= PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER
|
633 PCI_COMMAND_PARITY
| PCI_COMMAND_SERR
;
634 __raw_writew(reg_val
, IOP13XX_ATUE_ATUCMD
);
636 reg_val
= __raw_readl(IOP13XX_ATUE_ATUCR
);
637 reg_val
|= IOP13XX_ATUE_ATUCR_OUT_EN
|
638 IOP13XX_ATUE_ATUCR_IVM
;
639 __raw_writel(reg_val
, IOP13XX_ATUE_ATUCR
);
642 void __init
iop13xx_atue_disable(void)
646 __raw_writew(0x0, IOP13XX_ATUE_ATUCMD
);
647 __raw_writel(IOP13XX_ATUE_ATUCR_IVM
, IOP13XX_ATUE_ATUCR
);
649 /* wait for cycles to quiesce */
650 while (__raw_readl(IOP13XX_ATUE_PCSR
) & (IOP13XX_ATUE_PCSR_OUT_Q_BUSY
|
651 IOP13XX_ATUE_PCSR_IN_Q_BUSY
|
652 IOP13XX_ATUE_PCSR_LLRB_BUSY
))
655 /* BAR 0 ( Disabled ) */
656 __raw_writel(0x0, IOP13XX_ATUE_IAUBAR0
);
657 __raw_writel(0x0, IOP13XX_ATUE_IABAR0
);
658 __raw_writel(0x0, IOP13XX_ATUE_IAUTVR0
);
659 __raw_writel(0x0, IOP13XX_ATUE_IATVR0
);
660 __raw_writel(0x0, IOP13XX_ATUE_IALR0
);
661 reg_val
= __raw_readl(IOP13XX_ATUE_OUMBAR0
);
662 reg_val
&= ~IOP13XX_ATUE_OUMBAR_ENABLE
;
663 __raw_writel(reg_val
, IOP13XX_ATUE_OUMBAR0
);
665 /* BAR 1 ( Disabled ) */
666 __raw_writel(0x0, IOP13XX_ATUE_IAUBAR1
);
667 __raw_writel(0x0, IOP13XX_ATUE_IABAR1
);
668 __raw_writel(0x0, IOP13XX_ATUE_IAUTVR1
);
669 __raw_writel(0x0, IOP13XX_ATUE_IATVR1
);
670 __raw_writel(0x0, IOP13XX_ATUE_IALR1
);
671 reg_val
= __raw_readl(IOP13XX_ATUE_OUMBAR1
);
672 reg_val
&= ~IOP13XX_ATUE_OUMBAR_ENABLE
;
673 __raw_writel(reg_val
, IOP13XX_ATUE_OUMBAR1
);
675 /* BAR 2 ( Disabled ) */
676 __raw_writel(0x0, IOP13XX_ATUE_IAUBAR2
);
677 __raw_writel(0x0, IOP13XX_ATUE_IABAR2
);
678 __raw_writel(0x0, IOP13XX_ATUE_IAUTVR2
);
679 __raw_writel(0x0, IOP13XX_ATUE_IATVR2
);
680 __raw_writel(0x0, IOP13XX_ATUE_IALR2
);
681 reg_val
= __raw_readl(IOP13XX_ATUE_OUMBAR2
);
682 reg_val
&= ~IOP13XX_ATUE_OUMBAR_ENABLE
;
683 __raw_writel(reg_val
, IOP13XX_ATUE_OUMBAR2
);
685 /* BAR 3 ( Disabled ) */
686 reg_val
= __raw_readl(IOP13XX_ATUE_OUMBAR3
);
687 reg_val
&= ~IOP13XX_ATUE_OUMBAR_ENABLE
;
688 __raw_writel(reg_val
, IOP13XX_ATUE_OUMBAR3
);
693 __raw_writel((IOP13XX_PCIE_LOWER_IO_PA
>> 0x4) & 0xfffff000,
694 IOP13XX_ATUE_OIOBAR
);
695 __raw_writel(IOP13XX_PCIE_LOWER_IO_BA
, IOP13XX_ATUE_OIOWTVR
);
698 /* This function is called from iop13xx_pci_init() after assigning valid
699 * values to iop13xx_atux_pmmr_offset. This is the location for common
700 * setup of ATUX for all IOP13XX implementations.
702 void __init
iop13xx_atux_setup(void)
705 int func
= iop13xx_atu_function(IOP13XX_INIT_ATU_ATUX
);
707 /* Take PCI-X bus out of reset if bootloader hasn't already.
708 * According to spec, we should wait for 2^25 PCI clocks to meet
709 * the PCI timing parameter Trhfa (RST# high to first access).
710 * This is rarely necessary and often ignored.
712 reg_val
= __raw_readl(IOP13XX_ATUX_PCSR
);
713 if (reg_val
& IOP13XX_ATUX_PCSR_P_RSTOUT
) {
714 int msec
= (reg_val
>> IOP13XX_ATUX_PCSR_FREQ_OFFSET
) & 0x7;
715 msec
= 1000 / (8-msec
); /* bits 100=133MHz, 111=>33MHz */
716 __raw_writel(reg_val
& ~IOP13XX_ATUX_PCSR_P_RSTOUT
,
718 atux_trhfa_timeout
= jiffies
+ msecs_to_jiffies(msec
);
721 atux_trhfa_timeout
= jiffies
;
723 /* BAR 1 (1:1 mapping with Physical RAM) */
724 /* Set limit and enable */
725 __raw_writel(~(IOP13XX_MAX_RAM_SIZE
- PHYS_OFFSET
- 1) & ~0x1,
727 __raw_writel(0x0, IOP13XX_ATUX_IAUBAR1
);
729 /* Set base at the top of the reserved address space */
730 __raw_writel(PHYS_OFFSET
| PCI_BASE_ADDRESS_MEM_TYPE_64
|
731 PCI_BASE_ADDRESS_MEM_PREFETCH
, IOP13XX_ATUX_IABAR1
);
733 /* 1:1 mapping with physical ram
734 * (leave big endian byte swap disabled)
736 __raw_writel(0x0, IOP13XX_ATUX_IAUTVR1
);
737 __raw_writel(PHYS_OFFSET
, IOP13XX_ATUX_IATVR1
);
739 /* Outbound window 1 (PCIX/PCIE memory window) */
740 /* 32 bit Address Space */
741 __raw_writel(0x0, IOP13XX_ATUX_OUMWTVR1
);
743 __raw_writel(IOP13XX_ATUX_OUMBAR_ENABLE
|
744 IOP13XX_PCIX_MEM_PHYS_OFFSET
>> 32,
745 IOP13XX_ATUX_OUMBAR1
);
750 __raw_writel((IOP13XX_PCIX_LOWER_IO_PA
>> 0x4) & 0xfffff000,
751 IOP13XX_ATUX_OIOBAR
);
752 __raw_writel(IOP13XX_PCIX_LOWER_IO_BA
, IOP13XX_ATUX_OIOWTVR
);
754 /* clear startup errors */
755 iop13xx_atux_pci_status(1);
757 /* OIOBAR function number
759 reg_val
= __raw_readl(IOP13XX_ATUX_OIOBAR
);
762 __raw_writel(reg_val
, IOP13XX_ATUX_OIOBAR
);
764 /* OUMBAR function numbers
766 reg_val
= __raw_readl(IOP13XX_ATUX_OUMBAR0
);
767 reg_val
&= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK
<<
768 IOP13XX_ATU_OUMBAR_FUNC_NUM
);
769 reg_val
|= func
<< IOP13XX_ATU_OUMBAR_FUNC_NUM
;
770 __raw_writel(reg_val
, IOP13XX_ATUX_OUMBAR0
);
772 reg_val
= __raw_readl(IOP13XX_ATUX_OUMBAR1
);
773 reg_val
&= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK
<<
774 IOP13XX_ATU_OUMBAR_FUNC_NUM
);
775 reg_val
|= func
<< IOP13XX_ATU_OUMBAR_FUNC_NUM
;
776 __raw_writel(reg_val
, IOP13XX_ATUX_OUMBAR1
);
778 reg_val
= __raw_readl(IOP13XX_ATUX_OUMBAR2
);
779 reg_val
&= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK
<<
780 IOP13XX_ATU_OUMBAR_FUNC_NUM
);
781 reg_val
|= func
<< IOP13XX_ATU_OUMBAR_FUNC_NUM
;
782 __raw_writel(reg_val
, IOP13XX_ATUX_OUMBAR2
);
784 reg_val
= __raw_readl(IOP13XX_ATUX_OUMBAR3
);
785 reg_val
&= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK
<<
786 IOP13XX_ATU_OUMBAR_FUNC_NUM
);
787 reg_val
|= func
<< IOP13XX_ATU_OUMBAR_FUNC_NUM
;
788 __raw_writel(reg_val
, IOP13XX_ATUX_OUMBAR3
);
790 /* Enable inbound and outbound cycles
792 reg_val
= __raw_readw(IOP13XX_ATUX_ATUCMD
);
793 reg_val
|= PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER
|
794 PCI_COMMAND_PARITY
| PCI_COMMAND_SERR
;
795 __raw_writew(reg_val
, IOP13XX_ATUX_ATUCMD
);
797 reg_val
= __raw_readl(IOP13XX_ATUX_ATUCR
);
798 reg_val
|= IOP13XX_ATUX_ATUCR_OUT_EN
;
799 __raw_writel(reg_val
, IOP13XX_ATUX_ATUCR
);
802 void __init
iop13xx_atux_disable(void)
806 __raw_writew(0x0, IOP13XX_ATUX_ATUCMD
);
807 __raw_writel(0x0, IOP13XX_ATUX_ATUCR
);
809 /* wait for cycles to quiesce */
810 while (__raw_readl(IOP13XX_ATUX_PCSR
) & (IOP13XX_ATUX_PCSR_OUT_Q_BUSY
|
811 IOP13XX_ATUX_PCSR_IN_Q_BUSY
))
814 /* BAR 0 ( Disabled ) */
815 __raw_writel(0x0, IOP13XX_ATUX_IAUBAR0
);
816 __raw_writel(0x0, IOP13XX_ATUX_IABAR0
);
817 __raw_writel(0x0, IOP13XX_ATUX_IAUTVR0
);
818 __raw_writel(0x0, IOP13XX_ATUX_IATVR0
);
819 __raw_writel(0x0, IOP13XX_ATUX_IALR0
);
820 reg_val
= __raw_readl(IOP13XX_ATUX_OUMBAR0
);
821 reg_val
&= ~IOP13XX_ATUX_OUMBAR_ENABLE
;
822 __raw_writel(reg_val
, IOP13XX_ATUX_OUMBAR0
);
824 /* BAR 1 ( Disabled ) */
825 __raw_writel(0x0, IOP13XX_ATUX_IAUBAR1
);
826 __raw_writel(0x0, IOP13XX_ATUX_IABAR1
);
827 __raw_writel(0x0, IOP13XX_ATUX_IAUTVR1
);
828 __raw_writel(0x0, IOP13XX_ATUX_IATVR1
);
829 __raw_writel(0x0, IOP13XX_ATUX_IALR1
);
830 reg_val
= __raw_readl(IOP13XX_ATUX_OUMBAR1
);
831 reg_val
&= ~IOP13XX_ATUX_OUMBAR_ENABLE
;
832 __raw_writel(reg_val
, IOP13XX_ATUX_OUMBAR1
);
834 /* BAR 2 ( Disabled ) */
835 __raw_writel(0x0, IOP13XX_ATUX_IAUBAR2
);
836 __raw_writel(0x0, IOP13XX_ATUX_IABAR2
);
837 __raw_writel(0x0, IOP13XX_ATUX_IAUTVR2
);
838 __raw_writel(0x0, IOP13XX_ATUX_IATVR2
);
839 __raw_writel(0x0, IOP13XX_ATUX_IALR2
);
840 reg_val
= __raw_readl(IOP13XX_ATUX_OUMBAR2
);
841 reg_val
&= ~IOP13XX_ATUX_OUMBAR_ENABLE
;
842 __raw_writel(reg_val
, IOP13XX_ATUX_OUMBAR2
);
844 /* BAR 3 ( Disabled ) */
845 __raw_writel(0x0, IOP13XX_ATUX_IAUBAR3
);
846 __raw_writel(0x0, IOP13XX_ATUX_IABAR3
);
847 __raw_writel(0x0, IOP13XX_ATUX_IAUTVR3
);
848 __raw_writel(0x0, IOP13XX_ATUX_IATVR3
);
849 __raw_writel(0x0, IOP13XX_ATUX_IALR3
);
850 reg_val
= __raw_readl(IOP13XX_ATUX_OUMBAR3
);
851 reg_val
&= ~IOP13XX_ATUX_OUMBAR_ENABLE
;
852 __raw_writel(reg_val
, IOP13XX_ATUX_OUMBAR3
);
857 __raw_writel((IOP13XX_PCIX_LOWER_IO_PA
>> 0x4) & 0xfffff000,
858 IOP13XX_ATUX_OIOBAR
);
859 __raw_writel(IOP13XX_PCIX_LOWER_IO_BA
, IOP13XX_ATUX_OIOWTVR
);
862 void __init
iop13xx_set_atu_mmr_bases(void)
864 /* Based on ESSR0, determine the ATU X/E offsets */
865 switch(__raw_readl(IOP13XX_ESSR0
) &
866 (IOP13XX_CONTROLLER_ONLY
| IOP13XX_INTERFACE_SEL_PCIX
)) {
869 iop13xx_atux_pmmr_offset
= IOP13XX_ATU1_PMMR_OFFSET
;
870 iop13xx_atue_pmmr_offset
= IOP13XX_ATU2_PMMR_OFFSET
;
872 /* IOP13XX_CONTROLLER_ONLY = deasserted
873 * IOP13XX_INTERFACE_SEL_PCIX = asserted
875 case IOP13XX_CONTROLLER_ONLY
:
876 iop13xx_atux_pmmr_offset
= IOP13XX_ATU0_PMMR_OFFSET
;
877 iop13xx_atue_pmmr_offset
= IOP13XX_ATU2_PMMR_OFFSET
;
879 /* IOP13XX_CONTROLLER_ONLY = asserted
880 * IOP13XX_INTERFACE_SEL_PCIX = deasserted
882 case IOP13XX_INTERFACE_SEL_PCIX
:
883 iop13xx_atux_pmmr_offset
= IOP13XX_ATU1_PMMR_OFFSET
;
884 iop13xx_atue_pmmr_offset
= IOP13XX_ATU2_PMMR_OFFSET
;
886 /* both deasserted */
887 case IOP13XX_CONTROLLER_ONLY
| IOP13XX_INTERFACE_SEL_PCIX
:
888 iop13xx_atux_pmmr_offset
= IOP13XX_ATU2_PMMR_OFFSET
;
889 iop13xx_atue_pmmr_offset
= IOP13XX_ATU0_PMMR_OFFSET
;
896 void __init
iop13xx_atu_select(struct hw_pci
*plat_pci
)
900 /* set system defaults
901 * note: if "iop13xx_init_atu=" is specified this autodetect
902 * sequence will be bypassed
904 if (init_atu
== IOP13XX_INIT_ATU_DEFAULT
) {
905 /* check for single/dual interface */
906 if (__raw_readl(IOP13XX_ESSR0
) & IOP13XX_INTERFACE_SEL_PCIX
) {
907 /* ATUE must be present check the device id
908 * to see if ATUX is present.
910 init_atu
|= IOP13XX_INIT_ATU_ATUE
;
911 switch (__raw_readw(IOP13XX_ATUE_DID
) & 0xf0) {
915 init_atu
|= IOP13XX_INIT_ATU_ATUX
;
919 /* ATUX must be present check the device id
920 * to see if ATUE is present.
922 init_atu
|= IOP13XX_INIT_ATU_ATUX
;
923 switch (__raw_readw(IOP13XX_ATUX_DID
) & 0xf0) {
927 init_atu
|= IOP13XX_INIT_ATU_ATUE
;
932 /* check central resource and root complex capability */
933 if (init_atu
& IOP13XX_INIT_ATU_ATUX
)
934 if (!(__raw_readl(IOP13XX_ATUX_PCSR
) &
935 IOP13XX_ATUX_PCSR_CENTRAL_RES
))
936 init_atu
&= ~IOP13XX_INIT_ATU_ATUX
;
938 if (init_atu
& IOP13XX_INIT_ATU_ATUE
)
939 if (__raw_readl(IOP13XX_ATUE_PCSR
) &
940 IOP13XX_ATUE_PCSR_END_POINT
)
941 init_atu
&= ~IOP13XX_INIT_ATU_ATUE
;
944 for (i
= 0; i
< 2; i
++) {
945 if((init_atu
& (1 << i
)) == (1 << i
))
946 plat_pci
->nr_controllers
++;
950 void __init
iop13xx_pci_init(void)
952 /* clear pre-existing south bridge errors */
953 __raw_writel(__raw_readl(IOP13XX_XBG_BECSR
) & 3, IOP13XX_XBG_BECSR
);
955 /* Setup the Min Address for PCI memory... */
956 iop13xx_pcibios_min_mem
= IOP13XX_PCIX_LOWER_MEM_BA
;
958 /* if Linux is given control of an ATU
959 * clear out its prior configuration,
960 * otherwise do not touch the registers
962 if (init_atu
& IOP13XX_INIT_ATU_ATUE
) {
963 iop13xx_atue_disable();
964 iop13xx_atue_setup();
967 if (init_atu
& IOP13XX_INIT_ATU_ATUX
) {
968 iop13xx_atux_disable();
969 iop13xx_atux_setup();
972 hook_fault_code(16+6, iop13xx_pci_abort
, SIGBUS
,
973 "imprecise external abort");
976 /* intialize the pci memory space. handle any combination of
977 * atue and atux enabled/disabled
979 int iop13xx_pci_setup(int nr
, struct pci_sys_data
*sys
)
981 struct resource
*res
;
988 res
= kmalloc(sizeof(struct resource
) * 2, GFP_KERNEL
);
990 panic("PCI: unable to alloc resources");
992 memset(res
, 0, sizeof(struct resource
) * 2);
996 * ATUE is 1 when ATUX is also enabled
997 * ATUE is 0 when ATUX is disabled
1000 case IOP13XX_INIT_ATU_ATUX
:
1001 which_atu
= nr
? 0 : IOP13XX_INIT_ATU_ATUX
;
1003 case IOP13XX_INIT_ATU_ATUE
:
1004 which_atu
= nr
? 0 : IOP13XX_INIT_ATU_ATUE
;
1006 case (IOP13XX_INIT_ATU_ATUX
| IOP13XX_INIT_ATU_ATUE
):
1007 which_atu
= nr
? IOP13XX_INIT_ATU_ATUE
: IOP13XX_INIT_ATU_ATUX
;
1017 case IOP13XX_INIT_ATU_ATUX
:
1018 pcixsr
= __raw_readl(IOP13XX_ATUX_PCIXSR
);
1020 pcixsr
|= sys
->busnr
<< IOP13XX_ATUX_PCIXSR_BUS_NUM
|
1021 0 << IOP13XX_ATUX_PCIXSR_DEV_NUM
|
1022 iop13xx_atu_function(IOP13XX_INIT_ATU_ATUX
)
1023 << IOP13XX_ATUX_PCIXSR_FUNC_NUM
;
1024 __raw_writel(pcixsr
, IOP13XX_ATUX_PCIXSR
);
1026 res
[0].start
= IOP13XX_PCIX_LOWER_IO_PA
;
1027 res
[0].end
= IOP13XX_PCIX_UPPER_IO_PA
;
1028 res
[0].name
= "IQ81340 ATUX PCI I/O Space";
1029 res
[0].flags
= IORESOURCE_IO
;
1031 res
[1].start
= IOP13XX_PCIX_LOWER_MEM_RA
;
1032 res
[1].end
= IOP13XX_PCIX_UPPER_MEM_RA
;
1033 res
[1].name
= "IQ81340 ATUX PCI Memory Space";
1034 res
[1].flags
= IORESOURCE_MEM
;
1035 sys
->mem_offset
= IOP13XX_PCIX_MEM_OFFSET
;
1036 sys
->io_offset
= IOP13XX_PCIX_IO_OFFSET
;
1038 case IOP13XX_INIT_ATU_ATUE
:
1039 /* Note: the function number field in the PCSR is ro */
1040 pcsr
= __raw_readl(IOP13XX_ATUE_PCSR
);
1041 pcsr
&= ~(0xfff8 << 16);
1042 pcsr
|= sys
->busnr
<< IOP13XX_ATUE_PCSR_BUS_NUM
|
1043 0 << IOP13XX_ATUE_PCSR_DEV_NUM
;
1045 __raw_writel(pcsr
, IOP13XX_ATUE_PCSR
);
1047 res
[0].start
= IOP13XX_PCIE_LOWER_IO_PA
;
1048 res
[0].end
= IOP13XX_PCIE_UPPER_IO_PA
;
1049 res
[0].name
= "IQ81340 ATUE PCI I/O Space";
1050 res
[0].flags
= IORESOURCE_IO
;
1052 res
[1].start
= IOP13XX_PCIE_LOWER_MEM_RA
;
1053 res
[1].end
= IOP13XX_PCIE_UPPER_MEM_RA
;
1054 res
[1].name
= "IQ81340 ATUE PCI Memory Space";
1055 res
[1].flags
= IORESOURCE_MEM
;
1056 sys
->mem_offset
= IOP13XX_PCIE_MEM_OFFSET
;
1057 sys
->io_offset
= IOP13XX_PCIE_IO_OFFSET
;
1058 sys
->map_irq
= iop13xx_pcie_map_irq
;
1064 request_resource(&ioport_resource
, &res
[0]);
1065 request_resource(&iomem_resource
, &res
[1]);
1067 sys
->resource
[0] = &res
[0];
1068 sys
->resource
[1] = &res
[1];
1069 sys
->resource
[2] = NULL
;
1074 u16
iop13xx_dev_id(void)
1076 if (__raw_readl(IOP13XX_ESSR0
) & IOP13XX_INTERFACE_SEL_PCIX
)
1077 return __raw_readw(IOP13XX_ATUE_DID
);
1079 return __raw_readw(IOP13XX_ATUX_DID
);
1082 static int __init
iop13xx_init_atu_setup(char *str
)
1084 init_atu
= IOP13XX_INIT_ATU_NONE
;
1086 while (*str
!= '\0') {
1090 init_atu
|= IOP13XX_INIT_ATU_ATUX
;
1091 init_atu
&= ~IOP13XX_INIT_ATU_NONE
;
1095 init_atu
|= IOP13XX_INIT_ATU_ATUE
;
1096 init_atu
&= ~IOP13XX_INIT_ATU_NONE
;
1102 PRINTK("\"iop13xx_init_atu\" malformed at "
1103 "character: \'%c\'", *str
);
1105 init_atu
= IOP13XX_INIT_ATU_DEFAULT
;
1113 __setup("iop13xx_init_atu", iop13xx_init_atu_setup
);