| blob | 1ad0c880c80c2d1cd268087e338553be132cf952 |
1 /*
2 * linux/arch/arm/mm/proc-xscale.S
3 *
4 * Author: Nicolas Pitre
5 * Created: November 2000
6 * Copyright: (C) 2000, 2001 MontaVista Software Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * MMU functions for the Intel XScale CPUs
13 *
14 * 2001 Aug 21:
15 * some contributions by Brett Gaines <brett.w.gaines@intel.com>
16 * Copyright 2001 by Intel Corp.
17 *
18 * 2001 Sep 08:
19 * Completely revisited, many important fixes
20 * Nicolas Pitre <nico@cam.org>
21 */
23 #include <linux/linkage.h>
24 #include <linux/init.h>
25 #include <asm/assembler.h>
26 #include <asm/procinfo.h>
27 #include <asm/pgtable.h>
28 #include <asm/pgtable-hwdef.h>
29 #include <asm/page.h>
30 #include <asm/ptrace.h>
31 #include "proc-macros.S"
33 /*
34 * This is the maximum size of an area which will be flushed. If the area
35 * is larger than this, then we flush the whole cache
36 */
37 #define MAX_AREA_SIZE 32768
39 /*
40 * the cache line size of the I and D cache
41 */
42 #define CACHELINESIZE 32
44 /*
45 * the size of the data cache
46 */
47 #define CACHESIZE 32768
49 /*
50 * Virtual address used to allocate the cache when flushed
51 *
52 * This must be an address range which is _never_ used. It should
53 * apparently have a mapping in the corresponding page table for
54 * compatibility with future CPUs that _could_ require it. For instance we
55 * don't care.
56 *
57 * This must be aligned on a 2*CACHESIZE boundary. The code selects one of
58 * the 2 areas in alternance each time the clean_d_cache macro is used.
59 * Without this the XScale core exhibits cache eviction problems and no one
60 * knows why.
61 *
62 * Reminder: the vector table is located at 0xffff0000-0xffff0fff.
63 */
64 #define CLEAN_ADDR 0xfffe0000
66 /*
67 * This macro is used to wait for a CP15 write and is needed
68 * when we have to ensure that the last operation to the co-pro
69 * was completed before continuing with operation.
70 */
71 .macro cpwait, rd
72 mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15
73 mov \rd, \rd @ wait for completion
74 sub pc, pc, #4 @ flush instruction pipeline
75 .endm
77 .macro cpwait_ret, lr, rd
78 mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15
79 sub pc, \lr, \rd, LSR #32 @ wait for completion and
80 @ flush instruction pipeline
81 .endm
83 /*
84 * This macro cleans the entire dcache using line allocate.
85 * The main loop has been unrolled to reduce loop overhead.
86 * rd and rs are two scratch registers.
87 */
88 .macro clean_d_cache, rd, rs
89 ldr \rs, =clean_addr
90 ldr \rd, [\rs]
91 eor \rd, \rd, #CACHESIZE
92 str \rd, [\rs]
93 add \rs, \rd, #CACHESIZE
94 1: mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
95 add \rd, \rd, #CACHELINESIZE
96 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
97 add \rd, \rd, #CACHELINESIZE
98 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
99 add \rd, \rd, #CACHELINESIZE
100 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
101 add \rd, \rd, #CACHELINESIZE
102 teq \rd, \rs
103 bne 1b
104 .endm
106 .data
107 clean_addr: .word CLEAN_ADDR
109 .text
111 /*
112 * cpu_xscale_proc_init()
113 *
114 * Nothing too exciting at the moment
115 */
116 ENTRY(cpu_xscale_proc_init)
117 mov pc, lr
119 /*
120 * cpu_xscale_proc_fin()
121 */
122 ENTRY(cpu_xscale_proc_fin)
123 str lr, [sp, #-4]!
124 mov r0, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
125 msr cpsr_c, r0
126 bl xscale_flush_kern_cache_all @ clean caches
127 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
128 bic r0, r0, #0x1800 @ ...IZ...........
129 bic r0, r0, #0x0006 @ .............CA.
130 mcr p15, 0, r0, c1, c0, 0 @ disable caches
131 ldr pc, [sp], #4
133 /*
134 * cpu_xscale_reset(loc)
135 *
136 * Perform a soft reset of the system. Put the CPU into the
137 * same state as it would be if it had been reset, and branch
138 * to what would be the reset vector.
139 *
140 * loc: location to jump to for soft reset
141 */
142 .align 5
143 ENTRY(cpu_xscale_reset)
144 mov r1, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
145 msr cpsr_c, r1 @ reset CPSR
146 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
147 bic r1, r1, #0x0086 @ ........B....CA.
148 bic r1, r1, #0x3900 @ ..VIZ..S........
149 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
150 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches & BTB
151 bic r1, r1, #0x0001 @ ...............M
152 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
153 @ CAUTION: MMU turned off from this point. We count on the pipeline
154 @ already containing those two last instructions to survive.
155 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
156 mov pc, r0
158 /*
159 * cpu_xscale_do_idle()
160 *
161 * Cause the processor to idle
162 *
163 * For now we do nothing but go to idle mode for every case
164 *
165 * XScale supports clock switching, but using idle mode support
166 * allows external hardware to react to system state changes.
167 */
168 .align 5
170 ENTRY(cpu_xscale_do_idle)
171 mov r0, #1
172 mcr p14, 0, r0, c7, c0, 0 @ Go to IDLE
173 mov pc, lr
175 /* ================================= CACHE ================================ */
177 /*
178 * flush_user_cache_all()
179 *
180 * Invalidate all cache entries in a particular address
181 * space.
182 */
183 ENTRY(xscale_flush_user_cache_all)
184 /* FALLTHROUGH */
186 /*
187 * flush_kern_cache_all()
188 *
189 * Clean and invalidate the entire cache.
190 */
191 ENTRY(xscale_flush_kern_cache_all)
192 mov r2, #VM_EXEC
193 mov ip, #0
194 __flush_whole_cache:
195 clean_d_cache r0, r1
196 tst r2, #VM_EXEC
197 mcrne p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB
198 mcrne p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
199 mov pc, lr
201 /*
202 * flush_user_cache_range(start, end, vm_flags)
203 *
204 * Invalidate a range of cache entries in the specified
205 * address space.
206 *
207 * - start - start address (may not be aligned)
208 * - end - end address (exclusive, may not be aligned)
209 * - vma - vma_area_struct describing address space
210 */
211 .align 5
212 ENTRY(xscale_flush_user_cache_range)
213 mov ip, #0
214 sub r3, r1, r0 @ calculate total size
215 cmp r3, #MAX_AREA_SIZE
216 bhs __flush_whole_cache
218 1: tst r2, #VM_EXEC
219 mcrne p15, 0, r0, c7, c5, 1 @ Invalidate I cache line
220 mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line
221 mcr p15, 0, r0, c7, c6, 1 @ Invalidate D cache line
222 add r0, r0, #CACHELINESIZE
223 cmp r0, r1
224 blo 1b
225 tst r2, #VM_EXEC
226 mcrne p15, 0, ip, c7, c5, 6 @ Invalidate BTB
227 mcrne p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
228 mov pc, lr
230 /*
231 * coherent_kern_range(start, end)
232 *
233 * Ensure coherency between the Icache and the Dcache in the
234 * region described by start. If you have non-snooping
235 * Harvard caches, you need to implement this function.
236 *
237 * - start - virtual start address
238 * - end - virtual end address
239 *
240 * Note: single I-cache line invalidation isn't used here since
241 * it also trashes the mini I-cache used by JTAG debuggers.
242 */
243 ENTRY(xscale_coherent_kern_range)
244 bic r0, r0, #CACHELINESIZE - 1
245 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
246 add r0, r0, #CACHELINESIZE
247 cmp r0, r1
248 blo 1b
249 mov r0, #0
250 mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB
251 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
252 mov pc, lr
254 /*
255 * coherent_user_range(start, end)
256 *
257 * Ensure coherency between the Icache and the Dcache in the
258 * region described by start. If you have non-snooping
259 * Harvard caches, you need to implement this function.
260 *
261 * - start - virtual start address
262 * - end - virtual end address
263 */
264 ENTRY(xscale_coherent_user_range)
265 bic r0, r0, #CACHELINESIZE - 1
266 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
267 mcr p15, 0, r0, c7, c5, 1 @ Invalidate I cache entry
268 add r0, r0, #CACHELINESIZE
269 cmp r0, r1
270 blo 1b
271 mov r0, #0
272 mcr p15, 0, r0, c7, c5, 6 @ Invalidate BTB
273 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
274 mov pc, lr
276 /*
277 * flush_kern_dcache_page(void *page)
278 *
279 * Ensure no D cache aliasing occurs, either with itself or
280 * the I cache
281 *
282 * - addr - page aligned address
283 */
284 ENTRY(xscale_flush_kern_dcache_page)
285 add r1, r0, #PAGE_SZ
286 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
287 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
288 add r0, r0, #CACHELINESIZE
289 cmp r0, r1
290 blo 1b
291 mov r0, #0
292 mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB
293 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
294 mov pc, lr
296 /*
297 * dma_inv_range(start, end)
298 *
299 * Invalidate (discard) the specified virtual address range.
300 * May not write back any entries. If 'start' or 'end'
301 * are not cache line aligned, those lines must be written
302 * back.
303 *
304 * - start - virtual start address
305 * - end - virtual end address
306 */
307 ENTRY(xscale_dma_inv_range)
308 mrc p15, 0, r2, c0, c0, 0 @ read ID
309 eor r2, r2, #0x69000000
310 eor r2, r2, #0x00052000
311 bics r2, r2, #1
312 beq xscale_dma_flush_range
314 tst r0, #CACHELINESIZE - 1
315 bic r0, r0, #CACHELINESIZE - 1
316 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
317 tst r1, #CACHELINESIZE - 1
318 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
319 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
320 add r0, r0, #CACHELINESIZE
321 cmp r0, r1
322 blo 1b
323 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
324 mov pc, lr
326 /*
327 * dma_clean_range(start, end)
328 *
329 * Clean the specified virtual address range.
330 *
331 * - start - virtual start address
332 * - end - virtual end address
333 */
334 ENTRY(xscale_dma_clean_range)
335 bic r0, r0, #CACHELINESIZE - 1
336 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
337 add r0, r0, #CACHELINESIZE
338 cmp r0, r1
339 blo 1b
340 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
341 mov pc, lr
343 /*
344 * dma_flush_range(start, end)
345 *
346 * Clean and invalidate the specified virtual address range.
347 *
348 * - start - virtual start address
349 * - end - virtual end address
350 */
351 ENTRY(xscale_dma_flush_range)
352 bic r0, r0, #CACHELINESIZE - 1
353 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
354 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
355 add r0, r0, #CACHELINESIZE
356 cmp r0, r1
357 blo 1b
358 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
359 mov pc, lr
361 ENTRY(xscale_cache_fns)
362 .long xscale_flush_kern_cache_all
363 .long xscale_flush_user_cache_all
364 .long xscale_flush_user_cache_range
365 .long xscale_coherent_kern_range
366 .long xscale_coherent_user_range
367 .long xscale_flush_kern_dcache_page
368 .long xscale_dma_inv_range
369 .long xscale_dma_clean_range
370 .long xscale_dma_flush_range
372 ENTRY(cpu_xscale_dcache_clean_area)
373 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
374 add r0, r0, #CACHELINESIZE
375 subs r1, r1, #CACHELINESIZE
376 bhi 1b
377 mov pc, lr
379 /* =============================== PageTable ============================== */
381 #define PTE_CACHE_WRITE_ALLOCATE 0
383 /*
384 * cpu_xscale_switch_mm(pgd)
385 *
386 * Set the translation base pointer to be as described by pgd.
387 *
388 * pgd: new page tables
389 */
390 .align 5
391 ENTRY(cpu_xscale_switch_mm)
392 clean_d_cache r1, r2
393 mcr p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB
394 mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
395 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
396 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
397 cpwait_ret lr, ip
399 /*
400 * cpu_xscale_set_pte(ptep, pte)
401 *
402 * Set a PTE and flush it out
403 *
404 * Errata 40: must set memory to write-through for user read-only pages.
405 */
406 .align 5
407 ENTRY(cpu_xscale_set_pte)
408 str r1, [r0], #-2048 @ linux version
410 bic r2, r1, #0xff0
411 orr r2, r2, #PTE_TYPE_EXT @ extended page
413 eor r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
415 tst r3, #L_PTE_USER @ User?
416 orrne r2, r2, #PTE_EXT_AP_URO_SRW @ yes -> user r/o, system r/w
418 tst r3, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
419 orreq r2, r2, #PTE_EXT_AP_UNO_SRW @ yes -> user n/a, system r/w
420 @ combined with user -> user r/w
422 @
423 @ Handle the X bit. We want to set this bit for the minicache
424 @ (U = E = B = W = 0, C = 1) or when write allocate is enabled,
425 @ and we have a writeable, cacheable region. If we ignore the
426 @ U and E bits, we can allow user space to use the minicache as
427 @ well.
428 @
429 @ X = (C & ~W & ~B) | (C & W & B & write_allocate)
430 @
431 eor ip, r1, #L_PTE_CACHEABLE
432 tst ip, #L_PTE_CACHEABLE | L_PTE_WRITE | L_PTE_BUFFERABLE
433 #if PTE_CACHE_WRITE_ALLOCATE
434 eorne ip, r1, #L_PTE_CACHEABLE | L_PTE_WRITE | L_PTE_BUFFERABLE
435 tstne ip, #L_PTE_CACHEABLE | L_PTE_WRITE | L_PTE_BUFFERABLE
436 #endif
437 orreq r2, r2, #PTE_EXT_TEX(1)
439 @
440 @ Erratum 40: The B bit must be cleared for a user read-only
441 @ cacheable page.
442 @
443 @ B = B & ~(U & C & ~W)
444 @
445 and ip, r1, #L_PTE_USER | L_PTE_WRITE | L_PTE_CACHEABLE
446 teq ip, #L_PTE_USER | L_PTE_CACHEABLE
447 biceq r2, r2, #PTE_BUFFERABLE
449 tst r3, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
450 movne r2, #0 @ no -> fault
452 str r2, [r0] @ hardware version
453 mov ip, #0
454 mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line
455 mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
456 mov pc, lr
459 .ltorg
461 .align
463 __INIT
465 .type __xscale_setup, #function
466 __xscale_setup:
467 mcr p15, 0, ip, c7, c7, 0 @ invalidate I, D caches & BTB
468 mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
469 mcr p15, 0, ip, c8, c7, 0 @ invalidate I, D TLBs
470 #ifdef CONFIG_IWMMXT
471 mov r0, #0 @ initially disallow access to CP0/CP1
472 #else
473 mov r0, #1 @ Allow access to CP0
474 #endif
475 orr r0, r0, #1 << 6 @ cp6 for IOP3xx and Bulverde
476 orr r0, r0, #1 << 13 @ Its undefined whether this
477 mcr p15, 0, r0, c15, c1, 0 @ affects USR or SVC modes
479 adr r5, xscale_crval
480 ldmia r5, {r5, r6}
481 mrc p15, 0, r0, c1, c0, 0 @ get control register
482 bic r0, r0, r5
483 orr r0, r0, r6
484 mov pc, lr
485 .size __xscale_setup, . - __xscale_setup
487 /*
488 * R
489 * .RVI ZFRS BLDP WCAM
490 * ..11 1.01 .... .101
491 *
492 */
493 .type xscale_crval, #object
494 xscale_crval:
495 crval clear=0x00003b07, mmuset=0x00003905, ucset=0x00001900
497 __INITDATA
499 /*
500 * Purpose : Function pointers used to access above functions - all calls
501 * come through these
502 */
504 .type xscale_processor_functions, #object
505 ENTRY(xscale_processor_functions)
506 .word v5t_early_abort
507 .word cpu_xscale_proc_init
508 .word cpu_xscale_proc_fin
509 .word cpu_xscale_reset
510 .word cpu_xscale_do_idle
511 .word cpu_xscale_dcache_clean_area
512 .word cpu_xscale_switch_mm
513 .word cpu_xscale_set_pte
514 .size xscale_processor_functions, . - xscale_processor_functions
516 .section ".rodata"
518 .type cpu_arch_name, #object
519 cpu_arch_name:
520 .asciz "armv5te"
521 .size cpu_arch_name, . - cpu_arch_name
523 .type cpu_elf_name, #object
524 cpu_elf_name:
525 .asciz "v5"
526 .size cpu_elf_name, . - cpu_elf_name
528 .type cpu_80200_name, #object
529 cpu_80200_name:
530 .asciz "XScale-80200"
531 .size cpu_80200_name, . - cpu_80200_name
533 .type cpu_8032x_name, #object
534 cpu_8032x_name:
535 .asciz "XScale-IOP8032x Family"
536 .size cpu_8032x_name, . - cpu_8032x_name
538 .type cpu_8033x_name, #object
539 cpu_8033x_name:
540 .asciz "XScale-IOP8033x Family"
541 .size cpu_8033x_name, . - cpu_8033x_name
543 .type cpu_pxa250_name, #object
544 cpu_pxa250_name:
545 .asciz "XScale-PXA250"
546 .size cpu_pxa250_name, . - cpu_pxa250_name
548 .type cpu_pxa210_name, #object
549 cpu_pxa210_name:
550 .asciz "XScale-PXA210"
551 .size cpu_pxa210_name, . - cpu_pxa210_name
553 .type cpu_ixp42x_name, #object
554 cpu_ixp42x_name:
555 .asciz "XScale-IXP42x Family"
556 .size cpu_ixp42x_name, . - cpu_ixp42x_name
558 .type cpu_ixp46x_name, #object
559 cpu_ixp46x_name:
560 .asciz "XScale-IXP46x Family"
561 .size cpu_ixp46x_name, . - cpu_ixp46x_name
563 .type cpu_ixp2400_name, #object
564 cpu_ixp2400_name:
565 .asciz "XScale-IXP2400"
566 .size cpu_ixp2400_name, . - cpu_ixp2400_name
568 .type cpu_ixp2800_name, #object
569 cpu_ixp2800_name:
570 .asciz "XScale-IXP2800"
571 .size cpu_ixp2800_name, . - cpu_ixp2800_name
573 .type cpu_pxa255_name, #object
574 cpu_pxa255_name:
575 .asciz "XScale-PXA255"
576 .size cpu_pxa255_name, . - cpu_pxa255_name
578 .type cpu_pxa270_name, #object
579 cpu_pxa270_name:
580 .asciz "XScale-PXA270"
581 .size cpu_pxa270_name, . - cpu_pxa270_name
583 .align
585 .section ".proc.info.init", #alloc, #execinstr
587 .type __80200_proc_info,#object
588 __80200_proc_info:
589 .long 0x69052000
590 .long 0xfffffff0
591 .long PMD_TYPE_SECT | \
592 PMD_SECT_BUFFERABLE | \
593 PMD_SECT_CACHEABLE | \
594 PMD_SECT_AP_WRITE | \
595 PMD_SECT_AP_READ
596 b __xscale_setup
597 .long cpu_arch_name
598 .long cpu_elf_name
599 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
600 .long cpu_80200_name
601 .long xscale_processor_functions
602 .long v4wbi_tlb_fns
603 .long xscale_mc_user_fns
604 .long xscale_cache_fns
605 .size __80200_proc_info, . - __80200_proc_info
607 .type __8032x_proc_info,#object
608 __8032x_proc_info:
609 .long 0x69052420
610 .long 0xfffff5e0 @ mask should accomodate IOP80219 also
611 .long PMD_TYPE_SECT | \
612 PMD_SECT_BUFFERABLE | \
613 PMD_SECT_CACHEABLE | \
614 PMD_SECT_AP_WRITE | \
615 PMD_SECT_AP_READ
616 b __xscale_setup
617 .long cpu_arch_name
618 .long cpu_elf_name
619 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
620 .long cpu_8032x_name
621 .long xscale_processor_functions
622 .long v4wbi_tlb_fns
623 .long xscale_mc_user_fns
624 .long xscale_cache_fns
625 .size __8032x_proc_info, . - __8032x_proc_info
627 .type __8033x_proc_info,#object
628 __8033x_proc_info:
629 .long 0x69054010
630 .long 0xffffff30
631 .long PMD_TYPE_SECT | \
632 PMD_SECT_BUFFERABLE | \
633 PMD_SECT_CACHEABLE | \
634 PMD_SECT_AP_WRITE | \
635 PMD_SECT_AP_READ
636 b __xscale_setup
637 .long cpu_arch_name
638 .long cpu_elf_name
639 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
640 .long cpu_8033x_name
641 .long xscale_processor_functions
642 .long v4wbi_tlb_fns
643 .long xscale_mc_user_fns
644 .long xscale_cache_fns
645 .size __8033x_proc_info, . - __8033x_proc_info
647 .type __pxa250_proc_info,#object
648 __pxa250_proc_info:
649 .long 0x69052100
650 .long 0xfffff7f0
651 .long PMD_TYPE_SECT | \
652 PMD_SECT_BUFFERABLE | \
653 PMD_SECT_CACHEABLE | \
654 PMD_SECT_AP_WRITE | \
655 PMD_SECT_AP_READ
656 b __xscale_setup
657 .long cpu_arch_name
658 .long cpu_elf_name
659 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
660 .long cpu_pxa250_name
661 .long xscale_processor_functions
662 .long v4wbi_tlb_fns
663 .long xscale_mc_user_fns
664 .long xscale_cache_fns
665 .size __pxa250_proc_info, . - __pxa250_proc_info
667 .type __pxa210_proc_info,#object
668 __pxa210_proc_info:
669 .long 0x69052120
670 .long 0xfffff3f0
671 .long PMD_TYPE_SECT | \
672 PMD_SECT_BUFFERABLE | \
673 PMD_SECT_CACHEABLE | \
674 PMD_SECT_AP_WRITE | \
675 PMD_SECT_AP_READ
676 b __xscale_setup
677 .long cpu_arch_name
678 .long cpu_elf_name
679 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
680 .long cpu_pxa210_name
681 .long xscale_processor_functions
682 .long v4wbi_tlb_fns
683 .long xscale_mc_user_fns
684 .long xscale_cache_fns
685 .size __pxa210_proc_info, . - __pxa210_proc_info
687 .type __ixp2400_proc_info, #object
688 __ixp2400_proc_info:
689 .long 0x69054190
690 .long 0xfffffff0
691 .long PMD_TYPE_SECT | \
692 PMD_SECT_BUFFERABLE | \
693 PMD_SECT_CACHEABLE | \
694 PMD_SECT_AP_WRITE | \
695 PMD_SECT_AP_READ
696 b __xscale_setup
697 .long cpu_arch_name
698 .long cpu_elf_name
699 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
700 .long cpu_ixp2400_name
701 .long xscale_processor_functions
702 .long v4wbi_tlb_fns
703 .long xscale_mc_user_fns
704 .long xscale_cache_fns
705 .size __ixp2400_proc_info, . - __ixp2400_proc_info
707 .type __ixp2800_proc_info, #object
708 __ixp2800_proc_info:
709 .long 0x690541a0
710 .long 0xfffffff0
711 .long PMD_TYPE_SECT | \
712 PMD_SECT_BUFFERABLE | \
713 PMD_SECT_CACHEABLE | \
714 PMD_SECT_AP_WRITE | \
715 PMD_SECT_AP_READ
716 b __xscale_setup
717 .long cpu_arch_name
718 .long cpu_elf_name
719 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
720 .long cpu_ixp2800_name
721 .long xscale_processor_functions
722 .long v4wbi_tlb_fns
723 .long xscale_mc_user_fns
724 .long xscale_cache_fns
725 .size __ixp2800_proc_info, . - __ixp2800_proc_info
727 .type __ixp42x_proc_info, #object
728 __ixp42x_proc_info:
729 .long 0x690541c0
730 .long 0xffffffc0
731 .long PMD_TYPE_SECT | \
732 PMD_SECT_BUFFERABLE | \
733 PMD_SECT_CACHEABLE | \
734 PMD_SECT_AP_WRITE | \
735 PMD_SECT_AP_READ
736 b __xscale_setup
737 .long cpu_arch_name
738 .long cpu_elf_name
739 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
740 .long cpu_ixp42x_name
741 .long xscale_processor_functions
742 .long v4wbi_tlb_fns
743 .long xscale_mc_user_fns
744 .long xscale_cache_fns
745 .size __ixp42x_proc_info, . - __ixp42x_proc_info
747 .type __ixp46x_proc_info, #object
748 __ixp46x_proc_info:
749 .long 0x69054200
750 .long 0xffffff00
751 .long 0x00000c0e
752 b __xscale_setup
753 .long cpu_arch_name
754 .long cpu_elf_name
755 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
756 .long cpu_ixp46x_name
757 .long xscale_processor_functions
758 .long v4wbi_tlb_fns
759 .long xscale_mc_user_fns
760 .long xscale_cache_fns
761 .size __ixp46x_proc_info, . - __ixp46x_proc_info
763 .type __pxa255_proc_info,#object
764 __pxa255_proc_info:
765 .long 0x69052d00
766 .long 0xfffffff0
767 .long PMD_TYPE_SECT | \
768 PMD_SECT_BUFFERABLE | \
769 PMD_SECT_CACHEABLE | \
770 PMD_SECT_AP_WRITE | \
771 PMD_SECT_AP_READ
772 b __xscale_setup
773 .long cpu_arch_name
774 .long cpu_elf_name
775 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
776 .long cpu_pxa255_name
777 .long xscale_processor_functions
778 .long v4wbi_tlb_fns
779 .long xscale_mc_user_fns
780 .long xscale_cache_fns
781 .size __pxa255_proc_info, . - __pxa255_proc_info
783 .type __pxa270_proc_info,#object
784 __pxa270_proc_info:
785 .long 0x69054110
786 .long 0xfffffff0
787 .long PMD_TYPE_SECT | \
788 PMD_SECT_BUFFERABLE | \
789 PMD_SECT_CACHEABLE | \
790 PMD_SECT_AP_WRITE | \
791 PMD_SECT_AP_READ
792 b __xscale_setup
793 .long cpu_arch_name
794 .long cpu_elf_name
795 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
796 .long cpu_pxa270_name
797 .long xscale_processor_functions
798 .long v4wbi_tlb_fns
799 .long xscale_mc_user_fns
800 .long xscale_cache_fns
801 .size __pxa270_proc_info, . - __pxa270_proc_info