arch/arm/mach-orion5x/include/mach/orion5x.h

   1 /*
   2  * arch/arm/mach-orion5x/include/mach/orion5x.h
   3  *
   4  * Generic definitions of Orion SoC flavors:
   5  *  Orion-1, Orion-VoIP, Orion-NAS, and Orion-2.
   6  *
   7  * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
   8  *
   9  * This file is licensed under the terms of the GNU General Public
  10  * License version 2. This program is licensed "as is" without any
  11  * warranty of any kind, whether express or implied.
  12  */
  13
  14 #ifndef __ASM_ARCH_ORION5X_H
  15 #define __ASM_ARCH_ORION5X_H
  16
  17 /*****************************************************************************
  18  * Orion Address Maps
  19  *
  20  * phys
  21  * e0000000     PCIe MEM space
  22  * e8000000     PCI MEM space
  23  * f0000000     PCIe WA space (Orion-1/Orion-NAS only)
  24  * f1000000     on-chip peripheral registers
  25  * f2000000     PCIe I/O space
  26  * f2100000     PCI I/O space
  27  * f4000000     device bus mappings (boot)
  28  * fa000000     device bus mappings (cs0)
  29  * fa800000     device bus mappings (cs2)
  30  * fc000000     device bus mappings (cs0/cs1)
  31  *
  32  * virt         phys            size
  33  * fdd00000     f1000000        1M      on-chip peripheral registers
  34  * fde00000     f2000000        1M      PCIe I/O space
  35  * fdf00000     f2100000        1M      PCI I/O space
  36  * fe000000     f0000000        16M     PCIe WA space (Orion-1/Orion-NAS only)
  37  ****************************************************************************/
  38 #define ORION5X_REGS_PHYS_BASE          0xf1000000
  39 #define ORION5X_REGS_VIRT_BASE          0xfdd00000
  40 #define ORION5X_REGS_SIZE               SZ_1M
  41
  42 #define ORION5X_PCIE_IO_PHYS_BASE       0xf2000000
  43 #define ORION5X_PCIE_IO_VIRT_BASE       0xfde00000
  44 #define ORION5X_PCIE_IO_BUS_BASE        0x00000000
  45 #define ORION5X_PCIE_IO_SIZE            SZ_1M
  46
  47 #define ORION5X_PCI_IO_PHYS_BASE        0xf2100000
  48 #define ORION5X_PCI_IO_VIRT_BASE        0xfdf00000
  49 #define ORION5X_PCI_IO_BUS_BASE         0x00100000
  50 #define ORION5X_PCI_IO_SIZE             SZ_1M
  51
  52 /* Relevant only for Orion-1/Orion-NAS */
  53 #define ORION5X_PCIE_WA_PHYS_BASE       0xf0000000
  54 #define ORION5X_PCIE_WA_VIRT_BASE       0xfe000000
  55 #define ORION5X_PCIE_WA_SIZE            SZ_16M
  56
  57 #define ORION5X_PCIE_MEM_PHYS_BASE      0xe0000000
  58 #define ORION5X_PCIE_MEM_SIZE           SZ_128M
  59
  60 #define ORION5X_PCI_MEM_PHYS_BASE       0xe8000000
  61 #define ORION5X_PCI_MEM_SIZE            SZ_128M
  62
  63 /*******************************************************************************
  64  * Supported Devices & Revisions
  65  ******************************************************************************/
  66 /* Orion-1 (88F5181) and Orion-VoIP (88F5181L) */
  67 #define MV88F5181_DEV_ID        0x5181
  68 #define MV88F5181_REV_B1        3
  69 #define MV88F5181L_REV_A0       8
  70 #define MV88F5181L_REV_A1       9
  71 /* Orion-NAS (88F5182) */
  72 #define MV88F5182_DEV_ID        0x5182
  73 #define MV88F5182_REV_A2        2
  74 /* Orion-2 (88F5281) */
  75 #define MV88F5281_DEV_ID        0x5281
  76 #define MV88F5281_REV_D0        4
  77 #define MV88F5281_REV_D1        5
  78 #define MV88F5281_REV_D2        6
  79
  80 /*******************************************************************************
  81  * Orion Registers Map
  82  ******************************************************************************/
  83 #define ORION5X_DDR_VIRT_BASE           (ORION5X_REGS_VIRT_BASE | 0x00000)
  84 #define ORION5X_DDR_REG(x)              (ORION5X_DDR_VIRT_BASE | (x))
  85
  86 #define ORION5X_DEV_BUS_PHYS_BASE       (ORION5X_REGS_PHYS_BASE | 0x10000)
  87 #define ORION5X_DEV_BUS_VIRT_BASE       (ORION5X_REGS_VIRT_BASE | 0x10000)
  88 #define ORION5X_DEV_BUS_REG(x)          (ORION5X_DEV_BUS_VIRT_BASE | (x))
  89 #define  I2C_PHYS_BASE                  (ORION5X_DEV_BUS_PHYS_BASE | 0x1000)
  90 #define  UART0_PHYS_BASE                (ORION5X_DEV_BUS_PHYS_BASE | 0x2000)
  91 #define  UART0_VIRT_BASE                (ORION5X_DEV_BUS_VIRT_BASE | 0x2000)
  92 #define  UART1_PHYS_BASE                (ORION5X_DEV_BUS_PHYS_BASE | 0x2100)
  93 #define  UART1_VIRT_BASE                (ORION5X_DEV_BUS_VIRT_BASE | 0x2100)
  94
  95 #define ORION5X_BRIDGE_VIRT_BASE        (ORION5X_REGS_VIRT_BASE | 0x20000)
  96 #define ORION5X_BRIDGE_REG(x)           (ORION5X_BRIDGE_VIRT_BASE | (x))
  97 #define  TIMER_VIRT_BASE                (ORION5X_BRIDGE_VIRT_BASE | 0x300)
  98
  99 #define ORION5X_PCI_VIRT_BASE           (ORION5X_REGS_VIRT_BASE | 0x30000)
 100 #define ORION5X_PCI_REG(x)              (ORION5X_PCI_VIRT_BASE | (x))
 101
 102 #define ORION5X_PCIE_VIRT_BASE          (ORION5X_REGS_VIRT_BASE | 0x40000)
 103 #define ORION5X_PCIE_REG(x)             (ORION5X_PCIE_VIRT_BASE | (x))
 104
 105 #define ORION5X_USB0_PHYS_BASE          (ORION5X_REGS_PHYS_BASE | 0x50000)
 106 #define ORION5X_USB0_VIRT_BASE          (ORION5X_REGS_VIRT_BASE | 0x50000)
 107 #define ORION5X_USB0_REG(x)             (ORION5X_USB0_VIRT_BASE | (x))
 108
 109 #define ORION5X_XOR_PHYS_BASE           (ORION5X_REGS_PHYS_BASE | 0x60900)
 110 #define ORION5X_XOR_VIRT_BASE           (ORION5X_REGS_VIRT_BASE | 0x60900)
 111 #define ORION5X_XOR_REG(x)              (ORION5X_XOR_VIRT_BASE | (x))
 112
 113 #define ORION5X_ETH_PHYS_BASE           (ORION5X_REGS_PHYS_BASE | 0x70000)
 114 #define ORION5X_ETH_VIRT_BASE           (ORION5X_REGS_VIRT_BASE | 0x70000)
 115 #define ORION5X_ETH_REG(x)              (ORION5X_ETH_VIRT_BASE | (x))
 116
 117 #define ORION5X_SATA_PHYS_BASE          (ORION5X_REGS_PHYS_BASE | 0x80000)
 118 #define ORION5X_SATA_VIRT_BASE          (ORION5X_REGS_VIRT_BASE | 0x80000)
 119 #define ORION5X_SATA_REG(x)             (ORION5X_SATA_VIRT_BASE | (x))
 120
 121 #define ORION5X_USB1_PHYS_BASE          (ORION5X_REGS_PHYS_BASE | 0xa0000)
 122 #define ORION5X_USB1_VIRT_BASE          (ORION5X_REGS_VIRT_BASE | 0xa0000)
 123 #define ORION5X_USB1_REG(x)             (ORION5X_USB1_VIRT_BASE | (x))
 124
 125 /*******************************************************************************
 126  * Device Bus Registers
 127  ******************************************************************************/
 128 #define MPP_0_7_CTRL            ORION5X_DEV_BUS_REG(0x000)
 129 #define MPP_8_15_CTRL           ORION5X_DEV_BUS_REG(0x004)
 130 #define MPP_16_19_CTRL          ORION5X_DEV_BUS_REG(0x050)
 131 #define MPP_DEV_CTRL            ORION5X_DEV_BUS_REG(0x008)
 132 #define MPP_RESET_SAMPLE        ORION5X_DEV_BUS_REG(0x010)
 133 #define GPIO_OUT                ORION5X_DEV_BUS_REG(0x100)
 134 #define GPIO_IO_CONF            ORION5X_DEV_BUS_REG(0x104)
 135 #define GPIO_BLINK_EN           ORION5X_DEV_BUS_REG(0x108)
 136 #define GPIO_IN_POL             ORION5X_DEV_BUS_REG(0x10c)
 137 #define GPIO_DATA_IN            ORION5X_DEV_BUS_REG(0x110)
 138 #define GPIO_EDGE_CAUSE         ORION5X_DEV_BUS_REG(0x114)
 139 #define GPIO_EDGE_MASK          ORION5X_DEV_BUS_REG(0x118)
 140 #define GPIO_LEVEL_MASK         ORION5X_DEV_BUS_REG(0x11c)
 141 #define DEV_BANK_0_PARAM        ORION5X_DEV_BUS_REG(0x45c)
 142 #define DEV_BANK_1_PARAM        ORION5X_DEV_BUS_REG(0x460)
 143 #define DEV_BANK_2_PARAM        ORION5X_DEV_BUS_REG(0x464)
 144 #define DEV_BANK_BOOT_PARAM     ORION5X_DEV_BUS_REG(0x46c)
 145 #define DEV_BUS_CTRL            ORION5X_DEV_BUS_REG(0x4c0)
 146 #define DEV_BUS_INT_CAUSE       ORION5X_DEV_BUS_REG(0x4d0)
 147 #define DEV_BUS_INT_MASK        ORION5X_DEV_BUS_REG(0x4d4)
 148 #define GPIO_MAX                32
 149
 150 /***************************************************************************
 151  * Orion CPU Bridge Registers
 152  **************************************************************************/
 153 #define CPU_CONF                ORION5X_BRIDGE_REG(0x100)
 154 #define CPU_CTRL                ORION5X_BRIDGE_REG(0x104)
 155 #define CPU_RESET_MASK          ORION5X_BRIDGE_REG(0x108)
 156 #define  WDT_RESET              0x0002
 157 #define CPU_SOFT_RESET          ORION5X_BRIDGE_REG(0x10c)
 158 #define POWER_MNG_CTRL_REG      ORION5X_BRIDGE_REG(0x11C)
 159 #define BRIDGE_CAUSE            ORION5X_BRIDGE_REG(0x110)
 160 #define  WDT_INT_REQ            0x0008
 161 #define BRIDGE_MASK             ORION5X_BRIDGE_REG(0x114)
 162 #define  BRIDGE_INT_TIMER0      0x0002
 163 #define  BRIDGE_INT_TIMER1      0x0004
 164 #define  BRIDGE_INT_TIMER1_CLR  (~0x0004)
 165 #define MAIN_IRQ_CAUSE          ORION5X_BRIDGE_REG(0x200)
 166 #define MAIN_IRQ_MASK           ORION5X_BRIDGE_REG(0x204)
 167
 168
 169 #endif