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drm/radeon/kms: rewrite DP handling
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / gpu / drm / radeon / radeon_encoders.c
blob73efb4e0b8cd48edb03e543f10986a96d937c7ca
1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26 #include "drmP.h"
27 #include "drm_crtc_helper.h"
28 #include "radeon_drm.h"
29 #include "radeon.h"
30 #include "atom.h"
31
32 extern int atom_debug;
33
34 /* evil but including atombios.h is much worse */
35 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
36 struct drm_display_mode *mode);
37
38 static uint32_t radeon_encoder_clones(struct drm_encoder *encoder)
39 {
40 struct drm_device *dev = encoder->dev;
41 struct radeon_device *rdev = dev->dev_private;
42 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
43 struct drm_encoder *clone_encoder;
44 uint32_t index_mask = 0;
45 int count;
46
47 /* DIG routing gets problematic */
48 if (rdev->family >= CHIP_R600)
49 return index_mask;
50 /* LVDS/TV are too wacky */
51 if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
52 return index_mask;
53 /* DVO requires 2x ppll clocks depending on tmds chip */
54 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT)
55 return index_mask;
56
57 count = -1;
58 list_for_each_entry(clone_encoder, &dev->mode_config.encoder_list, head) {
59 struct radeon_encoder *radeon_clone = to_radeon_encoder(clone_encoder);
60 count++;
61
62 if (clone_encoder == encoder)
63 continue;
64 if (radeon_clone->devices & (ATOM_DEVICE_LCD_SUPPORT))
65 continue;
66 if (radeon_clone->devices & ATOM_DEVICE_DFP2_SUPPORT)
67 continue;
68 else
69 index_mask |= (1 << count);
70 }
71 return index_mask;
72 }
73
74 void radeon_setup_encoder_clones(struct drm_device *dev)
75 {
76 struct drm_encoder *encoder;
77
78 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
79 encoder->possible_clones = radeon_encoder_clones(encoder);
80 }
81 }
82
83 uint32_t
84 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device, uint8_t dac)
85 {
86 struct radeon_device *rdev = dev->dev_private;
87 uint32_t ret = 0;
88
89 switch (supported_device) {
90 case ATOM_DEVICE_CRT1_SUPPORT:
91 case ATOM_DEVICE_TV1_SUPPORT:
92 case ATOM_DEVICE_TV2_SUPPORT:
93 case ATOM_DEVICE_CRT2_SUPPORT:
94 case ATOM_DEVICE_CV_SUPPORT:
95 switch (dac) {
96 case 1: /* dac a */
97 if ((rdev->family == CHIP_RS300) ||
98 (rdev->family == CHIP_RS400) ||
99 (rdev->family == CHIP_RS480))
100 ret = ENCODER_INTERNAL_DAC2_ENUM_ID1;
101 else if (ASIC_IS_AVIVO(rdev))
102 ret = ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1;
103 else
104 ret = ENCODER_INTERNAL_DAC1_ENUM_ID1;
105 break;
106 case 2: /* dac b */
107 if (ASIC_IS_AVIVO(rdev))
108 ret = ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1;
109 else {
110 /*if (rdev->family == CHIP_R200)
111 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
112 else*/
113 ret = ENCODER_INTERNAL_DAC2_ENUM_ID1;
114 }
115 break;
116 case 3: /* external dac */
117 if (ASIC_IS_AVIVO(rdev))
118 ret = ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1;
119 else
120 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
121 break;
122 }
123 break;
124 case ATOM_DEVICE_LCD1_SUPPORT:
125 if (ASIC_IS_AVIVO(rdev))
126 ret = ENCODER_INTERNAL_LVTM1_ENUM_ID1;
127 else
128 ret = ENCODER_INTERNAL_LVDS_ENUM_ID1;
129 break;
130 case ATOM_DEVICE_DFP1_SUPPORT:
131 if ((rdev->family == CHIP_RS300) ||
132 (rdev->family == CHIP_RS400) ||
133 (rdev->family == CHIP_RS480))
134 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
135 else if (ASIC_IS_AVIVO(rdev))
136 ret = ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1;
137 else
138 ret = ENCODER_INTERNAL_TMDS1_ENUM_ID1;
139 break;
140 case ATOM_DEVICE_LCD2_SUPPORT:
141 case ATOM_DEVICE_DFP2_SUPPORT:
142 if ((rdev->family == CHIP_RS600) ||
143 (rdev->family == CHIP_RS690) ||
144 (rdev->family == CHIP_RS740))
145 ret = ENCODER_INTERNAL_DDI_ENUM_ID1;
146 else if (ASIC_IS_AVIVO(rdev))
147 ret = ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1;
148 else
149 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
150 break;
151 case ATOM_DEVICE_DFP3_SUPPORT:
152 ret = ENCODER_INTERNAL_LVTM1_ENUM_ID1;
153 break;
154 }
155
156 return ret;
157 }
158
159 static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
160 {
161 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
162 switch (radeon_encoder->encoder_id) {
163 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
164 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
165 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
166 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
167 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
168 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
169 case ENCODER_OBJECT_ID_INTERNAL_DDI:
170 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
171 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
172 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
173 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
174 return true;
175 default:
176 return false;
177 }
178 }
179
180 void
181 radeon_link_encoder_connector(struct drm_device *dev)
182 {
183 struct drm_connector *connector;
184 struct radeon_connector *radeon_connector;
185 struct drm_encoder *encoder;
186 struct radeon_encoder *radeon_encoder;
187
188 /* walk the list and link encoders to connectors */
189 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
190 radeon_connector = to_radeon_connector(connector);
191 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
192 radeon_encoder = to_radeon_encoder(encoder);
193 if (radeon_encoder->devices & radeon_connector->devices)
194 drm_mode_connector_attach_encoder(connector, encoder);
195 }
196 }
197 }
198
199 void radeon_encoder_set_active_device(struct drm_encoder *encoder)
200 {
201 struct drm_device *dev = encoder->dev;
202 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
203 struct drm_connector *connector;
204
205 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
206 if (connector->encoder == encoder) {
207 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
208 radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices;
209 DRM_DEBUG_KMS("setting active device to %08x from %08x %08x for encoder %d\n",
210 radeon_encoder->active_device, radeon_encoder->devices,
211 radeon_connector->devices, encoder->encoder_type);
212 }
213 }
214 }
215
216 struct drm_connector *
217 radeon_get_connector_for_encoder(struct drm_encoder *encoder)
218 {
219 struct drm_device *dev = encoder->dev;
220 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
221 struct drm_connector *connector;
222 struct radeon_connector *radeon_connector;
223
224 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
225 radeon_connector = to_radeon_connector(connector);
226 if (radeon_encoder->active_device & radeon_connector->devices)
227 return connector;
228 }
229 return NULL;
230 }
231
232 struct drm_encoder *radeon_atom_get_external_encoder(struct drm_encoder *encoder)
233 {
234 struct drm_device *dev = encoder->dev;
235 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
236 struct drm_encoder *other_encoder;
237 struct radeon_encoder *other_radeon_encoder;
238
239 if (radeon_encoder->is_ext_encoder)
240 return NULL;
241
242 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
243 if (other_encoder == encoder)
244 continue;
245 other_radeon_encoder = to_radeon_encoder(other_encoder);
246 if (other_radeon_encoder->is_ext_encoder &&
247 (radeon_encoder->devices & other_radeon_encoder->devices))
248 return other_encoder;
249 }
250 return NULL;
251 }
252
253 bool radeon_encoder_is_dp_bridge(struct drm_encoder *encoder)
254 {
255 struct drm_encoder *other_encoder = radeon_atom_get_external_encoder(encoder);
256
257 if (other_encoder) {
258 struct radeon_encoder *radeon_encoder = to_radeon_encoder(other_encoder);
259
260 switch (radeon_encoder->encoder_id) {
261 case ENCODER_OBJECT_ID_TRAVIS:
262 case ENCODER_OBJECT_ID_NUTMEG:
263 return true;
264 default:
265 return false;
266 }
267 }
268
269 return false;
270 }
271
272 void radeon_panel_mode_fixup(struct drm_encoder *encoder,
273 struct drm_display_mode *adjusted_mode)
274 {
275 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
276 struct drm_device *dev = encoder->dev;
277 struct radeon_device *rdev = dev->dev_private;
278 struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
279 unsigned hblank = native_mode->htotal - native_mode->hdisplay;
280 unsigned vblank = native_mode->vtotal - native_mode->vdisplay;
281 unsigned hover = native_mode->hsync_start - native_mode->hdisplay;
282 unsigned vover = native_mode->vsync_start - native_mode->vdisplay;
283 unsigned hsync_width = native_mode->hsync_end - native_mode->hsync_start;
284 unsigned vsync_width = native_mode->vsync_end - native_mode->vsync_start;
285
286 adjusted_mode->clock = native_mode->clock;
287 adjusted_mode->flags = native_mode->flags;
288
289 if (ASIC_IS_AVIVO(rdev)) {
290 adjusted_mode->hdisplay = native_mode->hdisplay;
291 adjusted_mode->vdisplay = native_mode->vdisplay;
292 }
293
294 adjusted_mode->htotal = native_mode->hdisplay + hblank;
295 adjusted_mode->hsync_start = native_mode->hdisplay + hover;
296 adjusted_mode->hsync_end = adjusted_mode->hsync_start + hsync_width;
297
298 adjusted_mode->vtotal = native_mode->vdisplay + vblank;
299 adjusted_mode->vsync_start = native_mode->vdisplay + vover;
300 adjusted_mode->vsync_end = adjusted_mode->vsync_start + vsync_width;
301
302 drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
303
304 if (ASIC_IS_AVIVO(rdev)) {
305 adjusted_mode->crtc_hdisplay = native_mode->hdisplay;
306 adjusted_mode->crtc_vdisplay = native_mode->vdisplay;
307 }
308
309 adjusted_mode->crtc_htotal = adjusted_mode->crtc_hdisplay + hblank;
310 adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hdisplay + hover;
311 adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_start + hsync_width;
312
313 adjusted_mode->crtc_vtotal = adjusted_mode->crtc_vdisplay + vblank;
314 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + vover;
315 adjusted_mode->crtc_vsync_end = adjusted_mode->crtc_vsync_start + vsync_width;
316
317 }
318
319 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
320 struct drm_display_mode *mode,
321 struct drm_display_mode *adjusted_mode)
322 {
323 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
324 struct drm_device *dev = encoder->dev;
325 struct radeon_device *rdev = dev->dev_private;
326
327 /* set the active encoder to connector routing */
328 radeon_encoder_set_active_device(encoder);
329 drm_mode_set_crtcinfo(adjusted_mode, 0);
330
331 /* hw bug */
332 if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
333 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
334 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
335
336 /* get the native mode for LVDS */
337 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
338 radeon_panel_mode_fixup(encoder, adjusted_mode);
339
340 /* get the native mode for TV */
341 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
342 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
343 if (tv_dac) {
344 if (tv_dac->tv_std == TV_STD_NTSC ||
345 tv_dac->tv_std == TV_STD_NTSC_J ||
346 tv_dac->tv_std == TV_STD_PAL_M)
347 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
348 else
349 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
350 }
351 }
352
353 if (ASIC_IS_DCE3(rdev) &&
354 (radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT))) {
355 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
356 radeon_dp_set_link_config(connector, mode);
357 }
358
359 return true;
360 }
361
362 static void
363 atombios_dac_setup(struct drm_encoder *encoder, int action)
364 {
365 struct drm_device *dev = encoder->dev;
366 struct radeon_device *rdev = dev->dev_private;
367 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
368 DAC_ENCODER_CONTROL_PS_ALLOCATION args;
369 int index = 0;
370 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
371
372 memset(&args, 0, sizeof(args));
373
374 switch (radeon_encoder->encoder_id) {
375 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
376 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
377 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
378 break;
379 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
380 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
381 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
382 break;
383 }
384
385 args.ucAction = action;
386
387 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
388 args.ucDacStandard = ATOM_DAC1_PS2;
389 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
390 args.ucDacStandard = ATOM_DAC1_CV;
391 else {
392 switch (dac_info->tv_std) {
393 case TV_STD_PAL:
394 case TV_STD_PAL_M:
395 case TV_STD_SCART_PAL:
396 case TV_STD_SECAM:
397 case TV_STD_PAL_CN:
398 args.ucDacStandard = ATOM_DAC1_PAL;
399 break;
400 case TV_STD_NTSC:
401 case TV_STD_NTSC_J:
402 case TV_STD_PAL_60:
403 default:
404 args.ucDacStandard = ATOM_DAC1_NTSC;
405 break;
406 }
407 }
408 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
409
410 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
411
412 }
413
414 static void
415 atombios_tv_setup(struct drm_encoder *encoder, int action)
416 {
417 struct drm_device *dev = encoder->dev;
418 struct radeon_device *rdev = dev->dev_private;
419 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
420 TV_ENCODER_CONTROL_PS_ALLOCATION args;
421 int index = 0;
422 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
423
424 memset(&args, 0, sizeof(args));
425
426 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
427
428 args.sTVEncoder.ucAction = action;
429
430 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
431 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
432 else {
433 switch (dac_info->tv_std) {
434 case TV_STD_NTSC:
435 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
436 break;
437 case TV_STD_PAL:
438 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
439 break;
440 case TV_STD_PAL_M:
441 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
442 break;
443 case TV_STD_PAL_60:
444 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
445 break;
446 case TV_STD_NTSC_J:
447 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
448 break;
449 case TV_STD_SCART_PAL:
450 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
451 break;
452 case TV_STD_SECAM:
453 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
454 break;
455 case TV_STD_PAL_CN:
456 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
457 break;
458 default:
459 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
460 break;
461 }
462 }
463
464 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
465
466 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
467
468 }
469
470 union dvo_encoder_control {
471 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
472 DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
473 DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
474 };
475
476 void
477 atombios_dvo_setup(struct drm_encoder *encoder, int action)
478 {
479 struct drm_device *dev = encoder->dev;
480 struct radeon_device *rdev = dev->dev_private;
481 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
482 union dvo_encoder_control args;
483 int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
484
485 memset(&args, 0, sizeof(args));
486
487 if (ASIC_IS_DCE3(rdev)) {
488 /* DCE3+ */
489 args.dvo_v3.ucAction = action;
490 args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
491 args.dvo_v3.ucDVOConfig = 0; /* XXX */
492 } else if (ASIC_IS_DCE2(rdev)) {
493 /* DCE2 (pre-DCE3 R6xx, RS600/690/740 */
494 args.dvo.sDVOEncoder.ucAction = action;
495 args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
496 /* DFP1, CRT1, TV1 depending on the type of port */
497 args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
498
499 if (radeon_encoder->pixel_clock > 165000)
500 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
501 } else {
502 /* R4xx, R5xx */
503 args.ext_tmds.sXTmdsEncoder.ucEnable = action;
504
505 if (radeon_encoder->pixel_clock > 165000)
506 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
507
508 /*if (pScrn->rgbBits == 8)*/
509 args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
510 }
511
512 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
513 }
514
515 union lvds_encoder_control {
516 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1;
517 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
518 };
519
520 void
521 atombios_digital_setup(struct drm_encoder *encoder, int action)
522 {
523 struct drm_device *dev = encoder->dev;
524 struct radeon_device *rdev = dev->dev_private;
525 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
526 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
527 union lvds_encoder_control args;
528 int index = 0;
529 int hdmi_detected = 0;
530 uint8_t frev, crev;
531
532 if (!dig)
533 return;
534
535 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
536 hdmi_detected = 1;
537
538 memset(&args, 0, sizeof(args));
539
540 switch (radeon_encoder->encoder_id) {
541 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
542 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
543 break;
544 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
545 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
546 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
547 break;
548 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
549 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
550 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
551 else
552 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
553 break;
554 }
555
556 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
557 return;
558
559 switch (frev) {
560 case 1:
561 case 2:
562 switch (crev) {
563 case 1:
564 args.v1.ucMisc = 0;
565 args.v1.ucAction = action;
566 if (hdmi_detected)
567 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
568 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
569 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
570 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
571 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
572 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
573 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
574 } else {
575 if (dig->linkb)
576 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
577 if (radeon_encoder->pixel_clock > 165000)
578 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
579 /*if (pScrn->rgbBits == 8) */
580 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
581 }
582 break;
583 case 2:
584 case 3:
585 args.v2.ucMisc = 0;
586 args.v2.ucAction = action;
587 if (crev == 3) {
588 if (dig->coherent_mode)
589 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
590 }
591 if (hdmi_detected)
592 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
593 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
594 args.v2.ucTruncate = 0;
595 args.v2.ucSpatial = 0;
596 args.v2.ucTemporal = 0;
597 args.v2.ucFRC = 0;
598 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
599 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
600 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
601 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
602 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
603 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
604 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
605 }
606 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
607 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
608 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
609 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
610 if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
611 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
612 }
613 } else {
614 if (dig->linkb)
615 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
616 if (radeon_encoder->pixel_clock > 165000)
617 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
618 }
619 break;
620 default:
621 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
622 break;
623 }
624 break;
625 default:
626 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
627 break;
628 }
629
630 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
631 }
632
633 int
634 atombios_get_encoder_mode(struct drm_encoder *encoder)
635 {
636 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
637 struct drm_device *dev = encoder->dev;
638 struct radeon_device *rdev = dev->dev_private;
639 struct drm_connector *connector;
640 struct radeon_connector *radeon_connector;
641 struct radeon_connector_atom_dig *dig_connector;
642
643 /* dp bridges are always DP */
644 if (radeon_encoder_is_dp_bridge(encoder))
645 return ATOM_ENCODER_MODE_DP;
646
647 connector = radeon_get_connector_for_encoder(encoder);
648 if (!connector) {
649 switch (radeon_encoder->encoder_id) {
650 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
651 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
652 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
653 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
654 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
655 return ATOM_ENCODER_MODE_DVI;
656 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
657 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
658 default:
659 return ATOM_ENCODER_MODE_CRT;
660 }
661 }
662 radeon_connector = to_radeon_connector(connector);
663
664 switch (connector->connector_type) {
665 case DRM_MODE_CONNECTOR_DVII:
666 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
667 if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) {
668 /* fix me */
669 if (ASIC_IS_DCE4(rdev))
670 return ATOM_ENCODER_MODE_DVI;
671 else
672 return ATOM_ENCODER_MODE_HDMI;
673 } else if (radeon_connector->use_digital)
674 return ATOM_ENCODER_MODE_DVI;
675 else
676 return ATOM_ENCODER_MODE_CRT;
677 break;
678 case DRM_MODE_CONNECTOR_DVID:
679 case DRM_MODE_CONNECTOR_HDMIA:
680 default:
681 if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) {
682 /* fix me */
683 if (ASIC_IS_DCE4(rdev))
684 return ATOM_ENCODER_MODE_DVI;
685 else
686 return ATOM_ENCODER_MODE_HDMI;
687 } else
688 return ATOM_ENCODER_MODE_DVI;
689 break;
690 case DRM_MODE_CONNECTOR_LVDS:
691 return ATOM_ENCODER_MODE_LVDS;
692 break;
693 case DRM_MODE_CONNECTOR_DisplayPort:
694 dig_connector = radeon_connector->con_priv;
695 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
696 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
697 return ATOM_ENCODER_MODE_DP;
698 else if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) {
699 /* fix me */
700 if (ASIC_IS_DCE4(rdev))
701 return ATOM_ENCODER_MODE_DVI;
702 else
703 return ATOM_ENCODER_MODE_HDMI;
704 } else
705 return ATOM_ENCODER_MODE_DVI;
706 break;
707 case DRM_MODE_CONNECTOR_eDP:
708 return ATOM_ENCODER_MODE_DP;
709 case DRM_MODE_CONNECTOR_DVIA:
710 case DRM_MODE_CONNECTOR_VGA:
711 return ATOM_ENCODER_MODE_CRT;
712 break;
713 case DRM_MODE_CONNECTOR_Composite:
714 case DRM_MODE_CONNECTOR_SVIDEO:
715 case DRM_MODE_CONNECTOR_9PinDIN:
716 /* fix me */
717 return ATOM_ENCODER_MODE_TV;
718 /*return ATOM_ENCODER_MODE_CV;*/
719 break;
720 }
721 }
722
723 /*
724 * DIG Encoder/Transmitter Setup
725 *
726 * DCE 3.0/3.1
727 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
728 * Supports up to 3 digital outputs
729 * - 2 DIG encoder blocks.
730 * DIG1 can drive UNIPHY link A or link B
731 * DIG2 can drive UNIPHY link B or LVTMA
732 *
733 * DCE 3.2
734 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
735 * Supports up to 5 digital outputs
736 * - 2 DIG encoder blocks.
737 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
738 *
739 * DCE 4.0/5.0
740 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
741 * Supports up to 6 digital outputs
742 * - 6 DIG encoder blocks.
743 * - DIG to PHY mapping is hardcoded
744 * DIG1 drives UNIPHY0 link A, A+B
745 * DIG2 drives UNIPHY0 link B
746 * DIG3 drives UNIPHY1 link A, A+B
747 * DIG4 drives UNIPHY1 link B
748 * DIG5 drives UNIPHY2 link A, A+B
749 * DIG6 drives UNIPHY2 link B
750 *
751 * DCE 4.1
752 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
753 * Supports up to 6 digital outputs
754 * - 2 DIG encoder blocks.
755 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
756 *
757 * Routing
758 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
759 * Examples:
760 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI
761 * crtc1 -> dig1 -> UNIPHY0 link B -> DP
762 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS
763 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI
764 */
765
766 union dig_encoder_control {
767 DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
768 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
769 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
770 DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
771 };
772
773 void
774 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode)
775 {
776 struct drm_device *dev = encoder->dev;
777 struct radeon_device *rdev = dev->dev_private;
778 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
779 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
780 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
781 union dig_encoder_control args;
782 int index = 0;
783 uint8_t frev, crev;
784 int dp_clock = 0;
785 int dp_lane_count = 0;
786 int hpd_id = RADEON_HPD_NONE;
787 int bpc = 8;
788
789 if (connector) {
790 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
791 struct radeon_connector_atom_dig *dig_connector =
792 radeon_connector->con_priv;
793
794 dp_clock = dig_connector->dp_clock;
795 dp_lane_count = dig_connector->dp_lane_count;
796 hpd_id = radeon_connector->hpd.hpd;
797 bpc = connector->display_info.bpc;
798 }
799
800 /* no dig encoder assigned */
801 if (dig->dig_encoder == -1)
802 return;
803
804 memset(&args, 0, sizeof(args));
805
806 if (ASIC_IS_DCE4(rdev))
807 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
808 else {
809 if (dig->dig_encoder)
810 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
811 else
812 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
813 }
814
815 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
816 return;
817
818 args.v1.ucAction = action;
819 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
820 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
821 args.v3.ucPanelMode = panel_mode;
822 else
823 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
824
825 if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) ||
826 (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP_MST))
827 args.v1.ucLaneNum = dp_lane_count;
828 else if (radeon_encoder->pixel_clock > 165000)
829 args.v1.ucLaneNum = 8;
830 else
831 args.v1.ucLaneNum = 4;
832
833 if (ASIC_IS_DCE5(rdev)) {
834 if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) ||
835 (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP_MST)) {
836 if (dp_clock == 270000)
837 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
838 else if (dp_clock == 540000)
839 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
840 }
841 args.v4.acConfig.ucDigSel = dig->dig_encoder;
842 switch (bpc) {
843 case 0:
844 args.v4.ucBitPerColor = PANEL_BPC_UNDEFINE;
845 break;
846 case 6:
847 args.v4.ucBitPerColor = PANEL_6BIT_PER_COLOR;
848 break;
849 case 8:
850 default:
851 args.v4.ucBitPerColor = PANEL_8BIT_PER_COLOR;
852 break;
853 case 10:
854 args.v4.ucBitPerColor = PANEL_10BIT_PER_COLOR;
855 break;
856 case 12:
857 args.v4.ucBitPerColor = PANEL_12BIT_PER_COLOR;
858 break;
859 case 16:
860 args.v4.ucBitPerColor = PANEL_16BIT_PER_COLOR;
861 break;
862 }
863 if (hpd_id == RADEON_HPD_NONE)
864 args.v4.ucHPD_ID = 0;
865 else
866 args.v4.ucHPD_ID = hpd_id + 1;
867 } else if (ASIC_IS_DCE4(rdev)) {
868 if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) && (dp_clock == 270000))
869 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
870 args.v3.acConfig.ucDigSel = dig->dig_encoder;
871 switch (bpc) {
872 case 0:
873 args.v3.ucBitPerColor = PANEL_BPC_UNDEFINE;
874 break;
875 case 6:
876 args.v3.ucBitPerColor = PANEL_6BIT_PER_COLOR;
877 break;
878 case 8:
879 default:
880 args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR;
881 break;
882 case 10:
883 args.v3.ucBitPerColor = PANEL_10BIT_PER_COLOR;
884 break;
885 case 12:
886 args.v3.ucBitPerColor = PANEL_12BIT_PER_COLOR;
887 break;
888 case 16:
889 args.v3.ucBitPerColor = PANEL_16BIT_PER_COLOR;
890 break;
891 }
892 } else {
893 if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) && (dp_clock == 270000))
894 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
895 switch (radeon_encoder->encoder_id) {
896 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
897 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
898 break;
899 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
900 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
901 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
902 break;
903 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
904 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
905 break;
906 }
907 if (dig->linkb)
908 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
909 else
910 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
911 }
912
913 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
914
915 }
916
917 union dig_transmitter_control {
918 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
919 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
920 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
921 DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
922 };
923
924 void
925 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
926 {
927 struct drm_device *dev = encoder->dev;
928 struct radeon_device *rdev = dev->dev_private;
929 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
930 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
931 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
932 union dig_transmitter_control args;
933 int index = 0;
934 uint8_t frev, crev;
935 bool is_dp = false;
936 int pll_id = 0;
937 int dp_clock = 0;
938 int dp_lane_count = 0;
939 int connector_object_id = 0;
940 int igp_lane_info = 0;
941
942 if (connector) {
943 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
944 struct radeon_connector_atom_dig *dig_connector =
945 radeon_connector->con_priv;
946
947 dp_clock = dig_connector->dp_clock;
948 dp_lane_count = dig_connector->dp_lane_count;
949 connector_object_id =
950 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
951 igp_lane_info = dig_connector->igp_lane_info;
952 }
953
954 /* no dig encoder assigned */
955 if (dig->dig_encoder == -1)
956 return;
957
958 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP)
959 is_dp = true;
960
961 memset(&args, 0, sizeof(args));
962
963 switch (radeon_encoder->encoder_id) {
964 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
965 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
966 break;
967 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
968 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
969 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
970 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
971 break;
972 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
973 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
974 break;
975 }
976
977 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
978 return;
979
980 args.v1.ucAction = action;
981 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
982 args.v1.usInitInfo = cpu_to_le16(connector_object_id);
983 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
984 args.v1.asMode.ucLaneSel = lane_num;
985 args.v1.asMode.ucLaneSet = lane_set;
986 } else {
987 if (is_dp)
988 args.v1.usPixelClock =
989 cpu_to_le16(dp_clock / 10);
990 else if (radeon_encoder->pixel_clock > 165000)
991 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
992 else
993 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
994 }
995 if (ASIC_IS_DCE4(rdev)) {
996 if (is_dp)
997 args.v3.ucLaneNum = dp_lane_count;
998 else if (radeon_encoder->pixel_clock > 165000)
999 args.v3.ucLaneNum = 8;
1000 else
1001 args.v3.ucLaneNum = 4;
1002
1003 if (dig->linkb)
1004 args.v3.acConfig.ucLinkSel = 1;
1005 if (dig->dig_encoder & 1)
1006 args.v3.acConfig.ucEncoderSel = 1;
1007
1008 /* Select the PLL for the PHY
1009 * DP PHY should be clocked from external src if there is
1010 * one.
1011 */
1012 if (encoder->crtc) {
1013 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1014 pll_id = radeon_crtc->pll_id;
1015 }
1016
1017 if (ASIC_IS_DCE5(rdev)) {
1018 /* On DCE5 DCPLL usually generates the DP ref clock */
1019 if (is_dp) {
1020 if (rdev->clock.dp_extclk)
1021 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
1022 else
1023 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
1024 } else
1025 args.v4.acConfig.ucRefClkSource = pll_id;
1026 } else {
1027 /* On DCE4, if there is an external clock, it generates the DP ref clock */
1028 if (is_dp && rdev->clock.dp_extclk)
1029 args.v3.acConfig.ucRefClkSource = 2; /* external src */
1030 else
1031 args.v3.acConfig.ucRefClkSource = pll_id;
1032 }
1033
1034 switch (radeon_encoder->encoder_id) {
1035 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1036 args.v3.acConfig.ucTransmitterSel = 0;
1037 break;
1038 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1039 args.v3.acConfig.ucTransmitterSel = 1;
1040 break;
1041 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1042 args.v3.acConfig.ucTransmitterSel = 2;
1043 break;
1044 }
1045
1046 if (is_dp)
1047 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
1048 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1049 if (dig->coherent_mode)
1050 args.v3.acConfig.fCoherentMode = 1;
1051 if (radeon_encoder->pixel_clock > 165000)
1052 args.v3.acConfig.fDualLinkConnector = 1;
1053 }
1054 } else if (ASIC_IS_DCE32(rdev)) {
1055 args.v2.acConfig.ucEncoderSel = dig->dig_encoder;
1056 if (dig->linkb)
1057 args.v2.acConfig.ucLinkSel = 1;
1058
1059 switch (radeon_encoder->encoder_id) {
1060 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1061 args.v2.acConfig.ucTransmitterSel = 0;
1062 break;
1063 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1064 args.v2.acConfig.ucTransmitterSel = 1;
1065 break;
1066 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1067 args.v2.acConfig.ucTransmitterSel = 2;
1068 break;
1069 }
1070
1071 if (is_dp)
1072 args.v2.acConfig.fCoherentMode = 1;
1073 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1074 if (dig->coherent_mode)
1075 args.v2.acConfig.fCoherentMode = 1;
1076 if (radeon_encoder->pixel_clock > 165000)
1077 args.v2.acConfig.fDualLinkConnector = 1;
1078 }
1079 } else {
1080 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
1081
1082 if (dig->dig_encoder)
1083 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
1084 else
1085 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
1086
1087 if ((rdev->flags & RADEON_IS_IGP) &&
1088 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
1089 if (is_dp || (radeon_encoder->pixel_clock <= 165000)) {
1090 if (igp_lane_info & 0x1)
1091 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
1092 else if (igp_lane_info & 0x2)
1093 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
1094 else if (igp_lane_info & 0x4)
1095 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
1096 else if (igp_lane_info & 0x8)
1097 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
1098 } else {
1099 if (igp_lane_info & 0x3)
1100 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
1101 else if (igp_lane_info & 0xc)
1102 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
1103 }
1104 }
1105
1106 if (dig->linkb)
1107 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
1108 else
1109 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
1110
1111 if (is_dp)
1112 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1113 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1114 if (dig->coherent_mode)
1115 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1116 if (radeon_encoder->pixel_clock > 165000)
1117 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
1118 }
1119 }
1120
1121 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1122 }
1123
1124 bool
1125 atombios_set_edp_panel_power(struct drm_connector *connector, int action)
1126 {
1127 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1128 struct drm_device *dev = radeon_connector->base.dev;
1129 struct radeon_device *rdev = dev->dev_private;
1130 union dig_transmitter_control args;
1131 int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1132 uint8_t frev, crev;
1133
1134 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
1135 goto done;
1136
1137 if (!ASIC_IS_DCE4(rdev))
1138 goto done;
1139
1140 if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
1141 (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
1142 goto done;
1143
1144 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1145 goto done;
1146
1147 memset(&args, 0, sizeof(args));
1148
1149 args.v1.ucAction = action;
1150
1151 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1152
1153 /* wait for the panel to power up */
1154 if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) {
1155 int i;
1156
1157 for (i = 0; i < 300; i++) {
1158 if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
1159 return true;
1160 mdelay(1);
1161 }
1162 return false;
1163 }
1164 done:
1165 return true;
1166 }
1167
1168 union external_encoder_control {
1169 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
1170 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
1171 };
1172
1173 static void
1174 atombios_external_encoder_setup(struct drm_encoder *encoder,
1175 struct drm_encoder *ext_encoder,
1176 int action)
1177 {
1178 struct drm_device *dev = encoder->dev;
1179 struct radeon_device *rdev = dev->dev_private;
1180 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1181 struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
1182 union external_encoder_control args;
1183 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1184 int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
1185 u8 frev, crev;
1186 int dp_clock = 0;
1187 int dp_lane_count = 0;
1188 int connector_object_id = 0;
1189 u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1190 int bpc = 8;
1191
1192 if (connector) {
1193 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1194 struct radeon_connector_atom_dig *dig_connector =
1195 radeon_connector->con_priv;
1196
1197 dp_clock = dig_connector->dp_clock;
1198 dp_lane_count = dig_connector->dp_lane_count;
1199 connector_object_id =
1200 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1201 bpc = connector->display_info.bpc;
1202 }
1203
1204 memset(&args, 0, sizeof(args));
1205
1206 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1207 return;
1208
1209 switch (frev) {
1210 case 1:
1211 /* no params on frev 1 */
1212 break;
1213 case 2:
1214 switch (crev) {
1215 case 1:
1216 case 2:
1217 args.v1.sDigEncoder.ucAction = action;
1218 args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1219 args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1220
1221 if (args.v1.sDigEncoder.ucEncoderMode == ATOM_ENCODER_MODE_DP) {
1222 if (dp_clock == 270000)
1223 args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1224 args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
1225 } else if (radeon_encoder->pixel_clock > 165000)
1226 args.v1.sDigEncoder.ucLaneNum = 8;
1227 else
1228 args.v1.sDigEncoder.ucLaneNum = 4;
1229 break;
1230 case 3:
1231 args.v3.sExtEncoder.ucAction = action;
1232 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1233 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
1234 else
1235 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1236 args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1237
1238 if (args.v3.sExtEncoder.ucEncoderMode == ATOM_ENCODER_MODE_DP) {
1239 if (dp_clock == 270000)
1240 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1241 else if (dp_clock == 540000)
1242 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1243 args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
1244 } else if (radeon_encoder->pixel_clock > 165000)
1245 args.v3.sExtEncoder.ucLaneNum = 8;
1246 else
1247 args.v3.sExtEncoder.ucLaneNum = 4;
1248 switch (ext_enum) {
1249 case GRAPH_OBJECT_ENUM_ID1:
1250 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1251 break;
1252 case GRAPH_OBJECT_ENUM_ID2:
1253 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1254 break;
1255 case GRAPH_OBJECT_ENUM_ID3:
1256 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1257 break;
1258 }
1259 switch (bpc) {
1260 case 0:
1261 args.v3.sExtEncoder.ucBitPerColor = PANEL_BPC_UNDEFINE;
1262 break;
1263 case 6:
1264 args.v3.sExtEncoder.ucBitPerColor = PANEL_6BIT_PER_COLOR;
1265 break;
1266 case 8:
1267 default:
1268 args.v3.sExtEncoder.ucBitPerColor = PANEL_8BIT_PER_COLOR;
1269 break;
1270 case 10:
1271 args.v3.sExtEncoder.ucBitPerColor = PANEL_10BIT_PER_COLOR;
1272 break;
1273 case 12:
1274 args.v3.sExtEncoder.ucBitPerColor = PANEL_12BIT_PER_COLOR;
1275 break;
1276 case 16:
1277 args.v3.sExtEncoder.ucBitPerColor = PANEL_16BIT_PER_COLOR;
1278 break;
1279 }
1280 break;
1281 default:
1282 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1283 return;
1284 }
1285 break;
1286 default:
1287 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1288 return;
1289 }
1290 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1291 }
1292
1293 static void
1294 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1295 {
1296 struct drm_device *dev = encoder->dev;
1297 struct radeon_device *rdev = dev->dev_private;
1298 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1299 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1300 ENABLE_YUV_PS_ALLOCATION args;
1301 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1302 uint32_t temp, reg;
1303
1304 memset(&args, 0, sizeof(args));
1305
1306 if (rdev->family >= CHIP_R600)
1307 reg = R600_BIOS_3_SCRATCH;
1308 else
1309 reg = RADEON_BIOS_3_SCRATCH;
1310
1311 /* XXX: fix up scratch reg handling */
1312 temp = RREG32(reg);
1313 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1314 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1315 (radeon_crtc->crtc_id << 18)));
1316 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1317 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1318 else
1319 WREG32(reg, 0);
1320
1321 if (enable)
1322 args.ucEnable = ATOM_ENABLE;
1323 args.ucCRTC = radeon_crtc->crtc_id;
1324
1325 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1326
1327 WREG32(reg, temp);
1328 }
1329
1330 static void
1331 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1332 {
1333 struct drm_device *dev = encoder->dev;
1334 struct radeon_device *rdev = dev->dev_private;
1335 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1336 struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder);
1337 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1338 int index = 0;
1339 bool is_dig = false;
1340 bool is_dce5_dac = false;
1341 bool is_dce5_dvo = false;
1342
1343 memset(&args, 0, sizeof(args));
1344
1345 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1346 radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1347 radeon_encoder->active_device);
1348 switch (radeon_encoder->encoder_id) {
1349 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1350 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1351 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1352 break;
1353 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1354 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1355 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1356 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1357 is_dig = true;
1358 break;
1359 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1360 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1361 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1362 break;
1363 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1364 if (ASIC_IS_DCE5(rdev))
1365 is_dce5_dvo = true;
1366 else if (ASIC_IS_DCE3(rdev))
1367 is_dig = true;
1368 else
1369 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1370 break;
1371 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1372 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1373 break;
1374 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1375 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1376 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1377 else
1378 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1379 break;
1380 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1381 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1382 if (ASIC_IS_DCE5(rdev))
1383 is_dce5_dac = true;
1384 else {
1385 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1386 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1387 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1388 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1389 else
1390 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1391 }
1392 break;
1393 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1394 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1395 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1396 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1397 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1398 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1399 else
1400 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1401 break;
1402 }
1403
1404 if (is_dig) {
1405 switch (mode) {
1406 case DRM_MODE_DPMS_ON:
1407 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1408 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) {
1409 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1410
1411 if (connector &&
1412 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
1413 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1414 struct radeon_connector_atom_dig *radeon_dig_connector =
1415 radeon_connector->con_priv;
1416 atombios_set_edp_panel_power(connector,
1417 ATOM_TRANSMITTER_ACTION_POWER_ON);
1418 radeon_dig_connector->edp_on = true;
1419 }
1420 if (ASIC_IS_DCE4(rdev))
1421 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1422 radeon_dp_link_train(encoder, connector);
1423 if (ASIC_IS_DCE4(rdev))
1424 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
1425 }
1426 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1427 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1428 break;
1429 case DRM_MODE_DPMS_STANDBY:
1430 case DRM_MODE_DPMS_SUSPEND:
1431 case DRM_MODE_DPMS_OFF:
1432 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1433 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) {
1434 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1435
1436 if (ASIC_IS_DCE4(rdev))
1437 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1438 if (connector &&
1439 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
1440 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1441 struct radeon_connector_atom_dig *radeon_dig_connector =
1442 radeon_connector->con_priv;
1443 atombios_set_edp_panel_power(connector,
1444 ATOM_TRANSMITTER_ACTION_POWER_OFF);
1445 radeon_dig_connector->edp_on = false;
1446 }
1447 }
1448 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1449 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1450 break;
1451 }
1452 } else if (is_dce5_dac) {
1453 switch (mode) {
1454 case DRM_MODE_DPMS_ON:
1455 atombios_dac_setup(encoder, ATOM_ENABLE);
1456 break;
1457 case DRM_MODE_DPMS_STANDBY:
1458 case DRM_MODE_DPMS_SUSPEND:
1459 case DRM_MODE_DPMS_OFF:
1460 atombios_dac_setup(encoder, ATOM_DISABLE);
1461 break;
1462 }
1463 } else if (is_dce5_dvo) {
1464 switch (mode) {
1465 case DRM_MODE_DPMS_ON:
1466 atombios_dvo_setup(encoder, ATOM_ENABLE);
1467 break;
1468 case DRM_MODE_DPMS_STANDBY:
1469 case DRM_MODE_DPMS_SUSPEND:
1470 case DRM_MODE_DPMS_OFF:
1471 atombios_dvo_setup(encoder, ATOM_DISABLE);
1472 break;
1473 }
1474 } else {
1475 switch (mode) {
1476 case DRM_MODE_DPMS_ON:
1477 args.ucAction = ATOM_ENABLE;
1478 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1479 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1480 args.ucAction = ATOM_LCD_BLON;
1481 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1482 }
1483 break;
1484 case DRM_MODE_DPMS_STANDBY:
1485 case DRM_MODE_DPMS_SUSPEND:
1486 case DRM_MODE_DPMS_OFF:
1487 args.ucAction = ATOM_DISABLE;
1488 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1489 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1490 args.ucAction = ATOM_LCD_BLOFF;
1491 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1492 }
1493 break;
1494 }
1495 }
1496
1497 if (ext_encoder) {
1498 int action;
1499
1500 switch (mode) {
1501 case DRM_MODE_DPMS_ON:
1502 default:
1503 if (ASIC_IS_DCE41(rdev))
1504 action = EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT;
1505 else
1506 action = ATOM_ENABLE;
1507 break;
1508 case DRM_MODE_DPMS_STANDBY:
1509 case DRM_MODE_DPMS_SUSPEND:
1510 case DRM_MODE_DPMS_OFF:
1511 if (ASIC_IS_DCE41(rdev))
1512 action = EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT;
1513 else
1514 action = ATOM_DISABLE;
1515 break;
1516 }
1517 atombios_external_encoder_setup(encoder, ext_encoder, action);
1518 }
1519
1520 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1521
1522 }
1523
1524 union crtc_source_param {
1525 SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1526 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1527 };
1528
1529 static void
1530 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1531 {
1532 struct drm_device *dev = encoder->dev;
1533 struct radeon_device *rdev = dev->dev_private;
1534 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1535 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1536 union crtc_source_param args;
1537 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1538 uint8_t frev, crev;
1539 struct radeon_encoder_atom_dig *dig;
1540
1541 memset(&args, 0, sizeof(args));
1542
1543 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1544 return;
1545
1546 switch (frev) {
1547 case 1:
1548 switch (crev) {
1549 case 1:
1550 default:
1551 if (ASIC_IS_AVIVO(rdev))
1552 args.v1.ucCRTC = radeon_crtc->crtc_id;
1553 else {
1554 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1555 args.v1.ucCRTC = radeon_crtc->crtc_id;
1556 } else {
1557 args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1558 }
1559 }
1560 switch (radeon_encoder->encoder_id) {
1561 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1562 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1563 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1564 break;
1565 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1566 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1567 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1568 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1569 else
1570 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1571 break;
1572 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1573 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1574 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1575 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1576 break;
1577 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1578 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1579 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1580 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1581 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1582 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1583 else
1584 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1585 break;
1586 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1587 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1588 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1589 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1590 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1591 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1592 else
1593 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1594 break;
1595 }
1596 break;
1597 case 2:
1598 args.v2.ucCRTC = radeon_crtc->crtc_id;
1599 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1600 switch (radeon_encoder->encoder_id) {
1601 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1602 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1603 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1604 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1605 dig = radeon_encoder->enc_priv;
1606 switch (dig->dig_encoder) {
1607 case 0:
1608 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1609 break;
1610 case 1:
1611 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1612 break;
1613 case 2:
1614 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1615 break;
1616 case 3:
1617 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1618 break;
1619 case 4:
1620 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1621 break;
1622 case 5:
1623 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1624 break;
1625 }
1626 break;
1627 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1628 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1629 break;
1630 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1631 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1632 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1633 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1634 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1635 else
1636 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1637 break;
1638 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1639 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1640 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1641 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1642 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1643 else
1644 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1645 break;
1646 }
1647 break;
1648 }
1649 break;
1650 default:
1651 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1652 return;
1653 }
1654
1655 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1656
1657 /* update scratch regs with new routing */
1658 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1659 }
1660
1661 static void
1662 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1663 struct drm_display_mode *mode)
1664 {
1665 struct drm_device *dev = encoder->dev;
1666 struct radeon_device *rdev = dev->dev_private;
1667 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1668 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1669
1670 /* Funky macbooks */
1671 if ((dev->pdev->device == 0x71C5) &&
1672 (dev->pdev->subsystem_vendor == 0x106b) &&
1673 (dev->pdev->subsystem_device == 0x0080)) {
1674 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1675 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1676
1677 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1678 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1679
1680 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1681 }
1682 }
1683
1684 /* set scaler clears this on some chips */
1685 if (ASIC_IS_AVIVO(rdev) &&
1686 (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {
1687 if (ASIC_IS_DCE4(rdev)) {
1688 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1689 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
1690 EVERGREEN_INTERLEAVE_EN);
1691 else
1692 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1693 } else {
1694 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1695 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1696 AVIVO_D1MODE_INTERLEAVE_EN);
1697 else
1698 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1699 }
1700 }
1701 }
1702
1703 static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1704 {
1705 struct drm_device *dev = encoder->dev;
1706 struct radeon_device *rdev = dev->dev_private;
1707 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1708 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1709 struct drm_encoder *test_encoder;
1710 struct radeon_encoder_atom_dig *dig;
1711 uint32_t dig_enc_in_use = 0;
1712
1713 /* DCE4/5 */
1714 if (ASIC_IS_DCE4(rdev)) {
1715 dig = radeon_encoder->enc_priv;
1716 if (ASIC_IS_DCE41(rdev))
1717 return radeon_crtc->crtc_id;
1718 else {
1719 switch (radeon_encoder->encoder_id) {
1720 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1721 if (dig->linkb)
1722 return 1;
1723 else
1724 return 0;
1725 break;
1726 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1727 if (dig->linkb)
1728 return 3;
1729 else
1730 return 2;
1731 break;
1732 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1733 if (dig->linkb)
1734 return 5;
1735 else
1736 return 4;
1737 break;
1738 }
1739 }
1740 }
1741
1742 /* on DCE32 and encoder can driver any block so just crtc id */
1743 if (ASIC_IS_DCE32(rdev)) {
1744 return radeon_crtc->crtc_id;
1745 }
1746
1747 /* on DCE3 - LVTMA can only be driven by DIGB */
1748 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1749 struct radeon_encoder *radeon_test_encoder;
1750
1751 if (encoder == test_encoder)
1752 continue;
1753
1754 if (!radeon_encoder_is_digital(test_encoder))
1755 continue;
1756
1757 radeon_test_encoder = to_radeon_encoder(test_encoder);
1758 dig = radeon_test_encoder->enc_priv;
1759
1760 if (dig->dig_encoder >= 0)
1761 dig_enc_in_use |= (1 << dig->dig_encoder);
1762 }
1763
1764 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
1765 if (dig_enc_in_use & 0x2)
1766 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
1767 return 1;
1768 }
1769 if (!(dig_enc_in_use & 1))
1770 return 0;
1771 return 1;
1772 }
1773
1774 static void
1775 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1776 struct drm_display_mode *mode,
1777 struct drm_display_mode *adjusted_mode)
1778 {
1779 struct drm_device *dev = encoder->dev;
1780 struct radeon_device *rdev = dev->dev_private;
1781 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1782 struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder);
1783
1784 radeon_encoder->pixel_clock = adjusted_mode->clock;
1785
1786 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
1787 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
1788 atombios_yuv_setup(encoder, true);
1789 else
1790 atombios_yuv_setup(encoder, false);
1791 }
1792
1793 switch (radeon_encoder->encoder_id) {
1794 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1795 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1796 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1797 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1798 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
1799 break;
1800 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1801 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1802 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1803 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1804 if (ASIC_IS_DCE4(rdev)) {
1805 /* disable the transmitter */
1806 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1807 /* setup and enable the encoder */
1808 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1809
1810 /* init and enable the transmitter */
1811 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1812 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1813 } else {
1814 /* disable the encoder and transmitter */
1815 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1816 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1817
1818 /* setup and enable the encoder and transmitter */
1819 atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
1820 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1821 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1822 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1823 }
1824 break;
1825 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1826 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1827 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1828 atombios_dvo_setup(encoder, ATOM_ENABLE);
1829 break;
1830 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1831 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1832 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1833 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1834 atombios_dac_setup(encoder, ATOM_ENABLE);
1835 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
1836 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1837 atombios_tv_setup(encoder, ATOM_ENABLE);
1838 else
1839 atombios_tv_setup(encoder, ATOM_DISABLE);
1840 }
1841 break;
1842 }
1843
1844 if (ext_encoder) {
1845 if (ASIC_IS_DCE41(rdev)) {
1846 atombios_external_encoder_setup(encoder, ext_encoder,
1847 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
1848 atombios_external_encoder_setup(encoder, ext_encoder,
1849 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
1850 } else
1851 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1852 }
1853
1854 atombios_apply_encoder_quirks(encoder, adjusted_mode);
1855
1856 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
1857 r600_hdmi_enable(encoder);
1858 r600_hdmi_setmode(encoder, adjusted_mode);
1859 }
1860 }
1861
1862 static bool
1863 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1864 {
1865 struct drm_device *dev = encoder->dev;
1866 struct radeon_device *rdev = dev->dev_private;
1867 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1868 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1869
1870 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
1871 ATOM_DEVICE_CV_SUPPORT |
1872 ATOM_DEVICE_CRT_SUPPORT)) {
1873 DAC_LOAD_DETECTION_PS_ALLOCATION args;
1874 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
1875 uint8_t frev, crev;
1876
1877 memset(&args, 0, sizeof(args));
1878
1879 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1880 return false;
1881
1882 args.sDacload.ucMisc = 0;
1883
1884 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
1885 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
1886 args.sDacload.ucDacType = ATOM_DAC_A;
1887 else
1888 args.sDacload.ucDacType = ATOM_DAC_B;
1889
1890 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
1891 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
1892 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
1893 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
1894 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1895 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
1896 if (crev >= 3)
1897 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1898 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1899 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
1900 if (crev >= 3)
1901 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1902 }
1903
1904 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1905
1906 return true;
1907 } else
1908 return false;
1909 }
1910
1911 static enum drm_connector_status
1912 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1913 {
1914 struct drm_device *dev = encoder->dev;
1915 struct radeon_device *rdev = dev->dev_private;
1916 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1917 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1918 uint32_t bios_0_scratch;
1919
1920 if (!atombios_dac_load_detect(encoder, connector)) {
1921 DRM_DEBUG_KMS("detect returned false \n");
1922 return connector_status_unknown;
1923 }
1924
1925 if (rdev->family >= CHIP_R600)
1926 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1927 else
1928 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1929
1930 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
1931 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1932 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
1933 return connector_status_connected;
1934 }
1935 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1936 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
1937 return connector_status_connected;
1938 }
1939 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1940 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
1941 return connector_status_connected;
1942 }
1943 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1944 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
1945 return connector_status_connected; /* CTV */
1946 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
1947 return connector_status_connected; /* STV */
1948 }
1949 return connector_status_disconnected;
1950 }
1951
1952 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
1953 {
1954 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1955 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1956
1957 if ((radeon_encoder->active_device &
1958 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
1959 radeon_encoder_is_dp_bridge(encoder)) {
1960 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1961 if (dig)
1962 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
1963 }
1964
1965 radeon_atom_output_lock(encoder, true);
1966 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1967
1968 if (connector) {
1969 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1970
1971 /* select the clock/data port if it uses a router */
1972 if (radeon_connector->router.cd_valid)
1973 radeon_router_select_cd_port(radeon_connector);
1974
1975 /* turn eDP panel on for mode set */
1976 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1977 atombios_set_edp_panel_power(connector,
1978 ATOM_TRANSMITTER_ACTION_POWER_ON);
1979 }
1980
1981 /* this is needed for the pll/ss setup to work correctly in some cases */
1982 atombios_set_encoder_crtc_source(encoder);
1983 }
1984
1985 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
1986 {
1987 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
1988 radeon_atom_output_lock(encoder, false);
1989 }
1990
1991 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
1992 {
1993 struct drm_device *dev = encoder->dev;
1994 struct radeon_device *rdev = dev->dev_private;
1995 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1996 struct radeon_encoder_atom_dig *dig;
1997
1998 /* check for pre-DCE3 cards with shared encoders;
1999 * can't really use the links individually, so don't disable
2000 * the encoder if it's in use by another connector
2001 */
2002 if (!ASIC_IS_DCE3(rdev)) {
2003 struct drm_encoder *other_encoder;
2004 struct radeon_encoder *other_radeon_encoder;
2005
2006 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
2007 other_radeon_encoder = to_radeon_encoder(other_encoder);
2008 if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
2009 drm_helper_encoder_in_use(other_encoder))
2010 goto disable_done;
2011 }
2012 }
2013
2014 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2015
2016 switch (radeon_encoder->encoder_id) {
2017 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2018 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2019 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2020 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2021 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
2022 break;
2023 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2024 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2025 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2026 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2027 if (ASIC_IS_DCE4(rdev))
2028 /* disable the transmitter */
2029 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
2030 else {
2031 /* disable the encoder and transmitter */
2032 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
2033 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
2034 }
2035 break;
2036 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2037 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2038 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2039 atombios_dvo_setup(encoder, ATOM_DISABLE);
2040 break;
2041 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2042 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2043 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2044 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2045 atombios_dac_setup(encoder, ATOM_DISABLE);
2046 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2047 atombios_tv_setup(encoder, ATOM_DISABLE);
2048 break;
2049 }
2050
2051 disable_done:
2052 if (radeon_encoder_is_digital(encoder)) {
2053 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
2054 r600_hdmi_disable(encoder);
2055 dig = radeon_encoder->enc_priv;
2056 dig->dig_encoder = -1;
2057 }
2058 radeon_encoder->active_device = 0;
2059 }
2060
2061 /* these are handled by the primary encoders */
2062 static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
2063 {
2064
2065 }
2066
2067 static void radeon_atom_ext_commit(struct drm_encoder *encoder)
2068 {
2069
2070 }
2071
2072 static void
2073 radeon_atom_ext_mode_set(struct drm_encoder *encoder,
2074 struct drm_display_mode *mode,
2075 struct drm_display_mode *adjusted_mode)
2076 {
2077
2078 }
2079
2080 static void radeon_atom_ext_disable(struct drm_encoder *encoder)
2081 {
2082
2083 }
2084
2085 static void
2086 radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
2087 {
2088
2089 }
2090
2091 static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder,
2092 struct drm_display_mode *mode,
2093 struct drm_display_mode *adjusted_mode)
2094 {
2095 return true;
2096 }
2097
2098 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
2099 .dpms = radeon_atom_ext_dpms,
2100 .mode_fixup = radeon_atom_ext_mode_fixup,
2101 .prepare = radeon_atom_ext_prepare,
2102 .mode_set = radeon_atom_ext_mode_set,
2103 .commit = radeon_atom_ext_commit,
2104 .disable = radeon_atom_ext_disable,
2105 /* no detect for TMDS/LVDS yet */
2106 };
2107
2108 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
2109 .dpms = radeon_atom_encoder_dpms,
2110 .mode_fixup = radeon_atom_mode_fixup,
2111 .prepare = radeon_atom_encoder_prepare,
2112 .mode_set = radeon_atom_encoder_mode_set,
2113 .commit = radeon_atom_encoder_commit,
2114 .disable = radeon_atom_encoder_disable,
2115 /* no detect for TMDS/LVDS yet */
2116 };
2117
2118 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
2119 .dpms = radeon_atom_encoder_dpms,
2120 .mode_fixup = radeon_atom_mode_fixup,
2121 .prepare = radeon_atom_encoder_prepare,
2122 .mode_set = radeon_atom_encoder_mode_set,
2123 .commit = radeon_atom_encoder_commit,
2124 .detect = radeon_atom_dac_detect,
2125 };
2126
2127 void radeon_enc_destroy(struct drm_encoder *encoder)
2128 {
2129 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2130 kfree(radeon_encoder->enc_priv);
2131 drm_encoder_cleanup(encoder);
2132 kfree(radeon_encoder);
2133 }
2134
2135 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
2136 .destroy = radeon_enc_destroy,
2137 };
2138
2139 struct radeon_encoder_atom_dac *
2140 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
2141 {
2142 struct drm_device *dev = radeon_encoder->base.dev;
2143 struct radeon_device *rdev = dev->dev_private;
2144 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
2145
2146 if (!dac)
2147 return NULL;
2148
2149 dac->tv_std = radeon_atombios_get_tv_info(rdev);
2150 return dac;
2151 }
2152
2153 struct radeon_encoder_atom_dig *
2154 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
2155 {
2156 int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
2157 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
2158
2159 if (!dig)
2160 return NULL;
2161
2162 /* coherent mode by default */
2163 dig->coherent_mode = true;
2164 dig->dig_encoder = -1;
2165
2166 if (encoder_enum == 2)
2167 dig->linkb = true;
2168 else
2169 dig->linkb = false;
2170
2171 return dig;
2172 }
2173
2174 void
2175 radeon_add_atom_encoder(struct drm_device *dev,
2176 uint32_t encoder_enum,
2177 uint32_t supported_device,
2178 u16 caps)
2179 {
2180 struct radeon_device *rdev = dev->dev_private;
2181 struct drm_encoder *encoder;
2182 struct radeon_encoder *radeon_encoder;
2183
2184 /* see if we already added it */
2185 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2186 radeon_encoder = to_radeon_encoder(encoder);
2187 if (radeon_encoder->encoder_enum == encoder_enum) {
2188 radeon_encoder->devices |= supported_device;
2189 return;
2190 }
2191
2192 }
2193
2194 /* add a new one */
2195 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
2196 if (!radeon_encoder)
2197 return;
2198
2199 encoder = &radeon_encoder->base;
2200 switch (rdev->num_crtc) {
2201 case 1:
2202 encoder->possible_crtcs = 0x1;
2203 break;
2204 case 2:
2205 default:
2206 encoder->possible_crtcs = 0x3;
2207 break;
2208 case 6:
2209 encoder->possible_crtcs = 0x3f;
2210 break;
2211 }
2212
2213 radeon_encoder->enc_priv = NULL;
2214
2215 radeon_encoder->encoder_enum = encoder_enum;
2216 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
2217 radeon_encoder->devices = supported_device;
2218 radeon_encoder->rmx_type = RMX_OFF;
2219 radeon_encoder->underscan_type = UNDERSCAN_OFF;
2220 radeon_encoder->is_ext_encoder = false;
2221 radeon_encoder->caps = caps;
2222
2223 switch (radeon_encoder->encoder_id) {
2224 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2225 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2226 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2227 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2228 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2229 radeon_encoder->rmx_type = RMX_FULL;
2230 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2231 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2232 } else {
2233 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2234 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2235 }
2236 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2237 break;
2238 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2239 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2240 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2241 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2242 break;
2243 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2244 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2245 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2246 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
2247 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2248 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2249 break;
2250 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2251 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2252 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2253 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2254 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2255 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2256 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2257 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2258 radeon_encoder->rmx_type = RMX_FULL;
2259 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2260 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2261 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2262 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2263 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2264 } else {
2265 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2266 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2267 }
2268 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2269 break;
2270 case ENCODER_OBJECT_ID_SI170B:
2271 case ENCODER_OBJECT_ID_CH7303:
2272 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2273 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2274 case ENCODER_OBJECT_ID_TITFP513:
2275 case ENCODER_OBJECT_ID_VT1623:
2276 case ENCODER_OBJECT_ID_HDMI_SI1930:
2277 case ENCODER_OBJECT_ID_TRAVIS:
2278 case ENCODER_OBJECT_ID_NUTMEG:
2279 /* these are handled by the primary encoders */
2280 radeon_encoder->is_ext_encoder = true;
2281 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2282 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2283 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
2284 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2285 else
2286 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2287 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);
2288 break;
2289 }
2290 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree