?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
drm/radeon/kms: rewrite DP handling
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / gpu / drm / radeon / r100.c
blobf2204cb1ccdfa96e0daa22ed9963a59555664f19
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #include <linux/seq_file.h>
29 #include <linux/slab.h>
30 #include "drmP.h"
31 #include "drm.h"
32 #include "radeon_drm.h"
33 #include "radeon_reg.h"
34 #include "radeon.h"
35 #include "radeon_asic.h"
36 #include "r100d.h"
37 #include "rs100d.h"
38 #include "rv200d.h"
39 #include "rv250d.h"
40 #include "atom.h"
41
42 #include <linux/firmware.h>
43 #include <linux/platform_device.h>
44
45 #include "r100_reg_safe.h"
46 #include "rn50_reg_safe.h"
47
48 /* Firmware Names */
49 #define FIRMWARE_R100 "radeon/R100_cp.bin"
50 #define FIRMWARE_R200 "radeon/R200_cp.bin"
51 #define FIRMWARE_R300 "radeon/R300_cp.bin"
52 #define FIRMWARE_R420 "radeon/R420_cp.bin"
53 #define FIRMWARE_RS690 "radeon/RS690_cp.bin"
54 #define FIRMWARE_RS600 "radeon/RS600_cp.bin"
55 #define FIRMWARE_R520 "radeon/R520_cp.bin"
56
57 MODULE_FIRMWARE(FIRMWARE_R100);
58 MODULE_FIRMWARE(FIRMWARE_R200);
59 MODULE_FIRMWARE(FIRMWARE_R300);
60 MODULE_FIRMWARE(FIRMWARE_R420);
61 MODULE_FIRMWARE(FIRMWARE_RS690);
62 MODULE_FIRMWARE(FIRMWARE_RS600);
63 MODULE_FIRMWARE(FIRMWARE_R520);
64
65 #include "r100_track.h"
66
67 /* This files gather functions specifics to:
68 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
69 */
70
71 void r100_pre_page_flip(struct radeon_device *rdev, int crtc)
72 {
73 /* enable the pflip int */
74 radeon_irq_kms_pflip_irq_get(rdev, crtc);
75 }
76
77 void r100_post_page_flip(struct radeon_device *rdev, int crtc)
78 {
79 /* disable the pflip int */
80 radeon_irq_kms_pflip_irq_put(rdev, crtc);
81 }
82
83 u32 r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
84 {
85 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
86 u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK;
87
88 /* Lock the graphics update lock */
89 /* update the scanout addresses */
90 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
91
92 /* Wait for update_pending to go high. */
93 while (!(RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET));
94 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
95
96 /* Unlock the lock, so double-buffering can take place inside vblank */
97 tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK;
98 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
99
100 /* Return current update_pending status: */
101 return RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET;
102 }
103
104 void r100_pm_get_dynpm_state(struct radeon_device *rdev)
105 {
106 int i;
107 rdev->pm.dynpm_can_upclock = true;
108 rdev->pm.dynpm_can_downclock = true;
109
110 switch (rdev->pm.dynpm_planned_action) {
111 case DYNPM_ACTION_MINIMUM:
112 rdev->pm.requested_power_state_index = 0;
113 rdev->pm.dynpm_can_downclock = false;
114 break;
115 case DYNPM_ACTION_DOWNCLOCK:
116 if (rdev->pm.current_power_state_index == 0) {
117 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
118 rdev->pm.dynpm_can_downclock = false;
119 } else {
120 if (rdev->pm.active_crtc_count > 1) {
121 for (i = 0; i < rdev->pm.num_power_states; i++) {
122 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
123 continue;
124 else if (i >= rdev->pm.current_power_state_index) {
125 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
126 break;
127 } else {
128 rdev->pm.requested_power_state_index = i;
129 break;
130 }
131 }
132 } else
133 rdev->pm.requested_power_state_index =
134 rdev->pm.current_power_state_index - 1;
135 }
136 /* don't use the power state if crtcs are active and no display flag is set */
137 if ((rdev->pm.active_crtc_count > 0) &&
138 (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags &
139 RADEON_PM_MODE_NO_DISPLAY)) {
140 rdev->pm.requested_power_state_index++;
141 }
142 break;
143 case DYNPM_ACTION_UPCLOCK:
144 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
145 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
146 rdev->pm.dynpm_can_upclock = false;
147 } else {
148 if (rdev->pm.active_crtc_count > 1) {
149 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
150 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
151 continue;
152 else if (i <= rdev->pm.current_power_state_index) {
153 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
154 break;
155 } else {
156 rdev->pm.requested_power_state_index = i;
157 break;
158 }
159 }
160 } else
161 rdev->pm.requested_power_state_index =
162 rdev->pm.current_power_state_index + 1;
163 }
164 break;
165 case DYNPM_ACTION_DEFAULT:
166 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
167 rdev->pm.dynpm_can_upclock = false;
168 break;
169 case DYNPM_ACTION_NONE:
170 default:
171 DRM_ERROR("Requested mode for not defined action\n");
172 return;
173 }
174 /* only one clock mode per power state */
175 rdev->pm.requested_clock_mode_index = 0;
176
177 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
178 rdev->pm.power_state[rdev->pm.requested_power_state_index].
179 clock_info[rdev->pm.requested_clock_mode_index].sclk,
180 rdev->pm.power_state[rdev->pm.requested_power_state_index].
181 clock_info[rdev->pm.requested_clock_mode_index].mclk,
182 rdev->pm.power_state[rdev->pm.requested_power_state_index].
183 pcie_lanes);
184 }
185
186 void r100_pm_init_profile(struct radeon_device *rdev)
187 {
188 /* default */
189 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
190 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
191 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
192 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
193 /* low sh */
194 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
195 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
196 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
197 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
198 /* mid sh */
199 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
200 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
201 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
202 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
203 /* high sh */
204 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
205 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
206 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
207 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
208 /* low mh */
209 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
210 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
211 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
212 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
213 /* mid mh */
214 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
215 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
216 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
217 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
218 /* high mh */
219 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
220 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
221 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
222 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
223 }
224
225 void r100_pm_misc(struct radeon_device *rdev)
226 {
227 int requested_index = rdev->pm.requested_power_state_index;
228 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
229 struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
230 u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl;
231
232 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
233 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
234 tmp = RREG32(voltage->gpio.reg);
235 if (voltage->active_high)
236 tmp |= voltage->gpio.mask;
237 else
238 tmp &= ~(voltage->gpio.mask);
239 WREG32(voltage->gpio.reg, tmp);
240 if (voltage->delay)
241 udelay(voltage->delay);
242 } else {
243 tmp = RREG32(voltage->gpio.reg);
244 if (voltage->active_high)
245 tmp &= ~voltage->gpio.mask;
246 else
247 tmp |= voltage->gpio.mask;
248 WREG32(voltage->gpio.reg, tmp);
249 if (voltage->delay)
250 udelay(voltage->delay);
251 }
252 }
253
254 sclk_cntl = RREG32_PLL(SCLK_CNTL);
255 sclk_cntl2 = RREG32_PLL(SCLK_CNTL2);
256 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3);
257 sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL);
258 sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3);
259 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
260 sclk_more_cntl |= REDUCED_SPEED_SCLK_EN;
261 if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE)
262 sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE;
263 else
264 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE;
265 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2)
266 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0);
267 else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4)
268 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2);
269 } else
270 sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN;
271
272 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
273 sclk_more_cntl |= IO_CG_VOLTAGE_DROP;
274 if (voltage->delay) {
275 sclk_more_cntl |= VOLTAGE_DROP_SYNC;
276 switch (voltage->delay) {
277 case 33:
278 sclk_more_cntl |= VOLTAGE_DELAY_SEL(0);
279 break;
280 case 66:
281 sclk_more_cntl |= VOLTAGE_DELAY_SEL(1);
282 break;
283 case 99:
284 sclk_more_cntl |= VOLTAGE_DELAY_SEL(2);
285 break;
286 case 132:
287 sclk_more_cntl |= VOLTAGE_DELAY_SEL(3);
288 break;
289 }
290 } else
291 sclk_more_cntl &= ~VOLTAGE_DROP_SYNC;
292 } else
293 sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP;
294
295 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
296 sclk_cntl &= ~FORCE_HDP;
297 else
298 sclk_cntl |= FORCE_HDP;
299
300 WREG32_PLL(SCLK_CNTL, sclk_cntl);
301 WREG32_PLL(SCLK_CNTL2, sclk_cntl2);
302 WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl);
303
304 /* set pcie lanes */
305 if ((rdev->flags & RADEON_IS_PCIE) &&
306 !(rdev->flags & RADEON_IS_IGP) &&
307 rdev->asic->set_pcie_lanes &&
308 (ps->pcie_lanes !=
309 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
310 radeon_set_pcie_lanes(rdev,
311 ps->pcie_lanes);
312 DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes);
313 }
314 }
315
316 void r100_pm_prepare(struct radeon_device *rdev)
317 {
318 struct drm_device *ddev = rdev->ddev;
319 struct drm_crtc *crtc;
320 struct radeon_crtc *radeon_crtc;
321 u32 tmp;
322
323 /* disable any active CRTCs */
324 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
325 radeon_crtc = to_radeon_crtc(crtc);
326 if (radeon_crtc->enabled) {
327 if (radeon_crtc->crtc_id) {
328 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
329 tmp |= RADEON_CRTC2_DISP_REQ_EN_B;
330 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
331 } else {
332 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
333 tmp |= RADEON_CRTC_DISP_REQ_EN_B;
334 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
335 }
336 }
337 }
338 }
339
340 void r100_pm_finish(struct radeon_device *rdev)
341 {
342 struct drm_device *ddev = rdev->ddev;
343 struct drm_crtc *crtc;
344 struct radeon_crtc *radeon_crtc;
345 u32 tmp;
346
347 /* enable any active CRTCs */
348 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
349 radeon_crtc = to_radeon_crtc(crtc);
350 if (radeon_crtc->enabled) {
351 if (radeon_crtc->crtc_id) {
352 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
353 tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B;
354 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
355 } else {
356 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
357 tmp &= ~RADEON_CRTC_DISP_REQ_EN_B;
358 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
359 }
360 }
361 }
362 }
363
364 bool r100_gui_idle(struct radeon_device *rdev)
365 {
366 if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)
367 return false;
368 else
369 return true;
370 }
371
372 /* hpd for digital panel detect/disconnect */
373 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
374 {
375 bool connected = false;
376
377 switch (hpd) {
378 case RADEON_HPD_1:
379 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
380 connected = true;
381 break;
382 case RADEON_HPD_2:
383 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
384 connected = true;
385 break;
386 default:
387 break;
388 }
389 return connected;
390 }
391
392 void r100_hpd_set_polarity(struct radeon_device *rdev,
393 enum radeon_hpd_id hpd)
394 {
395 u32 tmp;
396 bool connected = r100_hpd_sense(rdev, hpd);
397
398 switch (hpd) {
399 case RADEON_HPD_1:
400 tmp = RREG32(RADEON_FP_GEN_CNTL);
401 if (connected)
402 tmp &= ~RADEON_FP_DETECT_INT_POL;
403 else
404 tmp |= RADEON_FP_DETECT_INT_POL;
405 WREG32(RADEON_FP_GEN_CNTL, tmp);
406 break;
407 case RADEON_HPD_2:
408 tmp = RREG32(RADEON_FP2_GEN_CNTL);
409 if (connected)
410 tmp &= ~RADEON_FP2_DETECT_INT_POL;
411 else
412 tmp |= RADEON_FP2_DETECT_INT_POL;
413 WREG32(RADEON_FP2_GEN_CNTL, tmp);
414 break;
415 default:
416 break;
417 }
418 }
419
420 void r100_hpd_init(struct radeon_device *rdev)
421 {
422 struct drm_device *dev = rdev->ddev;
423 struct drm_connector *connector;
424
425 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
426 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
427 switch (radeon_connector->hpd.hpd) {
428 case RADEON_HPD_1:
429 rdev->irq.hpd[0] = true;
430 break;
431 case RADEON_HPD_2:
432 rdev->irq.hpd[1] = true;
433 break;
434 default:
435 break;
436 }
437 }
438 if (rdev->irq.installed)
439 r100_irq_set(rdev);
440 }
441
442 void r100_hpd_fini(struct radeon_device *rdev)
443 {
444 struct drm_device *dev = rdev->ddev;
445 struct drm_connector *connector;
446
447 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
448 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
449 switch (radeon_connector->hpd.hpd) {
450 case RADEON_HPD_1:
451 rdev->irq.hpd[0] = false;
452 break;
453 case RADEON_HPD_2:
454 rdev->irq.hpd[1] = false;
455 break;
456 default:
457 break;
458 }
459 }
460 }
461
462 /*
463 * PCI GART
464 */
465 void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
466 {
467 /* TODO: can we do somethings here ? */
468 /* It seems hw only cache one entry so we should discard this
469 * entry otherwise if first GPU GART read hit this entry it
470 * could end up in wrong address. */
471 }
472
473 int r100_pci_gart_init(struct radeon_device *rdev)
474 {
475 int r;
476
477 if (rdev->gart.table.ram.ptr) {
478 WARN(1, "R100 PCI GART already initialized\n");
479 return 0;
480 }
481 /* Initialize common gart structure */
482 r = radeon_gart_init(rdev);
483 if (r)
484 return r;
485 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
486 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
487 rdev->asic->gart_set_page = &r100_pci_gart_set_page;
488 return radeon_gart_table_ram_alloc(rdev);
489 }
490
491 /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
492 void r100_enable_bm(struct radeon_device *rdev)
493 {
494 uint32_t tmp;
495 /* Enable bus mastering */
496 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
497 WREG32(RADEON_BUS_CNTL, tmp);
498 }
499
500 int r100_pci_gart_enable(struct radeon_device *rdev)
501 {
502 uint32_t tmp;
503
504 radeon_gart_restore(rdev);
505 /* discard memory request outside of configured range */
506 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
507 WREG32(RADEON_AIC_CNTL, tmp);
508 /* set address range for PCI address translate */
509 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
510 WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
511 /* set PCI GART page-table base address */
512 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
513 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
514 WREG32(RADEON_AIC_CNTL, tmp);
515 r100_pci_gart_tlb_flush(rdev);
516 rdev->gart.ready = true;
517 return 0;
518 }
519
520 void r100_pci_gart_disable(struct radeon_device *rdev)
521 {
522 uint32_t tmp;
523
524 /* discard memory request outside of configured range */
525 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
526 WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
527 WREG32(RADEON_AIC_LO_ADDR, 0);
528 WREG32(RADEON_AIC_HI_ADDR, 0);
529 }
530
531 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
532 {
533 if (i < 0 || i > rdev->gart.num_gpu_pages) {
534 return -EINVAL;
535 }
536 rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr));
537 return 0;
538 }
539
540 void r100_pci_gart_fini(struct radeon_device *rdev)
541 {
542 radeon_gart_fini(rdev);
543 r100_pci_gart_disable(rdev);
544 radeon_gart_table_ram_free(rdev);
545 }
546
547 int r100_irq_set(struct radeon_device *rdev)
548 {
549 uint32_t tmp = 0;
550
551 if (!rdev->irq.installed) {
552 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
553 WREG32(R_000040_GEN_INT_CNTL, 0);
554 return -EINVAL;
555 }
556 if (rdev->irq.sw_int) {
557 tmp |= RADEON_SW_INT_ENABLE;
558 }
559 if (rdev->irq.gui_idle) {
560 tmp |= RADEON_GUI_IDLE_MASK;
561 }
562 if (rdev->irq.crtc_vblank_int[0] ||
563 rdev->irq.pflip[0]) {
564 tmp |= RADEON_CRTC_VBLANK_MASK;
565 }
566 if (rdev->irq.crtc_vblank_int[1] ||
567 rdev->irq.pflip[1]) {
568 tmp |= RADEON_CRTC2_VBLANK_MASK;
569 }
570 if (rdev->irq.hpd[0]) {
571 tmp |= RADEON_FP_DETECT_MASK;
572 }
573 if (rdev->irq.hpd[1]) {
574 tmp |= RADEON_FP2_DETECT_MASK;
575 }
576 WREG32(RADEON_GEN_INT_CNTL, tmp);
577 return 0;
578 }
579
580 void r100_irq_disable(struct radeon_device *rdev)
581 {
582 u32 tmp;
583
584 WREG32(R_000040_GEN_INT_CNTL, 0);
585 /* Wait and acknowledge irq */
586 mdelay(1);
587 tmp = RREG32(R_000044_GEN_INT_STATUS);
588 WREG32(R_000044_GEN_INT_STATUS, tmp);
589 }
590
591 static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
592 {
593 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
594 uint32_t irq_mask = RADEON_SW_INT_TEST |
595 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
596 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
597
598 /* the interrupt works, but the status bit is permanently asserted */
599 if (rdev->irq.gui_idle && radeon_gui_idle(rdev)) {
600 if (!rdev->irq.gui_idle_acked)
601 irq_mask |= RADEON_GUI_IDLE_STAT;
602 }
603
604 if (irqs) {
605 WREG32(RADEON_GEN_INT_STATUS, irqs);
606 }
607 return irqs & irq_mask;
608 }
609
610 int r100_irq_process(struct radeon_device *rdev)
611 {
612 uint32_t status, msi_rearm;
613 bool queue_hotplug = false;
614
615 /* reset gui idle ack. the status bit is broken */
616 rdev->irq.gui_idle_acked = false;
617
618 status = r100_irq_ack(rdev);
619 if (!status) {
620 return IRQ_NONE;
621 }
622 if (rdev->shutdown) {
623 return IRQ_NONE;
624 }
625 while (status) {
626 /* SW interrupt */
627 if (status & RADEON_SW_INT_TEST) {
628 radeon_fence_process(rdev);
629 }
630 /* gui idle interrupt */
631 if (status & RADEON_GUI_IDLE_STAT) {
632 rdev->irq.gui_idle_acked = true;
633 rdev->pm.gui_idle = true;
634 wake_up(&rdev->irq.idle_queue);
635 }
636 /* Vertical blank interrupts */
637 if (status & RADEON_CRTC_VBLANK_STAT) {
638 if (rdev->irq.crtc_vblank_int[0]) {
639 drm_handle_vblank(rdev->ddev, 0);
640 rdev->pm.vblank_sync = true;
641 wake_up(&rdev->irq.vblank_queue);
642 }
643 if (rdev->irq.pflip[0])
644 radeon_crtc_handle_flip(rdev, 0);
645 }
646 if (status & RADEON_CRTC2_VBLANK_STAT) {
647 if (rdev->irq.crtc_vblank_int[1]) {
648 drm_handle_vblank(rdev->ddev, 1);
649 rdev->pm.vblank_sync = true;
650 wake_up(&rdev->irq.vblank_queue);
651 }
652 if (rdev->irq.pflip[1])
653 radeon_crtc_handle_flip(rdev, 1);
654 }
655 if (status & RADEON_FP_DETECT_STAT) {
656 queue_hotplug = true;
657 DRM_DEBUG("HPD1\n");
658 }
659 if (status & RADEON_FP2_DETECT_STAT) {
660 queue_hotplug = true;
661 DRM_DEBUG("HPD2\n");
662 }
663 status = r100_irq_ack(rdev);
664 }
665 /* reset gui idle ack. the status bit is broken */
666 rdev->irq.gui_idle_acked = false;
667 if (queue_hotplug)
668 schedule_work(&rdev->hotplug_work);
669 if (rdev->msi_enabled) {
670 switch (rdev->family) {
671 case CHIP_RS400:
672 case CHIP_RS480:
673 msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
674 WREG32(RADEON_AIC_CNTL, msi_rearm);
675 WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
676 break;
677 default:
678 msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN;
679 WREG32(RADEON_MSI_REARM_EN, msi_rearm);
680 WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN);
681 break;
682 }
683 }
684 return IRQ_HANDLED;
685 }
686
687 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
688 {
689 if (crtc == 0)
690 return RREG32(RADEON_CRTC_CRNT_FRAME);
691 else
692 return RREG32(RADEON_CRTC2_CRNT_FRAME);
693 }
694
695 /* Who ever call radeon_fence_emit should call ring_lock and ask
696 * for enough space (today caller are ib schedule and buffer move) */
697 void r100_fence_ring_emit(struct radeon_device *rdev,
698 struct radeon_fence *fence)
699 {
700 /* We have to make sure that caches are flushed before
701 * CPU might read something from VRAM. */
702 radeon_ring_write(rdev, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
703 radeon_ring_write(rdev, RADEON_RB3D_DC_FLUSH_ALL);
704 radeon_ring_write(rdev, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
705 radeon_ring_write(rdev, RADEON_RB3D_ZC_FLUSH_ALL);
706 /* Wait until IDLE & CLEAN */
707 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
708 radeon_ring_write(rdev, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
709 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
710 radeon_ring_write(rdev, rdev->config.r100.hdp_cntl |
711 RADEON_HDP_READ_BUFFER_INVALIDATE);
712 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
713 radeon_ring_write(rdev, rdev->config.r100.hdp_cntl);
714 /* Emit fence sequence & fire IRQ */
715 radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
716 radeon_ring_write(rdev, fence->seq);
717 radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
718 radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
719 }
720
721 int r100_copy_blit(struct radeon_device *rdev,
722 uint64_t src_offset,
723 uint64_t dst_offset,
724 unsigned num_pages,
725 struct radeon_fence *fence)
726 {
727 uint32_t cur_pages;
728 uint32_t stride_bytes = PAGE_SIZE;
729 uint32_t pitch;
730 uint32_t stride_pixels;
731 unsigned ndw;
732 int num_loops;
733 int r = 0;
734
735 /* radeon limited to 16k stride */
736 stride_bytes &= 0x3fff;
737 /* radeon pitch is /64 */
738 pitch = stride_bytes / 64;
739 stride_pixels = stride_bytes / 4;
740 num_loops = DIV_ROUND_UP(num_pages, 8191);
741
742 /* Ask for enough room for blit + flush + fence */
743 ndw = 64 + (10 * num_loops);
744 r = radeon_ring_lock(rdev, ndw);
745 if (r) {
746 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
747 return -EINVAL;
748 }
749 while (num_pages > 0) {
750 cur_pages = num_pages;
751 if (cur_pages > 8191) {
752 cur_pages = 8191;
753 }
754 num_pages -= cur_pages;
755
756 /* pages are in Y direction - height
757 page width in X direction - width */
758 radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8));
759 radeon_ring_write(rdev,
760 RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
761 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
762 RADEON_GMC_SRC_CLIPPING |
763 RADEON_GMC_DST_CLIPPING |
764 RADEON_GMC_BRUSH_NONE |
765 (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
766 RADEON_GMC_SRC_DATATYPE_COLOR |
767 RADEON_ROP3_S |
768 RADEON_DP_SRC_SOURCE_MEMORY |
769 RADEON_GMC_CLR_CMP_CNTL_DIS |
770 RADEON_GMC_WR_MSK_DIS);
771 radeon_ring_write(rdev, (pitch << 22) | (src_offset >> 10));
772 radeon_ring_write(rdev, (pitch << 22) | (dst_offset >> 10));
773 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
774 radeon_ring_write(rdev, 0);
775 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
776 radeon_ring_write(rdev, num_pages);
777 radeon_ring_write(rdev, num_pages);
778 radeon_ring_write(rdev, cur_pages | (stride_pixels << 16));
779 }
780 radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
781 radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL);
782 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
783 radeon_ring_write(rdev,
784 RADEON_WAIT_2D_IDLECLEAN |
785 RADEON_WAIT_HOST_IDLECLEAN |
786 RADEON_WAIT_DMA_GUI_IDLE);
787 if (fence) {
788 r = radeon_fence_emit(rdev, fence);
789 }
790 radeon_ring_unlock_commit(rdev);
791 return r;
792 }
793
794 static int r100_cp_wait_for_idle(struct radeon_device *rdev)
795 {
796 unsigned i;
797 u32 tmp;
798
799 for (i = 0; i < rdev->usec_timeout; i++) {
800 tmp = RREG32(R_000E40_RBBM_STATUS);
801 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
802 return 0;
803 }
804 udelay(1);
805 }
806 return -1;
807 }
808
809 void r100_ring_start(struct radeon_device *rdev)
810 {
811 int r;
812
813 r = radeon_ring_lock(rdev, 2);
814 if (r) {
815 return;
816 }
817 radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
818 radeon_ring_write(rdev,
819 RADEON_ISYNC_ANY2D_IDLE3D |
820 RADEON_ISYNC_ANY3D_IDLE2D |
821 RADEON_ISYNC_WAIT_IDLEGUI |
822 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
823 radeon_ring_unlock_commit(rdev);
824 }
825
826
827 /* Load the microcode for the CP */
828 static int r100_cp_init_microcode(struct radeon_device *rdev)
829 {
830 struct platform_device *pdev;
831 const char *fw_name = NULL;
832 int err;
833
834 DRM_DEBUG_KMS("\n");
835
836 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
837 err = IS_ERR(pdev);
838 if (err) {
839 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
840 return -EINVAL;
841 }
842 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
843 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
844 (rdev->family == CHIP_RS200)) {
845 DRM_INFO("Loading R100 Microcode\n");
846 fw_name = FIRMWARE_R100;
847 } else if ((rdev->family == CHIP_R200) ||
848 (rdev->family == CHIP_RV250) ||
849 (rdev->family == CHIP_RV280) ||
850 (rdev->family == CHIP_RS300)) {
851 DRM_INFO("Loading R200 Microcode\n");
852 fw_name = FIRMWARE_R200;
853 } else if ((rdev->family == CHIP_R300) ||
854 (rdev->family == CHIP_R350) ||
855 (rdev->family == CHIP_RV350) ||
856 (rdev->family == CHIP_RV380) ||
857 (rdev->family == CHIP_RS400) ||
858 (rdev->family == CHIP_RS480)) {
859 DRM_INFO("Loading R300 Microcode\n");
860 fw_name = FIRMWARE_R300;
861 } else if ((rdev->family == CHIP_R420) ||
862 (rdev->family == CHIP_R423) ||
863 (rdev->family == CHIP_RV410)) {
864 DRM_INFO("Loading R400 Microcode\n");
865 fw_name = FIRMWARE_R420;
866 } else if ((rdev->family == CHIP_RS690) ||
867 (rdev->family == CHIP_RS740)) {
868 DRM_INFO("Loading RS690/RS740 Microcode\n");
869 fw_name = FIRMWARE_RS690;
870 } else if (rdev->family == CHIP_RS600) {
871 DRM_INFO("Loading RS600 Microcode\n");
872 fw_name = FIRMWARE_RS600;
873 } else if ((rdev->family == CHIP_RV515) ||
874 (rdev->family == CHIP_R520) ||
875 (rdev->family == CHIP_RV530) ||
876 (rdev->family == CHIP_R580) ||
877 (rdev->family == CHIP_RV560) ||
878 (rdev->family == CHIP_RV570)) {
879 DRM_INFO("Loading R500 Microcode\n");
880 fw_name = FIRMWARE_R520;
881 }
882
883 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
884 platform_device_unregister(pdev);
885 if (err) {
886 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
887 fw_name);
888 } else if (rdev->me_fw->size % 8) {
889 printk(KERN_ERR
890 "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
891 rdev->me_fw->size, fw_name);
892 err = -EINVAL;
893 release_firmware(rdev->me_fw);
894 rdev->me_fw = NULL;
895 }
896 return err;
897 }
898
899 static void r100_cp_load_microcode(struct radeon_device *rdev)
900 {
901 const __be32 *fw_data;
902 int i, size;
903
904 if (r100_gui_wait_for_idle(rdev)) {
905 printk(KERN_WARNING "Failed to wait GUI idle while "
906 "programming pipes. Bad things might happen.\n");
907 }
908
909 if (rdev->me_fw) {
910 size = rdev->me_fw->size / 4;
911 fw_data = (const __be32 *)&rdev->me_fw->data[0];
912 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
913 for (i = 0; i < size; i += 2) {
914 WREG32(RADEON_CP_ME_RAM_DATAH,
915 be32_to_cpup(&fw_data[i]));
916 WREG32(RADEON_CP_ME_RAM_DATAL,
917 be32_to_cpup(&fw_data[i + 1]));
918 }
919 }
920 }
921
922 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
923 {
924 unsigned rb_bufsz;
925 unsigned rb_blksz;
926 unsigned max_fetch;
927 unsigned pre_write_timer;
928 unsigned pre_write_limit;
929 unsigned indirect2_start;
930 unsigned indirect1_start;
931 uint32_t tmp;
932 int r;
933
934 if (r100_debugfs_cp_init(rdev)) {
935 DRM_ERROR("Failed to register debugfs file for CP !\n");
936 }
937 if (!rdev->me_fw) {
938 r = r100_cp_init_microcode(rdev);
939 if (r) {
940 DRM_ERROR("Failed to load firmware!\n");
941 return r;
942 }
943 }
944
945 /* Align ring size */
946 rb_bufsz = drm_order(ring_size / 8);
947 ring_size = (1 << (rb_bufsz + 1)) * 4;
948 r100_cp_load_microcode(rdev);
949 r = radeon_ring_init(rdev, ring_size);
950 if (r) {
951 return r;
952 }
953 /* Each time the cp read 1024 bytes (16 dword/quadword) update
954 * the rptr copy in system ram */
955 rb_blksz = 9;
956 /* cp will read 128bytes at a time (4 dwords) */
957 max_fetch = 1;
958 rdev->cp.align_mask = 16 - 1;
959 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
960 pre_write_timer = 64;
961 /* Force CP_RB_WPTR write if written more than one time before the
962 * delay expire
963 */
964 pre_write_limit = 0;
965 /* Setup the cp cache like this (cache size is 96 dwords) :
966 * RING 0 to 15
967 * INDIRECT1 16 to 79
968 * INDIRECT2 80 to 95
969 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
970 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
971 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
972 * Idea being that most of the gpu cmd will be through indirect1 buffer
973 * so it gets the bigger cache.
974 */
975 indirect2_start = 80;
976 indirect1_start = 16;
977 /* cp setup */
978 WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
979 tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
980 REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
981 REG_SET(RADEON_MAX_FETCH, max_fetch));
982 #ifdef __BIG_ENDIAN
983 tmp |= RADEON_BUF_SWAP_32BIT;
984 #endif
985 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE);
986
987 /* Set ring address */
988 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr);
989 WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr);
990 /* Force read & write ptr to 0 */
991 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE);
992 WREG32(RADEON_CP_RB_RPTR_WR, 0);
993 WREG32(RADEON_CP_RB_WPTR, 0);
994
995 /* set the wb address whether it's enabled or not */
996 WREG32(R_00070C_CP_RB_RPTR_ADDR,
997 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2));
998 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET);
999
1000 if (rdev->wb.enabled)
1001 WREG32(R_000770_SCRATCH_UMSK, 0xff);
1002 else {
1003 tmp |= RADEON_RB_NO_UPDATE;
1004 WREG32(R_000770_SCRATCH_UMSK, 0);
1005 }
1006
1007 WREG32(RADEON_CP_RB_CNTL, tmp);
1008 udelay(10);
1009 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
1010 rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR);
1011 /* protect against crazy HW on resume */
1012 rdev->cp.wptr &= rdev->cp.ptr_mask;
1013 /* Set cp mode to bus mastering & enable cp*/
1014 WREG32(RADEON_CP_CSQ_MODE,
1015 REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
1016 REG_SET(RADEON_INDIRECT1_START, indirect1_start));
1017 WREG32(RADEON_CP_RB_WPTR_DELAY, 0);
1018 WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D);
1019 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
1020 radeon_ring_start(rdev);
1021 r = radeon_ring_test(rdev);
1022 if (r) {
1023 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
1024 return r;
1025 }
1026 rdev->cp.ready = true;
1027 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
1028 return 0;
1029 }
1030
1031 void r100_cp_fini(struct radeon_device *rdev)
1032 {
1033 if (r100_cp_wait_for_idle(rdev)) {
1034 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
1035 }
1036 /* Disable ring */
1037 r100_cp_disable(rdev);
1038 radeon_ring_fini(rdev);
1039 DRM_INFO("radeon: cp finalized\n");
1040 }
1041
1042 void r100_cp_disable(struct radeon_device *rdev)
1043 {
1044 /* Disable ring */
1045 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1046 rdev->cp.ready = false;
1047 WREG32(RADEON_CP_CSQ_MODE, 0);
1048 WREG32(RADEON_CP_CSQ_CNTL, 0);
1049 WREG32(R_000770_SCRATCH_UMSK, 0);
1050 if (r100_gui_wait_for_idle(rdev)) {
1051 printk(KERN_WARNING "Failed to wait GUI idle while "
1052 "programming pipes. Bad things might happen.\n");
1053 }
1054 }
1055
1056 void r100_cp_commit(struct radeon_device *rdev)
1057 {
1058 WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
1059 (void)RREG32(RADEON_CP_RB_WPTR);
1060 }
1061
1062
1063 /*
1064 * CS functions
1065 */
1066 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1067 struct radeon_cs_packet *pkt,
1068 const unsigned *auth, unsigned n,
1069 radeon_packet0_check_t check)
1070 {
1071 unsigned reg;
1072 unsigned i, j, m;
1073 unsigned idx;
1074 int r;
1075
1076 idx = pkt->idx + 1;
1077 reg = pkt->reg;
1078 /* Check that register fall into register range
1079 * determined by the number of entry (n) in the
1080 * safe register bitmap.
1081 */
1082 if (pkt->one_reg_wr) {
1083 if ((reg >> 7) > n) {
1084 return -EINVAL;
1085 }
1086 } else {
1087 if (((reg + (pkt->count << 2)) >> 7) > n) {
1088 return -EINVAL;
1089 }
1090 }
1091 for (i = 0; i <= pkt->count; i++, idx++) {
1092 j = (reg >> 7);
1093 m = 1 << ((reg >> 2) & 31);
1094 if (auth[j] & m) {
1095 r = check(p, pkt, idx, reg);
1096 if (r) {
1097 return r;
1098 }
1099 }
1100 if (pkt->one_reg_wr) {
1101 if (!(auth[j] & m)) {
1102 break;
1103 }
1104 } else {
1105 reg += 4;
1106 }
1107 }
1108 return 0;
1109 }
1110
1111 void r100_cs_dump_packet(struct radeon_cs_parser *p,
1112 struct radeon_cs_packet *pkt)
1113 {
1114 volatile uint32_t *ib;
1115 unsigned i;
1116 unsigned idx;
1117
1118 ib = p->ib->ptr;
1119 idx = pkt->idx;
1120 for (i = 0; i <= (pkt->count + 1); i++, idx++) {
1121 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
1122 }
1123 }
1124
1125 /**
1126 * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
1127 * @parser: parser structure holding parsing context.
1128 * @pkt: where to store packet informations
1129 *
1130 * Assume that chunk_ib_index is properly set. Will return -EINVAL
1131 * if packet is bigger than remaining ib size. or if packets is unknown.
1132 **/
1133 int r100_cs_packet_parse(struct radeon_cs_parser *p,
1134 struct radeon_cs_packet *pkt,
1135 unsigned idx)
1136 {
1137 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
1138 uint32_t header;
1139
1140 if (idx >= ib_chunk->length_dw) {
1141 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
1142 idx, ib_chunk->length_dw);
1143 return -EINVAL;
1144 }
1145 header = radeon_get_ib_value(p, idx);
1146 pkt->idx = idx;
1147 pkt->type = CP_PACKET_GET_TYPE(header);
1148 pkt->count = CP_PACKET_GET_COUNT(header);
1149 switch (pkt->type) {
1150 case PACKET_TYPE0:
1151 pkt->reg = CP_PACKET0_GET_REG(header);
1152 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
1153 break;
1154 case PACKET_TYPE3:
1155 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
1156 break;
1157 case PACKET_TYPE2:
1158 pkt->count = -1;
1159 break;
1160 default:
1161 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
1162 return -EINVAL;
1163 }
1164 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
1165 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
1166 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
1167 return -EINVAL;
1168 }
1169 return 0;
1170 }
1171
1172 /**
1173 * r100_cs_packet_next_vline() - parse userspace VLINE packet
1174 * @parser: parser structure holding parsing context.
1175 *
1176 * Userspace sends a special sequence for VLINE waits.
1177 * PACKET0 - VLINE_START_END + value
1178 * PACKET0 - WAIT_UNTIL +_value
1179 * RELOC (P3) - crtc_id in reloc.
1180 *
1181 * This function parses this and relocates the VLINE START END
1182 * and WAIT UNTIL packets to the correct crtc.
1183 * It also detects a switched off crtc and nulls out the
1184 * wait in that case.
1185 */
1186 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
1187 {
1188 struct drm_mode_object *obj;
1189 struct drm_crtc *crtc;
1190 struct radeon_crtc *radeon_crtc;
1191 struct radeon_cs_packet p3reloc, waitreloc;
1192 int crtc_id;
1193 int r;
1194 uint32_t header, h_idx, reg;
1195 volatile uint32_t *ib;
1196
1197 ib = p->ib->ptr;
1198
1199 /* parse the wait until */
1200 r = r100_cs_packet_parse(p, &waitreloc, p->idx);
1201 if (r)
1202 return r;
1203
1204 /* check its a wait until and only 1 count */
1205 if (waitreloc.reg != RADEON_WAIT_UNTIL ||
1206 waitreloc.count != 0) {
1207 DRM_ERROR("vline wait had illegal wait until segment\n");
1208 return -EINVAL;
1209 }
1210
1211 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
1212 DRM_ERROR("vline wait had illegal wait until\n");
1213 return -EINVAL;
1214 }
1215
1216 /* jump over the NOP */
1217 r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
1218 if (r)
1219 return r;
1220
1221 h_idx = p->idx - 2;
1222 p->idx += waitreloc.count + 2;
1223 p->idx += p3reloc.count + 2;
1224
1225 header = radeon_get_ib_value(p, h_idx);
1226 crtc_id = radeon_get_ib_value(p, h_idx + 5);
1227 reg = CP_PACKET0_GET_REG(header);
1228 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
1229 if (!obj) {
1230 DRM_ERROR("cannot find crtc %d\n", crtc_id);
1231 return -EINVAL;
1232 }
1233 crtc = obj_to_crtc(obj);
1234 radeon_crtc = to_radeon_crtc(crtc);
1235 crtc_id = radeon_crtc->crtc_id;
1236
1237 if (!crtc->enabled) {
1238 /* if the CRTC isn't enabled - we need to nop out the wait until */
1239 ib[h_idx + 2] = PACKET2(0);
1240 ib[h_idx + 3] = PACKET2(0);
1241 } else if (crtc_id == 1) {
1242 switch (reg) {
1243 case AVIVO_D1MODE_VLINE_START_END:
1244 header &= ~R300_CP_PACKET0_REG_MASK;
1245 header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1246 break;
1247 case RADEON_CRTC_GUI_TRIG_VLINE:
1248 header &= ~R300_CP_PACKET0_REG_MASK;
1249 header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1250 break;
1251 default:
1252 DRM_ERROR("unknown crtc reloc\n");
1253 return -EINVAL;
1254 }
1255 ib[h_idx] = header;
1256 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
1257 }
1258
1259 return 0;
1260 }
1261
1262 /**
1263 * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
1264 * @parser: parser structure holding parsing context.
1265 * @data: pointer to relocation data
1266 * @offset_start: starting offset
1267 * @offset_mask: offset mask (to align start offset on)
1268 * @reloc: reloc informations
1269 *
1270 * Check next packet is relocation packet3, do bo validation and compute
1271 * GPU offset using the provided start.
1272 **/
1273 int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
1274 struct radeon_cs_reloc **cs_reloc)
1275 {
1276 struct radeon_cs_chunk *relocs_chunk;
1277 struct radeon_cs_packet p3reloc;
1278 unsigned idx;
1279 int r;
1280
1281 if (p->chunk_relocs_idx == -1) {
1282 DRM_ERROR("No relocation chunk !\n");
1283 return -EINVAL;
1284 }
1285 *cs_reloc = NULL;
1286 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
1287 r = r100_cs_packet_parse(p, &p3reloc, p->idx);
1288 if (r) {
1289 return r;
1290 }
1291 p->idx += p3reloc.count + 2;
1292 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
1293 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
1294 p3reloc.idx);
1295 r100_cs_dump_packet(p, &p3reloc);
1296 return -EINVAL;
1297 }
1298 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
1299 if (idx >= relocs_chunk->length_dw) {
1300 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
1301 idx, relocs_chunk->length_dw);
1302 r100_cs_dump_packet(p, &p3reloc);
1303 return -EINVAL;
1304 }
1305 /* FIXME: we assume reloc size is 4 dwords */
1306 *cs_reloc = p->relocs_ptr[(idx / 4)];
1307 return 0;
1308 }
1309
1310 static int r100_get_vtx_size(uint32_t vtx_fmt)
1311 {
1312 int vtx_size;
1313 vtx_size = 2;
1314 /* ordered according to bits in spec */
1315 if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1316 vtx_size++;
1317 if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1318 vtx_size += 3;
1319 if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1320 vtx_size++;
1321 if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1322 vtx_size++;
1323 if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1324 vtx_size += 3;
1325 if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1326 vtx_size++;
1327 if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1328 vtx_size++;
1329 if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1330 vtx_size += 2;
1331 if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1332 vtx_size += 2;
1333 if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1334 vtx_size++;
1335 if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1336 vtx_size += 2;
1337 if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1338 vtx_size++;
1339 if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1340 vtx_size += 2;
1341 if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1342 vtx_size++;
1343 if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1344 vtx_size++;
1345 /* blend weight */
1346 if (vtx_fmt & (0x7 << 15))
1347 vtx_size += (vtx_fmt >> 15) & 0x7;
1348 if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1349 vtx_size += 3;
1350 if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1351 vtx_size += 2;
1352 if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1353 vtx_size++;
1354 if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1355 vtx_size++;
1356 if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1357 vtx_size++;
1358 if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1359 vtx_size++;
1360 return vtx_size;
1361 }
1362
1363 static int r100_packet0_check(struct radeon_cs_parser *p,
1364 struct radeon_cs_packet *pkt,
1365 unsigned idx, unsigned reg)
1366 {
1367 struct radeon_cs_reloc *reloc;
1368 struct r100_cs_track *track;
1369 volatile uint32_t *ib;
1370 uint32_t tmp;
1371 int r;
1372 int i, face;
1373 u32 tile_flags = 0;
1374 u32 idx_value;
1375
1376 ib = p->ib->ptr;
1377 track = (struct r100_cs_track *)p->track;
1378
1379 idx_value = radeon_get_ib_value(p, idx);
1380
1381 switch (reg) {
1382 case RADEON_CRTC_GUI_TRIG_VLINE:
1383 r = r100_cs_packet_parse_vline(p);
1384 if (r) {
1385 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1386 idx, reg);
1387 r100_cs_dump_packet(p, pkt);
1388 return r;
1389 }
1390 break;
1391 /* FIXME: only allow PACKET3 blit? easier to check for out of
1392 * range access */
1393 case RADEON_DST_PITCH_OFFSET:
1394 case RADEON_SRC_PITCH_OFFSET:
1395 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1396 if (r)
1397 return r;
1398 break;
1399 case RADEON_RB3D_DEPTHOFFSET:
1400 r = r100_cs_packet_next_reloc(p, &reloc);
1401 if (r) {
1402 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1403 idx, reg);
1404 r100_cs_dump_packet(p, pkt);
1405 return r;
1406 }
1407 track->zb.robj = reloc->robj;
1408 track->zb.offset = idx_value;
1409 track->zb_dirty = true;
1410 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1411 break;
1412 case RADEON_RB3D_COLOROFFSET:
1413 r = r100_cs_packet_next_reloc(p, &reloc);
1414 if (r) {
1415 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1416 idx, reg);
1417 r100_cs_dump_packet(p, pkt);
1418 return r;
1419 }
1420 track->cb[0].robj = reloc->robj;
1421 track->cb[0].offset = idx_value;
1422 track->cb_dirty = true;
1423 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1424 break;
1425 case RADEON_PP_TXOFFSET_0:
1426 case RADEON_PP_TXOFFSET_1:
1427 case RADEON_PP_TXOFFSET_2:
1428 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1429 r = r100_cs_packet_next_reloc(p, &reloc);
1430 if (r) {
1431 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1432 idx, reg);
1433 r100_cs_dump_packet(p, pkt);
1434 return r;
1435 }
1436 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1437 track->textures[i].robj = reloc->robj;
1438 track->tex_dirty = true;
1439 break;
1440 case RADEON_PP_CUBIC_OFFSET_T0_0:
1441 case RADEON_PP_CUBIC_OFFSET_T0_1:
1442 case RADEON_PP_CUBIC_OFFSET_T0_2:
1443 case RADEON_PP_CUBIC_OFFSET_T0_3:
1444 case RADEON_PP_CUBIC_OFFSET_T0_4:
1445 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1446 r = r100_cs_packet_next_reloc(p, &reloc);
1447 if (r) {
1448 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1449 idx, reg);
1450 r100_cs_dump_packet(p, pkt);
1451 return r;
1452 }
1453 track->textures[0].cube_info[i].offset = idx_value;
1454 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1455 track->textures[0].cube_info[i].robj = reloc->robj;
1456 track->tex_dirty = true;
1457 break;
1458 case RADEON_PP_CUBIC_OFFSET_T1_0:
1459 case RADEON_PP_CUBIC_OFFSET_T1_1:
1460 case RADEON_PP_CUBIC_OFFSET_T1_2:
1461 case RADEON_PP_CUBIC_OFFSET_T1_3:
1462 case RADEON_PP_CUBIC_OFFSET_T1_4:
1463 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1464 r = r100_cs_packet_next_reloc(p, &reloc);
1465 if (r) {
1466 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1467 idx, reg);
1468 r100_cs_dump_packet(p, pkt);
1469 return r;
1470 }
1471 track->textures[1].cube_info[i].offset = idx_value;
1472 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1473 track->textures[1].cube_info[i].robj = reloc->robj;
1474 track->tex_dirty = true;
1475 break;
1476 case RADEON_PP_CUBIC_OFFSET_T2_0:
1477 case RADEON_PP_CUBIC_OFFSET_T2_1:
1478 case RADEON_PP_CUBIC_OFFSET_T2_2:
1479 case RADEON_PP_CUBIC_OFFSET_T2_3:
1480 case RADEON_PP_CUBIC_OFFSET_T2_4:
1481 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1482 r = r100_cs_packet_next_reloc(p, &reloc);
1483 if (r) {
1484 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1485 idx, reg);
1486 r100_cs_dump_packet(p, pkt);
1487 return r;
1488 }
1489 track->textures[2].cube_info[i].offset = idx_value;
1490 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1491 track->textures[2].cube_info[i].robj = reloc->robj;
1492 track->tex_dirty = true;
1493 break;
1494 case RADEON_RE_WIDTH_HEIGHT:
1495 track->maxy = ((idx_value >> 16) & 0x7FF);
1496 track->cb_dirty = true;
1497 track->zb_dirty = true;
1498 break;
1499 case RADEON_RB3D_COLORPITCH:
1500 r = r100_cs_packet_next_reloc(p, &reloc);
1501 if (r) {
1502 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1503 idx, reg);
1504 r100_cs_dump_packet(p, pkt);
1505 return r;
1506 }
1507
1508 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1509 tile_flags |= RADEON_COLOR_TILE_ENABLE;
1510 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1511 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1512
1513 tmp = idx_value & ~(0x7 << 16);
1514 tmp |= tile_flags;
1515 ib[idx] = tmp;
1516
1517 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1518 track->cb_dirty = true;
1519 break;
1520 case RADEON_RB3D_DEPTHPITCH:
1521 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1522 track->zb_dirty = true;
1523 break;
1524 case RADEON_RB3D_CNTL:
1525 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1526 case 7:
1527 case 8:
1528 case 9:
1529 case 11:
1530 case 12:
1531 track->cb[0].cpp = 1;
1532 break;
1533 case 3:
1534 case 4:
1535 case 15:
1536 track->cb[0].cpp = 2;
1537 break;
1538 case 6:
1539 track->cb[0].cpp = 4;
1540 break;
1541 default:
1542 DRM_ERROR("Invalid color buffer format (%d) !\n",
1543 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1544 return -EINVAL;
1545 }
1546 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1547 track->cb_dirty = true;
1548 track->zb_dirty = true;
1549 break;
1550 case RADEON_RB3D_ZSTENCILCNTL:
1551 switch (idx_value & 0xf) {
1552 case 0:
1553 track->zb.cpp = 2;
1554 break;
1555 case 2:
1556 case 3:
1557 case 4:
1558 case 5:
1559 case 9:
1560 case 11:
1561 track->zb.cpp = 4;
1562 break;
1563 default:
1564 break;
1565 }
1566 track->zb_dirty = true;
1567 break;
1568 case RADEON_RB3D_ZPASS_ADDR:
1569 r = r100_cs_packet_next_reloc(p, &reloc);
1570 if (r) {
1571 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1572 idx, reg);
1573 r100_cs_dump_packet(p, pkt);
1574 return r;
1575 }
1576 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1577 break;
1578 case RADEON_PP_CNTL:
1579 {
1580 uint32_t temp = idx_value >> 4;
1581 for (i = 0; i < track->num_texture; i++)
1582 track->textures[i].enabled = !!(temp & (1 << i));
1583 track->tex_dirty = true;
1584 }
1585 break;
1586 case RADEON_SE_VF_CNTL:
1587 track->vap_vf_cntl = idx_value;
1588 break;
1589 case RADEON_SE_VTX_FMT:
1590 track->vtx_size = r100_get_vtx_size(idx_value);
1591 break;
1592 case RADEON_PP_TEX_SIZE_0:
1593 case RADEON_PP_TEX_SIZE_1:
1594 case RADEON_PP_TEX_SIZE_2:
1595 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1596 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1597 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1598 track->tex_dirty = true;
1599 break;
1600 case RADEON_PP_TEX_PITCH_0:
1601 case RADEON_PP_TEX_PITCH_1:
1602 case RADEON_PP_TEX_PITCH_2:
1603 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1604 track->textures[i].pitch = idx_value + 32;
1605 track->tex_dirty = true;
1606 break;
1607 case RADEON_PP_TXFILTER_0:
1608 case RADEON_PP_TXFILTER_1:
1609 case RADEON_PP_TXFILTER_2:
1610 i = (reg - RADEON_PP_TXFILTER_0) / 24;
1611 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1612 >> RADEON_MAX_MIP_LEVEL_SHIFT);
1613 tmp = (idx_value >> 23) & 0x7;
1614 if (tmp == 2 || tmp == 6)
1615 track->textures[i].roundup_w = false;
1616 tmp = (idx_value >> 27) & 0x7;
1617 if (tmp == 2 || tmp == 6)
1618 track->textures[i].roundup_h = false;
1619 track->tex_dirty = true;
1620 break;
1621 case RADEON_PP_TXFORMAT_0:
1622 case RADEON_PP_TXFORMAT_1:
1623 case RADEON_PP_TXFORMAT_2:
1624 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1625 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1626 track->textures[i].use_pitch = 1;
1627 } else {
1628 track->textures[i].use_pitch = 0;
1629 track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1630 track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
1631 }
1632 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1633 track->textures[i].tex_coord_type = 2;
1634 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
1635 case RADEON_TXFORMAT_I8:
1636 case RADEON_TXFORMAT_RGB332:
1637 case RADEON_TXFORMAT_Y8:
1638 track->textures[i].cpp = 1;
1639 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1640 break;
1641 case RADEON_TXFORMAT_AI88:
1642 case RADEON_TXFORMAT_ARGB1555:
1643 case RADEON_TXFORMAT_RGB565:
1644 case RADEON_TXFORMAT_ARGB4444:
1645 case RADEON_TXFORMAT_VYUY422:
1646 case RADEON_TXFORMAT_YVYU422:
1647 case RADEON_TXFORMAT_SHADOW16:
1648 case RADEON_TXFORMAT_LDUDV655:
1649 case RADEON_TXFORMAT_DUDV88:
1650 track->textures[i].cpp = 2;
1651 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1652 break;
1653 case RADEON_TXFORMAT_ARGB8888:
1654 case RADEON_TXFORMAT_RGBA8888:
1655 case RADEON_TXFORMAT_SHADOW32:
1656 case RADEON_TXFORMAT_LDUDUV8888:
1657 track->textures[i].cpp = 4;
1658 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1659 break;
1660 case RADEON_TXFORMAT_DXT1:
1661 track->textures[i].cpp = 1;
1662 track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1663 break;
1664 case RADEON_TXFORMAT_DXT23:
1665 case RADEON_TXFORMAT_DXT45:
1666 track->textures[i].cpp = 1;
1667 track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1668 break;
1669 }
1670 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1671 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1672 track->tex_dirty = true;
1673 break;
1674 case RADEON_PP_CUBIC_FACES_0:
1675 case RADEON_PP_CUBIC_FACES_1:
1676 case RADEON_PP_CUBIC_FACES_2:
1677 tmp = idx_value;
1678 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1679 for (face = 0; face < 4; face++) {
1680 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1681 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
1682 }
1683 track->tex_dirty = true;
1684 break;
1685 default:
1686 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1687 reg, idx);
1688 return -EINVAL;
1689 }
1690 return 0;
1691 }
1692
1693 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1694 struct radeon_cs_packet *pkt,
1695 struct radeon_bo *robj)
1696 {
1697 unsigned idx;
1698 u32 value;
1699 idx = pkt->idx + 1;
1700 value = radeon_get_ib_value(p, idx + 2);
1701 if ((value + 1) > radeon_bo_size(robj)) {
1702 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1703 "(need %u have %lu) !\n",
1704 value + 1,
1705 radeon_bo_size(robj));
1706 return -EINVAL;
1707 }
1708 return 0;
1709 }
1710
1711 static int r100_packet3_check(struct radeon_cs_parser *p,
1712 struct radeon_cs_packet *pkt)
1713 {
1714 struct radeon_cs_reloc *reloc;
1715 struct r100_cs_track *track;
1716 unsigned idx;
1717 volatile uint32_t *ib;
1718 int r;
1719
1720 ib = p->ib->ptr;
1721 idx = pkt->idx + 1;
1722 track = (struct r100_cs_track *)p->track;
1723 switch (pkt->opcode) {
1724 case PACKET3_3D_LOAD_VBPNTR:
1725 r = r100_packet3_load_vbpntr(p, pkt, idx);
1726 if (r)
1727 return r;
1728 break;
1729 case PACKET3_INDX_BUFFER:
1730 r = r100_cs_packet_next_reloc(p, &reloc);
1731 if (r) {
1732 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1733 r100_cs_dump_packet(p, pkt);
1734 return r;
1735 }
1736 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
1737 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1738 if (r) {
1739 return r;
1740 }
1741 break;
1742 case 0x23:
1743 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1744 r = r100_cs_packet_next_reloc(p, &reloc);
1745 if (r) {
1746 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1747 r100_cs_dump_packet(p, pkt);
1748 return r;
1749 }
1750 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
1751 track->num_arrays = 1;
1752 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
1753
1754 track->arrays[0].robj = reloc->robj;
1755 track->arrays[0].esize = track->vtx_size;
1756
1757 track->max_indx = radeon_get_ib_value(p, idx+1);
1758
1759 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
1760 track->immd_dwords = pkt->count - 1;
1761 r = r100_cs_track_check(p->rdev, track);
1762 if (r)
1763 return r;
1764 break;
1765 case PACKET3_3D_DRAW_IMMD:
1766 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1767 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1768 return -EINVAL;
1769 }
1770 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
1771 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1772 track->immd_dwords = pkt->count - 1;
1773 r = r100_cs_track_check(p->rdev, track);
1774 if (r)
1775 return r;
1776 break;
1777 /* triggers drawing using in-packet vertex data */
1778 case PACKET3_3D_DRAW_IMMD_2:
1779 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1780 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1781 return -EINVAL;
1782 }
1783 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1784 track->immd_dwords = pkt->count;
1785 r = r100_cs_track_check(p->rdev, track);
1786 if (r)
1787 return r;
1788 break;
1789 /* triggers drawing using in-packet vertex data */
1790 case PACKET3_3D_DRAW_VBUF_2:
1791 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1792 r = r100_cs_track_check(p->rdev, track);
1793 if (r)
1794 return r;
1795 break;
1796 /* triggers drawing of vertex buffers setup elsewhere */
1797 case PACKET3_3D_DRAW_INDX_2:
1798 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1799 r = r100_cs_track_check(p->rdev, track);
1800 if (r)
1801 return r;
1802 break;
1803 /* triggers drawing using indices to vertex buffer */
1804 case PACKET3_3D_DRAW_VBUF:
1805 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1806 r = r100_cs_track_check(p->rdev, track);
1807 if (r)
1808 return r;
1809 break;
1810 /* triggers drawing of vertex buffers setup elsewhere */
1811 case PACKET3_3D_DRAW_INDX:
1812 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1813 r = r100_cs_track_check(p->rdev, track);
1814 if (r)
1815 return r;
1816 break;
1817 /* triggers drawing using indices to vertex buffer */
1818 case PACKET3_3D_CLEAR_HIZ:
1819 case PACKET3_3D_CLEAR_ZMASK:
1820 if (p->rdev->hyperz_filp != p->filp)
1821 return -EINVAL;
1822 break;
1823 case PACKET3_NOP:
1824 break;
1825 default:
1826 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1827 return -EINVAL;
1828 }
1829 return 0;
1830 }
1831
1832 int r100_cs_parse(struct radeon_cs_parser *p)
1833 {
1834 struct radeon_cs_packet pkt;
1835 struct r100_cs_track *track;
1836 int r;
1837
1838 track = kzalloc(sizeof(*track), GFP_KERNEL);
1839 r100_cs_track_clear(p->rdev, track);
1840 p->track = track;
1841 do {
1842 r = r100_cs_packet_parse(p, &pkt, p->idx);
1843 if (r) {
1844 return r;
1845 }
1846 p->idx += pkt.count + 2;
1847 switch (pkt.type) {
1848 case PACKET_TYPE0:
1849 if (p->rdev->family >= CHIP_R200)
1850 r = r100_cs_parse_packet0(p, &pkt,
1851 p->rdev->config.r100.reg_safe_bm,
1852 p->rdev->config.r100.reg_safe_bm_size,
1853 &r200_packet0_check);
1854 else
1855 r = r100_cs_parse_packet0(p, &pkt,
1856 p->rdev->config.r100.reg_safe_bm,
1857 p->rdev->config.r100.reg_safe_bm_size,
1858 &r100_packet0_check);
1859 break;
1860 case PACKET_TYPE2:
1861 break;
1862 case PACKET_TYPE3:
1863 r = r100_packet3_check(p, &pkt);
1864 break;
1865 default:
1866 DRM_ERROR("Unknown packet type %d !\n",
1867 pkt.type);
1868 return -EINVAL;
1869 }
1870 if (r) {
1871 return r;
1872 }
1873 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1874 return 0;
1875 }
1876
1877
1878 /*
1879 * Global GPU functions
1880 */
1881 void r100_errata(struct radeon_device *rdev)
1882 {
1883 rdev->pll_errata = 0;
1884
1885 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
1886 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
1887 }
1888
1889 if (rdev->family == CHIP_RV100 ||
1890 rdev->family == CHIP_RS100 ||
1891 rdev->family == CHIP_RS200) {
1892 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
1893 }
1894 }
1895
1896 /* Wait for vertical sync on primary CRTC */
1897 void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
1898 {
1899 uint32_t crtc_gen_cntl, tmp;
1900 int i;
1901
1902 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
1903 if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
1904 !(crtc_gen_cntl & RADEON_CRTC_EN)) {
1905 return;
1906 }
1907 /* Clear the CRTC_VBLANK_SAVE bit */
1908 WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
1909 for (i = 0; i < rdev->usec_timeout; i++) {
1910 tmp = RREG32(RADEON_CRTC_STATUS);
1911 if (tmp & RADEON_CRTC_VBLANK_SAVE) {
1912 return;
1913 }
1914 DRM_UDELAY(1);
1915 }
1916 }
1917
1918 /* Wait for vertical sync on secondary CRTC */
1919 void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
1920 {
1921 uint32_t crtc2_gen_cntl, tmp;
1922 int i;
1923
1924 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1925 if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
1926 !(crtc2_gen_cntl & RADEON_CRTC2_EN))
1927 return;
1928
1929 /* Clear the CRTC_VBLANK_SAVE bit */
1930 WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
1931 for (i = 0; i < rdev->usec_timeout; i++) {
1932 tmp = RREG32(RADEON_CRTC2_STATUS);
1933 if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
1934 return;
1935 }
1936 DRM_UDELAY(1);
1937 }
1938 }
1939
1940 int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
1941 {
1942 unsigned i;
1943 uint32_t tmp;
1944
1945 for (i = 0; i < rdev->usec_timeout; i++) {
1946 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
1947 if (tmp >= n) {
1948 return 0;
1949 }
1950 DRM_UDELAY(1);
1951 }
1952 return -1;
1953 }
1954
1955 int r100_gui_wait_for_idle(struct radeon_device *rdev)
1956 {
1957 unsigned i;
1958 uint32_t tmp;
1959
1960 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
1961 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
1962 " Bad things might happen.\n");
1963 }
1964 for (i = 0; i < rdev->usec_timeout; i++) {
1965 tmp = RREG32(RADEON_RBBM_STATUS);
1966 if (!(tmp & RADEON_RBBM_ACTIVE)) {
1967 return 0;
1968 }
1969 DRM_UDELAY(1);
1970 }
1971 return -1;
1972 }
1973
1974 int r100_mc_wait_for_idle(struct radeon_device *rdev)
1975 {
1976 unsigned i;
1977 uint32_t tmp;
1978
1979 for (i = 0; i < rdev->usec_timeout; i++) {
1980 /* read MC_STATUS */
1981 tmp = RREG32(RADEON_MC_STATUS);
1982 if (tmp & RADEON_MC_IDLE) {
1983 return 0;
1984 }
1985 DRM_UDELAY(1);
1986 }
1987 return -1;
1988 }
1989
1990 void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup, struct radeon_cp *cp)
1991 {
1992 lockup->last_cp_rptr = cp->rptr;
1993 lockup->last_jiffies = jiffies;
1994 }
1995
1996 /**
1997 * r100_gpu_cp_is_lockup() - check if CP is lockup by recording information
1998 * @rdev: radeon device structure
1999 * @lockup: r100_gpu_lockup structure holding CP lockup tracking informations
2000 * @cp: radeon_cp structure holding CP information
2001 *
2002 * We don't need to initialize the lockup tracking information as we will either
2003 * have CP rptr to a different value of jiffies wrap around which will force
2004 * initialization of the lockup tracking informations.
2005 *
2006 * A possible false positivie is if we get call after while and last_cp_rptr ==
2007 * the current CP rptr, even if it's unlikely it might happen. To avoid this
2008 * if the elapsed time since last call is bigger than 2 second than we return
2009 * false and update the tracking information. Due to this the caller must call
2010 * r100_gpu_cp_is_lockup several time in less than 2sec for lockup to be reported
2011 * the fencing code should be cautious about that.
2012 *
2013 * Caller should write to the ring to force CP to do something so we don't get
2014 * false positive when CP is just gived nothing to do.
2015 *
2016 **/
2017 bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, struct r100_gpu_lockup *lockup, struct radeon_cp *cp)
2018 {
2019 unsigned long cjiffies, elapsed;
2020
2021 cjiffies = jiffies;
2022 if (!time_after(cjiffies, lockup->last_jiffies)) {
2023 /* likely a wrap around */
2024 lockup->last_cp_rptr = cp->rptr;
2025 lockup->last_jiffies = jiffies;
2026 return false;
2027 }
2028 if (cp->rptr != lockup->last_cp_rptr) {
2029 /* CP is still working no lockup */
2030 lockup->last_cp_rptr = cp->rptr;
2031 lockup->last_jiffies = jiffies;
2032 return false;
2033 }
2034 elapsed = jiffies_to_msecs(cjiffies - lockup->last_jiffies);
2035 if (elapsed >= 10000) {
2036 dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed);
2037 return true;
2038 }
2039 /* give a chance to the GPU ... */
2040 return false;
2041 }
2042
2043 bool r100_gpu_is_lockup(struct radeon_device *rdev)
2044 {
2045 u32 rbbm_status;
2046 int r;
2047
2048 rbbm_status = RREG32(R_000E40_RBBM_STATUS);
2049 if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
2050 r100_gpu_lockup_update(&rdev->config.r100.lockup, &rdev->cp);
2051 return false;
2052 }
2053 /* force CP activities */
2054 r = radeon_ring_lock(rdev, 2);
2055 if (!r) {
2056 /* PACKET2 NOP */
2057 radeon_ring_write(rdev, 0x80000000);
2058 radeon_ring_write(rdev, 0x80000000);
2059 radeon_ring_unlock_commit(rdev);
2060 }
2061 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
2062 return r100_gpu_cp_is_lockup(rdev, &rdev->config.r100.lockup, &rdev->cp);
2063 }
2064
2065 void r100_bm_disable(struct radeon_device *rdev)
2066 {
2067 u32 tmp;
2068
2069 /* disable bus mastering */
2070 tmp = RREG32(R_000030_BUS_CNTL);
2071 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044);
2072 mdelay(1);
2073 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042);
2074 mdelay(1);
2075 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040);
2076 tmp = RREG32(RADEON_BUS_CNTL);
2077 mdelay(1);
2078 pci_read_config_word(rdev->pdev, 0x4, (u16*)&tmp);
2079 pci_write_config_word(rdev->pdev, 0x4, tmp & 0xFFFB);
2080 mdelay(1);
2081 }
2082
2083 int r100_asic_reset(struct radeon_device *rdev)
2084 {
2085 struct r100_mc_save save;
2086 u32 status, tmp;
2087 int ret = 0;
2088
2089 status = RREG32(R_000E40_RBBM_STATUS);
2090 if (!G_000E40_GUI_ACTIVE(status)) {
2091 return 0;
2092 }
2093 r100_mc_stop(rdev, &save);
2094 status = RREG32(R_000E40_RBBM_STATUS);
2095 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2096 /* stop CP */
2097 WREG32(RADEON_CP_CSQ_CNTL, 0);
2098 tmp = RREG32(RADEON_CP_RB_CNTL);
2099 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
2100 WREG32(RADEON_CP_RB_RPTR_WR, 0);
2101 WREG32(RADEON_CP_RB_WPTR, 0);
2102 WREG32(RADEON_CP_RB_CNTL, tmp);
2103 /* save PCI state */
2104 pci_save_state(rdev->pdev);
2105 /* disable bus mastering */
2106 r100_bm_disable(rdev);
2107 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) |
2108 S_0000F0_SOFT_RESET_RE(1) |
2109 S_0000F0_SOFT_RESET_PP(1) |
2110 S_0000F0_SOFT_RESET_RB(1));
2111 RREG32(R_0000F0_RBBM_SOFT_RESET);
2112 mdelay(500);
2113 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2114 mdelay(1);
2115 status = RREG32(R_000E40_RBBM_STATUS);
2116 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2117 /* reset CP */
2118 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
2119 RREG32(R_0000F0_RBBM_SOFT_RESET);
2120 mdelay(500);
2121 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2122 mdelay(1);
2123 status = RREG32(R_000E40_RBBM_STATUS);
2124 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2125 /* restore PCI & busmastering */
2126 pci_restore_state(rdev->pdev);
2127 r100_enable_bm(rdev);
2128 /* Check if GPU is idle */
2129 if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) ||
2130 G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) {
2131 dev_err(rdev->dev, "failed to reset GPU\n");
2132 rdev->gpu_lockup = true;
2133 ret = -1;
2134 } else
2135 dev_info(rdev->dev, "GPU reset succeed\n");
2136 r100_mc_resume(rdev, &save);
2137 return ret;
2138 }
2139
2140 void r100_set_common_regs(struct radeon_device *rdev)
2141 {
2142 struct drm_device *dev = rdev->ddev;
2143 bool force_dac2 = false;
2144 u32 tmp;
2145
2146 /* set these so they don't interfere with anything */
2147 WREG32(RADEON_OV0_SCALE_CNTL, 0);
2148 WREG32(RADEON_SUBPIC_CNTL, 0);
2149 WREG32(RADEON_VIPH_CONTROL, 0);
2150 WREG32(RADEON_I2C_CNTL_1, 0);
2151 WREG32(RADEON_DVI_I2C_CNTL_1, 0);
2152 WREG32(RADEON_CAP0_TRIG_CNTL, 0);
2153 WREG32(RADEON_CAP1_TRIG_CNTL, 0);
2154
2155 /* always set up dac2 on rn50 and some rv100 as lots
2156 * of servers seem to wire it up to a VGA port but
2157 * don't report it in the bios connector
2158 * table.
2159 */
2160 switch (dev->pdev->device) {
2161 /* RN50 */
2162 case 0x515e:
2163 case 0x5969:
2164 force_dac2 = true;
2165 break;
2166 /* RV100*/
2167 case 0x5159:
2168 case 0x515a:
2169 /* DELL triple head servers */
2170 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
2171 ((dev->pdev->subsystem_device == 0x016c) ||
2172 (dev->pdev->subsystem_device == 0x016d) ||
2173 (dev->pdev->subsystem_device == 0x016e) ||
2174 (dev->pdev->subsystem_device == 0x016f) ||
2175 (dev->pdev->subsystem_device == 0x0170) ||
2176 (dev->pdev->subsystem_device == 0x017d) ||
2177 (dev->pdev->subsystem_device == 0x017e) ||
2178 (dev->pdev->subsystem_device == 0x0183) ||
2179 (dev->pdev->subsystem_device == 0x018a) ||
2180 (dev->pdev->subsystem_device == 0x019a)))
2181 force_dac2 = true;
2182 break;
2183 }
2184
2185 if (force_dac2) {
2186 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
2187 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
2188 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
2189
2190 /* For CRT on DAC2, don't turn it on if BIOS didn't
2191 enable it, even it's detected.
2192 */
2193
2194 /* force it to crtc0 */
2195 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
2196 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
2197 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
2198
2199 /* set up the TV DAC */
2200 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
2201 RADEON_TV_DAC_STD_MASK |
2202 RADEON_TV_DAC_RDACPD |
2203 RADEON_TV_DAC_GDACPD |
2204 RADEON_TV_DAC_BDACPD |
2205 RADEON_TV_DAC_BGADJ_MASK |
2206 RADEON_TV_DAC_DACADJ_MASK);
2207 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
2208 RADEON_TV_DAC_NHOLD |
2209 RADEON_TV_DAC_STD_PS2 |
2210 (0x58 << 16));
2211
2212 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
2213 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
2214 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
2215 }
2216
2217 /* switch PM block to ACPI mode */
2218 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
2219 tmp &= ~RADEON_PM_MODE_SEL;
2220 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
2221
2222 }
2223
2224 /*
2225 * VRAM info
2226 */
2227 static void r100_vram_get_type(struct radeon_device *rdev)
2228 {
2229 uint32_t tmp;
2230
2231 rdev->mc.vram_is_ddr = false;
2232 if (rdev->flags & RADEON_IS_IGP)
2233 rdev->mc.vram_is_ddr = true;
2234 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
2235 rdev->mc.vram_is_ddr = true;
2236 if ((rdev->family == CHIP_RV100) ||
2237 (rdev->family == CHIP_RS100) ||
2238 (rdev->family == CHIP_RS200)) {
2239 tmp = RREG32(RADEON_MEM_CNTL);
2240 if (tmp & RV100_HALF_MODE) {
2241 rdev->mc.vram_width = 32;
2242 } else {
2243 rdev->mc.vram_width = 64;
2244 }
2245 if (rdev->flags & RADEON_SINGLE_CRTC) {
2246 rdev->mc.vram_width /= 4;
2247 rdev->mc.vram_is_ddr = true;
2248 }
2249 } else if (rdev->family <= CHIP_RV280) {
2250 tmp = RREG32(RADEON_MEM_CNTL);
2251 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
2252 rdev->mc.vram_width = 128;
2253 } else {
2254 rdev->mc.vram_width = 64;
2255 }
2256 } else {
2257 /* newer IGPs */
2258 rdev->mc.vram_width = 128;
2259 }
2260 }
2261
2262 static u32 r100_get_accessible_vram(struct radeon_device *rdev)
2263 {
2264 u32 aper_size;
2265 u8 byte;
2266
2267 aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2268
2269 /* Set HDP_APER_CNTL only on cards that are known not to be broken,
2270 * that is has the 2nd generation multifunction PCI interface
2271 */
2272 if (rdev->family == CHIP_RV280 ||
2273 rdev->family >= CHIP_RV350) {
2274 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
2275 ~RADEON_HDP_APER_CNTL);
2276 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
2277 return aper_size * 2;
2278 }
2279
2280 /* Older cards have all sorts of funny issues to deal with. First
2281 * check if it's a multifunction card by reading the PCI config
2282 * header type... Limit those to one aperture size
2283 */
2284 pci_read_config_byte(rdev->pdev, 0xe, &byte);
2285 if (byte & 0x80) {
2286 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
2287 DRM_INFO("Limiting VRAM to one aperture\n");
2288 return aper_size;
2289 }
2290
2291 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
2292 * have set it up. We don't write this as it's broken on some ASICs but
2293 * we expect the BIOS to have done the right thing (might be too optimistic...)
2294 */
2295 if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
2296 return aper_size * 2;
2297 return aper_size;
2298 }
2299
2300 void r100_vram_init_sizes(struct radeon_device *rdev)
2301 {
2302 u64 config_aper_size;
2303
2304 /* work out accessible VRAM */
2305 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2306 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2307 rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
2308 /* FIXME we don't use the second aperture yet when we could use it */
2309 if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
2310 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2311 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2312 if (rdev->flags & RADEON_IS_IGP) {
2313 uint32_t tom;
2314 /* read NB_TOM to get the amount of ram stolen for the GPU */
2315 tom = RREG32(RADEON_NB_TOM);
2316 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
2317 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2318 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2319 } else {
2320 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
2321 /* Some production boards of m6 will report 0
2322 * if it's 8 MB
2323 */
2324 if (rdev->mc.real_vram_size == 0) {
2325 rdev->mc.real_vram_size = 8192 * 1024;
2326 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2327 }
2328 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
2329 * Novell bug 204882 + along with lots of ubuntu ones
2330 */
2331 if (rdev->mc.aper_size > config_aper_size)
2332 config_aper_size = rdev->mc.aper_size;
2333
2334 if (config_aper_size > rdev->mc.real_vram_size)
2335 rdev->mc.mc_vram_size = config_aper_size;
2336 else
2337 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2338 }
2339 }
2340
2341 void r100_vga_set_state(struct radeon_device *rdev, bool state)
2342 {
2343 uint32_t temp;
2344
2345 temp = RREG32(RADEON_CONFIG_CNTL);
2346 if (state == false) {
2347 temp &= ~RADEON_CFG_VGA_RAM_EN;
2348 temp |= RADEON_CFG_VGA_IO_DIS;
2349 } else {
2350 temp &= ~RADEON_CFG_VGA_IO_DIS;
2351 }
2352 WREG32(RADEON_CONFIG_CNTL, temp);
2353 }
2354
2355 void r100_mc_init(struct radeon_device *rdev)
2356 {
2357 u64 base;
2358
2359 r100_vram_get_type(rdev);
2360 r100_vram_init_sizes(rdev);
2361 base = rdev->mc.aper_base;
2362 if (rdev->flags & RADEON_IS_IGP)
2363 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
2364 radeon_vram_location(rdev, &rdev->mc, base);
2365 rdev->mc.gtt_base_align = 0;
2366 if (!(rdev->flags & RADEON_IS_AGP))
2367 radeon_gtt_location(rdev, &rdev->mc);
2368 radeon_update_bandwidth_info(rdev);
2369 }
2370
2371
2372 /*
2373 * Indirect registers accessor
2374 */
2375 void r100_pll_errata_after_index(struct radeon_device *rdev)
2376 {
2377 if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) {
2378 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
2379 (void)RREG32(RADEON_CRTC_GEN_CNTL);
2380 }
2381 }
2382
2383 static void r100_pll_errata_after_data(struct radeon_device *rdev)
2384 {
2385 /* This workarounds is necessary on RV100, RS100 and RS200 chips
2386 * or the chip could hang on a subsequent access
2387 */
2388 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2389 udelay(5000);
2390 }
2391
2392 /* This function is required to workaround a hardware bug in some (all?)
2393 * revisions of the R300. This workaround should be called after every
2394 * CLOCK_CNTL_INDEX register access. If not, register reads afterward
2395 * may not be correct.
2396 */
2397 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2398 uint32_t save, tmp;
2399
2400 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
2401 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
2402 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
2403 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
2404 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
2405 }
2406 }
2407
2408 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2409 {
2410 uint32_t data;
2411
2412 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
2413 r100_pll_errata_after_index(rdev);
2414 data = RREG32(RADEON_CLOCK_CNTL_DATA);
2415 r100_pll_errata_after_data(rdev);
2416 return data;
2417 }
2418
2419 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2420 {
2421 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
2422 r100_pll_errata_after_index(rdev);
2423 WREG32(RADEON_CLOCK_CNTL_DATA, v);
2424 r100_pll_errata_after_data(rdev);
2425 }
2426
2427 void r100_set_safe_registers(struct radeon_device *rdev)
2428 {
2429 if (ASIC_IS_RN50(rdev)) {
2430 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2431 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2432 } else if (rdev->family < CHIP_R200) {
2433 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2434 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
2435 } else {
2436 r200_set_safe_registers(rdev);
2437 }
2438 }
2439
2440 /*
2441 * Debugfs info
2442 */
2443 #if defined(CONFIG_DEBUG_FS)
2444 static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
2445 {
2446 struct drm_info_node *node = (struct drm_info_node *) m->private;
2447 struct drm_device *dev = node->minor->dev;
2448 struct radeon_device *rdev = dev->dev_private;
2449 uint32_t reg, value;
2450 unsigned i;
2451
2452 seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2453 seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2454 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2455 for (i = 0; i < 64; i++) {
2456 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2457 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2458 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2459 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2460 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2461 }
2462 return 0;
2463 }
2464
2465 static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2466 {
2467 struct drm_info_node *node = (struct drm_info_node *) m->private;
2468 struct drm_device *dev = node->minor->dev;
2469 struct radeon_device *rdev = dev->dev_private;
2470 uint32_t rdp, wdp;
2471 unsigned count, i, j;
2472
2473 radeon_ring_free_size(rdev);
2474 rdp = RREG32(RADEON_CP_RB_RPTR);
2475 wdp = RREG32(RADEON_CP_RB_WPTR);
2476 count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
2477 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2478 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2479 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2480 seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
2481 seq_printf(m, "%u dwords in ring\n", count);
2482 for (j = 0; j <= count; j++) {
2483 i = (rdp + j) & rdev->cp.ptr_mask;
2484 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
2485 }
2486 return 0;
2487 }
2488
2489
2490 static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2491 {
2492 struct drm_info_node *node = (struct drm_info_node *) m->private;
2493 struct drm_device *dev = node->minor->dev;
2494 struct radeon_device *rdev = dev->dev_private;
2495 uint32_t csq_stat, csq2_stat, tmp;
2496 unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2497 unsigned i;
2498
2499 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2500 seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2501 csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2502 csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2503 r_rptr = (csq_stat >> 0) & 0x3ff;
2504 r_wptr = (csq_stat >> 10) & 0x3ff;
2505 ib1_rptr = (csq_stat >> 20) & 0x3ff;
2506 ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2507 ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2508 ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2509 seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2510 seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
2511 seq_printf(m, "Ring rptr %u\n", r_rptr);
2512 seq_printf(m, "Ring wptr %u\n", r_wptr);
2513 seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
2514 seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
2515 seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
2516 seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
2517 /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
2518 * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
2519 seq_printf(m, "Ring fifo:\n");
2520 for (i = 0; i < 256; i++) {
2521 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2522 tmp = RREG32(RADEON_CP_CSQ_DATA);
2523 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
2524 }
2525 seq_printf(m, "Indirect1 fifo:\n");
2526 for (i = 256; i <= 512; i++) {
2527 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2528 tmp = RREG32(RADEON_CP_CSQ_DATA);
2529 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
2530 }
2531 seq_printf(m, "Indirect2 fifo:\n");
2532 for (i = 640; i < ib1_wptr; i++) {
2533 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2534 tmp = RREG32(RADEON_CP_CSQ_DATA);
2535 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
2536 }
2537 return 0;
2538 }
2539
2540 static int r100_debugfs_mc_info(struct seq_file *m, void *data)
2541 {
2542 struct drm_info_node *node = (struct drm_info_node *) m->private;
2543 struct drm_device *dev = node->minor->dev;
2544 struct radeon_device *rdev = dev->dev_private;
2545 uint32_t tmp;
2546
2547 tmp = RREG32(RADEON_CONFIG_MEMSIZE);
2548 seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
2549 tmp = RREG32(RADEON_MC_FB_LOCATION);
2550 seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
2551 tmp = RREG32(RADEON_BUS_CNTL);
2552 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
2553 tmp = RREG32(RADEON_MC_AGP_LOCATION);
2554 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
2555 tmp = RREG32(RADEON_AGP_BASE);
2556 seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
2557 tmp = RREG32(RADEON_HOST_PATH_CNTL);
2558 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
2559 tmp = RREG32(0x01D0);
2560 seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
2561 tmp = RREG32(RADEON_AIC_LO_ADDR);
2562 seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
2563 tmp = RREG32(RADEON_AIC_HI_ADDR);
2564 seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
2565 tmp = RREG32(0x01E4);
2566 seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
2567 return 0;
2568 }
2569
2570 static struct drm_info_list r100_debugfs_rbbm_list[] = {
2571 {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
2572 };
2573
2574 static struct drm_info_list r100_debugfs_cp_list[] = {
2575 {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
2576 {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
2577 };
2578
2579 static struct drm_info_list r100_debugfs_mc_info_list[] = {
2580 {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
2581 };
2582 #endif
2583
2584 int r100_debugfs_rbbm_init(struct radeon_device *rdev)
2585 {
2586 #if defined(CONFIG_DEBUG_FS)
2587 return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
2588 #else
2589 return 0;
2590 #endif
2591 }
2592
2593 int r100_debugfs_cp_init(struct radeon_device *rdev)
2594 {
2595 #if defined(CONFIG_DEBUG_FS)
2596 return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
2597 #else
2598 return 0;
2599 #endif
2600 }
2601
2602 int r100_debugfs_mc_info_init(struct radeon_device *rdev)
2603 {
2604 #if defined(CONFIG_DEBUG_FS)
2605 return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
2606 #else
2607 return 0;
2608 #endif
2609 }
2610
2611 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
2612 uint32_t tiling_flags, uint32_t pitch,
2613 uint32_t offset, uint32_t obj_size)
2614 {
2615 int surf_index = reg * 16;
2616 int flags = 0;
2617
2618 if (rdev->family <= CHIP_RS200) {
2619 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2620 == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2621 flags |= RADEON_SURF_TILE_COLOR_BOTH;
2622 if (tiling_flags & RADEON_TILING_MACRO)
2623 flags |= RADEON_SURF_TILE_COLOR_MACRO;
2624 } else if (rdev->family <= CHIP_RV280) {
2625 if (tiling_flags & (RADEON_TILING_MACRO))
2626 flags |= R200_SURF_TILE_COLOR_MACRO;
2627 if (tiling_flags & RADEON_TILING_MICRO)
2628 flags |= R200_SURF_TILE_COLOR_MICRO;
2629 } else {
2630 if (tiling_flags & RADEON_TILING_MACRO)
2631 flags |= R300_SURF_TILE_MACRO;
2632 if (tiling_flags & RADEON_TILING_MICRO)
2633 flags |= R300_SURF_TILE_MICRO;
2634 }
2635
2636 if (tiling_flags & RADEON_TILING_SWAP_16BIT)
2637 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
2638 if (tiling_flags & RADEON_TILING_SWAP_32BIT)
2639 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
2640
2641 /* when we aren't tiling the pitch seems to needs to be furtherdivided down. - tested on power5 + rn50 server */
2642 if (tiling_flags & (RADEON_TILING_SWAP_16BIT | RADEON_TILING_SWAP_32BIT)) {
2643 if (!(tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO)))
2644 if (ASIC_IS_RN50(rdev))
2645 pitch /= 16;
2646 }
2647
2648 /* r100/r200 divide by 16 */
2649 if (rdev->family < CHIP_R300)
2650 flags |= pitch / 16;
2651 else
2652 flags |= pitch / 8;
2653
2654
2655 DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
2656 WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
2657 WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
2658 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
2659 return 0;
2660 }
2661
2662 void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
2663 {
2664 int surf_index = reg * 16;
2665 WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
2666 }
2667
2668 void r100_bandwidth_update(struct radeon_device *rdev)
2669 {
2670 fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
2671 fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
2672 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
2673 uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
2674 fixed20_12 memtcas_ff[8] = {
2675 dfixed_init(1),
2676 dfixed_init(2),
2677 dfixed_init(3),
2678 dfixed_init(0),
2679 dfixed_init_half(1),
2680 dfixed_init_half(2),
2681 dfixed_init(0),
2682 };
2683 fixed20_12 memtcas_rs480_ff[8] = {
2684 dfixed_init(0),
2685 dfixed_init(1),
2686 dfixed_init(2),
2687 dfixed_init(3),
2688 dfixed_init(0),
2689 dfixed_init_half(1),
2690 dfixed_init_half(2),
2691 dfixed_init_half(3),
2692 };
2693 fixed20_12 memtcas2_ff[8] = {
2694 dfixed_init(0),
2695 dfixed_init(1),
2696 dfixed_init(2),
2697 dfixed_init(3),
2698 dfixed_init(4),
2699 dfixed_init(5),
2700 dfixed_init(6),
2701 dfixed_init(7),
2702 };
2703 fixed20_12 memtrbs[8] = {
2704 dfixed_init(1),
2705 dfixed_init_half(1),
2706 dfixed_init(2),
2707 dfixed_init_half(2),
2708 dfixed_init(3),
2709 dfixed_init_half(3),
2710 dfixed_init(4),
2711 dfixed_init_half(4)
2712 };
2713 fixed20_12 memtrbs_r4xx[8] = {
2714 dfixed_init(4),
2715 dfixed_init(5),
2716 dfixed_init(6),
2717 dfixed_init(7),
2718 dfixed_init(8),
2719 dfixed_init(9),
2720 dfixed_init(10),
2721 dfixed_init(11)
2722 };
2723 fixed20_12 min_mem_eff;
2724 fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
2725 fixed20_12 cur_latency_mclk, cur_latency_sclk;
2726 fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
2727 disp_drain_rate2, read_return_rate;
2728 fixed20_12 time_disp1_drop_priority;
2729 int c;
2730 int cur_size = 16; /* in octawords */
2731 int critical_point = 0, critical_point2;
2732 /* uint32_t read_return_rate, time_disp1_drop_priority; */
2733 int stop_req, max_stop_req;
2734 struct drm_display_mode *mode1 = NULL;
2735 struct drm_display_mode *mode2 = NULL;
2736 uint32_t pixel_bytes1 = 0;
2737 uint32_t pixel_bytes2 = 0;
2738
2739 radeon_update_display_priority(rdev);
2740
2741 if (rdev->mode_info.crtcs[0]->base.enabled) {
2742 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
2743 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
2744 }
2745 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
2746 if (rdev->mode_info.crtcs[1]->base.enabled) {
2747 mode2 = &rdev->mode_info.crtcs[1]->base.mode;
2748 pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
2749 }
2750 }
2751
2752 min_mem_eff.full = dfixed_const_8(0);
2753 /* get modes */
2754 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
2755 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
2756 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
2757 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
2758 /* check crtc enables */
2759 if (mode2)
2760 mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
2761 if (mode1)
2762 mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
2763 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
2764 }
2765
2766 /*
2767 * determine is there is enough bw for current mode
2768 */
2769 sclk_ff = rdev->pm.sclk;
2770 mclk_ff = rdev->pm.mclk;
2771
2772 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
2773 temp_ff.full = dfixed_const(temp);
2774 mem_bw.full = dfixed_mul(mclk_ff, temp_ff);
2775
2776 pix_clk.full = 0;
2777 pix_clk2.full = 0;
2778 peak_disp_bw.full = 0;
2779 if (mode1) {
2780 temp_ff.full = dfixed_const(1000);
2781 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */
2782 pix_clk.full = dfixed_div(pix_clk, temp_ff);
2783 temp_ff.full = dfixed_const(pixel_bytes1);
2784 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff);
2785 }
2786 if (mode2) {
2787 temp_ff.full = dfixed_const(1000);
2788 pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */
2789 pix_clk2.full = dfixed_div(pix_clk2, temp_ff);
2790 temp_ff.full = dfixed_const(pixel_bytes2);
2791 peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff);
2792 }
2793
2794 mem_bw.full = dfixed_mul(mem_bw, min_mem_eff);
2795 if (peak_disp_bw.full >= mem_bw.full) {
2796 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
2797 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
2798 }
2799
2800 /* Get values from the EXT_MEM_CNTL register...converting its contents. */
2801 temp = RREG32(RADEON_MEM_TIMING_CNTL);
2802 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
2803 mem_trcd = ((temp >> 2) & 0x3) + 1;
2804 mem_trp = ((temp & 0x3)) + 1;
2805 mem_tras = ((temp & 0x70) >> 4) + 1;
2806 } else if (rdev->family == CHIP_R300 ||
2807 rdev->family == CHIP_R350) { /* r300, r350 */
2808 mem_trcd = (temp & 0x7) + 1;
2809 mem_trp = ((temp >> 8) & 0x7) + 1;
2810 mem_tras = ((temp >> 11) & 0xf) + 4;
2811 } else if (rdev->family == CHIP_RV350 ||
2812 rdev->family <= CHIP_RV380) {
2813 /* rv3x0 */
2814 mem_trcd = (temp & 0x7) + 3;
2815 mem_trp = ((temp >> 8) & 0x7) + 3;
2816 mem_tras = ((temp >> 11) & 0xf) + 6;
2817 } else if (rdev->family == CHIP_R420 ||
2818 rdev->family == CHIP_R423 ||
2819 rdev->family == CHIP_RV410) {
2820 /* r4xx */
2821 mem_trcd = (temp & 0xf) + 3;
2822 if (mem_trcd > 15)
2823 mem_trcd = 15;
2824 mem_trp = ((temp >> 8) & 0xf) + 3;
2825 if (mem_trp > 15)
2826 mem_trp = 15;
2827 mem_tras = ((temp >> 12) & 0x1f) + 6;
2828 if (mem_tras > 31)
2829 mem_tras = 31;
2830 } else { /* RV200, R200 */
2831 mem_trcd = (temp & 0x7) + 1;
2832 mem_trp = ((temp >> 8) & 0x7) + 1;
2833 mem_tras = ((temp >> 12) & 0xf) + 4;
2834 }
2835 /* convert to FF */
2836 trcd_ff.full = dfixed_const(mem_trcd);
2837 trp_ff.full = dfixed_const(mem_trp);
2838 tras_ff.full = dfixed_const(mem_tras);
2839
2840 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
2841 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2842 data = (temp & (7 << 20)) >> 20;
2843 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
2844 if (rdev->family == CHIP_RS480) /* don't think rs400 */
2845 tcas_ff = memtcas_rs480_ff[data];
2846 else
2847 tcas_ff = memtcas_ff[data];
2848 } else
2849 tcas_ff = memtcas2_ff[data];
2850
2851 if (rdev->family == CHIP_RS400 ||
2852 rdev->family == CHIP_RS480) {
2853 /* extra cas latency stored in bits 23-25 0-4 clocks */
2854 data = (temp >> 23) & 0x7;
2855 if (data < 5)
2856 tcas_ff.full += dfixed_const(data);
2857 }
2858
2859 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
2860 /* on the R300, Tcas is included in Trbs.
2861 */
2862 temp = RREG32(RADEON_MEM_CNTL);
2863 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
2864 if (data == 1) {
2865 if (R300_MEM_USE_CD_CH_ONLY & temp) {
2866 temp = RREG32(R300_MC_IND_INDEX);
2867 temp &= ~R300_MC_IND_ADDR_MASK;
2868 temp |= R300_MC_READ_CNTL_CD_mcind;
2869 WREG32(R300_MC_IND_INDEX, temp);
2870 temp = RREG32(R300_MC_IND_DATA);
2871 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
2872 } else {
2873 temp = RREG32(R300_MC_READ_CNTL_AB);
2874 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2875 }
2876 } else {
2877 temp = RREG32(R300_MC_READ_CNTL_AB);
2878 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2879 }
2880 if (rdev->family == CHIP_RV410 ||
2881 rdev->family == CHIP_R420 ||
2882 rdev->family == CHIP_R423)
2883 trbs_ff = memtrbs_r4xx[data];
2884 else
2885 trbs_ff = memtrbs[data];
2886 tcas_ff.full += trbs_ff.full;
2887 }
2888
2889 sclk_eff_ff.full = sclk_ff.full;
2890
2891 if (rdev->flags & RADEON_IS_AGP) {
2892 fixed20_12 agpmode_ff;
2893 agpmode_ff.full = dfixed_const(radeon_agpmode);
2894 temp_ff.full = dfixed_const_666(16);
2895 sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff);
2896 }
2897 /* TODO PCIE lanes may affect this - agpmode == 16?? */
2898
2899 if (ASIC_IS_R300(rdev)) {
2900 sclk_delay_ff.full = dfixed_const(250);
2901 } else {
2902 if ((rdev->family == CHIP_RV100) ||
2903 rdev->flags & RADEON_IS_IGP) {
2904 if (rdev->mc.vram_is_ddr)
2905 sclk_delay_ff.full = dfixed_const(41);
2906 else
2907 sclk_delay_ff.full = dfixed_const(33);
2908 } else {
2909 if (rdev->mc.vram_width == 128)
2910 sclk_delay_ff.full = dfixed_const(57);
2911 else
2912 sclk_delay_ff.full = dfixed_const(41);
2913 }
2914 }
2915
2916 mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff);
2917
2918 if (rdev->mc.vram_is_ddr) {
2919 if (rdev->mc.vram_width == 32) {
2920 k1.full = dfixed_const(40);
2921 c = 3;
2922 } else {
2923 k1.full = dfixed_const(20);
2924 c = 1;
2925 }
2926 } else {
2927 k1.full = dfixed_const(40);
2928 c = 3;
2929 }
2930
2931 temp_ff.full = dfixed_const(2);
2932 mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff);
2933 temp_ff.full = dfixed_const(c);
2934 mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff);
2935 temp_ff.full = dfixed_const(4);
2936 mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff);
2937 mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff);
2938 mc_latency_mclk.full += k1.full;
2939
2940 mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff);
2941 mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff);
2942
2943 /*
2944 HW cursor time assuming worst case of full size colour cursor.
2945 */
2946 temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
2947 temp_ff.full += trcd_ff.full;
2948 if (temp_ff.full < tras_ff.full)
2949 temp_ff.full = tras_ff.full;
2950 cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff);
2951
2952 temp_ff.full = dfixed_const(cur_size);
2953 cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff);
2954 /*
2955 Find the total latency for the display data.
2956 */
2957 disp_latency_overhead.full = dfixed_const(8);
2958 disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff);
2959 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
2960 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
2961
2962 if (mc_latency_mclk.full > mc_latency_sclk.full)
2963 disp_latency.full = mc_latency_mclk.full;
2964 else
2965 disp_latency.full = mc_latency_sclk.full;
2966
2967 /* setup Max GRPH_STOP_REQ default value */
2968 if (ASIC_IS_RV100(rdev))
2969 max_stop_req = 0x5c;
2970 else
2971 max_stop_req = 0x7c;
2972
2973 if (mode1) {
2974 /* CRTC1
2975 Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
2976 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
2977 */
2978 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
2979
2980 if (stop_req > max_stop_req)
2981 stop_req = max_stop_req;
2982
2983 /*
2984 Find the drain rate of the display buffer.
2985 */
2986 temp_ff.full = dfixed_const((16/pixel_bytes1));
2987 disp_drain_rate.full = dfixed_div(pix_clk, temp_ff);
2988
2989 /*
2990 Find the critical point of the display buffer.
2991 */
2992 crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency);
2993 crit_point_ff.full += dfixed_const_half(0);
2994
2995 critical_point = dfixed_trunc(crit_point_ff);
2996
2997 if (rdev->disp_priority == 2) {
2998 critical_point = 0;
2999 }
3000
3001 /*
3002 The critical point should never be above max_stop_req-4. Setting
3003 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
3004 */
3005 if (max_stop_req - critical_point < 4)
3006 critical_point = 0;
3007
3008 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
3009 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
3010 critical_point = 0x10;
3011 }
3012
3013 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
3014 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
3015 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3016 temp &= ~(RADEON_GRPH_START_REQ_MASK);
3017 if ((rdev->family == CHIP_R350) &&
3018 (stop_req > 0x15)) {
3019 stop_req -= 0x10;
3020 }
3021 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3022 temp |= RADEON_GRPH_BUFFER_SIZE;
3023 temp &= ~(RADEON_GRPH_CRITICAL_CNTL |
3024 RADEON_GRPH_CRITICAL_AT_SOF |
3025 RADEON_GRPH_STOP_CNTL);
3026 /*
3027 Write the result into the register.
3028 */
3029 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3030 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3031
3032 #if 0
3033 if ((rdev->family == CHIP_RS400) ||
3034 (rdev->family == CHIP_RS480)) {
3035 /* attempt to program RS400 disp regs correctly ??? */
3036 temp = RREG32(RS400_DISP1_REG_CNTL);
3037 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
3038 RS400_DISP1_STOP_REQ_LEVEL_MASK);
3039 WREG32(RS400_DISP1_REQ_CNTL1, (temp |
3040 (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3041 (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3042 temp = RREG32(RS400_DMIF_MEM_CNTL1);
3043 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
3044 RS400_DISP1_CRITICAL_POINT_STOP_MASK);
3045 WREG32(RS400_DMIF_MEM_CNTL1, (temp |
3046 (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
3047 (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
3048 }
3049 #endif
3050
3051 DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n",
3052 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */
3053 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
3054 }
3055
3056 if (mode2) {
3057 u32 grph2_cntl;
3058 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
3059
3060 if (stop_req > max_stop_req)
3061 stop_req = max_stop_req;
3062
3063 /*
3064 Find the drain rate of the display buffer.
3065 */
3066 temp_ff.full = dfixed_const((16/pixel_bytes2));
3067 disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff);
3068
3069 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
3070 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
3071 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3072 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
3073 if ((rdev->family == CHIP_R350) &&
3074 (stop_req > 0x15)) {
3075 stop_req -= 0x10;
3076 }
3077 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3078 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
3079 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL |
3080 RADEON_GRPH_CRITICAL_AT_SOF |
3081 RADEON_GRPH_STOP_CNTL);
3082
3083 if ((rdev->family == CHIP_RS100) ||
3084 (rdev->family == CHIP_RS200))
3085 critical_point2 = 0;
3086 else {
3087 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
3088 temp_ff.full = dfixed_const(temp);
3089 temp_ff.full = dfixed_mul(mclk_ff, temp_ff);
3090 if (sclk_ff.full < temp_ff.full)
3091 temp_ff.full = sclk_ff.full;
3092
3093 read_return_rate.full = temp_ff.full;
3094
3095 if (mode1) {
3096 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
3097 time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff);
3098 } else {
3099 time_disp1_drop_priority.full = 0;
3100 }
3101 crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
3102 crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2);
3103 crit_point_ff.full += dfixed_const_half(0);
3104
3105 critical_point2 = dfixed_trunc(crit_point_ff);
3106
3107 if (rdev->disp_priority == 2) {
3108 critical_point2 = 0;
3109 }
3110
3111 if (max_stop_req - critical_point2 < 4)
3112 critical_point2 = 0;
3113
3114 }
3115
3116 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
3117 /* some R300 cards have problem with this set to 0 */
3118 critical_point2 = 0x10;
3119 }
3120
3121 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3122 (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3123
3124 if ((rdev->family == CHIP_RS400) ||
3125 (rdev->family == CHIP_RS480)) {
3126 #if 0
3127 /* attempt to program RS400 disp2 regs correctly ??? */
3128 temp = RREG32(RS400_DISP2_REQ_CNTL1);
3129 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
3130 RS400_DISP2_STOP_REQ_LEVEL_MASK);
3131 WREG32(RS400_DISP2_REQ_CNTL1, (temp |
3132 (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3133 (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3134 temp = RREG32(RS400_DISP2_REQ_CNTL2);
3135 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
3136 RS400_DISP2_CRITICAL_POINT_STOP_MASK);
3137 WREG32(RS400_DISP2_REQ_CNTL2, (temp |
3138 (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
3139 (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
3140 #endif
3141 WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
3142 WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
3143 WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC);
3144 WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
3145 }
3146
3147 DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n",
3148 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
3149 }
3150 }
3151
3152 static inline void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
3153 {
3154 DRM_ERROR("pitch %d\n", t->pitch);
3155 DRM_ERROR("use_pitch %d\n", t->use_pitch);
3156 DRM_ERROR("width %d\n", t->width);
3157 DRM_ERROR("width_11 %d\n", t->width_11);
3158 DRM_ERROR("height %d\n", t->height);
3159 DRM_ERROR("height_11 %d\n", t->height_11);
3160 DRM_ERROR("num levels %d\n", t->num_levels);
3161 DRM_ERROR("depth %d\n", t->txdepth);
3162 DRM_ERROR("bpp %d\n", t->cpp);
3163 DRM_ERROR("coordinate type %d\n", t->tex_coord_type);
3164 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
3165 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
3166 DRM_ERROR("compress format %d\n", t->compress_format);
3167 }
3168
3169 static int r100_track_compress_size(int compress_format, int w, int h)
3170 {
3171 int block_width, block_height, block_bytes;
3172 int wblocks, hblocks;
3173 int min_wblocks;
3174 int sz;
3175
3176 block_width = 4;
3177 block_height = 4;
3178
3179 switch (compress_format) {
3180 case R100_TRACK_COMP_DXT1:
3181 block_bytes = 8;
3182 min_wblocks = 4;
3183 break;
3184 default:
3185 case R100_TRACK_COMP_DXT35:
3186 block_bytes = 16;
3187 min_wblocks = 2;
3188 break;
3189 }
3190
3191 hblocks = (h + block_height - 1) / block_height;
3192 wblocks = (w + block_width - 1) / block_width;
3193 if (wblocks < min_wblocks)
3194 wblocks = min_wblocks;
3195 sz = wblocks * hblocks * block_bytes;
3196 return sz;
3197 }
3198
3199 static int r100_cs_track_cube(struct radeon_device *rdev,
3200 struct r100_cs_track *track, unsigned idx)
3201 {
3202 unsigned face, w, h;
3203 struct radeon_bo *cube_robj;
3204 unsigned long size;
3205 unsigned compress_format = track->textures[idx].compress_format;
3206
3207 for (face = 0; face < 5; face++) {
3208 cube_robj = track->textures[idx].cube_info[face].robj;
3209 w = track->textures[idx].cube_info[face].width;
3210 h = track->textures[idx].cube_info[face].height;
3211
3212 if (compress_format) {
3213 size = r100_track_compress_size(compress_format, w, h);
3214 } else
3215 size = w * h;
3216 size *= track->textures[idx].cpp;
3217
3218 size += track->textures[idx].cube_info[face].offset;
3219
3220 if (size > radeon_bo_size(cube_robj)) {
3221 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
3222 size, radeon_bo_size(cube_robj));
3223 r100_cs_track_texture_print(&track->textures[idx]);
3224 return -1;
3225 }
3226 }
3227 return 0;
3228 }
3229
3230 static int r100_cs_track_texture_check(struct radeon_device *rdev,
3231 struct r100_cs_track *track)
3232 {
3233 struct radeon_bo *robj;
3234 unsigned long size;
3235 unsigned u, i, w, h, d;
3236 int ret;
3237
3238 for (u = 0; u < track->num_texture; u++) {
3239 if (!track->textures[u].enabled)
3240 continue;
3241 if (track->textures[u].lookup_disable)
3242 continue;
3243 robj = track->textures[u].robj;
3244 if (robj == NULL) {
3245 DRM_ERROR("No texture bound to unit %u\n", u);
3246 return -EINVAL;
3247 }
3248 size = 0;
3249 for (i = 0; i <= track->textures[u].num_levels; i++) {
3250 if (track->textures[u].use_pitch) {
3251 if (rdev->family < CHIP_R300)
3252 w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
3253 else
3254 w = track->textures[u].pitch / (1 << i);
3255 } else {
3256 w = track->textures[u].width;
3257 if (rdev->family >= CHIP_RV515)
3258 w |= track->textures[u].width_11;
3259 w = w / (1 << i);
3260 if (track->textures[u].roundup_w)
3261 w = roundup_pow_of_two(w);
3262 }
3263 h = track->textures[u].height;
3264 if (rdev->family >= CHIP_RV515)
3265 h |= track->textures[u].height_11;
3266 h = h / (1 << i);
3267 if (track->textures[u].roundup_h)
3268 h = roundup_pow_of_two(h);
3269 if (track->textures[u].tex_coord_type == 1) {
3270 d = (1 << track->textures[u].txdepth) / (1 << i);
3271 if (!d)
3272 d = 1;
3273 } else {
3274 d = 1;
3275 }
3276 if (track->textures[u].compress_format) {
3277
3278 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d;
3279 /* compressed textures are block based */
3280 } else
3281 size += w * h * d;
3282 }
3283 size *= track->textures[u].cpp;
3284
3285 switch (track->textures[u].tex_coord_type) {
3286 case 0:
3287 case 1:
3288 break;
3289 case 2:
3290 if (track->separate_cube) {
3291 ret = r100_cs_track_cube(rdev, track, u);
3292 if (ret)
3293 return ret;
3294 } else
3295 size *= 6;
3296 break;
3297 default:
3298 DRM_ERROR("Invalid texture coordinate type %u for unit "
3299 "%u\n", track->textures[u].tex_coord_type, u);
3300 return -EINVAL;
3301 }
3302 if (size > radeon_bo_size(robj)) {
3303 DRM_ERROR("Texture of unit %u needs %lu bytes but is "
3304 "%lu\n", u, size, radeon_bo_size(robj));
3305 r100_cs_track_texture_print(&track->textures[u]);
3306 return -EINVAL;
3307 }
3308 }
3309 return 0;
3310 }
3311
3312 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
3313 {
3314 unsigned i;
3315 unsigned long size;
3316 unsigned prim_walk;
3317 unsigned nverts;
3318 unsigned num_cb = track->cb_dirty ? track->num_cb : 0;
3319
3320 if (num_cb && !track->zb_cb_clear && !track->color_channel_mask &&
3321 !track->blend_read_enable)
3322 num_cb = 0;
3323
3324 for (i = 0; i < num_cb; i++) {
3325 if (track->cb[i].robj == NULL) {
3326 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
3327 return -EINVAL;
3328 }
3329 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
3330 size += track->cb[i].offset;
3331 if (size > radeon_bo_size(track->cb[i].robj)) {
3332 DRM_ERROR("[drm] Buffer too small for color buffer %d "
3333 "(need %lu have %lu) !\n", i, size,
3334 radeon_bo_size(track->cb[i].robj));
3335 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
3336 i, track->cb[i].pitch, track->cb[i].cpp,
3337 track->cb[i].offset, track->maxy);
3338 return -EINVAL;
3339 }
3340 }
3341 track->cb_dirty = false;
3342
3343 if (track->zb_dirty && track->z_enabled) {
3344 if (track->zb.robj == NULL) {
3345 DRM_ERROR("[drm] No buffer for z buffer !\n");
3346 return -EINVAL;
3347 }
3348 size = track->zb.pitch * track->zb.cpp * track->maxy;
3349 size += track->zb.offset;
3350 if (size > radeon_bo_size(track->zb.robj)) {
3351 DRM_ERROR("[drm] Buffer too small for z buffer "
3352 "(need %lu have %lu) !\n", size,
3353 radeon_bo_size(track->zb.robj));
3354 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
3355 track->zb.pitch, track->zb.cpp,
3356 track->zb.offset, track->maxy);
3357 return -EINVAL;
3358 }
3359 }
3360 track->zb_dirty = false;
3361
3362 if (track->aa_dirty && track->aaresolve) {
3363 if (track->aa.robj == NULL) {
3364 DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i);
3365 return -EINVAL;
3366 }
3367 /* I believe the format comes from colorbuffer0. */
3368 size = track->aa.pitch * track->cb[0].cpp * track->maxy;
3369 size += track->aa.offset;
3370 if (size > radeon_bo_size(track->aa.robj)) {
3371 DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d "
3372 "(need %lu have %lu) !\n", i, size,
3373 radeon_bo_size(track->aa.robj));
3374 DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n",
3375 i, track->aa.pitch, track->cb[0].cpp,
3376 track->aa.offset, track->maxy);
3377 return -EINVAL;
3378 }
3379 }
3380 track->aa_dirty = false;
3381
3382 prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
3383 if (track->vap_vf_cntl & (1 << 14)) {
3384 nverts = track->vap_alt_nverts;
3385 } else {
3386 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
3387 }
3388 switch (prim_walk) {
3389 case 1:
3390 for (i = 0; i < track->num_arrays; i++) {
3391 size = track->arrays[i].esize * track->max_indx * 4;
3392 if (track->arrays[i].robj == NULL) {
3393 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3394 "bound\n", prim_walk, i);
3395 return -EINVAL;
3396 }
3397 if (size > radeon_bo_size(track->arrays[i].robj)) {
3398 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3399 "need %lu dwords have %lu dwords\n",
3400 prim_walk, i, size >> 2,
3401 radeon_bo_size(track->arrays[i].robj)
3402 >> 2);
3403 DRM_ERROR("Max indices %u\n", track->max_indx);
3404 return -EINVAL;
3405 }
3406 }
3407 break;
3408 case 2:
3409 for (i = 0; i < track->num_arrays; i++) {
3410 size = track->arrays[i].esize * (nverts - 1) * 4;
3411 if (track->arrays[i].robj == NULL) {
3412 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3413 "bound\n", prim_walk, i);
3414 return -EINVAL;
3415 }
3416 if (size > radeon_bo_size(track->arrays[i].robj)) {
3417 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3418 "need %lu dwords have %lu dwords\n",
3419 prim_walk, i, size >> 2,
3420 radeon_bo_size(track->arrays[i].robj)
3421 >> 2);
3422 return -EINVAL;
3423 }
3424 }
3425 break;
3426 case 3:
3427 size = track->vtx_size * nverts;
3428 if (size != track->immd_dwords) {
3429 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
3430 track->immd_dwords, size);
3431 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
3432 nverts, track->vtx_size);
3433 return -EINVAL;
3434 }
3435 break;
3436 default:
3437 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
3438 prim_walk);
3439 return -EINVAL;
3440 }
3441
3442 if (track->tex_dirty) {
3443 track->tex_dirty = false;
3444 return r100_cs_track_texture_check(rdev, track);
3445 }
3446 return 0;
3447 }
3448
3449 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
3450 {
3451 unsigned i, face;
3452
3453 track->cb_dirty = true;
3454 track->zb_dirty = true;
3455 track->tex_dirty = true;
3456 track->aa_dirty = true;
3457
3458 if (rdev->family < CHIP_R300) {
3459 track->num_cb = 1;
3460 if (rdev->family <= CHIP_RS200)
3461 track->num_texture = 3;
3462 else
3463 track->num_texture = 6;
3464 track->maxy = 2048;
3465 track->separate_cube = 1;
3466 } else {
3467 track->num_cb = 4;
3468 track->num_texture = 16;
3469 track->maxy = 4096;
3470 track->separate_cube = 0;
3471 track->aaresolve = false;
3472 track->aa.robj = NULL;
3473 }
3474
3475 for (i = 0; i < track->num_cb; i++) {
3476 track->cb[i].robj = NULL;
3477 track->cb[i].pitch = 8192;
3478 track->cb[i].cpp = 16;
3479 track->cb[i].offset = 0;
3480 }
3481 track->z_enabled = true;
3482 track->zb.robj = NULL;
3483 track->zb.pitch = 8192;
3484 track->zb.cpp = 4;
3485 track->zb.offset = 0;
3486 track->vtx_size = 0x7F;
3487 track->immd_dwords = 0xFFFFFFFFUL;
3488 track->num_arrays = 11;
3489 track->max_indx = 0x00FFFFFFUL;
3490 for (i = 0; i < track->num_arrays; i++) {
3491 track->arrays[i].robj = NULL;
3492 track->arrays[i].esize = 0x7F;
3493 }
3494 for (i = 0; i < track->num_texture; i++) {
3495 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
3496 track->textures[i].pitch = 16536;
3497 track->textures[i].width = 16536;
3498 track->textures[i].height = 16536;
3499 track->textures[i].width_11 = 1 << 11;
3500 track->textures[i].height_11 = 1 << 11;
3501 track->textures[i].num_levels = 12;
3502 if (rdev->family <= CHIP_RS200) {
3503 track->textures[i].tex_coord_type = 0;
3504 track->textures[i].txdepth = 0;
3505 } else {
3506 track->textures[i].txdepth = 16;
3507 track->textures[i].tex_coord_type = 1;
3508 }
3509 track->textures[i].cpp = 64;
3510 track->textures[i].robj = NULL;
3511 /* CS IB emission code makes sure texture unit are disabled */
3512 track->textures[i].enabled = false;
3513 track->textures[i].lookup_disable = false;
3514 track->textures[i].roundup_w = true;
3515 track->textures[i].roundup_h = true;
3516 if (track->separate_cube)
3517 for (face = 0; face < 5; face++) {
3518 track->textures[i].cube_info[face].robj = NULL;
3519 track->textures[i].cube_info[face].width = 16536;
3520 track->textures[i].cube_info[face].height = 16536;
3521 track->textures[i].cube_info[face].offset = 0;
3522 }
3523 }
3524 }
3525
3526 int r100_ring_test(struct radeon_device *rdev)
3527 {
3528 uint32_t scratch;
3529 uint32_t tmp = 0;
3530 unsigned i;
3531 int r;
3532
3533 r = radeon_scratch_get(rdev, &scratch);
3534 if (r) {
3535 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3536 return r;
3537 }
3538 WREG32(scratch, 0xCAFEDEAD);
3539 r = radeon_ring_lock(rdev, 2);
3540 if (r) {
3541 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3542 radeon_scratch_free(rdev, scratch);
3543 return r;
3544 }
3545 radeon_ring_write(rdev, PACKET0(scratch, 0));
3546 radeon_ring_write(rdev, 0xDEADBEEF);
3547 radeon_ring_unlock_commit(rdev);
3548 for (i = 0; i < rdev->usec_timeout; i++) {
3549 tmp = RREG32(scratch);
3550 if (tmp == 0xDEADBEEF) {
3551 break;
3552 }
3553 DRM_UDELAY(1);
3554 }
3555 if (i < rdev->usec_timeout) {
3556 DRM_INFO("ring test succeeded in %d usecs\n", i);
3557 } else {
3558 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
3559 scratch, tmp);
3560 r = -EINVAL;
3561 }
3562 radeon_scratch_free(rdev, scratch);
3563 return r;
3564 }
3565
3566 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3567 {
3568 radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1));
3569 radeon_ring_write(rdev, ib->gpu_addr);
3570 radeon_ring_write(rdev, ib->length_dw);
3571 }
3572
3573 int r100_ib_test(struct radeon_device *rdev)
3574 {
3575 struct radeon_ib *ib;
3576 uint32_t scratch;
3577 uint32_t tmp = 0;
3578 unsigned i;
3579 int r;
3580
3581 r = radeon_scratch_get(rdev, &scratch);
3582 if (r) {
3583 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3584 return r;
3585 }
3586 WREG32(scratch, 0xCAFEDEAD);
3587 r = radeon_ib_get(rdev, &ib);
3588 if (r) {
3589 return r;
3590 }
3591 ib->ptr[0] = PACKET0(scratch, 0);
3592 ib->ptr[1] = 0xDEADBEEF;
3593 ib->ptr[2] = PACKET2(0);
3594 ib->ptr[3] = PACKET2(0);
3595 ib->ptr[4] = PACKET2(0);
3596 ib->ptr[5] = PACKET2(0);
3597 ib->ptr[6] = PACKET2(0);
3598 ib->ptr[7] = PACKET2(0);
3599 ib->length_dw = 8;
3600 r = radeon_ib_schedule(rdev, ib);
3601 if (r) {
3602 radeon_scratch_free(rdev, scratch);
3603 radeon_ib_free(rdev, &ib);
3604 return r;
3605 }
3606 r = radeon_fence_wait(ib->fence, false);
3607 if (r) {
3608 return r;
3609 }
3610 for (i = 0; i < rdev->usec_timeout; i++) {
3611 tmp = RREG32(scratch);
3612 if (tmp == 0xDEADBEEF) {
3613 break;
3614 }
3615 DRM_UDELAY(1);
3616 }
3617 if (i < rdev->usec_timeout) {
3618 DRM_INFO("ib test succeeded in %u usecs\n", i);
3619 } else {
3620 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3621 scratch, tmp);
3622 r = -EINVAL;
3623 }
3624 radeon_scratch_free(rdev, scratch);
3625 radeon_ib_free(rdev, &ib);
3626 return r;
3627 }
3628
3629 void r100_ib_fini(struct radeon_device *rdev)
3630 {
3631 radeon_ib_pool_fini(rdev);
3632 }
3633
3634 int r100_ib_init(struct radeon_device *rdev)
3635 {
3636 int r;
3637
3638 r = radeon_ib_pool_init(rdev);
3639 if (r) {
3640 dev_err(rdev->dev, "failed initializing IB pool (%d).\n", r);
3641 r100_ib_fini(rdev);
3642 return r;
3643 }
3644 r = r100_ib_test(rdev);
3645 if (r) {
3646 dev_err(rdev->dev, "failed testing IB (%d).\n", r);
3647 r100_ib_fini(rdev);
3648 return r;
3649 }
3650 return 0;
3651 }
3652
3653 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3654 {
3655 /* Shutdown CP we shouldn't need to do that but better be safe than
3656 * sorry
3657 */
3658 rdev->cp.ready = false;
3659 WREG32(R_000740_CP_CSQ_CNTL, 0);
3660
3661 /* Save few CRTC registers */
3662 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
3663 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3664 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3665 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3666 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3667 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3668 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3669 }
3670
3671 /* Disable VGA aperture access */
3672 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
3673 /* Disable cursor, overlay, crtc */
3674 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3675 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3676 S_000054_CRTC_DISPLAY_DIS(1));
3677 WREG32(R_000050_CRTC_GEN_CNTL,
3678 (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3679 S_000050_CRTC_DISP_REQ_EN_B(1));
3680 WREG32(R_000420_OV0_SCALE_CNTL,
3681 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3682 WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3683 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3684 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3685 S_000360_CUR2_LOCK(1));
3686 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3687 (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3688 S_0003F8_CRTC2_DISPLAY_DIS(1) |
3689 S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3690 WREG32(R_000360_CUR2_OFFSET,
3691 C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3692 }
3693 }
3694
3695 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3696 {
3697 /* Update base address for crtc */
3698 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3699 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3700 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3701 }
3702 /* Restore CRTC registers */
3703 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
3704 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3705 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3706 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3707 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3708 }
3709 }
3710
3711 void r100_vga_render_disable(struct radeon_device *rdev)
3712 {
3713 u32 tmp;
3714
3715 tmp = RREG8(R_0003C2_GENMO_WT);
3716 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3717 }
3718
3719 static void r100_debugfs(struct radeon_device *rdev)
3720 {
3721 int r;
3722
3723 r = r100_debugfs_mc_info_init(rdev);
3724 if (r)
3725 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3726 }
3727
3728 static void r100_mc_program(struct radeon_device *rdev)
3729 {
3730 struct r100_mc_save save;
3731
3732 /* Stops all mc clients */
3733 r100_mc_stop(rdev, &save);
3734 if (rdev->flags & RADEON_IS_AGP) {
3735 WREG32(R_00014C_MC_AGP_LOCATION,
3736 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3737 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3738 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3739 if (rdev->family > CHIP_RV200)
3740 WREG32(R_00015C_AGP_BASE_2,
3741 upper_32_bits(rdev->mc.agp_base) & 0xff);
3742 } else {
3743 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3744 WREG32(R_000170_AGP_BASE, 0);
3745 if (rdev->family > CHIP_RV200)
3746 WREG32(R_00015C_AGP_BASE_2, 0);
3747 }
3748 /* Wait for mc idle */
3749 if (r100_mc_wait_for_idle(rdev))
3750 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3751 /* Program MC, should be a 32bits limited address space */
3752 WREG32(R_000148_MC_FB_LOCATION,
3753 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3754 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3755 r100_mc_resume(rdev, &save);
3756 }
3757
3758 void r100_clock_startup(struct radeon_device *rdev)
3759 {
3760 u32 tmp;
3761
3762 if (radeon_dynclks != -1 && radeon_dynclks)
3763 radeon_legacy_set_clock_gating(rdev, 1);
3764 /* We need to force on some of the block */
3765 tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3766 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3767 if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3768 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3769 WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3770 }
3771
3772 static int r100_startup(struct radeon_device *rdev)
3773 {
3774 int r;
3775
3776 /* set common regs */
3777 r100_set_common_regs(rdev);
3778 /* program mc */
3779 r100_mc_program(rdev);
3780 /* Resume clock */
3781 r100_clock_startup(rdev);
3782 /* Initialize GART (initialize after TTM so we can allocate
3783 * memory through TTM but finalize after TTM) */
3784 r100_enable_bm(rdev);
3785 if (rdev->flags & RADEON_IS_PCI) {
3786 r = r100_pci_gart_enable(rdev);
3787 if (r)
3788 return r;
3789 }
3790
3791 /* allocate wb buffer */
3792 r = radeon_wb_init(rdev);
3793 if (r)
3794 return r;
3795
3796 /* Enable IRQ */
3797 r100_irq_set(rdev);
3798 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
3799 /* 1M ring buffer */
3800 r = r100_cp_init(rdev, 1024 * 1024);
3801 if (r) {
3802 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
3803 return r;
3804 }
3805 r = r100_ib_init(rdev);
3806 if (r) {
3807 dev_err(rdev->dev, "failed initializing IB (%d).\n", r);
3808 return r;
3809 }
3810 return 0;
3811 }
3812
3813 int r100_resume(struct radeon_device *rdev)
3814 {
3815 /* Make sur GART are not working */
3816 if (rdev->flags & RADEON_IS_PCI)
3817 r100_pci_gart_disable(rdev);
3818 /* Resume clock before doing reset */
3819 r100_clock_startup(rdev);
3820 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3821 if (radeon_asic_reset(rdev)) {
3822 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3823 RREG32(R_000E40_RBBM_STATUS),
3824 RREG32(R_0007C0_CP_STAT));
3825 }
3826 /* post */
3827 radeon_combios_asic_init(rdev->ddev);
3828 /* Resume clock after posting */
3829 r100_clock_startup(rdev);
3830 /* Initialize surface registers */
3831 radeon_surface_init(rdev);
3832 return r100_startup(rdev);
3833 }
3834
3835 int r100_suspend(struct radeon_device *rdev)
3836 {
3837 r100_cp_disable(rdev);
3838 radeon_wb_disable(rdev);
3839 r100_irq_disable(rdev);
3840 if (rdev->flags & RADEON_IS_PCI)
3841 r100_pci_gart_disable(rdev);
3842 return 0;
3843 }
3844
3845 void r100_fini(struct radeon_device *rdev)
3846 {
3847 r100_cp_fini(rdev);
3848 radeon_wb_fini(rdev);
3849 r100_ib_fini(rdev);
3850 radeon_gem_fini(rdev);
3851 if (rdev->flags & RADEON_IS_PCI)
3852 r100_pci_gart_fini(rdev);
3853 radeon_agp_fini(rdev);
3854 radeon_irq_kms_fini(rdev);
3855 radeon_fence_driver_fini(rdev);
3856 radeon_bo_fini(rdev);
3857 radeon_atombios_fini(rdev);
3858 kfree(rdev->bios);
3859 rdev->bios = NULL;
3860 }
3861
3862 /*
3863 * Due to how kexec works, it can leave the hw fully initialised when it
3864 * boots the new kernel. However doing our init sequence with the CP and
3865 * WB stuff setup causes GPU hangs on the RN50 at least. So at startup
3866 * do some quick sanity checks and restore sane values to avoid this
3867 * problem.
3868 */
3869 void r100_restore_sanity(struct radeon_device *rdev)
3870 {
3871 u32 tmp;
3872
3873 tmp = RREG32(RADEON_CP_CSQ_CNTL);
3874 if (tmp) {
3875 WREG32(RADEON_CP_CSQ_CNTL, 0);
3876 }
3877 tmp = RREG32(RADEON_CP_RB_CNTL);
3878 if (tmp) {
3879 WREG32(RADEON_CP_RB_CNTL, 0);
3880 }
3881 tmp = RREG32(RADEON_SCRATCH_UMSK);
3882 if (tmp) {
3883 WREG32(RADEON_SCRATCH_UMSK, 0);
3884 }
3885 }
3886
3887 int r100_init(struct radeon_device *rdev)
3888 {
3889 int r;
3890
3891 /* Register debugfs file specific to this group of asics */
3892 r100_debugfs(rdev);
3893 /* Disable VGA */
3894 r100_vga_render_disable(rdev);
3895 /* Initialize scratch registers */
3896 radeon_scratch_init(rdev);
3897 /* Initialize surface registers */
3898 radeon_surface_init(rdev);
3899 /* sanity check some register to avoid hangs like after kexec */
3900 r100_restore_sanity(rdev);
3901 /* TODO: disable VGA need to use VGA request */
3902 /* BIOS*/
3903 if (!radeon_get_bios(rdev)) {
3904 if (ASIC_IS_AVIVO(rdev))
3905 return -EINVAL;
3906 }
3907 if (rdev->is_atom_bios) {
3908 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
3909 return -EINVAL;
3910 } else {
3911 r = radeon_combios_init(rdev);
3912 if (r)
3913 return r;
3914 }
3915 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3916 if (radeon_asic_reset(rdev)) {
3917 dev_warn(rdev->dev,
3918 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3919 RREG32(R_000E40_RBBM_STATUS),
3920 RREG32(R_0007C0_CP_STAT));
3921 }
3922 /* check if cards are posted or not */
3923 if (radeon_boot_test_post_card(rdev) == false)
3924 return -EINVAL;
3925 /* Set asic errata */
3926 r100_errata(rdev);
3927 /* Initialize clocks */
3928 radeon_get_clock_info(rdev->ddev);
3929 /* initialize AGP */
3930 if (rdev->flags & RADEON_IS_AGP) {
3931 r = radeon_agp_init(rdev);
3932 if (r) {
3933 radeon_agp_disable(rdev);
3934 }
3935 }
3936 /* initialize VRAM */
3937 r100_mc_init(rdev);
3938 /* Fence driver */
3939 r = radeon_fence_driver_init(rdev);
3940 if (r)
3941 return r;
3942 r = radeon_irq_kms_init(rdev);
3943 if (r)
3944 return r;
3945 /* Memory manager */
3946 r = radeon_bo_init(rdev);
3947 if (r)
3948 return r;
3949 if (rdev->flags & RADEON_IS_PCI) {
3950 r = r100_pci_gart_init(rdev);
3951 if (r)
3952 return r;
3953 }
3954 r100_set_safe_registers(rdev);
3955 rdev->accel_working = true;
3956 r = r100_startup(rdev);
3957 if (r) {
3958 /* Somethings want wront with the accel init stop accel */
3959 dev_err(rdev->dev, "Disabling GPU acceleration\n");
3960 r100_cp_fini(rdev);
3961 radeon_wb_fini(rdev);
3962 r100_ib_fini(rdev);
3963 radeon_irq_kms_fini(rdev);
3964 if (rdev->flags & RADEON_IS_PCI)
3965 r100_pci_gart_fini(rdev);
3966 rdev->accel_working = false;
3967 }
3968 return 0;
3969 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree