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drm/nouveau: remove cpu_writers lock
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / gpu / drm / nouveau / nouveau_drv.h
blobb78663fc334c8e6a83ad052cc68a22920d21d8e9
1 /*
2 * Copyright 2005 Stephane Marchesin.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #ifndef __NOUVEAU_DRV_H__
26 #define __NOUVEAU_DRV_H__
27
28 #define DRIVER_AUTHOR "Stephane Marchesin"
29 #define DRIVER_EMAIL "dri-devel@lists.sourceforge.net"
30
31 #define DRIVER_NAME "nouveau"
32 #define DRIVER_DESC "nVidia Riva/TNT/GeForce"
33 #define DRIVER_DATE "20090420"
34
35 #define DRIVER_MAJOR 0
36 #define DRIVER_MINOR 0
37 #define DRIVER_PATCHLEVEL 16
38
39 #define NOUVEAU_FAMILY 0x0000FFFF
40 #define NOUVEAU_FLAGS 0xFFFF0000
41
42 #include "ttm/ttm_bo_api.h"
43 #include "ttm/ttm_bo_driver.h"
44 #include "ttm/ttm_placement.h"
45 #include "ttm/ttm_memory.h"
46 #include "ttm/ttm_module.h"
47
48 struct nouveau_fpriv {
49 struct ttm_object_file *tfile;
50 };
51
52 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
53
54 #include "nouveau_drm.h"
55 #include "nouveau_reg.h"
56 #include "nouveau_bios.h"
57 struct nouveau_grctx;
58
59 #define MAX_NUM_DCB_ENTRIES 16
60
61 #define NOUVEAU_MAX_CHANNEL_NR 128
62 #define NOUVEAU_MAX_TILE_NR 15
63
64 #define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL)
65 #define NV50_VM_BLOCK (512*1024*1024ULL)
66 #define NV50_VM_VRAM_NR (NV50_VM_MAX_VRAM / NV50_VM_BLOCK)
67
68 struct nouveau_tile_reg {
69 struct nouveau_fence *fence;
70 uint32_t addr;
71 uint32_t size;
72 bool used;
73 };
74
75 struct nouveau_bo {
76 struct ttm_buffer_object bo;
77 struct ttm_placement placement;
78 u32 placements[3];
79 u32 busy_placements[3];
80 struct ttm_bo_kmap_obj kmap;
81 struct list_head head;
82
83 /* protected by ttm_bo_reserve() */
84 struct drm_file *reserved_by;
85 struct list_head entry;
86 int pbbo_index;
87 bool validate_mapped;
88
89 struct nouveau_channel *channel;
90
91 bool mappable;
92 bool no_vm;
93
94 uint32_t tile_mode;
95 uint32_t tile_flags;
96 struct nouveau_tile_reg *tile;
97
98 struct drm_gem_object *gem;
99 int pin_refcnt;
100 };
101
102 #define nouveau_bo_tile_layout(nvbo) \
103 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK)
104
105 static inline struct nouveau_bo *
106 nouveau_bo(struct ttm_buffer_object *bo)
107 {
108 return container_of(bo, struct nouveau_bo, bo);
109 }
110
111 static inline struct nouveau_bo *
112 nouveau_gem_object(struct drm_gem_object *gem)
113 {
114 return gem ? gem->driver_private : NULL;
115 }
116
117 /* TODO: submit equivalent to TTM generic API upstream? */
118 static inline void __iomem *
119 nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo)
120 {
121 bool is_iomem;
122 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual(
123 &nvbo->kmap, &is_iomem);
124 WARN_ON_ONCE(ioptr && !is_iomem);
125 return ioptr;
126 }
127
128 enum nouveau_flags {
129 NV_NFORCE = 0x10000000,
130 NV_NFORCE2 = 0x20000000
131 };
132
133 #define NVOBJ_ENGINE_SW 0
134 #define NVOBJ_ENGINE_GR 1
135 #define NVOBJ_ENGINE_DISPLAY 2
136 #define NVOBJ_ENGINE_INT 0xdeadbeef
137
138 #define NVOBJ_FLAG_ZERO_ALLOC (1 << 1)
139 #define NVOBJ_FLAG_ZERO_FREE (1 << 2)
140 struct nouveau_gpuobj {
141 struct drm_device *dev;
142 struct kref refcount;
143 struct list_head list;
144
145 struct drm_mm_node *im_pramin;
146 struct nouveau_bo *im_backing;
147 uint32_t *im_backing_suspend;
148 int im_bound;
149
150 uint32_t flags;
151
152 u32 size;
153 u32 pinst;
154 u32 cinst;
155 u64 vinst;
156
157 uint32_t engine;
158 uint32_t class;
159
160 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *);
161 void *priv;
162 };
163
164 struct nouveau_channel {
165 struct drm_device *dev;
166 int id;
167
168 atomic_t refcount;
169 struct mutex mutex;
170
171 /* owner of this fifo */
172 struct drm_file *file_priv;
173 /* mapping of the fifo itself */
174 struct drm_local_map *map;
175
176 /* mapping of the regs controling the fifo */
177 void __iomem *user;
178 uint32_t user_get;
179 uint32_t user_put;
180
181 /* Fencing */
182 struct {
183 /* lock protects the pending list only */
184 spinlock_t lock;
185 struct list_head pending;
186 uint32_t sequence;
187 uint32_t sequence_ack;
188 atomic_t last_sequence_irq;
189 } fence;
190
191 /* DMA push buffer */
192 struct nouveau_gpuobj *pushbuf;
193 struct nouveau_bo *pushbuf_bo;
194 uint32_t pushbuf_base;
195
196 /* Notifier memory */
197 struct nouveau_bo *notifier_bo;
198 struct drm_mm notifier_heap;
199
200 /* PFIFO context */
201 struct nouveau_gpuobj *ramfc;
202 struct nouveau_gpuobj *cache;
203
204 /* PGRAPH context */
205 /* XXX may be merge 2 pointers as private data ??? */
206 struct nouveau_gpuobj *ramin_grctx;
207 void *pgraph_ctx;
208
209 /* NV50 VM */
210 struct nouveau_gpuobj *vm_pd;
211 struct nouveau_gpuobj *vm_gart_pt;
212 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR];
213
214 /* Objects */
215 struct nouveau_gpuobj *ramin; /* Private instmem */
216 struct drm_mm ramin_heap; /* Private PRAMIN heap */
217 struct nouveau_ramht *ramht; /* Hash table */
218
219 /* GPU object info for stuff used in-kernel (mm_enabled) */
220 uint32_t m2mf_ntfy;
221 uint32_t vram_handle;
222 uint32_t gart_handle;
223 bool accel_done;
224
225 /* Push buffer state (only for drm's channel on !mm_enabled) */
226 struct {
227 int max;
228 int free;
229 int cur;
230 int put;
231 /* access via pushbuf_bo */
232
233 int ib_base;
234 int ib_max;
235 int ib_free;
236 int ib_put;
237 } dma;
238
239 uint32_t sw_subchannel[8];
240
241 struct {
242 struct nouveau_gpuobj *vblsem;
243 uint32_t vblsem_offset;
244 uint32_t vblsem_rval;
245 struct list_head vbl_wait;
246 } nvsw;
247
248 struct {
249 bool active;
250 char name[32];
251 struct drm_info_list info;
252 } debugfs;
253 };
254
255 struct nouveau_instmem_engine {
256 void *priv;
257
258 int (*init)(struct drm_device *dev);
259 void (*takedown)(struct drm_device *dev);
260 int (*suspend)(struct drm_device *dev);
261 void (*resume)(struct drm_device *dev);
262
263 int (*populate)(struct drm_device *, struct nouveau_gpuobj *,
264 uint32_t *size);
265 void (*clear)(struct drm_device *, struct nouveau_gpuobj *);
266 int (*bind)(struct drm_device *, struct nouveau_gpuobj *);
267 int (*unbind)(struct drm_device *, struct nouveau_gpuobj *);
268 void (*flush)(struct drm_device *);
269 };
270
271 struct nouveau_mc_engine {
272 int (*init)(struct drm_device *dev);
273 void (*takedown)(struct drm_device *dev);
274 };
275
276 struct nouveau_timer_engine {
277 int (*init)(struct drm_device *dev);
278 void (*takedown)(struct drm_device *dev);
279 uint64_t (*read)(struct drm_device *dev);
280 };
281
282 struct nouveau_fb_engine {
283 int num_tiles;
284
285 int (*init)(struct drm_device *dev);
286 void (*takedown)(struct drm_device *dev);
287
288 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,
289 uint32_t size, uint32_t pitch);
290 };
291
292 struct nouveau_fifo_engine {
293 int channels;
294
295 struct nouveau_gpuobj *playlist[2];
296 int cur_playlist;
297
298 int (*init)(struct drm_device *);
299 void (*takedown)(struct drm_device *);
300
301 void (*disable)(struct drm_device *);
302 void (*enable)(struct drm_device *);
303 bool (*reassign)(struct drm_device *, bool enable);
304 bool (*cache_pull)(struct drm_device *dev, bool enable);
305
306 int (*channel_id)(struct drm_device *);
307
308 int (*create_context)(struct nouveau_channel *);
309 void (*destroy_context)(struct nouveau_channel *);
310 int (*load_context)(struct nouveau_channel *);
311 int (*unload_context)(struct drm_device *);
312 void (*tlb_flush)(struct drm_device *dev);
313 };
314
315 struct nouveau_pgraph_object_method {
316 int id;
317 int (*exec)(struct nouveau_channel *chan, int grclass, int mthd,
318 uint32_t data);
319 };
320
321 struct nouveau_pgraph_object_class {
322 int id;
323 bool software;
324 struct nouveau_pgraph_object_method *methods;
325 };
326
327 struct nouveau_pgraph_engine {
328 struct nouveau_pgraph_object_class *grclass;
329 bool accel_blocked;
330 int grctx_size;
331
332 /* NV2x/NV3x context table (0x400780) */
333 struct nouveau_gpuobj *ctx_table;
334
335 int (*init)(struct drm_device *);
336 void (*takedown)(struct drm_device *);
337
338 void (*fifo_access)(struct drm_device *, bool);
339
340 struct nouveau_channel *(*channel)(struct drm_device *);
341 int (*create_context)(struct nouveau_channel *);
342 void (*destroy_context)(struct nouveau_channel *);
343 int (*load_context)(struct nouveau_channel *);
344 int (*unload_context)(struct drm_device *);
345 void (*tlb_flush)(struct drm_device *dev);
346
347 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,
348 uint32_t size, uint32_t pitch);
349 };
350
351 struct nouveau_display_engine {
352 int (*early_init)(struct drm_device *);
353 void (*late_takedown)(struct drm_device *);
354 int (*create)(struct drm_device *);
355 int (*init)(struct drm_device *);
356 void (*destroy)(struct drm_device *);
357 };
358
359 struct nouveau_gpio_engine {
360 int (*init)(struct drm_device *);
361 void (*takedown)(struct drm_device *);
362
363 int (*get)(struct drm_device *, enum dcb_gpio_tag);
364 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state);
365
366 void (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on);
367 };
368
369 struct nouveau_pm_voltage_level {
370 u8 voltage;
371 u8 vid;
372 };
373
374 struct nouveau_pm_voltage {
375 bool supported;
376 u8 vid_mask;
377
378 struct nouveau_pm_voltage_level *level;
379 int nr_level;
380 };
381
382 #define NOUVEAU_PM_MAX_LEVEL 8
383 struct nouveau_pm_level {
384 struct device_attribute dev_attr;
385 char name[32];
386 int id;
387
388 u32 core;
389 u32 memory;
390 u32 shader;
391 u32 unk05;
392
393 u8 voltage;
394 u8 fanspeed;
395
396 u16 memscript;
397 };
398
399 struct nouveau_pm_temp_sensor_constants {
400 u16 offset_constant;
401 s16 offset_mult;
402 u16 offset_div;
403 u16 slope_mult;
404 u16 slope_div;
405 };
406
407 struct nouveau_pm_threshold_temp {
408 s16 critical;
409 s16 down_clock;
410 s16 fan_boost;
411 };
412
413 struct nouveau_pm_memtiming {
414 u32 reg_100220;
415 u32 reg_100224;
416 u32 reg_100228;
417 u32 reg_10022c;
418 u32 reg_100230;
419 u32 reg_100234;
420 u32 reg_100238;
421 u32 reg_10023c;
422 };
423
424 struct nouveau_pm_memtimings {
425 bool supported;
426 struct nouveau_pm_memtiming *timing;
427 int nr_timing;
428 };
429
430 struct nouveau_pm_engine {
431 struct nouveau_pm_voltage voltage;
432 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL];
433 int nr_perflvl;
434 struct nouveau_pm_memtimings memtimings;
435 struct nouveau_pm_temp_sensor_constants sensor_constants;
436 struct nouveau_pm_threshold_temp threshold_temp;
437
438 struct nouveau_pm_level boot;
439 struct nouveau_pm_level *cur;
440
441 struct device *hwmon;
442
443 int (*clock_get)(struct drm_device *, u32 id);
444 void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *,
445 u32 id, int khz);
446 void (*clock_set)(struct drm_device *, void *);
447 int (*voltage_get)(struct drm_device *);
448 int (*voltage_set)(struct drm_device *, int voltage);
449 int (*fanspeed_get)(struct drm_device *);
450 int (*fanspeed_set)(struct drm_device *, int fanspeed);
451 int (*temp_get)(struct drm_device *);
452 };
453
454 struct nouveau_engine {
455 struct nouveau_instmem_engine instmem;
456 struct nouveau_mc_engine mc;
457 struct nouveau_timer_engine timer;
458 struct nouveau_fb_engine fb;
459 struct nouveau_pgraph_engine graph;
460 struct nouveau_fifo_engine fifo;
461 struct nouveau_display_engine display;
462 struct nouveau_gpio_engine gpio;
463 struct nouveau_pm_engine pm;
464 };
465
466 struct nouveau_pll_vals {
467 union {
468 struct {
469 #ifdef __BIG_ENDIAN
470 uint8_t N1, M1, N2, M2;
471 #else
472 uint8_t M1, N1, M2, N2;
473 #endif
474 };
475 struct {
476 uint16_t NM1, NM2;
477 } __attribute__((packed));
478 };
479 int log2P;
480
481 int refclk;
482 };
483
484 enum nv04_fp_display_regs {
485 FP_DISPLAY_END,
486 FP_TOTAL,
487 FP_CRTC,
488 FP_SYNC_START,
489 FP_SYNC_END,
490 FP_VALID_START,
491 FP_VALID_END
492 };
493
494 struct nv04_crtc_reg {
495 unsigned char MiscOutReg;
496 uint8_t CRTC[0xa0];
497 uint8_t CR58[0x10];
498 uint8_t Sequencer[5];
499 uint8_t Graphics[9];
500 uint8_t Attribute[21];
501 unsigned char DAC[768];
502
503 /* PCRTC regs */
504 uint32_t fb_start;
505 uint32_t crtc_cfg;
506 uint32_t cursor_cfg;
507 uint32_t gpio_ext;
508 uint32_t crtc_830;
509 uint32_t crtc_834;
510 uint32_t crtc_850;
511 uint32_t crtc_eng_ctrl;
512
513 /* PRAMDAC regs */
514 uint32_t nv10_cursync;
515 struct nouveau_pll_vals pllvals;
516 uint32_t ramdac_gen_ctrl;
517 uint32_t ramdac_630;
518 uint32_t ramdac_634;
519 uint32_t tv_setup;
520 uint32_t tv_vtotal;
521 uint32_t tv_vskew;
522 uint32_t tv_vsync_delay;
523 uint32_t tv_htotal;
524 uint32_t tv_hskew;
525 uint32_t tv_hsync_delay;
526 uint32_t tv_hsync_delay2;
527 uint32_t fp_horiz_regs[7];
528 uint32_t fp_vert_regs[7];
529 uint32_t dither;
530 uint32_t fp_control;
531 uint32_t dither_regs[6];
532 uint32_t fp_debug_0;
533 uint32_t fp_debug_1;
534 uint32_t fp_debug_2;
535 uint32_t fp_margin_color;
536 uint32_t ramdac_8c0;
537 uint32_t ramdac_a20;
538 uint32_t ramdac_a24;
539 uint32_t ramdac_a34;
540 uint32_t ctv_regs[38];
541 };
542
543 struct nv04_output_reg {
544 uint32_t output;
545 int head;
546 };
547
548 struct nv04_mode_state {
549 struct nv04_crtc_reg crtc_reg[2];
550 uint32_t pllsel;
551 uint32_t sel_clk;
552 };
553
554 enum nouveau_card_type {
555 NV_04 = 0x00,
556 NV_10 = 0x10,
557 NV_20 = 0x20,
558 NV_30 = 0x30,
559 NV_40 = 0x40,
560 NV_50 = 0x50,
561 NV_C0 = 0xc0,
562 };
563
564 struct drm_nouveau_private {
565 struct drm_device *dev;
566
567 /* the card type, takes NV_* as values */
568 enum nouveau_card_type card_type;
569 /* exact chipset, derived from NV_PMC_BOOT_0 */
570 int chipset;
571 int flags;
572
573 void __iomem *mmio;
574
575 spinlock_t ramin_lock;
576 void __iomem *ramin;
577 u32 ramin_size;
578 u32 ramin_base;
579 bool ramin_available;
580 struct drm_mm ramin_heap;
581 struct list_head gpuobj_list;
582
583 struct nouveau_bo *vga_ram;
584
585 struct workqueue_struct *wq;
586 struct work_struct irq_work;
587 struct work_struct hpd_work;
588
589 struct {
590 spinlock_t lock;
591 uint32_t hpd0_bits;
592 uint32_t hpd1_bits;
593 } hpd_state;
594
595 struct list_head vbl_waiting;
596
597 struct {
598 struct drm_global_reference mem_global_ref;
599 struct ttm_bo_global_ref bo_global_ref;
600 struct ttm_bo_device bdev;
601 atomic_t validate_sequence;
602 } ttm;
603
604 struct {
605 spinlock_t lock;
606 struct drm_mm heap;
607 struct nouveau_bo *bo;
608 } fence;
609
610 struct {
611 spinlock_t lock;
612 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR];
613 } channels;
614
615 struct nouveau_engine engine;
616 struct nouveau_channel *channel;
617
618 /* For PFIFO and PGRAPH. */
619 spinlock_t context_switch_lock;
620
621 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
622 struct nouveau_ramht *ramht;
623 struct nouveau_gpuobj *ramfc;
624 struct nouveau_gpuobj *ramro;
625
626 uint32_t ramin_rsvd_vram;
627
628 struct {
629 enum {
630 NOUVEAU_GART_NONE = 0,
631 NOUVEAU_GART_AGP,
632 NOUVEAU_GART_SGDMA
633 } type;
634 uint64_t aper_base;
635 uint64_t aper_size;
636 uint64_t aper_free;
637
638 struct nouveau_gpuobj *sg_ctxdma;
639 struct page *sg_dummy_page;
640 dma_addr_t sg_dummy_bus;
641 } gart_info;
642
643 /* nv10-nv40 tiling regions */
644 struct nouveau_tile_reg tile[NOUVEAU_MAX_TILE_NR];
645
646 /* VRAM/fb configuration */
647 uint64_t vram_size;
648 uint64_t vram_sys_base;
649 u32 vram_rblock_size;
650
651 uint64_t fb_phys;
652 uint64_t fb_available_size;
653 uint64_t fb_mappable_pages;
654 uint64_t fb_aper_free;
655 int fb_mtrr;
656
657 /* G8x/G9x virtual address space */
658 uint64_t vm_gart_base;
659 uint64_t vm_gart_size;
660 uint64_t vm_vram_base;
661 uint64_t vm_vram_size;
662 uint64_t vm_end;
663 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR];
664 int vm_vram_pt_nr;
665
666 struct nvbios vbios;
667
668 struct nv04_mode_state mode_reg;
669 struct nv04_mode_state saved_reg;
670 uint32_t saved_vga_font[4][16384];
671 uint32_t crtc_owner;
672 uint32_t dac_users[4];
673
674 struct nouveau_suspend_resume {
675 uint32_t *ramin_copy;
676 } susres;
677
678 struct backlight_device *backlight;
679
680 struct nouveau_channel *evo;
681 struct {
682 struct dcb_entry *dcb;
683 u16 script;
684 u32 pclk;
685 } evo_irq;
686
687 struct {
688 struct dentry *channel_root;
689 } debugfs;
690
691 struct nouveau_fbdev *nfbdev;
692 struct apertures_struct *apertures;
693 };
694
695 static inline struct drm_nouveau_private *
696 nouveau_private(struct drm_device *dev)
697 {
698 return dev->dev_private;
699 }
700
701 static inline struct drm_nouveau_private *
702 nouveau_bdev(struct ttm_bo_device *bd)
703 {
704 return container_of(bd, struct drm_nouveau_private, ttm.bdev);
705 }
706
707 static inline int
708 nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo)
709 {
710 struct nouveau_bo *prev;
711
712 if (!pnvbo)
713 return -EINVAL;
714 prev = *pnvbo;
715
716 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL;
717 if (prev) {
718 struct ttm_buffer_object *bo = &prev->bo;
719
720 ttm_bo_unref(&bo);
721 }
722
723 return 0;
724 }
725
726 /* nouveau_drv.c */
727 extern int nouveau_agpmode;
728 extern int nouveau_duallink;
729 extern int nouveau_uscript_lvds;
730 extern int nouveau_uscript_tmds;
731 extern int nouveau_vram_pushbuf;
732 extern int nouveau_vram_notify;
733 extern int nouveau_fbpercrtc;
734 extern int nouveau_tv_disable;
735 extern char *nouveau_tv_norm;
736 extern int nouveau_reg_debug;
737 extern char *nouveau_vbios;
738 extern int nouveau_ignorelid;
739 extern int nouveau_nofbaccel;
740 extern int nouveau_noaccel;
741 extern int nouveau_force_post;
742 extern int nouveau_override_conntype;
743 extern char *nouveau_perflvl;
744 extern int nouveau_perflvl_wr;
745
746 extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state);
747 extern int nouveau_pci_resume(struct pci_dev *pdev);
748
749 /* nouveau_state.c */
750 extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
751 extern int nouveau_load(struct drm_device *, unsigned long flags);
752 extern int nouveau_firstopen(struct drm_device *);
753 extern void nouveau_lastclose(struct drm_device *);
754 extern int nouveau_unload(struct drm_device *);
755 extern int nouveau_ioctl_getparam(struct drm_device *, void *data,
756 struct drm_file *);
757 extern int nouveau_ioctl_setparam(struct drm_device *, void *data,
758 struct drm_file *);
759 extern bool nouveau_wait_until(struct drm_device *, uint64_t timeout,
760 uint32_t reg, uint32_t mask, uint32_t val);
761 extern bool nouveau_wait_for_idle(struct drm_device *);
762 extern int nouveau_card_init(struct drm_device *);
763
764 /* nouveau_mem.c */
765 extern int nouveau_mem_vram_init(struct drm_device *);
766 extern void nouveau_mem_vram_fini(struct drm_device *);
767 extern int nouveau_mem_gart_init(struct drm_device *);
768 extern void nouveau_mem_gart_fini(struct drm_device *);
769 extern int nouveau_mem_init_agp(struct drm_device *);
770 extern int nouveau_mem_reset_agp(struct drm_device *);
771 extern void nouveau_mem_close(struct drm_device *);
772 extern struct nouveau_tile_reg *nv10_mem_set_tiling(struct drm_device *dev,
773 uint32_t addr,
774 uint32_t size,
775 uint32_t pitch);
776 extern void nv10_mem_expire_tiling(struct drm_device *dev,
777 struct nouveau_tile_reg *tile,
778 struct nouveau_fence *fence);
779 extern int nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt,
780 uint32_t size, uint32_t flags,
781 uint64_t phys);
782 extern void nv50_mem_vm_unbind(struct drm_device *, uint64_t virt,
783 uint32_t size);
784
785 /* nouveau_notifier.c */
786 extern int nouveau_notifier_init_channel(struct nouveau_channel *);
787 extern void nouveau_notifier_takedown_channel(struct nouveau_channel *);
788 extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle,
789 int cout, uint32_t *offset);
790 extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *);
791 extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data,
792 struct drm_file *);
793 extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data,
794 struct drm_file *);
795
796 /* nouveau_channel.c */
797 extern struct drm_ioctl_desc nouveau_ioctls[];
798 extern int nouveau_max_ioctl;
799 extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *);
800 extern int nouveau_channel_alloc(struct drm_device *dev,
801 struct nouveau_channel **chan,
802 struct drm_file *file_priv,
803 uint32_t fb_ctxdma, uint32_t tt_ctxdma);
804 extern struct nouveau_channel *
805 nouveau_channel_get(struct drm_device *, struct drm_file *, int id);
806 extern void nouveau_channel_put(struct nouveau_channel **);
807
808 /* nouveau_object.c */
809 extern int nouveau_gpuobj_early_init(struct drm_device *);
810 extern int nouveau_gpuobj_init(struct drm_device *);
811 extern void nouveau_gpuobj_takedown(struct drm_device *);
812 extern int nouveau_gpuobj_suspend(struct drm_device *dev);
813 extern void nouveau_gpuobj_suspend_cleanup(struct drm_device *dev);
814 extern void nouveau_gpuobj_resume(struct drm_device *dev);
815 extern int nouveau_gpuobj_channel_init(struct nouveau_channel *,
816 uint32_t vram_h, uint32_t tt_h);
817 extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *);
818 extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *,
819 uint32_t size, int align, uint32_t flags,
820 struct nouveau_gpuobj **);
821 extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *,
822 struct nouveau_gpuobj **);
823 extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst,
824 u32 size, u32 flags,
825 struct nouveau_gpuobj **);
826 extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class,
827 uint64_t offset, uint64_t size, int access,
828 int target, struct nouveau_gpuobj **);
829 extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *,
830 uint64_t offset, uint64_t size,
831 int access, struct nouveau_gpuobj **,
832 uint32_t *o_ret);
833 extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class,
834 struct nouveau_gpuobj **);
835 extern int nouveau_gpuobj_sw_new(struct nouveau_channel *, int class,
836 struct nouveau_gpuobj **);
837 extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data,
838 struct drm_file *);
839 extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data,
840 struct drm_file *);
841
842 /* nouveau_irq.c */
843 extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
844 extern void nouveau_irq_preinstall(struct drm_device *);
845 extern int nouveau_irq_postinstall(struct drm_device *);
846 extern void nouveau_irq_uninstall(struct drm_device *);
847
848 /* nouveau_sgdma.c */
849 extern int nouveau_sgdma_init(struct drm_device *);
850 extern void nouveau_sgdma_takedown(struct drm_device *);
851 extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset,
852 uint32_t *page);
853 extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *);
854
855 /* nouveau_debugfs.c */
856 #if defined(CONFIG_DRM_NOUVEAU_DEBUG)
857 extern int nouveau_debugfs_init(struct drm_minor *);
858 extern void nouveau_debugfs_takedown(struct drm_minor *);
859 extern int nouveau_debugfs_channel_init(struct nouveau_channel *);
860 extern void nouveau_debugfs_channel_fini(struct nouveau_channel *);
861 #else
862 static inline int
863 nouveau_debugfs_init(struct drm_minor *minor)
864 {
865 return 0;
866 }
867
868 static inline void nouveau_debugfs_takedown(struct drm_minor *minor)
869 {
870 }
871
872 static inline int
873 nouveau_debugfs_channel_init(struct nouveau_channel *chan)
874 {
875 return 0;
876 }
877
878 static inline void
879 nouveau_debugfs_channel_fini(struct nouveau_channel *chan)
880 {
881 }
882 #endif
883
884 /* nouveau_dma.c */
885 extern void nouveau_dma_pre_init(struct nouveau_channel *);
886 extern int nouveau_dma_init(struct nouveau_channel *);
887 extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size);
888
889 /* nouveau_acpi.c */
890 #define ROM_BIOS_PAGE 4096
891 #if defined(CONFIG_ACPI)
892 void nouveau_register_dsm_handler(void);
893 void nouveau_unregister_dsm_handler(void);
894 int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len);
895 bool nouveau_acpi_rom_supported(struct pci_dev *pdev);
896 int nouveau_acpi_edid(struct drm_device *, struct drm_connector *);
897 #else
898 static inline void nouveau_register_dsm_handler(void) {}
899 static inline void nouveau_unregister_dsm_handler(void) {}
900 static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; }
901 static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; }
902 static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; }
903 #endif
904
905 /* nouveau_backlight.c */
906 #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
907 extern int nouveau_backlight_init(struct drm_device *);
908 extern void nouveau_backlight_exit(struct drm_device *);
909 #else
910 static inline int nouveau_backlight_init(struct drm_device *dev)
911 {
912 return 0;
913 }
914
915 static inline void nouveau_backlight_exit(struct drm_device *dev) { }
916 #endif
917
918 /* nouveau_bios.c */
919 extern int nouveau_bios_init(struct drm_device *);
920 extern void nouveau_bios_takedown(struct drm_device *dev);
921 extern int nouveau_run_vbios_init(struct drm_device *);
922 extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table,
923 struct dcb_entry *);
924 extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *,
925 enum dcb_gpio_tag);
926 extern struct dcb_connector_table_entry *
927 nouveau_bios_connector_entry(struct drm_device *, int index);
928 extern u32 get_pll_register(struct drm_device *, enum pll_types);
929 extern int get_pll_limits(struct drm_device *, uint32_t limit_match,
930 struct pll_lims *);
931 extern int nouveau_bios_run_display_table(struct drm_device *,
932 struct dcb_entry *,
933 uint32_t script, int pxclk);
934 extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *,
935 int *length);
936 extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *);
937 extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *);
938 extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk,
939 bool *dl, bool *if_is_24bit);
940 extern int run_tmds_table(struct drm_device *, struct dcb_entry *,
941 int head, int pxclk);
942 extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head,
943 enum LVDS_script, int pxclk);
944
945 /* nouveau_ttm.c */
946 int nouveau_ttm_global_init(struct drm_nouveau_private *);
947 void nouveau_ttm_global_release(struct drm_nouveau_private *);
948 int nouveau_ttm_mmap(struct file *, struct vm_area_struct *);
949
950 /* nouveau_dp.c */
951 int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
952 uint8_t *data, int data_nr);
953 bool nouveau_dp_detect(struct drm_encoder *);
954 bool nouveau_dp_link_train(struct drm_encoder *);
955
956 /* nv04_fb.c */
957 extern int nv04_fb_init(struct drm_device *);
958 extern void nv04_fb_takedown(struct drm_device *);
959
960 /* nv10_fb.c */
961 extern int nv10_fb_init(struct drm_device *);
962 extern void nv10_fb_takedown(struct drm_device *);
963 extern void nv10_fb_set_region_tiling(struct drm_device *, int, uint32_t,
964 uint32_t, uint32_t);
965
966 /* nv30_fb.c */
967 extern int nv30_fb_init(struct drm_device *);
968 extern void nv30_fb_takedown(struct drm_device *);
969
970 /* nv40_fb.c */
971 extern int nv40_fb_init(struct drm_device *);
972 extern void nv40_fb_takedown(struct drm_device *);
973 extern void nv40_fb_set_region_tiling(struct drm_device *, int, uint32_t,
974 uint32_t, uint32_t);
975 /* nv50_fb.c */
976 extern int nv50_fb_init(struct drm_device *);
977 extern void nv50_fb_takedown(struct drm_device *);
978 extern void nv50_fb_vm_trap(struct drm_device *, int display, const char *);
979
980 /* nvc0_fb.c */
981 extern int nvc0_fb_init(struct drm_device *);
982 extern void nvc0_fb_takedown(struct drm_device *);
983
984 /* nv04_fifo.c */
985 extern int nv04_fifo_init(struct drm_device *);
986 extern void nv04_fifo_disable(struct drm_device *);
987 extern void nv04_fifo_enable(struct drm_device *);
988 extern bool nv04_fifo_reassign(struct drm_device *, bool);
989 extern bool nv04_fifo_cache_pull(struct drm_device *, bool);
990 extern int nv04_fifo_channel_id(struct drm_device *);
991 extern int nv04_fifo_create_context(struct nouveau_channel *);
992 extern void nv04_fifo_destroy_context(struct nouveau_channel *);
993 extern int nv04_fifo_load_context(struct nouveau_channel *);
994 extern int nv04_fifo_unload_context(struct drm_device *);
995
996 /* nv10_fifo.c */
997 extern int nv10_fifo_init(struct drm_device *);
998 extern int nv10_fifo_channel_id(struct drm_device *);
999 extern int nv10_fifo_create_context(struct nouveau_channel *);
1000 extern void nv10_fifo_destroy_context(struct nouveau_channel *);
1001 extern int nv10_fifo_load_context(struct nouveau_channel *);
1002 extern int nv10_fifo_unload_context(struct drm_device *);
1003
1004 /* nv40_fifo.c */
1005 extern int nv40_fifo_init(struct drm_device *);
1006 extern int nv40_fifo_create_context(struct nouveau_channel *);
1007 extern void nv40_fifo_destroy_context(struct nouveau_channel *);
1008 extern int nv40_fifo_load_context(struct nouveau_channel *);
1009 extern int nv40_fifo_unload_context(struct drm_device *);
1010
1011 /* nv50_fifo.c */
1012 extern int nv50_fifo_init(struct drm_device *);
1013 extern void nv50_fifo_takedown(struct drm_device *);
1014 extern int nv50_fifo_channel_id(struct drm_device *);
1015 extern int nv50_fifo_create_context(struct nouveau_channel *);
1016 extern void nv50_fifo_destroy_context(struct nouveau_channel *);
1017 extern int nv50_fifo_load_context(struct nouveau_channel *);
1018 extern int nv50_fifo_unload_context(struct drm_device *);
1019 extern void nv50_fifo_tlb_flush(struct drm_device *dev);
1020
1021 /* nvc0_fifo.c */
1022 extern int nvc0_fifo_init(struct drm_device *);
1023 extern void nvc0_fifo_takedown(struct drm_device *);
1024 extern void nvc0_fifo_disable(struct drm_device *);
1025 extern void nvc0_fifo_enable(struct drm_device *);
1026 extern bool nvc0_fifo_reassign(struct drm_device *, bool);
1027 extern bool nvc0_fifo_cache_pull(struct drm_device *, bool);
1028 extern int nvc0_fifo_channel_id(struct drm_device *);
1029 extern int nvc0_fifo_create_context(struct nouveau_channel *);
1030 extern void nvc0_fifo_destroy_context(struct nouveau_channel *);
1031 extern int nvc0_fifo_load_context(struct nouveau_channel *);
1032 extern int nvc0_fifo_unload_context(struct drm_device *);
1033
1034 /* nv04_graph.c */
1035 extern struct nouveau_pgraph_object_class nv04_graph_grclass[];
1036 extern int nv04_graph_init(struct drm_device *);
1037 extern void nv04_graph_takedown(struct drm_device *);
1038 extern void nv04_graph_fifo_access(struct drm_device *, bool);
1039 extern struct nouveau_channel *nv04_graph_channel(struct drm_device *);
1040 extern int nv04_graph_create_context(struct nouveau_channel *);
1041 extern void nv04_graph_destroy_context(struct nouveau_channel *);
1042 extern int nv04_graph_load_context(struct nouveau_channel *);
1043 extern int nv04_graph_unload_context(struct drm_device *);
1044 extern void nv04_graph_context_switch(struct drm_device *);
1045
1046 /* nv10_graph.c */
1047 extern struct nouveau_pgraph_object_class nv10_graph_grclass[];
1048 extern int nv10_graph_init(struct drm_device *);
1049 extern void nv10_graph_takedown(struct drm_device *);
1050 extern struct nouveau_channel *nv10_graph_channel(struct drm_device *);
1051 extern int nv10_graph_create_context(struct nouveau_channel *);
1052 extern void nv10_graph_destroy_context(struct nouveau_channel *);
1053 extern int nv10_graph_load_context(struct nouveau_channel *);
1054 extern int nv10_graph_unload_context(struct drm_device *);
1055 extern void nv10_graph_context_switch(struct drm_device *);
1056 extern void nv10_graph_set_region_tiling(struct drm_device *, int, uint32_t,
1057 uint32_t, uint32_t);
1058
1059 /* nv20_graph.c */
1060 extern struct nouveau_pgraph_object_class nv20_graph_grclass[];
1061 extern struct nouveau_pgraph_object_class nv30_graph_grclass[];
1062 extern int nv20_graph_create_context(struct nouveau_channel *);
1063 extern void nv20_graph_destroy_context(struct nouveau_channel *);
1064 extern int nv20_graph_load_context(struct nouveau_channel *);
1065 extern int nv20_graph_unload_context(struct drm_device *);
1066 extern int nv20_graph_init(struct drm_device *);
1067 extern void nv20_graph_takedown(struct drm_device *);
1068 extern int nv30_graph_init(struct drm_device *);
1069 extern void nv20_graph_set_region_tiling(struct drm_device *, int, uint32_t,
1070 uint32_t, uint32_t);
1071
1072 /* nv40_graph.c */
1073 extern struct nouveau_pgraph_object_class nv40_graph_grclass[];
1074 extern int nv40_graph_init(struct drm_device *);
1075 extern void nv40_graph_takedown(struct drm_device *);
1076 extern struct nouveau_channel *nv40_graph_channel(struct drm_device *);
1077 extern int nv40_graph_create_context(struct nouveau_channel *);
1078 extern void nv40_graph_destroy_context(struct nouveau_channel *);
1079 extern int nv40_graph_load_context(struct nouveau_channel *);
1080 extern int nv40_graph_unload_context(struct drm_device *);
1081 extern void nv40_grctx_init(struct nouveau_grctx *);
1082 extern void nv40_graph_set_region_tiling(struct drm_device *, int, uint32_t,
1083 uint32_t, uint32_t);
1084
1085 /* nv50_graph.c */
1086 extern struct nouveau_pgraph_object_class nv50_graph_grclass[];
1087 extern int nv50_graph_init(struct drm_device *);
1088 extern void nv50_graph_takedown(struct drm_device *);
1089 extern void nv50_graph_fifo_access(struct drm_device *, bool);
1090 extern struct nouveau_channel *nv50_graph_channel(struct drm_device *);
1091 extern int nv50_graph_create_context(struct nouveau_channel *);
1092 extern void nv50_graph_destroy_context(struct nouveau_channel *);
1093 extern int nv50_graph_load_context(struct nouveau_channel *);
1094 extern int nv50_graph_unload_context(struct drm_device *);
1095 extern void nv50_graph_context_switch(struct drm_device *);
1096 extern int nv50_grctx_init(struct nouveau_grctx *);
1097 extern void nv50_graph_tlb_flush(struct drm_device *dev);
1098 extern void nv86_graph_tlb_flush(struct drm_device *dev);
1099
1100 /* nvc0_graph.c */
1101 extern int nvc0_graph_init(struct drm_device *);
1102 extern void nvc0_graph_takedown(struct drm_device *);
1103 extern void nvc0_graph_fifo_access(struct drm_device *, bool);
1104 extern struct nouveau_channel *nvc0_graph_channel(struct drm_device *);
1105 extern int nvc0_graph_create_context(struct nouveau_channel *);
1106 extern void nvc0_graph_destroy_context(struct nouveau_channel *);
1107 extern int nvc0_graph_load_context(struct nouveau_channel *);
1108 extern int nvc0_graph_unload_context(struct drm_device *);
1109
1110 /* nv04_instmem.c */
1111 extern int nv04_instmem_init(struct drm_device *);
1112 extern void nv04_instmem_takedown(struct drm_device *);
1113 extern int nv04_instmem_suspend(struct drm_device *);
1114 extern void nv04_instmem_resume(struct drm_device *);
1115 extern int nv04_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1116 uint32_t *size);
1117 extern void nv04_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1118 extern int nv04_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1119 extern int nv04_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1120 extern void nv04_instmem_flush(struct drm_device *);
1121
1122 /* nv50_instmem.c */
1123 extern int nv50_instmem_init(struct drm_device *);
1124 extern void nv50_instmem_takedown(struct drm_device *);
1125 extern int nv50_instmem_suspend(struct drm_device *);
1126 extern void nv50_instmem_resume(struct drm_device *);
1127 extern int nv50_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1128 uint32_t *size);
1129 extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1130 extern int nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1131 extern int nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1132 extern void nv50_instmem_flush(struct drm_device *);
1133 extern void nv84_instmem_flush(struct drm_device *);
1134 extern void nv50_vm_flush(struct drm_device *, int engine);
1135
1136 /* nvc0_instmem.c */
1137 extern int nvc0_instmem_init(struct drm_device *);
1138 extern void nvc0_instmem_takedown(struct drm_device *);
1139 extern int nvc0_instmem_suspend(struct drm_device *);
1140 extern void nvc0_instmem_resume(struct drm_device *);
1141 extern int nvc0_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1142 uint32_t *size);
1143 extern void nvc0_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1144 extern int nvc0_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1145 extern int nvc0_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1146 extern void nvc0_instmem_flush(struct drm_device *);
1147
1148 /* nv04_mc.c */
1149 extern int nv04_mc_init(struct drm_device *);
1150 extern void nv04_mc_takedown(struct drm_device *);
1151
1152 /* nv40_mc.c */
1153 extern int nv40_mc_init(struct drm_device *);
1154 extern void nv40_mc_takedown(struct drm_device *);
1155
1156 /* nv50_mc.c */
1157 extern int nv50_mc_init(struct drm_device *);
1158 extern void nv50_mc_takedown(struct drm_device *);
1159
1160 /* nv04_timer.c */
1161 extern int nv04_timer_init(struct drm_device *);
1162 extern uint64_t nv04_timer_read(struct drm_device *);
1163 extern void nv04_timer_takedown(struct drm_device *);
1164
1165 extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd,
1166 unsigned long arg);
1167
1168 /* nv04_dac.c */
1169 extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *);
1170 extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder);
1171 extern int nv04_dac_output_offset(struct drm_encoder *encoder);
1172 extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable);
1173 extern bool nv04_dac_in_use(struct drm_encoder *encoder);
1174
1175 /* nv04_dfp.c */
1176 extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *);
1177 extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent);
1178 extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent,
1179 int head, bool dl);
1180 extern void nv04_dfp_disable(struct drm_device *dev, int head);
1181 extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode);
1182
1183 /* nv04_tv.c */
1184 extern int nv04_tv_identify(struct drm_device *dev, int i2c_index);
1185 extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *);
1186
1187 /* nv17_tv.c */
1188 extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *);
1189
1190 /* nv04_display.c */
1191 extern int nv04_display_early_init(struct drm_device *);
1192 extern void nv04_display_late_takedown(struct drm_device *);
1193 extern int nv04_display_create(struct drm_device *);
1194 extern int nv04_display_init(struct drm_device *);
1195 extern void nv04_display_destroy(struct drm_device *);
1196
1197 /* nv04_crtc.c */
1198 extern int nv04_crtc_create(struct drm_device *, int index);
1199
1200 /* nouveau_bo.c */
1201 extern struct ttm_bo_driver nouveau_bo_driver;
1202 extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *,
1203 int size, int align, uint32_t flags,
1204 uint32_t tile_mode, uint32_t tile_flags,
1205 bool no_vm, bool mappable, struct nouveau_bo **);
1206 extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags);
1207 extern int nouveau_bo_unpin(struct nouveau_bo *);
1208 extern int nouveau_bo_map(struct nouveau_bo *);
1209 extern void nouveau_bo_unmap(struct nouveau_bo *);
1210 extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type,
1211 uint32_t busy);
1212 extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index);
1213 extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val);
1214 extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index);
1215 extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val);
1216
1217 /* nouveau_fence.c */
1218 struct nouveau_fence;
1219 extern int nouveau_fence_init(struct drm_device *);
1220 extern void nouveau_fence_fini(struct drm_device *);
1221 extern int nouveau_fence_channel_init(struct nouveau_channel *);
1222 extern void nouveau_fence_channel_fini(struct nouveau_channel *);
1223 extern void nouveau_fence_update(struct nouveau_channel *);
1224 extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **,
1225 bool emit);
1226 extern int nouveau_fence_emit(struct nouveau_fence *);
1227 extern void nouveau_fence_work(struct nouveau_fence *fence,
1228 void (*work)(void *priv, bool signalled),
1229 void *priv);
1230 struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *);
1231 extern bool nouveau_fence_signalled(void *obj, void *arg);
1232 extern int nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr);
1233 extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *);
1234 extern int nouveau_fence_flush(void *obj, void *arg);
1235 extern void nouveau_fence_unref(void **obj);
1236 extern void *nouveau_fence_ref(void *obj);
1237
1238 /* nouveau_gem.c */
1239 extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *,
1240 int size, int align, uint32_t flags,
1241 uint32_t tile_mode, uint32_t tile_flags,
1242 bool no_vm, bool mappable, struct nouveau_bo **);
1243 extern int nouveau_gem_object_new(struct drm_gem_object *);
1244 extern void nouveau_gem_object_del(struct drm_gem_object *);
1245 extern int nouveau_gem_ioctl_new(struct drm_device *, void *,
1246 struct drm_file *);
1247 extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *,
1248 struct drm_file *);
1249 extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *,
1250 struct drm_file *);
1251 extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *,
1252 struct drm_file *);
1253 extern int nouveau_gem_ioctl_info(struct drm_device *, void *,
1254 struct drm_file *);
1255
1256 /* nv10_gpio.c */
1257 int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1258 int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
1259
1260 /* nv50_gpio.c */
1261 int nv50_gpio_init(struct drm_device *dev);
1262 int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1263 int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
1264 void nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on);
1265
1266 /* nv50_calc. */
1267 int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk,
1268 int *N1, int *M1, int *N2, int *M2, int *P);
1269 int nv50_calc_pll2(struct drm_device *, struct pll_lims *,
1270 int clk, int *N, int *fN, int *M, int *P);
1271
1272 #ifndef ioread32_native
1273 #ifdef __BIG_ENDIAN
1274 #define ioread16_native ioread16be
1275 #define iowrite16_native iowrite16be
1276 #define ioread32_native ioread32be
1277 #define iowrite32_native iowrite32be
1278 #else /* def __BIG_ENDIAN */
1279 #define ioread16_native ioread16
1280 #define iowrite16_native iowrite16
1281 #define ioread32_native ioread32
1282 #define iowrite32_native iowrite32
1283 #endif /* def __BIG_ENDIAN else */
1284 #endif /* !ioread32_native */
1285
1286 /* channel control reg access */
1287 static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg)
1288 {
1289 return ioread32_native(chan->user + reg);
1290 }
1291
1292 static inline void nvchan_wr32(struct nouveau_channel *chan,
1293 unsigned reg, u32 val)
1294 {
1295 iowrite32_native(val, chan->user + reg);
1296 }
1297
1298 /* register access */
1299 static inline u32 nv_rd32(struct drm_device *dev, unsigned reg)
1300 {
1301 struct drm_nouveau_private *dev_priv = dev->dev_private;
1302 return ioread32_native(dev_priv->mmio + reg);
1303 }
1304
1305 static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val)
1306 {
1307 struct drm_nouveau_private *dev_priv = dev->dev_private;
1308 iowrite32_native(val, dev_priv->mmio + reg);
1309 }
1310
1311 static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val)
1312 {
1313 u32 tmp = nv_rd32(dev, reg);
1314 nv_wr32(dev, reg, (tmp & ~mask) | val);
1315 return tmp;
1316 }
1317
1318 static inline u8 nv_rd08(struct drm_device *dev, unsigned reg)
1319 {
1320 struct drm_nouveau_private *dev_priv = dev->dev_private;
1321 return ioread8(dev_priv->mmio + reg);
1322 }
1323
1324 static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val)
1325 {
1326 struct drm_nouveau_private *dev_priv = dev->dev_private;
1327 iowrite8(val, dev_priv->mmio + reg);
1328 }
1329
1330 #define nv_wait(dev, reg, mask, val) \
1331 nouveau_wait_until(dev, 2000000000ULL, (reg), (mask), (val))
1332
1333 /* PRAMIN access */
1334 static inline u32 nv_ri32(struct drm_device *dev, unsigned offset)
1335 {
1336 struct drm_nouveau_private *dev_priv = dev->dev_private;
1337 return ioread32_native(dev_priv->ramin + offset);
1338 }
1339
1340 static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val)
1341 {
1342 struct drm_nouveau_private *dev_priv = dev->dev_private;
1343 iowrite32_native(val, dev_priv->ramin + offset);
1344 }
1345
1346 /* object access */
1347 extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset);
1348 extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val);
1349
1350 /*
1351 * Logging
1352 * Argument d is (struct drm_device *).
1353 */
1354 #define NV_PRINTK(level, d, fmt, arg...) \
1355 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \
1356 pci_name(d->pdev), ##arg)
1357 #ifndef NV_DEBUG_NOTRACE
1358 #define NV_DEBUG(d, fmt, arg...) do { \
1359 if (drm_debug & DRM_UT_DRIVER) { \
1360 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1361 __LINE__, ##arg); \
1362 } \
1363 } while (0)
1364 #define NV_DEBUG_KMS(d, fmt, arg...) do { \
1365 if (drm_debug & DRM_UT_KMS) { \
1366 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1367 __LINE__, ##arg); \
1368 } \
1369 } while (0)
1370 #else
1371 #define NV_DEBUG(d, fmt, arg...) do { \
1372 if (drm_debug & DRM_UT_DRIVER) \
1373 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1374 } while (0)
1375 #define NV_DEBUG_KMS(d, fmt, arg...) do { \
1376 if (drm_debug & DRM_UT_KMS) \
1377 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1378 } while (0)
1379 #endif
1380 #define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg)
1381 #define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1382 #define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg)
1383 #define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1384 #define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg)
1385
1386 /* nouveau_reg_debug bitmask */
1387 enum {
1388 NOUVEAU_REG_DEBUG_MC = 0x1,
1389 NOUVEAU_REG_DEBUG_VIDEO = 0x2,
1390 NOUVEAU_REG_DEBUG_FB = 0x4,
1391 NOUVEAU_REG_DEBUG_EXTDEV = 0x8,
1392 NOUVEAU_REG_DEBUG_CRTC = 0x10,
1393 NOUVEAU_REG_DEBUG_RAMDAC = 0x20,
1394 NOUVEAU_REG_DEBUG_VGACRTC = 0x40,
1395 NOUVEAU_REG_DEBUG_RMVIO = 0x80,
1396 NOUVEAU_REG_DEBUG_VGAATTR = 0x100,
1397 NOUVEAU_REG_DEBUG_EVO = 0x200,
1398 };
1399
1400 #define NV_REG_DEBUG(type, dev, fmt, arg...) do { \
1401 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \
1402 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \
1403 } while (0)
1404
1405 static inline bool
1406 nv_two_heads(struct drm_device *dev)
1407 {
1408 struct drm_nouveau_private *dev_priv = dev->dev_private;
1409 const int impl = dev->pci_device & 0x0ff0;
1410
1411 if (dev_priv->card_type >= NV_10 && impl != 0x0100 &&
1412 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
1413 return true;
1414
1415 return false;
1416 }
1417
1418 static inline bool
1419 nv_gf4_disp_arch(struct drm_device *dev)
1420 {
1421 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110;
1422 }
1423
1424 static inline bool
1425 nv_two_reg_pll(struct drm_device *dev)
1426 {
1427 struct drm_nouveau_private *dev_priv = dev->dev_private;
1428 const int impl = dev->pci_device & 0x0ff0;
1429
1430 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40)
1431 return true;
1432 return false;
1433 }
1434
1435 static inline bool
1436 nv_match_device(struct drm_device *dev, unsigned device,
1437 unsigned sub_vendor, unsigned sub_device)
1438 {
1439 return dev->pdev->device == device &&
1440 dev->pdev->subsystem_vendor == sub_vendor &&
1441 dev->pdev->subsystem_device == sub_device;
1442 }
1443
1444 #define NV_SW 0x0000506e
1445 #define NV_SW_DMA_SEMAPHORE 0x00000060
1446 #define NV_SW_SEMAPHORE_OFFSET 0x00000064
1447 #define NV_SW_SEMAPHORE_ACQUIRE 0x00000068
1448 #define NV_SW_SEMAPHORE_RELEASE 0x0000006c
1449 #define NV_SW_YIELD 0x00000080
1450 #define NV_SW_DMA_VBLSEM 0x0000018c
1451 #define NV_SW_VBLSEM_OFFSET 0x00000400
1452 #define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404
1453 #define NV_SW_VBLSEM_RELEASE 0x00000408
1454
1455 #endif /* __NOUVEAU_DRV_H__ */
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree