2 * Defines, structures, APIs for edac_core module
4 * (C) 2007 Linux Networx (http://lnxi.com)
5 * This file may be distributed under the terms of the
6 * GNU General Public License.
8 * Written by Thayne Harbaugh
9 * Based on work by Dan Hollis <goemon at anime dot net> and others.
10 * http://www.anime.net/~goemon/linux-ecc/
12 * NMI handling support added by
13 * Dave Peterson <dsp@llnl.gov> <dave_peterson@pobox.com>
15 * Refactored for multi-source files:
16 * Doug Thompson <norsk5@xmission.com>
23 #include <linux/kernel.h>
24 #include <linux/types.h>
25 #include <linux/module.h>
26 #include <linux/spinlock.h>
27 #include <linux/smp.h>
28 #include <linux/pci.h>
29 #include <linux/time.h>
30 #include <linux/nmi.h>
31 #include <linux/rcupdate.h>
32 #include <linux/completion.h>
33 #include <linux/kobject.h>
34 #include <linux/platform_device.h>
35 #include <linux/sysdev.h>
36 #include <linux/workqueue.h>
38 #define EDAC_MC_LABEL_LEN 31
39 #define EDAC_DEVICE_NAME_LEN 31
40 #define EDAC_ATTRIB_VALUE_LEN 15
41 #define MC_PROC_NAME_MAX_LEN 7
44 #define PAGES_TO_MiB( pages ) ( ( pages ) >> ( 20 - PAGE_SHIFT ) )
45 #define MiB_TO_PAGES(mb) ((mb) >> (20 - PAGE_SHIFT))
46 #else /* PAGE_SHIFT > 20 */
47 #define PAGES_TO_MiB( pages ) ( ( pages ) << ( PAGE_SHIFT - 20 ) )
48 #define MiB_TO_PAGES(mb) ((mb) >> (PAGE_SHIFT - 20))
51 #define edac_printk(level, prefix, fmt, arg...) \
52 printk(level "EDAC " prefix ": " fmt, ##arg)
54 #define edac_mc_printk(mci, level, fmt, arg...) \
55 printk(level "EDAC MC%d: " fmt, mci->mc_idx, ##arg)
57 #define edac_mc_chipset_printk(mci, level, prefix, fmt, arg...) \
58 printk(level "EDAC " prefix " MC%d: " fmt, mci->mc_idx, ##arg)
60 #define edac_device_printk(ctl, level, fmt, arg...) \
61 printk(level "EDAC DEVICE%d: " fmt, ctl->dev_idx, ##arg)
63 #define edac_pci_printk(ctl, level, fmt, arg...) \
64 printk(level "EDAC PCI%d: " fmt, ctl->pci_idx, ##arg)
66 /* prefixes for edac_printk() and edac_mc_printk() */
68 #define EDAC_PCI "PCI"
69 #define EDAC_DEBUG "DEBUG"
71 #ifdef CONFIG_EDAC_DEBUG
72 extern int edac_debug_level
;
73 extern const char *edac_mem_types
[];
75 #define edac_debug_printk(level, fmt, arg...) \
77 if (level <= edac_debug_level) \
78 edac_printk(KERN_DEBUG, EDAC_DEBUG, \
79 "%s: " fmt, __func__, ##arg); \
82 #define debugf0( ... ) edac_debug_printk(0, __VA_ARGS__ )
83 #define debugf1( ... ) edac_debug_printk(1, __VA_ARGS__ )
84 #define debugf2( ... ) edac_debug_printk(2, __VA_ARGS__ )
85 #define debugf3( ... ) edac_debug_printk(3, __VA_ARGS__ )
86 #define debugf4( ... ) edac_debug_printk(4, __VA_ARGS__ )
88 #else /* !CONFIG_EDAC_DEBUG */
90 #define debugf0( ... )
91 #define debugf1( ... )
92 #define debugf2( ... )
93 #define debugf3( ... )
94 #define debugf4( ... )
96 #endif /* !CONFIG_EDAC_DEBUG */
98 #define PCI_VEND_DEV(vend, dev) PCI_VENDOR_ID_ ## vend, \
99 PCI_DEVICE_ID_ ## vend ## _ ## dev
101 #define edac_dev_name(dev) (dev)->dev_name
111 DEV_X32
, /* Do these parts exist? */
112 DEV_X64
/* Do these parts exist? */
115 #define DEV_FLAG_UNKNOWN BIT(DEV_UNKNOWN)
116 #define DEV_FLAG_X1 BIT(DEV_X1)
117 #define DEV_FLAG_X2 BIT(DEV_X2)
118 #define DEV_FLAG_X4 BIT(DEV_X4)
119 #define DEV_FLAG_X8 BIT(DEV_X8)
120 #define DEV_FLAG_X16 BIT(DEV_X16)
121 #define DEV_FLAG_X32 BIT(DEV_X32)
122 #define DEV_FLAG_X64 BIT(DEV_X64)
126 MEM_EMPTY
= 0, /* Empty csrow */
127 MEM_RESERVED
, /* Reserved csrow type */
128 MEM_UNKNOWN
, /* Unknown csrow type */
129 MEM_FPM
, /* Fast page mode */
130 MEM_EDO
, /* Extended data out */
131 MEM_BEDO
, /* Burst Extended data out */
132 MEM_SDR
, /* Single data rate SDRAM */
133 MEM_RDR
, /* Registered single data rate SDRAM */
134 MEM_DDR
, /* Double data rate SDRAM */
135 MEM_RDDR
, /* Registered Double data rate SDRAM */
136 MEM_RMBS
, /* Rambus DRAM */
137 MEM_DDR2
, /* DDR2 RAM */
138 MEM_FB_DDR2
, /* fully buffered DDR2 */
139 MEM_RDDR2
, /* Registered DDR2 RAM */
140 MEM_XDR
, /* Rambus XDR */
141 MEM_DDR3
, /* DDR3 RAM */
142 MEM_RDDR3
, /* Registered DDR3 RAM */
145 #define MEM_FLAG_EMPTY BIT(MEM_EMPTY)
146 #define MEM_FLAG_RESERVED BIT(MEM_RESERVED)
147 #define MEM_FLAG_UNKNOWN BIT(MEM_UNKNOWN)
148 #define MEM_FLAG_FPM BIT(MEM_FPM)
149 #define MEM_FLAG_EDO BIT(MEM_EDO)
150 #define MEM_FLAG_BEDO BIT(MEM_BEDO)
151 #define MEM_FLAG_SDR BIT(MEM_SDR)
152 #define MEM_FLAG_RDR BIT(MEM_RDR)
153 #define MEM_FLAG_DDR BIT(MEM_DDR)
154 #define MEM_FLAG_RDDR BIT(MEM_RDDR)
155 #define MEM_FLAG_RMBS BIT(MEM_RMBS)
156 #define MEM_FLAG_DDR2 BIT(MEM_DDR2)
157 #define MEM_FLAG_FB_DDR2 BIT(MEM_FB_DDR2)
158 #define MEM_FLAG_RDDR2 BIT(MEM_RDDR2)
159 #define MEM_FLAG_XDR BIT(MEM_XDR)
160 #define MEM_FLAG_DDR3 BIT(MEM_DDR3)
161 #define MEM_FLAG_RDDR3 BIT(MEM_RDDR3)
163 /* chipset Error Detection and Correction capabilities and mode */
165 EDAC_UNKNOWN
= 0, /* Unknown if ECC is available */
166 EDAC_NONE
, /* Doesnt support ECC */
167 EDAC_RESERVED
, /* Reserved ECC type */
168 EDAC_PARITY
, /* Detects parity errors */
169 EDAC_EC
, /* Error Checking - no correction */
170 EDAC_SECDED
, /* Single bit error correction, Double detection */
171 EDAC_S2ECD2ED
, /* Chipkill x2 devices - do these exist? */
172 EDAC_S4ECD4ED
, /* Chipkill x4 devices */
173 EDAC_S8ECD8ED
, /* Chipkill x8 devices */
174 EDAC_S16ECD16ED
, /* Chipkill x16 devices */
177 #define EDAC_FLAG_UNKNOWN BIT(EDAC_UNKNOWN)
178 #define EDAC_FLAG_NONE BIT(EDAC_NONE)
179 #define EDAC_FLAG_PARITY BIT(EDAC_PARITY)
180 #define EDAC_FLAG_EC BIT(EDAC_EC)
181 #define EDAC_FLAG_SECDED BIT(EDAC_SECDED)
182 #define EDAC_FLAG_S2ECD2ED BIT(EDAC_S2ECD2ED)
183 #define EDAC_FLAG_S4ECD4ED BIT(EDAC_S4ECD4ED)
184 #define EDAC_FLAG_S8ECD8ED BIT(EDAC_S8ECD8ED)
185 #define EDAC_FLAG_S16ECD16ED BIT(EDAC_S16ECD16ED)
187 /* scrubbing capabilities */
189 SCRUB_UNKNOWN
= 0, /* Unknown if scrubber is available */
190 SCRUB_NONE
, /* No scrubber */
191 SCRUB_SW_PROG
, /* SW progressive (sequential) scrubbing */
192 SCRUB_SW_SRC
, /* Software scrub only errors */
193 SCRUB_SW_PROG_SRC
, /* Progressive software scrub from an error */
194 SCRUB_SW_TUNABLE
, /* Software scrub frequency is tunable */
195 SCRUB_HW_PROG
, /* HW progressive (sequential) scrubbing */
196 SCRUB_HW_SRC
, /* Hardware scrub only errors */
197 SCRUB_HW_PROG_SRC
, /* Progressive hardware scrub from an error */
198 SCRUB_HW_TUNABLE
/* Hardware scrub frequency is tunable */
201 #define SCRUB_FLAG_SW_PROG BIT(SCRUB_SW_PROG)
202 #define SCRUB_FLAG_SW_SRC BIT(SCRUB_SW_SRC)
203 #define SCRUB_FLAG_SW_PROG_SRC BIT(SCRUB_SW_PROG_SRC)
204 #define SCRUB_FLAG_SW_TUN BIT(SCRUB_SW_SCRUB_TUNABLE)
205 #define SCRUB_FLAG_HW_PROG BIT(SCRUB_HW_PROG)
206 #define SCRUB_FLAG_HW_SRC BIT(SCRUB_HW_SRC)
207 #define SCRUB_FLAG_HW_PROG_SRC BIT(SCRUB_HW_PROG_SRC)
208 #define SCRUB_FLAG_HW_TUN BIT(SCRUB_HW_TUNABLE)
210 /* FIXME - should have notify capabilities: NMI, LOG, PROC, etc */
212 /* EDAC internal operation states */
213 #define OP_ALLOC 0x100
214 #define OP_RUNNING_POLL 0x201
215 #define OP_RUNNING_INTERRUPT 0x202
216 #define OP_RUNNING_POLL_INTR 0x203
217 #define OP_OFFLINE 0x300
220 * There are several things to be aware of that aren't at all obvious:
223 * SOCKETS, SOCKET SETS, BANKS, ROWS, CHIP-SELECT ROWS, CHANNELS, etc..
225 * These are some of the many terms that are thrown about that don't always
226 * mean what people think they mean (Inconceivable!). In the interest of
227 * creating a common ground for discussion, terms and their definitions
228 * will be established.
230 * Memory devices: The individual chip on a memory stick. These devices
231 * commonly output 4 and 8 bits each. Grouping several
232 * of these in parallel provides 64 bits which is common
233 * for a memory stick.
235 * Memory Stick: A printed circuit board that agregates multiple
236 * memory devices in parallel. This is the atomic
237 * memory component that is purchaseable by Joe consumer
238 * and loaded into a memory socket.
240 * Socket: A physical connector on the motherboard that accepts
241 * a single memory stick.
243 * Channel: Set of memory devices on a memory stick that must be
244 * grouped in parallel with one or more additional
245 * channels from other memory sticks. This parallel
246 * grouping of the output from multiple channels are
247 * necessary for the smallest granularity of memory access.
248 * Some memory controllers are capable of single channel -
249 * which means that memory sticks can be loaded
250 * individually. Other memory controllers are only
251 * capable of dual channel - which means that memory
252 * sticks must be loaded as pairs (see "socket set").
254 * Chip-select row: All of the memory devices that are selected together.
255 * for a single, minimum grain of memory access.
256 * This selects all of the parallel memory devices across
257 * all of the parallel channels. Common chip-select rows
258 * for single channel are 64 bits, for dual channel 128
261 * Single-Ranked stick: A Single-ranked stick has 1 chip-select row of memmory.
262 * Motherboards commonly drive two chip-select pins to
263 * a memory stick. A single-ranked stick, will occupy
264 * only one of those rows. The other will be unused.
266 * Double-Ranked stick: A double-ranked stick has two chip-select rows which
267 * access different sets of memory devices. The two
268 * rows cannot be accessed concurrently.
270 * Double-sided stick: DEPRECATED TERM, see Double-Ranked stick.
271 * A double-sided stick has two chip-select rows which
272 * access different sets of memory devices. The two
273 * rows cannot be accessed concurrently. "Double-sided"
274 * is irrespective of the memory devices being mounted
275 * on both sides of the memory stick.
277 * Socket set: All of the memory sticks that are required for
278 * a single memory access or all of the memory sticks
279 * spanned by a chip-select row. A single socket set
280 * has two chip-select rows and if double-sided sticks
281 * are used these will occupy those chip-select rows.
283 * Bank: This term is avoided because it is unclear when
284 * needing to distinguish between chip-select rows and
294 * STRUCTURE ORGANIZATION AND CHOICES
298 * PS - I enjoyed writing all that about as much as you enjoyed reading it.
301 struct channel_info
{
302 int chan_idx
; /* channel index */
303 u32 ce_count
; /* Correctable Errors for this CHANNEL */
304 char label
[EDAC_MC_LABEL_LEN
+ 1]; /* DIMM label on motherboard */
305 struct csrow_info
*csrow
; /* the parent */
309 unsigned long first_page
; /* first page number in dimm */
310 unsigned long last_page
; /* last page number in dimm */
311 unsigned long page_mask
; /* used for interleaving -
314 u32 nr_pages
; /* number of pages in csrow */
315 u32 grain
; /* granularity of reported error in bytes */
316 int csrow_idx
; /* the chip-select row */
317 enum dev_type dtype
; /* memory device type */
318 u32 ue_count
; /* Uncorrectable Errors for this csrow */
319 u32 ce_count
; /* Correctable Errors for this csrow */
320 enum mem_type mtype
; /* memory csrow type */
321 enum edac_type edac_mode
; /* EDAC mode for this csrow */
322 struct mem_ctl_info
*mci
; /* the parent */
324 struct kobject kobj
; /* sysfs kobject for this csrow */
326 /* channel information for this csrow */
328 struct channel_info
*channels
;
331 struct mcidev_sysfs_group
{
332 const char *name
; /* group name */
333 const struct mcidev_sysfs_attribute
*mcidev_attr
; /* group attributes */
336 struct mcidev_sysfs_group_kobj
{
337 struct list_head list
; /* list for all instances within a mc */
339 struct kobject kobj
; /* kobj for the group */
341 const struct mcidev_sysfs_group
*grp
; /* group description table */
342 struct mem_ctl_info
*mci
; /* the parent */
345 /* mcidev_sysfs_attribute structure
346 * used for driver sysfs attributes and in mem_ctl_info
347 * sysfs top level entries
349 struct mcidev_sysfs_attribute
{
350 /* It should use either attr or grp */
351 struct attribute attr
;
352 const struct mcidev_sysfs_group
*grp
; /* Points to a group of attributes */
354 /* Ops for show/store values at the attribute - not used on group */
355 ssize_t (*show
)(struct mem_ctl_info
*,char *);
356 ssize_t (*store
)(struct mem_ctl_info
*, const char *,size_t);
359 /* MEMORY controller information structure
361 struct mem_ctl_info
{
362 struct list_head link
; /* for global list of mem_ctl_info structs */
364 struct module
*owner
; /* Module owner of this control struct */
366 unsigned long mtype_cap
; /* memory types supported by mc */
367 unsigned long edac_ctl_cap
; /* Mem controller EDAC capabilities */
368 unsigned long edac_cap
; /* configuration capabilities - this is
369 * closely related to edac_ctl_cap. The
370 * difference is that the controller may be
371 * capable of s4ecd4ed which would be listed
372 * in edac_ctl_cap, but if channels aren't
373 * capable of s4ecd4ed then the edac_cap would
374 * not have that capability.
376 unsigned long scrub_cap
; /* chipset scrub capabilities */
377 enum scrub_type scrub_mode
; /* current scrub mode */
379 /* Translates sdram memory scrub rate given in bytes/sec to the
380 internal representation and configures whatever else needs
383 int (*set_sdram_scrub_rate
) (struct mem_ctl_info
* mci
, u32 bw
);
385 /* Get the current sdram memory scrub rate from the internal
386 representation and converts it to the closest matching
387 bandwith in bytes/sec.
389 int (*get_sdram_scrub_rate
) (struct mem_ctl_info
* mci
, u32
* bw
);
392 /* pointer to edac checking routine */
393 void (*edac_check
) (struct mem_ctl_info
* mci
);
396 * Remaps memory pages: controller pages to physical pages.
397 * For most MC's, this will be NULL.
399 /* FIXME - why not send the phys page to begin with? */
400 unsigned long (*ctl_page_to_phys
) (struct mem_ctl_info
* mci
,
404 struct csrow_info
*csrows
;
406 * FIXME - what about controllers on other busses? - IDs must be
407 * unique. dev pointer should be sufficiently unique, but
408 * BUS:SLOT.FUNC numbers may not be unique.
411 const char *mod_name
;
413 const char *ctl_name
;
414 const char *dev_name
;
415 char proc_name
[MC_PROC_NAME_MAX_LEN
+ 1];
417 u32 ue_noinfo_count
; /* Uncorrectable Errors w/o info */
418 u32 ce_noinfo_count
; /* Correctable Errors w/o info */
419 u32 ue_count
; /* Total Uncorrectable Errors for this MC */
420 u32 ce_count
; /* Total Correctable Errors for this MC */
421 unsigned long start_time
; /* mci load start time (in jiffies) */
423 /* this stuff is for safe removal of mc devices from global list while
424 * NMI handlers may be traversing list
427 struct completion complete
;
429 /* edac sysfs device control */
430 struct kobject edac_mci_kobj
;
432 /* list for all grp instances within a mc */
433 struct list_head grp_kobj_list
;
435 /* Additional top controller level attributes, but specified
436 * by the low level driver.
438 * Set by the low level driver to provide attributes at the
439 * controller level, same level as 'ue_count' and 'ce_count' above.
440 * An array of structures, NULL terminated
442 * If attributes are desired, then set to array of attributes
443 * If no attributes are desired, leave NULL
445 const struct mcidev_sysfs_attribute
*mc_driver_sysfs_attributes
;
447 /* work struct for this MC */
448 struct delayed_work work
;
450 /* the internal state of this controller instance */
455 * The following are the structures to provide for a generic
456 * or abstract 'edac_device'. This set of structures and the
457 * code that implements the APIs for the same, provide for
458 * registering EDAC type devices which are NOT standard memory.
460 * CPU caches (L1 and L2)
463 * Fabric switch units
464 * PCIe interface controllers
465 * other EDAC/ECC type devices that can be monitored for
468 * It allows for a 2 level set of hiearchry. For example:
470 * cache could be composed of L1, L2 and L3 levels of cache.
471 * Each CPU core would have its own L1 cache, while sharing
472 * L2 and maybe L3 caches.
474 * View them arranged, via the sysfs presentation:
475 * /sys/devices/system/edac/..
477 * mc/ <existing memory device directory>
478 * cpu/cpu0/.. <L1 and L2 block directory>
483 * cpu/cpu1/.. <L1 and L2 block directory>
490 * the L1 and L2 directories would be "edac_device_block's"
493 struct edac_device_counter
{
498 /* forward reference */
499 struct edac_device_ctl_info
;
500 struct edac_device_block
;
502 /* edac_dev_sysfs_attribute structure
503 * used for driver sysfs attributes in mem_ctl_info
504 * for extra controls and attributes:
505 * like high level error Injection controls
507 struct edac_dev_sysfs_attribute
{
508 struct attribute attr
;
509 ssize_t (*show
)(struct edac_device_ctl_info
*, char *);
510 ssize_t (*store
)(struct edac_device_ctl_info
*, const char *, size_t);
513 /* edac_dev_sysfs_block_attribute structure
515 * used in leaf 'block' nodes for adding controls/attributes
517 * each block in each instance of the containing control structure
518 * can have an array of the following. The show and store functions
519 * will be filled in with the show/store function in the
522 * The 'value' field will be the actual value field used for
525 struct edac_dev_sysfs_block_attribute
{
526 struct attribute attr
;
527 ssize_t (*show
)(struct kobject
*, struct attribute
*, char *);
528 ssize_t (*store
)(struct kobject
*, struct attribute
*,
529 const char *, size_t);
530 struct edac_device_block
*block
;
535 /* device block control structure */
536 struct edac_device_block
{
537 struct edac_device_instance
*instance
; /* Up Pointer */
538 char name
[EDAC_DEVICE_NAME_LEN
+ 1];
540 struct edac_device_counter counters
; /* basic UE and CE counters */
542 int nr_attribs
; /* how many attributes */
544 /* this block's attributes, could be NULL */
545 struct edac_dev_sysfs_block_attribute
*block_attributes
;
547 /* edac sysfs device control */
551 /* device instance control structure */
552 struct edac_device_instance
{
553 struct edac_device_ctl_info
*ctl
; /* Up pointer */
554 char name
[EDAC_DEVICE_NAME_LEN
+ 4];
556 struct edac_device_counter counters
; /* instance counters */
558 u32 nr_blocks
; /* how many blocks */
559 struct edac_device_block
*blocks
; /* block array */
561 /* edac sysfs device control */
567 * Abstract edac_device control info structure
570 struct edac_device_ctl_info
{
571 /* for global list of edac_device_ctl_info structs */
572 struct list_head link
;
574 struct module
*owner
; /* Module owner of this control struct */
578 /* Per instance controls for this edac_device */
579 int log_ue
; /* boolean for logging UEs */
580 int log_ce
; /* boolean for logging CEs */
581 int panic_on_ue
; /* boolean for panic'ing on an UE */
582 unsigned poll_msec
; /* number of milliseconds to poll interval */
583 unsigned long delay
; /* number of jiffies for poll_msec */
585 /* Additional top controller level attributes, but specified
586 * by the low level driver.
588 * Set by the low level driver to provide attributes at the
589 * controller level, same level as 'ue_count' and 'ce_count' above.
590 * An array of structures, NULL terminated
592 * If attributes are desired, then set to array of attributes
593 * If no attributes are desired, leave NULL
595 struct edac_dev_sysfs_attribute
*sysfs_attributes
;
597 /* pointer to main 'edac' class in sysfs */
598 struct sysdev_class
*edac_class
;
600 /* the internal state of this controller instance */
602 /* work struct for this instance */
603 struct delayed_work work
;
605 /* pointer to edac polling checking routine:
606 * If NOT NULL: points to polling check routine
607 * If NULL: Then assumes INTERRUPT operation, where
608 * MC driver will receive events
610 void (*edac_check
) (struct edac_device_ctl_info
* edac_dev
);
612 struct device
*dev
; /* pointer to device structure */
614 const char *mod_name
; /* module name */
615 const char *ctl_name
; /* edac controller name */
616 const char *dev_name
; /* pci/platform/etc... name */
618 void *pvt_info
; /* pointer to 'private driver' info */
620 unsigned long start_time
; /* edac_device load start time (jiffies) */
622 /* these are for safe removal of mc devices from global list while
623 * NMI handlers may be traversing list
626 struct completion removal_complete
;
628 /* sysfs top name under 'edac' directory
635 char name
[EDAC_DEVICE_NAME_LEN
+ 1];
637 /* Number of instances supported on this control structure
638 * and the array of those instances
641 struct edac_device_instance
*instances
;
643 /* Event counters for the this whole EDAC Device */
644 struct edac_device_counter counters
;
646 /* edac sysfs device control for the 'name'
647 * device this structure controls
652 /* To get from the instance's wq to the beginning of the ctl structure */
653 #define to_edac_mem_ctl_work(w) \
654 container_of(w, struct mem_ctl_info, work)
656 #define to_edac_device_ctl_work(w) \
657 container_of(w,struct edac_device_ctl_info,work)
660 * The alloc() and free() functions for the 'edac_device' control info
661 * structure. A MC driver will allocate one of these for each edac_device
662 * it is going to control/register with the EDAC CORE.
664 extern struct edac_device_ctl_info
*edac_device_alloc_ctl_info(
665 unsigned sizeof_private
,
666 char *edac_device_name
, unsigned nr_instances
,
667 char *edac_block_name
, unsigned nr_blocks
,
668 unsigned offset_value
,
669 struct edac_dev_sysfs_block_attribute
*block_attributes
,
673 /* The offset value can be:
674 * -1 indicating no offset value
675 * 0 for zero-based block numbers
676 * 1 for 1-based block number
677 * other for other-based block number
679 #define BLOCK_OFFSET_VALUE_OFF ((unsigned) -1)
681 extern void edac_device_free_ctl_info(struct edac_device_ctl_info
*ctl_info
);
685 struct edac_pci_counter
{
691 * Abstract edac_pci control info structure
694 struct edac_pci_ctl_info
{
695 /* for global list of edac_pci_ctl_info structs */
696 struct list_head link
;
700 struct sysdev_class
*edac_class
; /* pointer to class */
702 /* the internal state of this controller instance */
704 /* work struct for this instance */
705 struct delayed_work work
;
707 /* pointer to edac polling checking routine:
708 * If NOT NULL: points to polling check routine
709 * If NULL: Then assumes INTERRUPT operation, where
710 * MC driver will receive events
712 void (*edac_check
) (struct edac_pci_ctl_info
* edac_dev
);
714 struct device
*dev
; /* pointer to device structure */
716 const char *mod_name
; /* module name */
717 const char *ctl_name
; /* edac controller name */
718 const char *dev_name
; /* pci/platform/etc... name */
720 void *pvt_info
; /* pointer to 'private driver' info */
722 unsigned long start_time
; /* edac_pci load start time (jiffies) */
724 /* these are for safe removal of devices from global list while
725 * NMI handlers may be traversing list
728 struct completion complete
;
730 /* sysfs top name under 'edac' directory
737 char name
[EDAC_DEVICE_NAME_LEN
+ 1];
739 /* Event counters for the this whole EDAC Device */
740 struct edac_pci_counter counters
;
742 /* edac sysfs device control for the 'name'
743 * device this structure controls
746 struct completion kobj_complete
;
749 #define to_edac_pci_ctl_work(w) \
750 container_of(w, struct edac_pci_ctl_info,work)
752 /* write all or some bits in a byte-register*/
753 static inline void pci_write_bits8(struct pci_dev
*pdev
, int offset
, u8 value
,
759 pci_read_config_byte(pdev
, offset
, &buf
);
765 pci_write_config_byte(pdev
, offset
, value
);
768 /* write all or some bits in a word-register*/
769 static inline void pci_write_bits16(struct pci_dev
*pdev
, int offset
,
772 if (mask
!= 0xffff) {
775 pci_read_config_word(pdev
, offset
, &buf
);
781 pci_write_config_word(pdev
, offset
, value
);
787 * edac local routine to do pci_write_config_dword, but adds
788 * a mask parameter. If mask is all ones, ignore the mask.
789 * Otherwise utilize the mask to isolate specified bits
791 * write all or some bits in a dword-register
793 static inline void pci_write_bits32(struct pci_dev
*pdev
, int offset
,
796 if (mask
!= 0xffffffff) {
799 pci_read_config_dword(pdev
, offset
, &buf
);
805 pci_write_config_dword(pdev
, offset
, value
);
808 #endif /* CONFIG_PCI */
810 extern struct mem_ctl_info
*edac_mc_alloc(unsigned sz_pvt
, unsigned nr_csrows
,
811 unsigned nr_chans
, int edac_index
);
812 extern int edac_mc_add_mc(struct mem_ctl_info
*mci
);
813 extern void edac_mc_free(struct mem_ctl_info
*mci
);
814 extern struct mem_ctl_info
*edac_mc_find(int idx
);
815 extern struct mem_ctl_info
*find_mci_by_dev(struct device
*dev
);
816 extern struct mem_ctl_info
*edac_mc_del_mc(struct device
*dev
);
817 extern int edac_mc_find_csrow_by_page(struct mem_ctl_info
*mci
,
821 * The no info errors are used when error overflows are reported.
822 * There are a limited number of error logging registers that can
823 * be exausted. When all registers are exhausted and an additional
824 * error occurs then an error overflow register records that an
825 * error occured and the type of error, but doesn't have any
826 * further information. The ce/ue versions make for cleaner
827 * reporting logic and function interface - reduces conditional
828 * statement clutter and extra function arguments.
830 extern void edac_mc_handle_ce(struct mem_ctl_info
*mci
,
831 unsigned long page_frame_number
,
832 unsigned long offset_in_page
,
833 unsigned long syndrome
, int row
, int channel
,
835 extern void edac_mc_handle_ce_no_info(struct mem_ctl_info
*mci
,
837 extern void edac_mc_handle_ue(struct mem_ctl_info
*mci
,
838 unsigned long page_frame_number
,
839 unsigned long offset_in_page
, int row
,
841 extern void edac_mc_handle_ue_no_info(struct mem_ctl_info
*mci
,
843 extern void edac_mc_handle_fbd_ue(struct mem_ctl_info
*mci
, unsigned int csrow
,
844 unsigned int channel0
, unsigned int channel1
,
846 extern void edac_mc_handle_fbd_ce(struct mem_ctl_info
*mci
, unsigned int csrow
,
847 unsigned int channel
, char *msg
);
852 extern int edac_device_add_device(struct edac_device_ctl_info
*edac_dev
);
853 extern struct edac_device_ctl_info
*edac_device_del_device(struct device
*dev
);
854 extern void edac_device_handle_ue(struct edac_device_ctl_info
*edac_dev
,
855 int inst_nr
, int block_nr
, const char *msg
);
856 extern void edac_device_handle_ce(struct edac_device_ctl_info
*edac_dev
,
857 int inst_nr
, int block_nr
, const char *msg
);
858 extern int edac_device_alloc_index(void);
863 extern struct edac_pci_ctl_info
*edac_pci_alloc_ctl_info(unsigned int sz_pvt
,
864 const char *edac_pci_name
);
866 extern void edac_pci_free_ctl_info(struct edac_pci_ctl_info
*pci
);
868 extern void edac_pci_reset_delay_period(struct edac_pci_ctl_info
*pci
,
869 unsigned long value
);
871 extern int edac_pci_alloc_index(void);
872 extern int edac_pci_add_device(struct edac_pci_ctl_info
*pci
, int edac_idx
);
873 extern struct edac_pci_ctl_info
*edac_pci_del_device(struct device
*dev
);
875 extern struct edac_pci_ctl_info
*edac_pci_create_generic_ctl(
877 const char *mod_name
);
879 extern void edac_pci_release_generic_ctl(struct edac_pci_ctl_info
*pci
);
880 extern int edac_pci_create_sysfs(struct edac_pci_ctl_info
*pci
);
881 extern void edac_pci_remove_sysfs(struct edac_pci_ctl_info
*pci
);
886 extern char *edac_op_state_to_string(int op_state
);
888 #endif /* _EDAC_CORE_H_ */