drivers/pcmcia/m8xx_pcmcia.c

   1 /*
   2  * m8xx_pcmcia.c - Linux PCMCIA socket driver for the mpc8xx series.
   3  *
   4  * (C) 1999-2000 Magnus Damm <damm@opensource.se>
   5  * (C) 2001-2002 Montavista Software, Inc.
   6  *     <mlocke@mvista.com>
   7  *
   8  * Support for two slots by Cyclades Corporation
   9  *     <oliver.kurth@cyclades.de>
  10  * Further fixes, v2.6 kernel port
  11  *     <marcelo.tosatti@cyclades.com>
  12  *
  13  * Some fixes, additions (C) 2005-2007 Montavista Software, Inc.
  14  *     <vbordug@ru.mvista.com>
  15  *
  16  * "The ExCA standard specifies that socket controllers should provide
  17  * two IO and five memory windows per socket, which can be independently
  18  * configured and positioned in the host address space and mapped to
  19  * arbitrary segments of card address space. " - David A Hinds. 1999
  20  *
  21  * This controller does _not_ meet the ExCA standard.
  22  *
  23  * m8xx pcmcia controller brief info:
  24  * + 8 windows (attrib, mem, i/o)
  25  * + up to two slots (SLOT_A and SLOT_B)
  26  * + inputpins, outputpins, event and mask registers.
  27  * - no offset register. sigh.
  28  *
  29  * Because of the lacking offset register we must map the whole card.
  30  * We assign each memory window PCMCIA_MEM_WIN_SIZE address space.
  31  * Make sure there is (PCMCIA_MEM_WIN_SIZE * PCMCIA_MEM_WIN_NO
  32  * * PCMCIA_SOCKETS_NO) bytes at PCMCIA_MEM_WIN_BASE.
  33  * The i/o windows are dynamically allocated at PCMCIA_IO_WIN_BASE.
  34  * They are maximum 64KByte each...
  35  */
  36
  37 #include <linux/module.h>
  38 #include <linux/init.h>
  39 #include <linux/types.h>
  40 #include <linux/fcntl.h>
  41 #include <linux/string.h>
  42
  43 #include <linux/kernel.h>
  44 #include <linux/errno.h>
  45 #include <linux/timer.h>
  46 #include <linux/ioport.h>
  47 #include <linux/delay.h>
  48 #include <linux/interrupt.h>
  49 #include <linux/fsl_devices.h>
  50 #include <linux/bitops.h>
  51 #include <linux/of_device.h>
  52 #include <linux/of_platform.h>
  53
  54 #include <asm/io.h>
  55 #include <asm/system.h>
  56 #include <asm/time.h>
  57 #include <asm/mpc8xx.h>
  58 #include <asm/8xx_immap.h>
  59 #include <asm/irq.h>
  60 #include <asm/fs_pd.h>
  61
  62 #include <pcmcia/cs.h>
  63 #include <pcmcia/ss.h>
  64
  65 #define pcmcia_info(args...) printk(KERN_INFO "m8xx_pcmcia: "args)
  66 #define pcmcia_error(args...) printk(KERN_ERR "m8xx_pcmcia: "args)
  67
  68 static const char *version = "Version 0.06, Aug 2005";
  69 MODULE_LICENSE("Dual MPL/GPL");
  70
  71 #if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B)
  72
  73 /* The RPX series use SLOT_B */
  74 #if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE)
  75 #define CONFIG_PCMCIA_SLOT_B
  76 #define CONFIG_BD_IS_MHZ
  77 #endif
  78
  79 /* The ADS board use SLOT_A */
  80 #ifdef CONFIG_ADS
  81 #define CONFIG_PCMCIA_SLOT_A
  82 #define CONFIG_BD_IS_MHZ
  83 #endif
  84
  85 /* The FADS series are a mess */
  86 #ifdef CONFIG_FADS
  87 #if defined(CONFIG_MPC860T) || defined(CONFIG_MPC860) || defined(CONFIG_MPC821)
  88 #define CONFIG_PCMCIA_SLOT_A
  89 #else
  90 #define CONFIG_PCMCIA_SLOT_B
  91 #endif
  92 #endif
  93
  94 #if defined(CONFIG_MPC885ADS)
  95 #define CONFIG_PCMCIA_SLOT_A
  96 #define PCMCIA_GLITCHY_CD
  97 #endif
  98
  99 /* Cyclades ACS uses both slots */
 100 #ifdef CONFIG_PRxK
 101 #define CONFIG_PCMCIA_SLOT_A
 102 #define CONFIG_PCMCIA_SLOT_B
 103 #endif
 104
 105 #endif                          /* !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) */
 106
 107 #if defined(CONFIG_PCMCIA_SLOT_A) && defined(CONFIG_PCMCIA_SLOT_B)
 108
 109 #define PCMCIA_SOCKETS_NO 2
 110 /* We have only 8 windows, dualsocket support will be limited. */
 111 #define PCMCIA_MEM_WIN_NO 2
 112 #define PCMCIA_IO_WIN_NO  2
 113 #define PCMCIA_SLOT_MSG "SLOT_A and SLOT_B"
 114
 115 #elif defined(CONFIG_PCMCIA_SLOT_A) || defined(CONFIG_PCMCIA_SLOT_B)
 116
 117 #define PCMCIA_SOCKETS_NO 1
 118 /* full support for one slot */
 119 #define PCMCIA_MEM_WIN_NO 5
 120 #define PCMCIA_IO_WIN_NO  2
 121
 122 /* define _slot_ to be able to optimize macros */
 123
 124 #ifdef CONFIG_PCMCIA_SLOT_A
 125 #define _slot_ 0
 126 #define PCMCIA_SLOT_MSG "SLOT_A"
 127 #else
 128 #define _slot_ 1
 129 #define PCMCIA_SLOT_MSG "SLOT_B"
 130 #endif
 131
 132 #else
 133 #error m8xx_pcmcia: Bad configuration!
 134 #endif
 135
 136 /* ------------------------------------------------------------------------- */
 137
 138 #define PCMCIA_MEM_WIN_BASE 0xe0000000  /* base address for memory window 0   */
 139 #define PCMCIA_MEM_WIN_SIZE 0x04000000  /* each memory window is 64 MByte     */
 140 #define PCMCIA_IO_WIN_BASE  _IO_BASE    /* base address for io window 0       */
 141 /* ------------------------------------------------------------------------- */
 142
 143 static int pcmcia_schlvl;
 144
 145 static DEFINE_SPINLOCK(events_lock);
 146
 147 #define PCMCIA_SOCKET_KEY_5V 1
 148 #define PCMCIA_SOCKET_KEY_LV 2
 149
 150 /* look up table for pgcrx registers */
 151 static u32 *m8xx_pgcrx[2];
 152
 153 /*
 154  * This structure is used to address each window in the PCMCIA controller.
 155  *
 156  * Keep in mind that we assume that pcmcia_win[n+1] is mapped directly
 157  * after pcmcia_win[n]...
 158  */
 159
 160 struct pcmcia_win {
 161         u32 br;
 162         u32 or;
 163 };
 164
 165 /*
 166  * For some reason the hardware guys decided to make both slots share
 167  * some registers.
 168  *
 169  * Could someone invent object oriented hardware ?
 170  *
 171  * The macros are used to get the right bit from the registers.
 172  * SLOT_A : slot = 0
 173  * SLOT_B : slot = 1
 174  */
 175
 176 #define M8XX_PCMCIA_VS1(slot)      (0x80000000 >> (slot << 4))
 177 #define M8XX_PCMCIA_VS2(slot)      (0x40000000 >> (slot << 4))
 178 #define M8XX_PCMCIA_VS_MASK(slot)  (0xc0000000 >> (slot << 4))
 179 #define M8XX_PCMCIA_VS_SHIFT(slot) (30 - (slot << 4))
 180
 181 #define M8XX_PCMCIA_WP(slot)       (0x20000000 >> (slot << 4))
 182 #define M8XX_PCMCIA_CD2(slot)      (0x10000000 >> (slot << 4))
 183 #define M8XX_PCMCIA_CD1(slot)      (0x08000000 >> (slot << 4))
 184 #define M8XX_PCMCIA_BVD2(slot)     (0x04000000 >> (slot << 4))
 185 #define M8XX_PCMCIA_BVD1(slot)     (0x02000000 >> (slot << 4))
 186 #define M8XX_PCMCIA_RDY(slot)      (0x01000000 >> (slot << 4))
 187 #define M8XX_PCMCIA_RDY_L(slot)    (0x00800000 >> (slot << 4))
 188 #define M8XX_PCMCIA_RDY_H(slot)    (0x00400000 >> (slot << 4))
 189 #define M8XX_PCMCIA_RDY_R(slot)    (0x00200000 >> (slot << 4))
 190 #define M8XX_PCMCIA_RDY_F(slot)    (0x00100000 >> (slot << 4))
 191 #define M8XX_PCMCIA_MASK(slot)     (0xFFFF0000 >> (slot << 4))
 192
 193 #define M8XX_PCMCIA_POR_VALID    0x00000001
 194 #define M8XX_PCMCIA_POR_WRPROT   0x00000002
 195 #define M8XX_PCMCIA_POR_ATTRMEM  0x00000010
 196 #define M8XX_PCMCIA_POR_IO       0x00000018
 197 #define M8XX_PCMCIA_POR_16BIT    0x00000040
 198
 199 #define M8XX_PGCRX(slot)  m8xx_pgcrx[slot]
 200
 201 #define M8XX_PGCRX_CXOE    0x00000080
 202 #define M8XX_PGCRX_CXRESET 0x00000040
 203
 204 /* we keep one lookup table per socket to check flags */
 205
 206 #define PCMCIA_EVENTS_MAX 5     /* 4 max at a time + termination */
 207
 208 struct event_table {
 209         u32 regbit;
 210         u32 eventbit;
 211 };
 212
 213 static const char driver_name[] = "m8xx-pcmcia";
 214
 215 struct socket_info {
 216         void (*handler) (void *info, u32 events);
 217         void *info;
 218
 219         u32 slot;
 220         pcmconf8xx_t *pcmcia;
 221         u32 bus_freq;
 222         int hwirq;
 223
 224         socket_state_t state;
 225         struct pccard_mem_map mem_win[PCMCIA_MEM_WIN_NO];
 226         struct pccard_io_map io_win[PCMCIA_IO_WIN_NO];
 227         struct event_table events[PCMCIA_EVENTS_MAX];
 228         struct pcmcia_socket socket;
 229 };
 230
 231 static struct socket_info socket[PCMCIA_SOCKETS_NO];
 232
 233 /*
 234  * Search this table to see if the windowsize is
 235  * supported...
 236  */
 237
 238 #define M8XX_SIZES_NO 32
 239
 240 static const u32 m8xx_size_to_gray[M8XX_SIZES_NO] = {
 241         0x00000001, 0x00000002, 0x00000008, 0x00000004,
 242         0x00000080, 0x00000040, 0x00000010, 0x00000020,
 243         0x00008000, 0x00004000, 0x00001000, 0x00002000,
 244         0x00000100, 0x00000200, 0x00000800, 0x00000400,
 245
 246         0x0fffffff, 0xffffffff, 0xffffffff, 0xffffffff,
 247         0x01000000, 0x02000000, 0xffffffff, 0x04000000,
 248         0x00010000, 0x00020000, 0x00080000, 0x00040000,
 249         0x00800000, 0x00400000, 0x00100000, 0x00200000
 250 };
 251
 252 /* ------------------------------------------------------------------------- */
 253
 254 static irqreturn_t m8xx_interrupt(int irq, void *dev);
 255
 256 #define PCMCIA_BMT_LIMIT (15*4) /* Bus Monitor Timeout value */
 257
 258 /* ------------------------------------------------------------------------- */
 259 /* board specific stuff:                                                     */
 260 /* voltage_set(), hardware_enable() and hardware_disable()                   */
 261 /* ------------------------------------------------------------------------- */
 262 /* RPX Boards from Embedded Planet                                           */
 263
 264 #if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE)
 265
 266 /* The RPX boards seems to have it's bus monitor timeout set to 6*8 clocks.
 267  * SYPCR is write once only, therefore must the slowest memory be faster
 268  * than the bus monitor or we will get a machine check due to the bus timeout.
 269  */
 270
 271 #define PCMCIA_BOARD_MSG "RPX CLASSIC or RPX LITE"
 272
 273 #undef PCMCIA_BMT_LIMIT
 274 #define PCMCIA_BMT_LIMIT (6*8)
 275
 276 static int voltage_set(int slot, int vcc, int vpp)
 277 {
 278         u32 reg = 0;
 279
 280         switch (vcc) {
 281         case 0:
 282                 break;
 283         case 33:
 284                 reg |= BCSR1_PCVCTL4;
 285                 break;
 286         case 50:
 287                 reg |= BCSR1_PCVCTL5;
 288                 break;
 289         default:
 290                 return 1;
 291         }
 292
 293         switch (vpp) {
 294         case 0:
 295                 break;
 296         case 33:
 297         case 50:
 298                 if (vcc == vpp)
 299                         reg |= BCSR1_PCVCTL6;
 300                 else
 301                         return 1;
 302                 break;
 303         case 120:
 304                 reg |= BCSR1_PCVCTL7;
 305         default:
 306                 return 1;
 307         }
 308
 309         if (!((vcc == 50) || (vcc == 0)))
 310                 return 1;
 311
 312         /* first, turn off all power */
 313
 314         out_be32(((u32 *) RPX_CSR_ADDR),
 315                  in_be32(((u32 *) RPX_CSR_ADDR)) & ~(BCSR1_PCVCTL4 |
 316                                                      BCSR1_PCVCTL5 |
 317                                                      BCSR1_PCVCTL6 |
 318                                                      BCSR1_PCVCTL7));
 319
 320         /* enable new powersettings */
 321
 322         out_be32(((u32 *) RPX_CSR_ADDR), in_be32(((u32 *) RPX_CSR_ADDR)) | reg);
 323
 324         return 0;
 325 }
 326
 327 #define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V
 328 #define hardware_enable(_slot_) /* No hardware to enable */
 329 #define hardware_disable(_slot_)        /* No hardware to disable */
 330
 331 #endif                          /* CONFIG_RPXCLASSIC */
 332
 333 /* FADS Boards from Motorola                                               */
 334
 335 #if defined(CONFIG_FADS)
 336
 337 #define PCMCIA_BOARD_MSG "FADS"
 338
 339 static int voltage_set(int slot, int vcc, int vpp)
 340 {
 341         u32 reg = 0;
 342
 343         switch (vcc) {
 344         case 0:
 345                 break;
 346         case 33:
 347                 reg |= BCSR1_PCCVCC0;
 348                 break;
 349         case 50:
 350                 reg |= BCSR1_PCCVCC1;
 351                 break;
 352         default:
 353                 return 1;
 354         }
 355
 356         switch (vpp) {
 357         case 0:
 358                 break;
 359         case 33:
 360         case 50:
 361                 if (vcc == vpp)
 362                         reg |= BCSR1_PCCVPP1;
 363                 else
 364                         return 1;
 365                 break;
 366         case 120:
 367                 if ((vcc == 33) || (vcc == 50))
 368                         reg |= BCSR1_PCCVPP0;
 369                 else
 370                         return 1;
 371         default:
 372                 return 1;
 373         }
 374
 375         /* first, turn off all power */
 376         out_be32((u32 *) BCSR1,
 377                  in_be32((u32 *) BCSR1) & ~(BCSR1_PCCVCC_MASK |
 378                                             BCSR1_PCCVPP_MASK));
 379
 380         /* enable new powersettings */
 381         out_be32((u32 *) BCSR1, in_be32((u32 *) BCSR1) | reg);
 382
 383         return 0;
 384 }
 385
 386 #define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V
 387
 388 static void hardware_enable(int slot)
 389 {
 390         out_be32((u32 *) BCSR1, in_be32((u32 *) BCSR1) & ~BCSR1_PCCEN);
 391 }
 392
 393 static void hardware_disable(int slot)
 394 {
 395         out_be32((u32 *) BCSR1, in_be32((u32 *) BCSR1) | BCSR1_PCCEN);
 396 }
 397
 398 #endif
 399
 400 /* MPC885ADS Boards */
 401
 402 #if defined(CONFIG_MPC885ADS)
 403
 404 #define PCMCIA_BOARD_MSG "MPC885ADS"
 405 #define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V
 406
 407 static inline void hardware_enable(int slot)
 408 {
 409         m8xx_pcmcia_ops.hw_ctrl(slot, 1);
 410 }
 411
 412 static inline void hardware_disable(int slot)
 413 {
 414         m8xx_pcmcia_ops.hw_ctrl(slot, 0);
 415 }
 416
 417 static inline int voltage_set(int slot, int vcc, int vpp)
 418 {
 419         return m8xx_pcmcia_ops.voltage_set(slot, vcc, vpp);
 420 }
 421
 422 #endif
 423
 424 /* ------------------------------------------------------------------------- */
 425 /* Motorola MBX860                                                           */
 426
 427 #if defined(CONFIG_MBX)
 428
 429 #define PCMCIA_BOARD_MSG "MBX"
 430
 431 static int voltage_set(int slot, int vcc, int vpp)
 432 {
 433         u8 reg = 0;
 434
 435         switch (vcc) {
 436         case 0:
 437                 break;
 438         case 33:
 439                 reg |= CSR2_VCC_33;
 440                 break;
 441         case 50:
 442                 reg |= CSR2_VCC_50;
 443                 break;
 444         default:
 445                 return 1;
 446         }
 447
 448         switch (vpp) {
 449         case 0:
 450                 break;
 451         case 33:
 452         case 50:
 453                 if (vcc == vpp)
 454                         reg |= CSR2_VPP_VCC;
 455                 else
 456                         return 1;
 457                 break;
 458         case 120:
 459                 if ((vcc == 33) || (vcc == 50))
 460                         reg |= CSR2_VPP_12;
 461                 else
 462                         return 1;
 463         default:
 464                 return 1;
 465         }
 466
 467         /* first, turn off all power */
 468         out_8((u8 *) MBX_CSR2_ADDR,
 469               in_8((u8 *) MBX_CSR2_ADDR) & ~(CSR2_VCC_MASK | CSR2_VPP_MASK));
 470
 471         /* enable new powersettings */
 472         out_8((u8 *) MBX_CSR2_ADDR, in_8((u8 *) MBX_CSR2_ADDR) | reg);
 473
 474         return 0;
 475 }
 476
 477 #define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V
 478 #define hardware_enable(_slot_) /* No hardware to enable */
 479 #define hardware_disable(_slot_)        /* No hardware to disable */
 480
 481 #endif                          /* CONFIG_MBX */
 482
 483 #if defined(CONFIG_PRxK)
 484 #include <asm/cpld.h>
 485 extern volatile fpga_pc_regs *fpga_pc;
 486
 487 #define PCMCIA_BOARD_MSG "MPC855T"
 488
 489 static int voltage_set(int slot, int vcc, int vpp)
 490 {
 491         u8 reg = 0;
 492         u8 regread;
 493         cpld_regs *ccpld = get_cpld();
 494
 495         switch (vcc) {
 496         case 0:
 497                 break;
 498         case 33:
 499                 reg |= PCMCIA_VCC_33;
 500                 break;
 501         case 50:
 502                 reg |= PCMCIA_VCC_50;
 503                 break;
 504         default:
 505                 return 1;
 506         }
 507
 508         switch (vpp) {
 509         case 0:
 510                 break;
 511         case 33:
 512         case 50:
 513                 if (vcc == vpp)
 514                         reg |= PCMCIA_VPP_VCC;
 515                 else
 516                         return 1;
 517                 break;
 518         case 120:
 519                 if ((vcc == 33) || (vcc == 50))
 520                         reg |= PCMCIA_VPP_12;
 521                 else
 522                         return 1;
 523         default:
 524                 return 1;
 525         }
 526
 527         reg = reg >> (slot << 2);
 528         regread = in_8(&ccpld->fpga_pc_ctl);
 529         if (reg !=
 530             (regread & ((PCMCIA_VCC_MASK | PCMCIA_VPP_MASK) >> (slot << 2)))) {
 531                 /* enable new powersettings */
 532                 regread =
 533                     regread & ~((PCMCIA_VCC_MASK | PCMCIA_VPP_MASK) >>
 534                                 (slot << 2));
 535                 out_8(&ccpld->fpga_pc_ctl, reg | regread);
 536                 msleep(100);
 537         }
 538
 539         return 0;
 540 }
 541
 542 #define socket_get(_slot_) PCMCIA_SOCKET_KEY_LV
 543 #define hardware_enable(_slot_) /* No hardware to enable */
 544 #define hardware_disable(_slot_)        /* No hardware to disable */
 545
 546 #endif                          /* CONFIG_PRxK */
 547
 548 static u32 pending_events[PCMCIA_SOCKETS_NO];
 549 static DEFINE_SPINLOCK(pending_event_lock);
 550
 551 static irqreturn_t m8xx_interrupt(int irq, void *dev)
 552 {
 553         struct socket_info *s;
 554         struct event_table *e;
 555         unsigned int i, events, pscr, pipr, per;
 556         pcmconf8xx_t *pcmcia = socket[0].pcmcia;
 557
 558         pr_debug("m8xx_pcmcia: Interrupt!\n");
 559         /* get interrupt sources */
 560
 561         pscr = in_be32(&pcmcia->pcmc_pscr);
 562         pipr = in_be32(&pcmcia->pcmc_pipr);
 563         per = in_be32(&pcmcia->pcmc_per);
 564
 565         for (i = 0; i < PCMCIA_SOCKETS_NO; i++) {
 566                 s = &socket[i];
 567                 e = &s->events[0];
 568                 events = 0;
 569
 570                 while (e->regbit) {
 571                         if (pscr & e->regbit)
 572                                 events |= e->eventbit;
 573
 574                         e++;
 575                 }
 576
 577                 /*
 578                  * report only if both card detect signals are the same
 579                  * not too nice done,
 580                  * we depend on that CD2 is the bit to the left of CD1...
 581                  */
 582                 if (events & SS_DETECT)
 583                         if (((pipr & M8XX_PCMCIA_CD2(i)) >> 1) ^
 584                             (pipr & M8XX_PCMCIA_CD1(i))) {
 585                                 events &= ~SS_DETECT;
 586                         }
 587 #ifdef PCMCIA_GLITCHY_CD
 588                 /*
 589                  * I've experienced CD problems with my ADS board.
 590                  * We make an extra check to see if there was a
 591                  * real change of Card detection.
 592                  */
 593
 594                 if ((events & SS_DETECT) &&
 595                     ((pipr &
 596                       (M8XX_PCMCIA_CD2(i) | M8XX_PCMCIA_CD1(i))) == 0) &&
 597                     (s->state.Vcc | s->state.Vpp)) {
 598                         events &= ~SS_DETECT;
 599                         /*printk( "CD glitch workaround - CD = 0x%08x!\n",
 600                            (pipr & (M8XX_PCMCIA_CD2(i)
 601                            | M8XX_PCMCIA_CD1(i)))); */
 602                 }
 603 #endif
 604
 605                 /* call the handler */
 606
 607                 pr_debug("m8xx_pcmcia: slot %u: events = 0x%02x, pscr = 0x%08x, "
 608                         "pipr = 0x%08x\n", i, events, pscr, pipr);
 609
 610                 if (events) {
 611                         spin_lock(&pending_event_lock);
 612                         pending_events[i] |= events;
 613                         spin_unlock(&pending_event_lock);
 614                         /*
 615                          * Turn off RDY_L bits in the PER mask on
 616                          * CD interrupt receival.
 617                          *
 618                          * They can generate bad interrupts on the
 619                          * ACS4,8,16,32.   - marcelo
 620                          */
 621                         per &= ~M8XX_PCMCIA_RDY_L(0);
 622                         per &= ~M8XX_PCMCIA_RDY_L(1);
 623
 624                         out_be32(&pcmcia->pcmc_per, per);
 625
 626                         if (events)
 627                                 pcmcia_parse_events(&socket[i].socket, events);
 628                 }
 629         }
 630
 631         /* clear the interrupt sources */
 632         out_be32(&pcmcia->pcmc_pscr, pscr);
 633
 634         pr_debug("m8xx_pcmcia: Interrupt done.\n");
 635
 636         return IRQ_HANDLED;
 637 }
 638
 639 static u32 m8xx_get_graycode(u32 size)
 640 {
 641         u32 k;
 642
 643         for (k = 0; k < M8XX_SIZES_NO; k++)
 644                 if (m8xx_size_to_gray[k] == size)
 645                         break;
 646
 647         if ((k == M8XX_SIZES_NO) || (m8xx_size_to_gray[k] == -1))
 648                 k = -1;
 649
 650         return k;
 651 }
 652
 653 static u32 m8xx_get_speed(u32 ns, u32 is_io, u32 bus_freq)
 654 {
 655         u32 reg, clocks, psst, psl, psht;
 656
 657         if (!ns) {
 658
 659                 /*
 660                  * We get called with IO maps setup to 0ns
 661                  * if not specified by the user.
 662                  * They should be 255ns.
 663                  */
 664
 665                 if (is_io)
 666                         ns = 255;
 667                 else
 668                         ns = 100;       /* fast memory if 0 */
 669         }
 670
 671         /*
 672          * In PSST, PSL, PSHT fields we tell the controller
 673          * timing parameters in CLKOUT clock cycles.
 674          * CLKOUT is the same as GCLK2_50.
 675          */
 676
 677 /* how we want to adjust the timing - in percent */
 678
 679 #define ADJ 180                 /* 80 % longer accesstime - to be sure */
 680
 681         clocks = ((bus_freq / 1000) * ns) / 1000;
 682         clocks = (clocks * ADJ) / (100 * 1000);
 683         if (clocks >= PCMCIA_BMT_LIMIT) {
 684                 printk("Max access time limit reached\n");
 685                 clocks = PCMCIA_BMT_LIMIT - 1;
 686         }
 687
 688         psst = clocks / 7;      /* setup time */
 689         psht = clocks / 7;      /* hold time */
 690         psl = (clocks * 5) / 7; /* strobe length */
 691
 692         psst += clocks - (psst + psht + psl);
 693
 694         reg = psst << 12;
 695         reg |= psl << 7;
 696         reg |= psht << 16;
 697
 698         return reg;
 699 }
 700
 701 static int m8xx_get_status(struct pcmcia_socket *sock, unsigned int *value)
 702 {
 703         int lsock = container_of(sock, struct socket_info, socket)->slot;
 704         struct socket_info *s = &socket[lsock];
 705         unsigned int pipr, reg;
 706         pcmconf8xx_t *pcmcia = s->pcmcia;
 707
 708         pipr = in_be32(&pcmcia->pcmc_pipr);
 709
 710         *value = ((pipr & (M8XX_PCMCIA_CD1(lsock)
 711                            | M8XX_PCMCIA_CD2(lsock))) == 0) ? SS_DETECT : 0;
 712         *value |= (pipr & M8XX_PCMCIA_WP(lsock)) ? SS_WRPROT : 0;
 713
 714         if (s->state.flags & SS_IOCARD)
 715                 *value |= (pipr & M8XX_PCMCIA_BVD1(lsock)) ? SS_STSCHG : 0;
 716         else {
 717                 *value |= (pipr & M8XX_PCMCIA_RDY(lsock)) ? SS_READY : 0;
 718                 *value |= (pipr & M8XX_PCMCIA_BVD1(lsock)) ? SS_BATDEAD : 0;
 719                 *value |= (pipr & M8XX_PCMCIA_BVD2(lsock)) ? SS_BATWARN : 0;
 720         }
 721
 722         if (s->state.Vcc | s->state.Vpp)
 723                 *value |= SS_POWERON;
 724
 725         /*
 726          * Voltage detection:
 727          * This driver only supports 16-Bit pc-cards.
 728          * Cardbus is not handled here.
 729          *
 730          * To determine what voltage to use we must read the VS1 and VS2 pin.
 731          * Depending on what socket type is present,
 732          * different combinations mean different things.
 733          *
 734          * Card Key  Socket Key   VS1   VS2   Card         Vcc for CIS parse
 735          *
 736          * 5V        5V, LV*      NC    NC    5V only       5V (if available)
 737          *
 738          * 5V        5V, LV*      GND   NC    5 or 3.3V     as low as possible
 739          *
 740          * 5V        5V, LV*      GND   GND   5, 3.3, x.xV  as low as possible
 741          *
 742          * LV*       5V            -     -    shall not fit into socket
 743          *
 744          * LV*       LV*          GND   NC    3.3V only     3.3V
 745          *
 746          * LV*       LV*          NC    GND   x.xV          x.xV (if avail.)
 747          *
 748          * LV*       LV*          GND   GND   3.3 or x.xV   as low as possible
 749          *
 750          * *LV means Low Voltage
 751          *
 752          *
 753          * That gives us the following table:
 754          *
 755          * Socket    VS1  VS2   Voltage
 756          *
 757          * 5V        NC   NC    5V
 758          * 5V        NC   GND   none (should not be possible)
 759          * 5V        GND  NC    >= 3.3V
 760          * 5V        GND  GND   >= x.xV
 761          *
 762          * LV        NC   NC    5V   (if available)
 763          * LV        NC   GND   x.xV (if available)
 764          * LV        GND  NC    3.3V
 765          * LV        GND  GND   >= x.xV
 766          *
 767          * So, how do I determine if I have a 5V or a LV
 768          * socket on my board?  Look at the socket!
 769          *
 770          *
 771          * Socket with 5V key:
 772          * ++--------------------------------------------+
 773          * ||                                            |
 774          * ||                                           ||
 775          * ||                                           ||
 776          * |                                             |
 777          * +---------------------------------------------+
 778          *
 779          * Socket with LV key:
 780          * ++--------------------------------------------+
 781          * ||                                            |
 782          * |                                            ||
 783          * |                                            ||
 784          * |                                             |
 785          * +---------------------------------------------+
 786          *
 787          *
 788          * With other words - LV only cards does not fit
 789          * into the 5V socket!
 790          */
 791
 792         /* read out VS1 and VS2 */
 793
 794         reg = (pipr & M8XX_PCMCIA_VS_MASK(lsock))
 795             >> M8XX_PCMCIA_VS_SHIFT(lsock);
 796
 797         if (socket_get(lsock) == PCMCIA_SOCKET_KEY_LV) {
 798                 switch (reg) {
 799                 case 1:
 800                         *value |= SS_3VCARD;
 801                         break;  /* GND, NC - 3.3V only */
 802                 case 2:
 803                         *value |= SS_XVCARD;
 804                         break;  /* NC. GND - x.xV only */
 805                 };
 806         }
 807
 808         pr_debug("m8xx_pcmcia: GetStatus(%d) = %#2.2x\n", lsock, *value);
 809         return 0;
 810 }
 811
 812 static int m8xx_set_socket(struct pcmcia_socket *sock, socket_state_t * state)
 813 {
 814         int lsock = container_of(sock, struct socket_info, socket)->slot;
 815         struct socket_info *s = &socket[lsock];
 816         struct event_table *e;
 817         unsigned int reg;
 818         unsigned long flags;
 819         pcmconf8xx_t *pcmcia = socket[0].pcmcia;
 820
 821         pr_debug("m8xx_pcmcia: SetSocket(%d, flags %#3.3x, Vcc %d, Vpp %d, "
 822                 "io_irq %d, csc_mask %#2.2x)\n", lsock, state->flags,
 823                 state->Vcc, state->Vpp, state->io_irq, state->csc_mask);
 824
 825         /* First, set voltage - bail out if invalid */
 826         if (voltage_set(lsock, state->Vcc, state->Vpp))
 827                 return -EINVAL;
 828
 829         /* Take care of reset... */
 830         if (state->flags & SS_RESET)
 831                 out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) | M8XX_PGCRX_CXRESET);   /* active high */
 832         else
 833                 out_be32(M8XX_PGCRX(lsock),
 834                          in_be32(M8XX_PGCRX(lsock)) & ~M8XX_PGCRX_CXRESET);
 835
 836         /* ... and output enable. */
 837
 838         /* The CxOE signal is connected to a 74541 on the ADS.
 839            I guess most other boards used the ADS as a reference.
 840            I tried to control the CxOE signal with SS_OUTPUT_ENA,
 841            but the reset signal seems connected via the 541.
 842            If the CxOE is left high are some signals tristated and
 843            no pullups are present -> the cards act weird.
 844            So right now the buffers are enabled if the power is on. */
 845
 846         if (state->Vcc || state->Vpp)
 847                 out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) & ~M8XX_PGCRX_CXOE);     /* active low */
 848         else
 849                 out_be32(M8XX_PGCRX(lsock),
 850                          in_be32(M8XX_PGCRX(lsock)) | M8XX_PGCRX_CXOE);
 851
 852         /*
 853          * We'd better turn off interrupts before
 854          * we mess with the events-table..
 855          */
 856
 857         spin_lock_irqsave(&events_lock, flags);
 858
 859         /*
 860          * Play around with the interrupt mask to be able to
 861          * give the events the generic pcmcia driver wants us to.
 862          */
 863
 864         e = &s->events[0];
 865         reg = 0;
 866
 867         if (state->csc_mask & SS_DETECT) {
 868                 e->eventbit = SS_DETECT;
 869                 reg |= e->regbit = (M8XX_PCMCIA_CD2(lsock)
 870                                     | M8XX_PCMCIA_CD1(lsock));
 871                 e++;
 872         }
 873         if (state->flags & SS_IOCARD) {
 874                 /*
 875                  * I/O card
 876                  */
 877                 if (state->csc_mask & SS_STSCHG) {
 878                         e->eventbit = SS_STSCHG;
 879                         reg |= e->regbit = M8XX_PCMCIA_BVD1(lsock);
 880                         e++;
 881                 }
 882                 /*
 883                  * If io_irq is non-zero we should enable irq.
 884                  */
 885                 if (state->io_irq) {
 886                         out_be32(M8XX_PGCRX(lsock),
 887                                  in_be32(M8XX_PGCRX(lsock)) |
 888                                  mk_int_int_mask(s->hwirq) << 24);
 889                         /*
 890                          * Strange thing here:
 891                          * The manual does not tell us which interrupt
 892                          * the sources generate.
 893                          * Anyhow, I found out that RDY_L generates IREQLVL.
 894                          *
 895                          * We use level triggerd interrupts, and they don't
 896                          * have to be cleared in PSCR in the interrupt handler.
 897                          */
 898                         reg |= M8XX_PCMCIA_RDY_L(lsock);
 899                 } else
 900                         out_be32(M8XX_PGCRX(lsock),
 901                                  in_be32(M8XX_PGCRX(lsock)) & 0x00ffffff);
 902         } else {
 903                 /*
 904                  * Memory card
 905                  */
 906                 if (state->csc_mask & SS_BATDEAD) {
 907                         e->eventbit = SS_BATDEAD;
 908                         reg |= e->regbit = M8XX_PCMCIA_BVD1(lsock);
 909                         e++;
 910                 }
 911                 if (state->csc_mask & SS_BATWARN) {
 912                         e->eventbit = SS_BATWARN;
 913                         reg |= e->regbit = M8XX_PCMCIA_BVD2(lsock);
 914                         e++;
 915                 }
 916                 /* What should I trigger on - low/high,raise,fall? */
 917                 if (state->csc_mask & SS_READY) {
 918                         e->eventbit = SS_READY;
 919                         reg |= e->regbit = 0;   //??
 920                         e++;
 921                 }
 922         }
 923
 924         e->regbit = 0;          /* terminate list */
 925
 926         /*
 927          * Clear the status changed .
 928          * Port A and Port B share the same port.
 929          * Writing ones will clear the bits.
 930          */
 931
 932         out_be32(&pcmcia->pcmc_pscr, reg);
 933
 934         /*
 935          * Write the mask.
 936          * Port A and Port B share the same port.
 937          * Need for read-modify-write.
 938          * Ones will enable the interrupt.
 939          */
 940
 941         reg |=
 942             in_be32(&pcmcia->
 943                     pcmc_per) & (M8XX_PCMCIA_MASK(0) | M8XX_PCMCIA_MASK(1));
 944         out_be32(&pcmcia->pcmc_per, reg);
 945
 946         spin_unlock_irqrestore(&events_lock, flags);
 947
 948         /* copy the struct and modify the copy */
 949
 950         s->state = *state;
 951
 952         return 0;
 953 }
 954
 955 static int m8xx_set_io_map(struct pcmcia_socket *sock, struct pccard_io_map *io)
 956 {
 957         int lsock = container_of(sock, struct socket_info, socket)->slot;
 958
 959         struct socket_info *s = &socket[lsock];
 960         struct pcmcia_win *w;
 961         unsigned int reg, winnr;
 962         pcmconf8xx_t *pcmcia = s->pcmcia;
 963
 964 #define M8XX_SIZE (io->stop - io->start + 1)
 965 #define M8XX_BASE (PCMCIA_IO_WIN_BASE + io->start)
 966
 967         pr_debug("m8xx_pcmcia: SetIOMap(%d, %d, %#2.2x, %d ns, "
 968                 "%#4.4llx-%#4.4llx)\n", lsock, io->map, io->flags,
 969                 io->speed, (unsigned long long)io->start,
 970                 (unsigned long long)io->stop);
 971
 972         if ((io->map >= PCMCIA_IO_WIN_NO) || (io->start > 0xffff)
 973             || (io->stop > 0xffff) || (io->stop < io->start))
 974                 return -EINVAL;
 975
 976         if ((reg = m8xx_get_graycode(M8XX_SIZE)) == -1)
 977                 return -EINVAL;
 978
 979         if (io->flags & MAP_ACTIVE) {
 980
 981                 pr_debug("m8xx_pcmcia: io->flags & MAP_ACTIVE\n");
 982
 983                 winnr = (PCMCIA_MEM_WIN_NO * PCMCIA_SOCKETS_NO)
 984                     + (lsock * PCMCIA_IO_WIN_NO) + io->map;
 985
 986                 /* setup registers */
 987
 988                 w = (void *)&pcmcia->pcmc_pbr0;
 989                 w += winnr;
 990
 991                 out_be32(&w->or, 0);    /* turn off window first */
 992                 out_be32(&w->br, M8XX_BASE);
 993
 994                 reg <<= 27;
 995                 reg |= M8XX_PCMCIA_POR_IO | (lsock << 2);
 996
 997                 reg |= m8xx_get_speed(io->speed, 1, s->bus_freq);
 998
 999                 if (io->flags & MAP_WRPROT)
1000                         reg |= M8XX_PCMCIA_POR_WRPROT;
1001
1002                 /*if(io->flags & (MAP_16BIT | MAP_AUTOSZ)) */
1003                 if (io->flags & MAP_16BIT)
1004                         reg |= M8XX_PCMCIA_POR_16BIT;
1005
1006                 if (io->flags & MAP_ACTIVE)
1007                         reg |= M8XX_PCMCIA_POR_VALID;
1008
1009                 out_be32(&w->or, reg);
1010
1011                 pr_debug("m8xx_pcmcia: Socket %u: Mapped io window %u at "
1012                         "%#8.8x, OR = %#8.8x.\n", lsock, io->map, w->br, w->or);
1013         } else {
1014                 /* shutdown IO window */
1015                 winnr = (PCMCIA_MEM_WIN_NO * PCMCIA_SOCKETS_NO)
1016                     + (lsock * PCMCIA_IO_WIN_NO) + io->map;
1017
1018                 /* setup registers */
1019
1020                 w = (void *)&pcmcia->pcmc_pbr0;
1021                 w += winnr;
1022
1023                 out_be32(&w->or, 0);    /* turn off window */
1024                 out_be32(&w->br, 0);    /* turn off base address */
1025
1026                 pr_debug("m8xx_pcmcia: Socket %u: Unmapped io window %u at "
1027                         "%#8.8x, OR = %#8.8x.\n", lsock, io->map, w->br, w->or);
1028         }
1029
1030         /* copy the struct and modify the copy */
1031         s->io_win[io->map] = *io;
1032         s->io_win[io->map].flags &= (MAP_WRPROT | MAP_16BIT | MAP_ACTIVE);
1033         pr_debug("m8xx_pcmcia: SetIOMap exit\n");
1034
1035         return 0;
1036 }
1037
1038 static int m8xx_set_mem_map(struct pcmcia_socket *sock,
1039                             struct pccard_mem_map *mem)
1040 {
1041         int lsock = container_of(sock, struct socket_info, socket)->slot;
1042         struct socket_info *s = &socket[lsock];
1043         struct pcmcia_win *w;
1044         struct pccard_mem_map *old;
1045         unsigned int reg, winnr;
1046         pcmconf8xx_t *pcmcia = s->pcmcia;
1047
1048         pr_debug("m8xx_pcmcia: SetMemMap(%d, %d, %#2.2x, %d ns, "
1049                 "%#5.5llx, %#5.5x)\n", lsock, mem->map, mem->flags,
1050                 mem->speed, (unsigned long long)mem->static_start,
1051                 mem->card_start);
1052
1053         if ((mem->map >= PCMCIA_MEM_WIN_NO)
1054 //          || ((mem->s) >= PCMCIA_MEM_WIN_SIZE)
1055             || (mem->card_start >= 0x04000000)
1056             || (mem->static_start & 0xfff)      /* 4KByte resolution */
1057             ||(mem->card_start & 0xfff))
1058                 return -EINVAL;
1059
1060         if ((reg = m8xx_get_graycode(PCMCIA_MEM_WIN_SIZE)) == -1) {
1061                 printk("Cannot set size to 0x%08x.\n", PCMCIA_MEM_WIN_SIZE);
1062                 return -EINVAL;
1063         }
1064         reg <<= 27;
1065
1066         winnr = (lsock * PCMCIA_MEM_WIN_NO) + mem->map;
1067
1068         /* Setup the window in the pcmcia controller */
1069
1070         w = (void *)&pcmcia->pcmc_pbr0;
1071         w += winnr;
1072
1073         reg |= lsock << 2;
1074
1075         reg |= m8xx_get_speed(mem->speed, 0, s->bus_freq);
1076
1077         if (mem->flags & MAP_ATTRIB)
1078                 reg |= M8XX_PCMCIA_POR_ATTRMEM;
1079
1080         if (mem->flags & MAP_WRPROT)
1081                 reg |= M8XX_PCMCIA_POR_WRPROT;
1082
1083         if (mem->flags & MAP_16BIT)
1084                 reg |= M8XX_PCMCIA_POR_16BIT;
1085
1086         if (mem->flags & MAP_ACTIVE)
1087                 reg |= M8XX_PCMCIA_POR_VALID;
1088
1089         out_be32(&w->or, reg);
1090
1091         pr_debug("m8xx_pcmcia: Socket %u: Mapped memory window %u at %#8.8x, "
1092                 "OR = %#8.8x.\n", lsock, mem->map, w->br, w->or);
1093
1094         if (mem->flags & MAP_ACTIVE) {
1095                 /* get the new base address */
1096                 mem->static_start = PCMCIA_MEM_WIN_BASE +
1097                     (PCMCIA_MEM_WIN_SIZE * winnr)
1098                     + mem->card_start;
1099         }
1100
1101         pr_debug("m8xx_pcmcia: SetMemMap(%d, %d, %#2.2x, %d ns, "
1102                 "%#5.5llx, %#5.5x)\n", lsock, mem->map, mem->flags,
1103                 mem->speed, (unsigned long long)mem->static_start,
1104                 mem->card_start);
1105
1106         /* copy the struct and modify the copy */
1107
1108         old = &s->mem_win[mem->map];
1109
1110         *old = *mem;
1111         old->flags &= (MAP_ATTRIB | MAP_WRPROT | MAP_16BIT | MAP_ACTIVE);
1112
1113         return 0;
1114 }
1115
1116 static int m8xx_sock_init(struct pcmcia_socket *sock)
1117 {
1118         int i;
1119         pccard_io_map io = { 0, 0, 0, 0, 1 };
1120         pccard_mem_map mem = { 0, 0, 0, 0, 0, 0 };
1121
1122         pr_debug("m8xx_pcmcia: sock_init(%d)\n", s);
1123
1124         m8xx_set_socket(sock, &dead_socket);
1125         for (i = 0; i < PCMCIA_IO_WIN_NO; i++) {
1126                 io.map = i;
1127                 m8xx_set_io_map(sock, &io);
1128         }
1129         for (i = 0; i < PCMCIA_MEM_WIN_NO; i++) {
1130                 mem.map = i;
1131                 m8xx_set_mem_map(sock, &mem);
1132         }
1133
1134         return 0;
1135
1136 }
1137
1138 static int m8xx_sock_suspend(struct pcmcia_socket *sock)
1139 {
1140         return m8xx_set_socket(sock, &dead_socket);
1141 }
1142
1143 static struct pccard_operations m8xx_services = {
1144         .init = m8xx_sock_init,
1145         .suspend = m8xx_sock_suspend,
1146         .get_status = m8xx_get_status,
1147         .set_socket = m8xx_set_socket,
1148         .set_io_map = m8xx_set_io_map,
1149         .set_mem_map = m8xx_set_mem_map,
1150 };
1151
1152 static int __init m8xx_probe(struct of_device *ofdev,
1153                              const struct of_device_id *match)
1154 {
1155         struct pcmcia_win *w;
1156         unsigned int i, m, hwirq;
1157         pcmconf8xx_t *pcmcia;
1158         int status;
1159         struct device_node *np = ofdev->dev.of_node;
1160
1161         pcmcia_info("%s\n", version);
1162
1163         pcmcia = of_iomap(np, 0);
1164         if (pcmcia == NULL)
1165                 return -EINVAL;
1166
1167         pcmcia_schlvl = irq_of_parse_and_map(np, 0);
1168         hwirq = irq_map[pcmcia_schlvl].hwirq;
1169         if (pcmcia_schlvl < 0) {
1170                 iounmap(pcmcia);
1171                 return -EINVAL;
1172         }
1173
1174         m8xx_pgcrx[0] = &pcmcia->pcmc_pgcra;
1175         m8xx_pgcrx[1] = &pcmcia->pcmc_pgcrb;
1176
1177         pcmcia_info(PCMCIA_BOARD_MSG " using " PCMCIA_SLOT_MSG
1178                     " with IRQ %u  (%d). \n", pcmcia_schlvl, hwirq);
1179
1180         /* Configure Status change interrupt */
1181
1182         if (request_irq(pcmcia_schlvl, m8xx_interrupt, IRQF_SHARED,
1183                         driver_name, socket)) {
1184                 pcmcia_error("Cannot allocate IRQ %u for SCHLVL!\n",
1185                              pcmcia_schlvl);
1186                 iounmap(pcmcia);
1187                 return -1;
1188         }
1189
1190         w = (void *)&pcmcia->pcmc_pbr0;
1191
1192         out_be32(&pcmcia->pcmc_pscr, M8XX_PCMCIA_MASK(0) | M8XX_PCMCIA_MASK(1));
1193         clrbits32(&pcmcia->pcmc_per, M8XX_PCMCIA_MASK(0) | M8XX_PCMCIA_MASK(1));
1194
1195         /* connect interrupt and disable CxOE */
1196
1197         out_be32(M8XX_PGCRX(0),
1198                  M8XX_PGCRX_CXOE | (mk_int_int_mask(hwirq) << 16));
1199         out_be32(M8XX_PGCRX(1),
1200                  M8XX_PGCRX_CXOE | (mk_int_int_mask(hwirq) << 16));
1201
1202         /* intialize the fixed memory windows */
1203
1204         for (i = 0; i < PCMCIA_SOCKETS_NO; i++) {
1205                 for (m = 0; m < PCMCIA_MEM_WIN_NO; m++) {
1206                         out_be32(&w->br, PCMCIA_MEM_WIN_BASE +
1207                                  (PCMCIA_MEM_WIN_SIZE
1208                                   * (m + i * PCMCIA_MEM_WIN_NO)));
1209
1210                         out_be32(&w->or, 0);    /* set to not valid */
1211
1212                         w++;
1213                 }
1214         }
1215
1216         /* turn off voltage */
1217         voltage_set(0, 0, 0);
1218         voltage_set(1, 0, 0);
1219
1220         /* Enable external hardware */
1221         hardware_enable(0);
1222         hardware_enable(1);
1223
1224         for (i = 0; i < PCMCIA_SOCKETS_NO; i++) {
1225                 socket[i].slot = i;
1226                 socket[i].socket.owner = THIS_MODULE;
1227                 socket[i].socket.features =
1228                     SS_CAP_PCCARD | SS_CAP_MEM_ALIGN | SS_CAP_STATIC_MAP;
1229                 socket[i].socket.irq_mask = 0x000;
1230                 socket[i].socket.map_size = 0x1000;
1231                 socket[i].socket.io_offset = 0;
1232                 socket[i].socket.pci_irq = pcmcia_schlvl;
1233                 socket[i].socket.ops = &m8xx_services;
1234                 socket[i].socket.resource_ops = &pccard_iodyn_ops;
1235                 socket[i].socket.cb_dev = NULL;
1236                 socket[i].socket.dev.parent = &ofdev->dev;
1237                 socket[i].pcmcia = pcmcia;
1238                 socket[i].bus_freq = ppc_proc_freq;
1239                 socket[i].hwirq = hwirq;
1240
1241         }
1242
1243         for (i = 0; i < PCMCIA_SOCKETS_NO; i++) {
1244                 status = pcmcia_register_socket(&socket[i].socket);
1245                 if (status < 0)
1246                         pcmcia_error("Socket register failed\n");
1247         }
1248
1249         return 0;
1250 }
1251
1252 static int m8xx_remove(struct of_device *ofdev)
1253 {
1254         u32 m, i;
1255         struct pcmcia_win *w;
1256         pcmconf8xx_t *pcmcia = socket[0].pcmcia;
1257
1258         for (i = 0; i < PCMCIA_SOCKETS_NO; i++) {
1259                 w = (void *)&pcmcia->pcmc_pbr0;
1260
1261                 out_be32(&pcmcia->pcmc_pscr, M8XX_PCMCIA_MASK(i));
1262                 out_be32(&pcmcia->pcmc_per,
1263                          in_be32(&pcmcia->pcmc_per) & ~M8XX_PCMCIA_MASK(i));
1264
1265                 /* turn off interrupt and disable CxOE */
1266                 out_be32(M8XX_PGCRX(i), M8XX_PGCRX_CXOE);
1267
1268                 /* turn off memory windows */
1269                 for (m = 0; m < PCMCIA_MEM_WIN_NO; m++) {
1270                         out_be32(&w->or, 0);    /* set to not valid */
1271                         w++;
1272                 }
1273
1274                 /* turn off voltage */
1275                 voltage_set(i, 0, 0);
1276
1277                 /* disable external hardware */
1278                 hardware_disable(i);
1279         }
1280         for (i = 0; i < PCMCIA_SOCKETS_NO; i++)
1281                 pcmcia_unregister_socket(&socket[i].socket);
1282         iounmap(pcmcia);
1283
1284         free_irq(pcmcia_schlvl, NULL);
1285
1286         return 0;
1287 }
1288
1289 static const struct of_device_id m8xx_pcmcia_match[] = {
1290         {
1291          .type = "pcmcia",
1292          .compatible = "fsl,pq-pcmcia",
1293          },
1294         {},
1295 };
1296
1297 MODULE_DEVICE_TABLE(of, m8xx_pcmcia_match);
1298
1299 static struct of_platform_driver m8xx_pcmcia_driver = {
1300         .driver = {
1301                 .name = driver_name,
1302                 .owner = THIS_MODULE,
1303                 .of_match_table = m8xx_pcmcia_match,
1304         },
1305         .probe = m8xx_probe,
1306         .remove = m8xx_remove,
1307 };
1308
1309 static int __init m8xx_init(void)
1310 {
1311         return of_register_platform_driver(&m8xx_pcmcia_driver);
1312 }
1313
1314 static void __exit m8xx_exit(void)
1315 {
1316         of_unregister_platform_driver(&m8xx_pcmcia_driver);
1317 }
1318
1319 module_init(m8xx_init);
1320 module_exit(m8xx_exit);