drivers/pcmcia/m32r_cfc.c

   1 /*
   2  *  drivers/pcmcia/m32r_cfc.c
   3  *
   4  *  Device driver for the CFC functionality of M32R.
   5  *
   6  *  Copyright (c) 2001, 2002, 2003, 2004
   7  *    Hiroyuki Kondo, Naoto Sugai, Hayato Fujiwara
   8  */
   9
  10 #include <linux/module.h>
  11 #include <linux/moduleparam.h>
  12 #include <linux/init.h>
  13 #include <linux/types.h>
  14 #include <linux/fcntl.h>
  15 #include <linux/string.h>
  16 #include <linux/kernel.h>
  17 #include <linux/errno.h>
  18 #include <linux/timer.h>
  19 #include <linux/ioport.h>
  20 #include <linux/delay.h>
  21 #include <linux/workqueue.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/bitops.h>
  25 #include <asm/irq.h>
  26 #include <asm/io.h>
  27 #include <asm/system.h>
  28
  29 #include <pcmcia/ss.h>
  30 #include <pcmcia/cs.h>
  31
  32 #undef MAX_IO_WIN       /* FIXME */
  33 #define MAX_IO_WIN 1
  34 #undef MAX_WIN          /* FIXME */
  35 #define MAX_WIN 1
  36
  37 #include "m32r_cfc.h"
  38
  39 /* Poll status interval -- 0 means default to interrupt */
  40 static int poll_interval = 0;
  41
  42 typedef enum pcc_space { as_none = 0, as_comm, as_attr, as_io } pcc_as_t;
  43
  44 typedef struct pcc_socket {
  45         u_short                 type, flags;
  46         struct pcmcia_socket    socket;
  47         unsigned int            number;
  48         unsigned int            ioaddr;
  49         u_long                  mapaddr;
  50         u_long                  base;   /* PCC register base */
  51         u_char                  cs_irq1, cs_irq2, intr;
  52         pccard_io_map           io_map[MAX_IO_WIN];
  53         pccard_mem_map          mem_map[MAX_WIN];
  54         u_char                  io_win;
  55         u_char                  mem_win;
  56         pcc_as_t                current_space;
  57         u_char                  last_iodbex;
  58 #ifdef CONFIG_PROC_FS
  59         struct proc_dir_entry *proc;
  60 #endif
  61 } pcc_socket_t;
  62
  63 static int pcc_sockets = 0;
  64 static pcc_socket_t socket[M32R_MAX_PCC] = {
  65         { 0, }, /* ... */
  66 };
  67
  68 /*====================================================================*/
  69
  70 static unsigned int pcc_get(u_short, unsigned int);
  71 static void pcc_set(u_short, unsigned int , unsigned int );
  72
  73 static DEFINE_SPINLOCK(pcc_lock);
  74
  75 #if !defined(CONFIG_PLAT_USRV)
  76 static inline u_long pcc_port2addr(unsigned long port, int size) {
  77         u_long addr = 0;
  78         u_long odd;
  79
  80         if (size == 1) {        /* byte access */
  81                 odd = (port&1) << 11;
  82                 port -= port & 1;
  83                 addr = CFC_IO_MAPBASE_BYTE - CFC_IOPORT_BASE + odd + port;
  84         } else if (size == 2)
  85                 addr = CFC_IO_MAPBASE_WORD - CFC_IOPORT_BASE + port;
  86
  87         return addr;
  88 }
  89 #else   /* CONFIG_PLAT_USRV */
  90 static inline u_long pcc_port2addr(unsigned long port, int size) {
  91         u_long odd;
  92         u_long addr = ((port - CFC_IOPORT_BASE) & 0xf000) << 8;
  93
  94         if (size == 1) {        /* byte access */
  95                 odd = port & 1;
  96                 port -= odd;
  97                 odd <<= 11;
  98                 addr = (addr | CFC_IO_MAPBASE_BYTE) + odd + (port & 0xfff);
  99         } else if (size == 2)   /* word access */
 100                 addr = (addr | CFC_IO_MAPBASE_WORD) + (port & 0xfff);
 101
 102         return addr;
 103 }
 104 #endif  /* CONFIG_PLAT_USRV */
 105
 106 void pcc_ioread_byte(int sock, unsigned long port, void *buf, size_t size,
 107         size_t nmemb, int flag)
 108 {
 109         u_long addr;
 110         unsigned char *bp = (unsigned char *)buf;
 111         unsigned long flags;
 112
 113         pr_debug("m32r_cfc: pcc_ioread_byte: sock=%d, port=%#lx, buf=%p, "
 114                  "size=%u, nmemb=%d, flag=%d\n",
 115                   sock, port, buf, size, nmemb, flag);
 116
 117         addr = pcc_port2addr(port, 1);
 118         if (!addr) {
 119                 printk("m32r_cfc:ioread_byte null port :%#lx\n",port);
 120                 return;
 121         }
 122         pr_debug("m32r_cfc: pcc_ioread_byte: addr=%#lx\n", addr);
 123
 124         spin_lock_irqsave(&pcc_lock, flags);
 125         /* read Byte */
 126         while (nmemb--)
 127                 *bp++ = readb(addr);
 128         spin_unlock_irqrestore(&pcc_lock, flags);
 129 }
 130
 131 void pcc_ioread_word(int sock, unsigned long port, void *buf, size_t size,
 132         size_t nmemb, int flag)
 133 {
 134         u_long addr;
 135         unsigned short *bp = (unsigned short *)buf;
 136         unsigned long flags;
 137
 138         pr_debug("m32r_cfc: pcc_ioread_word: sock=%d, port=%#lx, "
 139                  "buf=%p, size=%u, nmemb=%d, flag=%d\n",
 140                  sock, port, buf, size, nmemb, flag);
 141
 142         if (size != 2)
 143                 printk("m32r_cfc: ioread_word :illigal size %u : %#lx\n", size,
 144                         port);
 145         if (size == 9)
 146                 printk("m32r_cfc: ioread_word :insw \n");
 147
 148         addr = pcc_port2addr(port, 2);
 149         if (!addr) {
 150                 printk("m32r_cfc:ioread_word null port :%#lx\n",port);
 151                 return;
 152         }
 153         pr_debug("m32r_cfc: pcc_ioread_word: addr=%#lx\n", addr);
 154
 155         spin_lock_irqsave(&pcc_lock, flags);
 156         /* read Word */
 157         while (nmemb--)
 158                 *bp++ = readw(addr);
 159         spin_unlock_irqrestore(&pcc_lock, flags);
 160 }
 161
 162 void pcc_iowrite_byte(int sock, unsigned long port, void *buf, size_t size,
 163         size_t nmemb, int flag)
 164 {
 165         u_long addr;
 166         unsigned char *bp = (unsigned char *)buf;
 167         unsigned long flags;
 168
 169         pr_debug("m32r_cfc: pcc_iowrite_byte: sock=%d, port=%#lx, "
 170                  "buf=%p, size=%u, nmemb=%d, flag=%d\n",
 171                  sock, port, buf, size, nmemb, flag);
 172
 173         /* write Byte */
 174         addr = pcc_port2addr(port, 1);
 175         if (!addr) {
 176                 printk("m32r_cfc:iowrite_byte null port:%#lx\n",port);
 177                 return;
 178         }
 179         pr_debug("m32r_cfc: pcc_iowrite_byte: addr=%#lx\n", addr);
 180
 181         spin_lock_irqsave(&pcc_lock, flags);
 182         while (nmemb--)
 183                 writeb(*bp++, addr);
 184         spin_unlock_irqrestore(&pcc_lock, flags);
 185 }
 186
 187 void pcc_iowrite_word(int sock, unsigned long port, void *buf, size_t size,
 188         size_t nmemb, int flag)
 189 {
 190         u_long addr;
 191         unsigned short *bp = (unsigned short *)buf;
 192         unsigned long flags;
 193
 194         pr_debug("m32r_cfc: pcc_iowrite_word: sock=%d, port=%#lx, "
 195                  "buf=%p, size=%u, nmemb=%d, flag=%d\n",
 196                  sock, port, buf, size, nmemb, flag);
 197
 198         if(size != 2)
 199                 printk("m32r_cfc: iowrite_word :illigal size %u : %#lx\n",
 200                         size, port);
 201         if(size == 9)
 202                 printk("m32r_cfc: iowrite_word :outsw \n");
 203
 204         addr = pcc_port2addr(port, 2);
 205         if (!addr) {
 206                 printk("m32r_cfc:iowrite_word null addr :%#lx\n",port);
 207                 return;
 208         }
 209 #if 1
 210         if (addr & 1) {
 211                 printk("m32r_cfc:iowrite_word port addr (%#lx):%#lx\n", port,
 212                         addr);
 213                 return;
 214         }
 215 #endif
 216         pr_debug("m32r_cfc: pcc_iowrite_word: addr=%#lx\n", addr);
 217
 218         spin_lock_irqsave(&pcc_lock, flags);
 219         while (nmemb--)
 220                 writew(*bp++, addr);
 221         spin_unlock_irqrestore(&pcc_lock, flags);
 222 }
 223
 224 /*====================================================================*/
 225
 226 #define IS_REGISTERED           0x2000
 227 #define IS_ALIVE                0x8000
 228
 229 typedef struct pcc_t {
 230         char                    *name;
 231         u_short                 flags;
 232 } pcc_t;
 233
 234 static pcc_t pcc[] = {
 235 #if !defined(CONFIG_PLAT_USRV)
 236         { "m32r_cfc", 0 }, { "", 0 },
 237 #else   /* CONFIG_PLAT_USRV */
 238         { "m32r_cfc", 0 }, { "m32r_cfc", 0 }, { "m32r_cfc", 0 },
 239         { "m32r_cfc", 0 }, { "m32r_cfc", 0 }, { "", 0 },
 240 #endif  /* CONFIG_PLAT_USRV */
 241 };
 242
 243 static irqreturn_t pcc_interrupt(int, void *);
 244
 245 /*====================================================================*/
 246
 247 static struct timer_list poll_timer;
 248
 249 static unsigned int pcc_get(u_short sock, unsigned int reg)
 250 {
 251         unsigned int val = inw(reg);
 252         pr_debug("m32r_cfc: pcc_get: reg(0x%08x)=0x%04x\n", reg, val);
 253         return val;
 254 }
 255
 256
 257 static void pcc_set(u_short sock, unsigned int reg, unsigned int data)
 258 {
 259         outw(data, reg);
 260         pr_debug("m32r_cfc: pcc_set: reg(0x%08x)=0x%04x\n", reg, data);
 261 }
 262
 263 /*======================================================================
 264
 265         See if a card is present, powered up, in IO mode, and already
 266         bound to a (non PC Card) Linux driver.  We leave these alone.
 267
 268         We make an exception for cards that seem to be serial devices.
 269
 270 ======================================================================*/
 271
 272 static int __init is_alive(u_short sock)
 273 {
 274         unsigned int stat;
 275
 276         pr_debug("m32r_cfc: is_alive:\n");
 277
 278         printk("CF: ");
 279         stat = pcc_get(sock, (unsigned int)PLD_CFSTS);
 280         if (!stat)
 281                 printk("No ");
 282         printk("Card is detected at socket %d : stat = 0x%08x\n", sock, stat);
 283         pr_debug("m32r_cfc: is_alive: sock stat is 0x%04x\n", stat);
 284
 285         return 0;
 286 }
 287
 288 static void add_pcc_socket(ulong base, int irq, ulong mapaddr,
 289                            unsigned int ioaddr)
 290 {
 291         pcc_socket_t *t = &socket[pcc_sockets];
 292
 293         pr_debug("m32r_cfc: add_pcc_socket: base=%#lx, irq=%d, "
 294                  "mapaddr=%#lx, ioaddr=%08x\n",
 295                  base, irq, mapaddr, ioaddr);
 296
 297         /* add sockets */
 298         t->ioaddr = ioaddr;
 299         t->mapaddr = mapaddr;
 300 #if !defined(CONFIG_PLAT_USRV)
 301         t->base = 0;
 302         t->flags = 0;
 303         t->cs_irq1 = irq;               // insert irq
 304         t->cs_irq2 = irq + 1;           // eject irq
 305 #else   /* CONFIG_PLAT_USRV */
 306         t->base = base;
 307         t->flags = 0;
 308         t->cs_irq1 = 0;                 // insert irq
 309         t->cs_irq2 = 0;                 // eject irq
 310 #endif  /* CONFIG_PLAT_USRV */
 311
 312         if (is_alive(pcc_sockets))
 313                 t->flags |= IS_ALIVE;
 314
 315         /* add pcc */
 316 #if !defined(CONFIG_PLAT_USRV)
 317         request_region((unsigned int)PLD_CFRSTCR, 0x20, "m32r_cfc");
 318 #else   /* CONFIG_PLAT_USRV */
 319         {
 320                 unsigned int reg_base;
 321
 322                 reg_base = (unsigned int)PLD_CFRSTCR;
 323                 reg_base |= pcc_sockets << 8;
 324                 request_region(reg_base, 0x20, "m32r_cfc");
 325         }
 326 #endif  /* CONFIG_PLAT_USRV */
 327         printk(KERN_INFO "  %s ", pcc[pcc_sockets].name);
 328         printk("pcc at 0x%08lx\n", t->base);
 329
 330         /* Update socket interrupt information, capabilities */
 331         t->socket.features |= (SS_CAP_PCCARD | SS_CAP_STATIC_MAP);
 332         t->socket.map_size = M32R_PCC_MAPSIZE;
 333         t->socket.io_offset = ioaddr;   /* use for io access offset */
 334         t->socket.irq_mask = 0;
 335 #if !defined(CONFIG_PLAT_USRV)
 336         t->socket.pci_irq = PLD_IRQ_CFIREQ ;    /* card interrupt */
 337 #else   /* CONFIG_PLAT_USRV */
 338         t->socket.pci_irq = PLD_IRQ_CF0 + pcc_sockets;
 339 #endif  /* CONFIG_PLAT_USRV */
 340
 341 #ifndef CONFIG_PLAT_USRV
 342         /* insert interrupt */
 343         request_irq(irq, pcc_interrupt, 0, "m32r_cfc", pcc_interrupt);
 344 #ifndef CONFIG_PLAT_MAPPI3
 345         /* eject interrupt */
 346         request_irq(irq+1, pcc_interrupt, 0, "m32r_cfc", pcc_interrupt);
 347 #endif
 348         pr_debug("m32r_cfc: enable CFMSK, RDYSEL\n");
 349         pcc_set(pcc_sockets, (unsigned int)PLD_CFIMASK, 0x01);
 350 #endif  /* CONFIG_PLAT_USRV */
 351 #if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_USRV) || defined(CONFIG_PLAT_OPSPUT)
 352         pcc_set(pcc_sockets, (unsigned int)PLD_CFCR1, 0x0200);
 353 #endif
 354         pcc_sockets++;
 355
 356         return;
 357 }
 358
 359
 360 /*====================================================================*/
 361
 362 static irqreturn_t pcc_interrupt(int irq, void *dev)
 363 {
 364         int i;
 365         u_int events = 0;
 366         int handled = 0;
 367
 368         pr_debug("m32r_cfc: pcc_interrupt: irq=%d, dev=%p\n", irq, dev);
 369         for (i = 0; i < pcc_sockets; i++) {
 370                 if (socket[i].cs_irq1 != irq && socket[i].cs_irq2 != irq)
 371                         continue;
 372
 373                 handled = 1;
 374                 pr_debug("m32r_cfc: pcc_interrupt: socket %d irq 0x%02x ",
 375                         i, irq);
 376                 events |= SS_DETECT;    /* insert or eject */
 377                 if (events)
 378                         pcmcia_parse_events(&socket[i].socket, events);
 379         }
 380         pr_debug("m32r_cfc: pcc_interrupt: done\n");
 381
 382         return IRQ_RETVAL(handled);
 383 } /* pcc_interrupt */
 384
 385 static void pcc_interrupt_wrapper(u_long data)
 386 {
 387         pr_debug("m32r_cfc: pcc_interrupt_wrapper:\n");
 388         pcc_interrupt(0, NULL);
 389         init_timer(&poll_timer);
 390         poll_timer.expires = jiffies + poll_interval;
 391         add_timer(&poll_timer);
 392 }
 393
 394 /*====================================================================*/
 395
 396 static int _pcc_get_status(u_short sock, u_int *value)
 397 {
 398         u_int status;
 399
 400         pr_debug("m32r_cfc: _pcc_get_status:\n");
 401         status = pcc_get(sock, (unsigned int)PLD_CFSTS);
 402         *value = (status) ? SS_DETECT : 0;
 403         pr_debug("m32r_cfc: _pcc_get_status: status=0x%08x\n", status);
 404
 405 #if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_USRV) || defined(CONFIG_PLAT_OPSPUT)
 406         if ( status ) {
 407                 /* enable CF power */
 408                 status = inw((unsigned int)PLD_CPCR);
 409                 if (!(status & PLD_CPCR_CF)) {
 410                         pr_debug("m32r_cfc: _pcc_get_status: "
 411                                  "power on (CPCR=0x%08x)\n", status);
 412                         status |= PLD_CPCR_CF;
 413                         outw(status, (unsigned int)PLD_CPCR);
 414                         udelay(100);
 415                 }
 416                 *value |= SS_POWERON;
 417
 418                 pcc_set(sock, (unsigned int)PLD_CFBUFCR,0);/* enable buffer */
 419                 udelay(100);
 420
 421                 *value |= SS_READY;             /* always ready */
 422                 *value |= SS_3VCARD;
 423         } else {
 424                 /* disable CF power */
 425                 status = inw((unsigned int)PLD_CPCR);
 426                 status &= ~PLD_CPCR_CF;
 427                 outw(status, (unsigned int)PLD_CPCR);
 428                 udelay(100);
 429                 pr_debug("m32r_cfc: _pcc_get_status: "
 430                          "power off (CPCR=0x%08x)\n", status);
 431         }
 432 #elif defined(CONFIG_PLAT_MAPPI2) || defined(CONFIG_PLAT_MAPPI3)
 433         if ( status ) {
 434                 status = pcc_get(sock, (unsigned int)PLD_CPCR);
 435                 if (status == 0) { /* power off */
 436                         pcc_set(sock, (unsigned int)PLD_CPCR, 1);
 437                         pcc_set(sock, (unsigned int)PLD_CFBUFCR,0); /* force buffer off for ZA-36 */
 438                         udelay(50);
 439                 }
 440                 *value |= SS_POWERON;
 441
 442                 pcc_set(sock, (unsigned int)PLD_CFBUFCR,0);
 443                 udelay(50);
 444                 pcc_set(sock, (unsigned int)PLD_CFRSTCR, 0x0101);
 445                 udelay(25); /* for IDE reset */
 446                 pcc_set(sock, (unsigned int)PLD_CFRSTCR, 0x0100);
 447                 mdelay(2);  /* for IDE reset */
 448
 449                 *value |= SS_READY;
 450                 *value |= SS_3VCARD;
 451         } else {
 452                 /* disable CF power */
 453                 pcc_set(sock, (unsigned int)PLD_CPCR, 0);
 454                 udelay(100);
 455                 pr_debug("m32r_cfc: _pcc_get_status: "
 456                          "power off (CPCR=0x%08x)\n", status);
 457         }
 458 #else
 459 #error no platform configuration
 460 #endif
 461         pr_debug("m32r_cfc: _pcc_get_status: GetStatus(%d) = %#4.4x\n",
 462                  sock, *value);
 463         return 0;
 464 } /* _get_status */
 465
 466 /*====================================================================*/
 467
 468 static int _pcc_set_socket(u_short sock, socket_state_t *state)
 469 {
 470         pr_debug("m32r_cfc: SetSocket(%d, flags %#3.3x, Vcc %d, Vpp %d, "
 471                   "io_irq %d, csc_mask %#2.2x)\n", sock, state->flags,
 472                   state->Vcc, state->Vpp, state->io_irq, state->csc_mask);
 473
 474 #if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_USRV) || defined(CONFIG_PLAT_OPSPUT) || defined(CONFIG_PLAT_MAPPI2) || defined(CONFIG_PLAT_MAPPI3)
 475         if (state->Vcc) {
 476                 if ((state->Vcc != 50) && (state->Vcc != 33))
 477                         return -EINVAL;
 478                 /* accept 5V and 3.3V */
 479         }
 480 #endif
 481         if (state->flags & SS_RESET) {
 482                 pr_debug(":RESET\n");
 483                 pcc_set(sock,(unsigned int)PLD_CFRSTCR,0x101);
 484         }else{
 485                 pcc_set(sock,(unsigned int)PLD_CFRSTCR,0x100);
 486         }
 487         if (state->flags & SS_OUTPUT_ENA){
 488                 pr_debug(":OUTPUT_ENA\n");
 489                 /* bit clear */
 490                 pcc_set(sock,(unsigned int)PLD_CFBUFCR,0);
 491         } else {
 492                 pcc_set(sock,(unsigned int)PLD_CFBUFCR,1);
 493         }
 494
 495         if(state->flags & SS_IOCARD){
 496                 pr_debug(":IOCARD");
 497         }
 498         if (state->flags & SS_PWR_AUTO) {
 499                 pr_debug(":PWR_AUTO");
 500         }
 501         if (state->csc_mask & SS_DETECT)
 502                 pr_debug(":csc-SS_DETECT");
 503         if (state->flags & SS_IOCARD) {
 504                 if (state->csc_mask & SS_STSCHG)
 505                         pr_debug(":STSCHG");
 506         } else {
 507                 if (state->csc_mask & SS_BATDEAD)
 508                         pr_debug(":BATDEAD");
 509                 if (state->csc_mask & SS_BATWARN)
 510                         pr_debug(":BATWARN");
 511                 if (state->csc_mask & SS_READY)
 512                         pr_debug(":READY");
 513         }
 514         pr_debug("\n");
 515         return 0;
 516 } /* _set_socket */
 517
 518 /*====================================================================*/
 519
 520 static int _pcc_set_io_map(u_short sock, struct pccard_io_map *io)
 521 {
 522         u_char map;
 523
 524         pr_debug("m32r_cfc: SetIOMap(%d, %d, %#2.2x, %d ns, "
 525                   "%#llx-%#llx)\n", sock, io->map, io->flags,
 526                   io->speed, (unsigned long long)io->start,
 527                   (unsigned long long)io->stop);
 528         map = io->map;
 529
 530         return 0;
 531 } /* _set_io_map */
 532
 533 /*====================================================================*/
 534
 535 static int _pcc_set_mem_map(u_short sock, struct pccard_mem_map *mem)
 536 {
 537
 538         u_char map = mem->map;
 539         u_long addr;
 540         pcc_socket_t *t = &socket[sock];
 541
 542         pr_debug("m32r_cfc: SetMemMap(%d, %d, %#2.2x, %d ns, "
 543                  "%#llx, %#x)\n", sock, map, mem->flags,
 544                  mem->speed, (unsigned long long)mem->static_start,
 545                  mem->card_start);
 546
 547         /*
 548          * sanity check
 549          */
 550         if ((map > MAX_WIN) || (mem->card_start > 0x3ffffff)){
 551                 return -EINVAL;
 552         }
 553
 554         /*
 555          * de-activate
 556          */
 557         if ((mem->flags & MAP_ACTIVE) == 0) {
 558                 t->current_space = as_none;
 559                 return 0;
 560         }
 561
 562         /*
 563          * Set mode
 564          */
 565         if (mem->flags & MAP_ATTRIB) {
 566                 t->current_space = as_attr;
 567         } else {
 568                 t->current_space = as_comm;
 569         }
 570
 571         /*
 572          * Set address
 573          */
 574         addr = t->mapaddr + (mem->card_start & M32R_PCC_MAPMASK);
 575         mem->static_start = addr + mem->card_start;
 576
 577         return 0;
 578
 579 } /* _set_mem_map */
 580
 581 #if 0 /* driver model ordering issue */
 582 /*======================================================================
 583
 584         Routines for accessing socket information and register dumps via
 585         /proc/bus/pccard/...
 586
 587 ======================================================================*/
 588
 589 static ssize_t show_info(struct class_device *class_dev, char *buf)
 590 {
 591         pcc_socket_t *s = container_of(class_dev, struct pcc_socket,
 592                 socket.dev);
 593
 594         return sprintf(buf, "type:     %s\nbase addr:    0x%08lx\n",
 595                 pcc[s->type].name, s->base);
 596 }
 597
 598 static ssize_t show_exca(struct class_device *class_dev, char *buf)
 599 {
 600         /* FIXME */
 601
 602         return 0;
 603 }
 604
 605 static CLASS_DEVICE_ATTR(info, S_IRUGO, show_info, NULL);
 606 static CLASS_DEVICE_ATTR(exca, S_IRUGO, show_exca, NULL);
 607 #endif
 608
 609 /*====================================================================*/
 610
 611 /* this is horribly ugly... proper locking needs to be done here at
 612  * some time... */
 613 #define LOCKED(x) do {                                  \
 614         int retval;                                     \
 615         unsigned long flags;                            \
 616         spin_lock_irqsave(&pcc_lock, flags);            \
 617         retval = x;                                     \
 618         spin_unlock_irqrestore(&pcc_lock, flags);       \
 619         return retval;                                  \
 620 } while (0)
 621
 622
 623 static int pcc_get_status(struct pcmcia_socket *s, u_int *value)
 624 {
 625         unsigned int sock = container_of(s, struct pcc_socket, socket)->number;
 626
 627         if (socket[sock].flags & IS_ALIVE) {
 628                 dev_dbg(&s->dev, "pcc_get_status: sock(%d) -EINVAL\n", sock);
 629                 *value = 0;
 630                 return -EINVAL;
 631         }
 632         dev_dbg(&s->dev, "pcc_get_status: sock(%d)\n", sock);
 633         LOCKED(_pcc_get_status(sock, value));
 634 }
 635
 636 static int pcc_set_socket(struct pcmcia_socket *s, socket_state_t *state)
 637 {
 638         unsigned int sock = container_of(s, struct pcc_socket, socket)->number;
 639
 640         if (socket[sock].flags & IS_ALIVE) {
 641                 dev_dbg(&s->dev, "pcc_set_socket: sock(%d) -EINVAL\n", sock);
 642                 return -EINVAL;
 643         }
 644         dev_dbg(&s->dev, "pcc_set_socket: sock(%d)\n", sock);
 645         LOCKED(_pcc_set_socket(sock, state));
 646 }
 647
 648 static int pcc_set_io_map(struct pcmcia_socket *s, struct pccard_io_map *io)
 649 {
 650         unsigned int sock = container_of(s, struct pcc_socket, socket)->number;
 651
 652         if (socket[sock].flags & IS_ALIVE) {
 653                 dev_dbg(&s->dev, "pcc_set_io_map: sock(%d) -EINVAL\n", sock);
 654                 return -EINVAL;
 655         }
 656         dev_dbg(&s->dev, "pcc_set_io_map: sock(%d)\n", sock);
 657         LOCKED(_pcc_set_io_map(sock, io));
 658 }
 659
 660 static int pcc_set_mem_map(struct pcmcia_socket *s, struct pccard_mem_map *mem)
 661 {
 662         unsigned int sock = container_of(s, struct pcc_socket, socket)->number;
 663
 664         if (socket[sock].flags & IS_ALIVE) {
 665                 dev_dbg(&s->dev, "pcc_set_mem_map: sock(%d) -EINVAL\n", sock);
 666                 return -EINVAL;
 667         }
 668         dev_dbg(&s->dev, "pcc_set_mem_map: sock(%d)\n", sock);
 669         LOCKED(_pcc_set_mem_map(sock, mem));
 670 }
 671
 672 static int pcc_init(struct pcmcia_socket *s)
 673 {
 674         dev_dbg(&s->dev, "pcc_init()\n");
 675         return 0;
 676 }
 677
 678 static struct pccard_operations pcc_operations = {
 679         .init                   = pcc_init,
 680         .get_status             = pcc_get_status,
 681         .set_socket             = pcc_set_socket,
 682         .set_io_map             = pcc_set_io_map,
 683         .set_mem_map            = pcc_set_mem_map,
 684 };
 685
 686
 687 /*====================================================================*/
 688
 689 static struct platform_driver pcc_driver = {
 690         .driver = {
 691                 .name           = "cfc",
 692                 .owner          = THIS_MODULE,
 693         },
 694 };
 695
 696 static struct platform_device pcc_device = {
 697         .name = "cfc",
 698         .id = 0,
 699 };
 700
 701 /*====================================================================*/
 702
 703 static int __init init_m32r_pcc(void)
 704 {
 705         int i, ret;
 706
 707         ret = platform_driver_register(&pcc_driver);
 708         if (ret)
 709                 return ret;
 710
 711         ret = platform_device_register(&pcc_device);
 712         if (ret){
 713                 platform_driver_unregister(&pcc_driver);
 714                 return ret;
 715         }
 716
 717 #if defined(CONFIG_PLAT_MAPPI2) || defined(CONFIG_PLAT_MAPPI3)
 718         pcc_set(0, (unsigned int)PLD_CFCR0, 0x0f0f);
 719         pcc_set(0, (unsigned int)PLD_CFCR1, 0x0200);
 720 #endif
 721
 722         pcc_sockets = 0;
 723
 724 #if !defined(CONFIG_PLAT_USRV)
 725         add_pcc_socket(M32R_PCC0_BASE, PLD_IRQ_CFC_INSERT, CFC_ATTR_MAPBASE,
 726                        CFC_IOPORT_BASE);
 727 #else   /* CONFIG_PLAT_USRV */
 728         {
 729                 ulong base, mapaddr;
 730                 unsigned int ioaddr;
 731
 732                 for (i = 0 ; i < M32R_MAX_PCC ; i++) {
 733                         base = (ulong)PLD_CFRSTCR;
 734                         base = base | (i << 8);
 735                         ioaddr = (i + 1) << 12;
 736                         mapaddr = CFC_ATTR_MAPBASE | (i << 20);
 737                         add_pcc_socket(base, 0, mapaddr, ioaddr);
 738                 }
 739         }
 740 #endif  /* CONFIG_PLAT_USRV */
 741
 742         if (pcc_sockets == 0) {
 743                 printk("socket is not found.\n");
 744                 platform_device_unregister(&pcc_device);
 745                 platform_driver_unregister(&pcc_driver);
 746                 return -ENODEV;
 747         }
 748
 749         /* Set up interrupt handler(s) */
 750
 751         for (i = 0 ; i < pcc_sockets ; i++) {
 752                 socket[i].socket.dev.parent = &pcc_device.dev;
 753                 socket[i].socket.ops = &pcc_operations;
 754                 socket[i].socket.resource_ops = &pccard_static_ops;
 755                 socket[i].socket.owner = THIS_MODULE;
 756                 socket[i].number = i;
 757                 ret = pcmcia_register_socket(&socket[i].socket);
 758                 if (!ret)
 759                         socket[i].flags |= IS_REGISTERED;
 760
 761 #if 0   /* driver model ordering issue */
 762                 class_device_create_file(&socket[i].socket.dev,
 763                                          &class_device_attr_info);
 764                 class_device_create_file(&socket[i].socket.dev,
 765                                          &class_device_attr_exca);
 766 #endif
 767         }
 768
 769         /* Finally, schedule a polling interrupt */
 770         if (poll_interval != 0) {
 771                 poll_timer.function = pcc_interrupt_wrapper;
 772                 poll_timer.data = 0;
 773                 init_timer(&poll_timer);
 774                 poll_timer.expires = jiffies + poll_interval;
 775                 add_timer(&poll_timer);
 776         }
 777
 778         return 0;
 779 } /* init_m32r_pcc */
 780
 781 static void __exit exit_m32r_pcc(void)
 782 {
 783         int i;
 784
 785         for (i = 0; i < pcc_sockets; i++)
 786                 if (socket[i].flags & IS_REGISTERED)
 787                         pcmcia_unregister_socket(&socket[i].socket);
 788
 789         platform_device_unregister(&pcc_device);
 790         if (poll_interval != 0)
 791                 del_timer_sync(&poll_timer);
 792
 793         platform_driver_unregister(&pcc_driver);
 794 } /* exit_m32r_pcc */
 795
 796 module_init(init_m32r_pcc);
 797 module_exit(exit_m32r_pcc);
 798 MODULE_LICENSE("Dual MPL/GPL");
 799 /*====================================================================*/