drivers/edac/edac_core.h

   1 /*
   2  * Defines, structures, APIs for edac_core module
   3  *
   4  * (C) 2007 Linux Networx (http://lnxi.com)
   5  * This file may be distributed under the terms of the
   6  * GNU General Public License.
   7  *
   8  * Written by Thayne Harbaugh
   9  * Based on work by Dan Hollis <goemon at anime dot net> and others.
  10  *      http://www.anime.net/~goemon/linux-ecc/
  11  *
  12  * NMI handling support added by
  13  *     Dave Peterson <dsp@llnl.gov> <dave_peterson@pobox.com>
  14  *
  15  * Refactored for multi-source files:
  16  *      Doug Thompson <norsk5@xmission.com>
  17  *
  18  */
  19
  20 #ifndef _EDAC_CORE_H_
  21 #define _EDAC_CORE_H_
  22
  23 #include <linux/kernel.h>
  24 #include <linux/types.h>
  25 #include <linux/module.h>
  26 #include <linux/spinlock.h>
  27 #include <linux/smp.h>
  28 #include <linux/pci.h>
  29 #include <linux/time.h>
  30 #include <linux/nmi.h>
  31 #include <linux/rcupdate.h>
  32 #include <linux/completion.h>
  33 #include <linux/kobject.h>
  34 #include <linux/platform_device.h>
  35 #include <linux/sysdev.h>
  36 #include <linux/workqueue.h>
  37
  38 #define EDAC_MC_LABEL_LEN       31
  39 #define EDAC_DEVICE_NAME_LEN    31
  40 #define EDAC_ATTRIB_VALUE_LEN   15
  41 #define MC_PROC_NAME_MAX_LEN    7
  42
  43 #if PAGE_SHIFT < 20
  44 #define PAGES_TO_MiB( pages )   ( ( pages ) >> ( 20 - PAGE_SHIFT ) )
  45 #else                           /* PAGE_SHIFT > 20 */
  46 #define PAGES_TO_MiB( pages )   ( ( pages ) << ( PAGE_SHIFT - 20 ) )
  47 #endif
  48
  49 #define edac_printk(level, prefix, fmt, arg...) \
  50         printk(level "EDAC " prefix ": " fmt, ##arg)
  51
  52 #define edac_mc_printk(mci, level, fmt, arg...) \
  53         printk(level "EDAC MC%d: " fmt, mci->mc_idx, ##arg)
  54
  55 #define edac_mc_chipset_printk(mci, level, prefix, fmt, arg...) \
  56         printk(level "EDAC " prefix " MC%d: " fmt, mci->mc_idx, ##arg)
  57
  58 #define edac_device_printk(ctl, level, fmt, arg...) \
  59         printk(level "EDAC DEVICE%d: " fmt, ctl->dev_idx, ##arg)
  60
  61 #define edac_pci_printk(ctl, level, fmt, arg...) \
  62         printk(level "EDAC PCI%d: " fmt, ctl->pci_idx, ##arg)
  63
  64 /* prefixes for edac_printk() and edac_mc_printk() */
  65 #define EDAC_MC "MC"
  66 #define EDAC_PCI "PCI"
  67 #define EDAC_DEBUG "DEBUG"
  68
  69 #ifdef CONFIG_EDAC_DEBUG
  70 extern int edac_debug_level;
  71 extern const char *edac_mem_types[];
  72
  73 #define edac_debug_printk(level, fmt, arg...)                           \
  74         do {                                                            \
  75                 if (level <= edac_debug_level)                          \
  76                         edac_printk(KERN_DEBUG, EDAC_DEBUG,             \
  77                                     "%s: " fmt, __func__, ##arg);       \
  78         } while (0)
  79
  80 #define debugf0( ... ) edac_debug_printk(0, __VA_ARGS__ )
  81 #define debugf1( ... ) edac_debug_printk(1, __VA_ARGS__ )
  82 #define debugf2( ... ) edac_debug_printk(2, __VA_ARGS__ )
  83 #define debugf3( ... ) edac_debug_printk(3, __VA_ARGS__ )
  84 #define debugf4( ... ) edac_debug_printk(4, __VA_ARGS__ )
  85
  86 #else                           /* !CONFIG_EDAC_DEBUG */
  87
  88 #define debugf0( ... )
  89 #define debugf1( ... )
  90 #define debugf2( ... )
  91 #define debugf3( ... )
  92 #define debugf4( ... )
  93
  94 #endif                          /* !CONFIG_EDAC_DEBUG */
  95
  96 #define PCI_VEND_DEV(vend, dev) PCI_VENDOR_ID_ ## vend, \
  97         PCI_DEVICE_ID_ ## vend ## _ ## dev
  98
  99 #define edac_dev_name(dev) (dev)->dev_name
 100
 101 /* memory devices */
 102 enum dev_type {
 103         DEV_UNKNOWN = 0,
 104         DEV_X1,
 105         DEV_X2,
 106         DEV_X4,
 107         DEV_X8,
 108         DEV_X16,
 109         DEV_X32,                /* Do these parts exist? */
 110         DEV_X64                 /* Do these parts exist? */
 111 };
 112
 113 #define DEV_FLAG_UNKNOWN        BIT(DEV_UNKNOWN)
 114 #define DEV_FLAG_X1             BIT(DEV_X1)
 115 #define DEV_FLAG_X2             BIT(DEV_X2)
 116 #define DEV_FLAG_X4             BIT(DEV_X4)
 117 #define DEV_FLAG_X8             BIT(DEV_X8)
 118 #define DEV_FLAG_X16            BIT(DEV_X16)
 119 #define DEV_FLAG_X32            BIT(DEV_X32)
 120 #define DEV_FLAG_X64            BIT(DEV_X64)
 121
 122 /* memory types */
 123 enum mem_type {
 124         MEM_EMPTY = 0,          /* Empty csrow */
 125         MEM_RESERVED,           /* Reserved csrow type */
 126         MEM_UNKNOWN,            /* Unknown csrow type */
 127         MEM_FPM,                /* Fast page mode */
 128         MEM_EDO,                /* Extended data out */
 129         MEM_BEDO,               /* Burst Extended data out */
 130         MEM_SDR,                /* Single data rate SDRAM */
 131         MEM_RDR,                /* Registered single data rate SDRAM */
 132         MEM_DDR,                /* Double data rate SDRAM */
 133         MEM_RDDR,               /* Registered Double data rate SDRAM */
 134         MEM_RMBS,               /* Rambus DRAM */
 135         MEM_DDR2,               /* DDR2 RAM */
 136         MEM_FB_DDR2,            /* fully buffered DDR2 */
 137         MEM_RDDR2,              /* Registered DDR2 RAM */
 138         MEM_XDR,                /* Rambus XDR */
 139         MEM_DDR3,               /* DDR3 RAM */
 140         MEM_RDDR3,              /* Registered DDR3 RAM */
 141 };
 142
 143 #define MEM_FLAG_EMPTY          BIT(MEM_EMPTY)
 144 #define MEM_FLAG_RESERVED       BIT(MEM_RESERVED)
 145 #define MEM_FLAG_UNKNOWN        BIT(MEM_UNKNOWN)
 146 #define MEM_FLAG_FPM            BIT(MEM_FPM)
 147 #define MEM_FLAG_EDO            BIT(MEM_EDO)
 148 #define MEM_FLAG_BEDO           BIT(MEM_BEDO)
 149 #define MEM_FLAG_SDR            BIT(MEM_SDR)
 150 #define MEM_FLAG_RDR            BIT(MEM_RDR)
 151 #define MEM_FLAG_DDR            BIT(MEM_DDR)
 152 #define MEM_FLAG_RDDR           BIT(MEM_RDDR)
 153 #define MEM_FLAG_RMBS           BIT(MEM_RMBS)
 154 #define MEM_FLAG_DDR2           BIT(MEM_DDR2)
 155 #define MEM_FLAG_FB_DDR2        BIT(MEM_FB_DDR2)
 156 #define MEM_FLAG_RDDR2          BIT(MEM_RDDR2)
 157 #define MEM_FLAG_XDR            BIT(MEM_XDR)
 158 #define MEM_FLAG_DDR3            BIT(MEM_DDR3)
 159 #define MEM_FLAG_RDDR3           BIT(MEM_RDDR3)
 160
 161 /* chipset Error Detection and Correction capabilities and mode */
 162 enum edac_type {
 163         EDAC_UNKNOWN = 0,       /* Unknown if ECC is available */
 164         EDAC_NONE,              /* Doesnt support ECC */
 165         EDAC_RESERVED,          /* Reserved ECC type */
 166         EDAC_PARITY,            /* Detects parity errors */
 167         EDAC_EC,                /* Error Checking - no correction */
 168         EDAC_SECDED,            /* Single bit error correction, Double detection */
 169         EDAC_S2ECD2ED,          /* Chipkill x2 devices - do these exist? */
 170         EDAC_S4ECD4ED,          /* Chipkill x4 devices */
 171         EDAC_S8ECD8ED,          /* Chipkill x8 devices */
 172         EDAC_S16ECD16ED,        /* Chipkill x16 devices */
 173 };
 174
 175 #define EDAC_FLAG_UNKNOWN       BIT(EDAC_UNKNOWN)
 176 #define EDAC_FLAG_NONE          BIT(EDAC_NONE)
 177 #define EDAC_FLAG_PARITY        BIT(EDAC_PARITY)
 178 #define EDAC_FLAG_EC            BIT(EDAC_EC)
 179 #define EDAC_FLAG_SECDED        BIT(EDAC_SECDED)
 180 #define EDAC_FLAG_S2ECD2ED      BIT(EDAC_S2ECD2ED)
 181 #define EDAC_FLAG_S4ECD4ED      BIT(EDAC_S4ECD4ED)
 182 #define EDAC_FLAG_S8ECD8ED      BIT(EDAC_S8ECD8ED)
 183 #define EDAC_FLAG_S16ECD16ED    BIT(EDAC_S16ECD16ED)
 184
 185 /* scrubbing capabilities */
 186 enum scrub_type {
 187         SCRUB_UNKNOWN = 0,      /* Unknown if scrubber is available */
 188         SCRUB_NONE,             /* No scrubber */
 189         SCRUB_SW_PROG,          /* SW progressive (sequential) scrubbing */
 190         SCRUB_SW_SRC,           /* Software scrub only errors */
 191         SCRUB_SW_PROG_SRC,      /* Progressive software scrub from an error */
 192         SCRUB_SW_TUNABLE,       /* Software scrub frequency is tunable */
 193         SCRUB_HW_PROG,          /* HW progressive (sequential) scrubbing */
 194         SCRUB_HW_SRC,           /* Hardware scrub only errors */
 195         SCRUB_HW_PROG_SRC,      /* Progressive hardware scrub from an error */
 196         SCRUB_HW_TUNABLE        /* Hardware scrub frequency is tunable */
 197 };
 198
 199 #define SCRUB_FLAG_SW_PROG      BIT(SCRUB_SW_PROG)
 200 #define SCRUB_FLAG_SW_SRC       BIT(SCRUB_SW_SRC)
 201 #define SCRUB_FLAG_SW_PROG_SRC  BIT(SCRUB_SW_PROG_SRC)
 202 #define SCRUB_FLAG_SW_TUN       BIT(SCRUB_SW_SCRUB_TUNABLE)
 203 #define SCRUB_FLAG_HW_PROG      BIT(SCRUB_HW_PROG)
 204 #define SCRUB_FLAG_HW_SRC       BIT(SCRUB_HW_SRC)
 205 #define SCRUB_FLAG_HW_PROG_SRC  BIT(SCRUB_HW_PROG_SRC)
 206 #define SCRUB_FLAG_HW_TUN       BIT(SCRUB_HW_TUNABLE)
 207
 208 /* FIXME - should have notify capabilities: NMI, LOG, PROC, etc */
 209
 210 /* EDAC internal operation states */
 211 #define OP_ALLOC                0x100
 212 #define OP_RUNNING_POLL         0x201
 213 #define OP_RUNNING_INTERRUPT    0x202
 214 #define OP_RUNNING_POLL_INTR    0x203
 215 #define OP_OFFLINE              0x300
 216
 217 /*
 218  * There are several things to be aware of that aren't at all obvious:
 219  *
 220  *
 221  * SOCKETS, SOCKET SETS, BANKS, ROWS, CHIP-SELECT ROWS, CHANNELS, etc..
 222  *
 223  * These are some of the many terms that are thrown about that don't always
 224  * mean what people think they mean (Inconceivable!).  In the interest of
 225  * creating a common ground for discussion, terms and their definitions
 226  * will be established.
 227  *
 228  * Memory devices:      The individual chip on a memory stick.  These devices
 229  *                      commonly output 4 and 8 bits each.  Grouping several
 230  *                      of these in parallel provides 64 bits which is common
 231  *                      for a memory stick.
 232  *
 233  * Memory Stick:        A printed circuit board that agregates multiple
 234  *                      memory devices in parallel.  This is the atomic
 235  *                      memory component that is purchaseable by Joe consumer
 236  *                      and loaded into a memory socket.
 237  *
 238  * Socket:              A physical connector on the motherboard that accepts
 239  *                      a single memory stick.
 240  *
 241  * Channel:             Set of memory devices on a memory stick that must be
 242  *                      grouped in parallel with one or more additional
 243  *                      channels from other memory sticks.  This parallel
 244  *                      grouping of the output from multiple channels are
 245  *                      necessary for the smallest granularity of memory access.
 246  *                      Some memory controllers are capable of single channel -
 247  *                      which means that memory sticks can be loaded
 248  *                      individually.  Other memory controllers are only
 249  *                      capable of dual channel - which means that memory
 250  *                      sticks must be loaded as pairs (see "socket set").
 251  *
 252  * Chip-select row:     All of the memory devices that are selected together.
 253  *                      for a single, minimum grain of memory access.
 254  *                      This selects all of the parallel memory devices across
 255  *                      all of the parallel channels.  Common chip-select rows
 256  *                      for single channel are 64 bits, for dual channel 128
 257  *                      bits.
 258  *
 259  * Single-Ranked stick: A Single-ranked stick has 1 chip-select row of memmory.
 260  *                      Motherboards commonly drive two chip-select pins to
 261  *                      a memory stick. A single-ranked stick, will occupy
 262  *                      only one of those rows. The other will be unused.
 263  *
 264  * Double-Ranked stick: A double-ranked stick has two chip-select rows which
 265  *                      access different sets of memory devices.  The two
 266  *                      rows cannot be accessed concurrently.
 267  *
 268  * Double-sided stick:  DEPRECATED TERM, see Double-Ranked stick.
 269  *                      A double-sided stick has two chip-select rows which
 270  *                      access different sets of memory devices.  The two
 271  *                      rows cannot be accessed concurrently.  "Double-sided"
 272  *                      is irrespective of the memory devices being mounted
 273  *                      on both sides of the memory stick.
 274  *
 275  * Socket set:          All of the memory sticks that are required for
 276  *                      a single memory access or all of the memory sticks
 277  *                      spanned by a chip-select row.  A single socket set
 278  *                      has two chip-select rows and if double-sided sticks
 279  *                      are used these will occupy those chip-select rows.
 280  *
 281  * Bank:                This term is avoided because it is unclear when
 282  *                      needing to distinguish between chip-select rows and
 283  *                      socket sets.
 284  *
 285  * Controller pages:
 286  *
 287  * Physical pages:
 288  *
 289  * Virtual pages:
 290  *
 291  *
 292  * STRUCTURE ORGANIZATION AND CHOICES
 293  *
 294  *
 295  *
 296  * PS - I enjoyed writing all that about as much as you enjoyed reading it.
 297  */
 298
 299 struct channel_info {
 300         int chan_idx;           /* channel index */
 301         u32 ce_count;           /* Correctable Errors for this CHANNEL */
 302         char label[EDAC_MC_LABEL_LEN + 1];      /* DIMM label on motherboard */
 303         struct csrow_info *csrow;       /* the parent */
 304 };
 305
 306 struct csrow_info {
 307         unsigned long first_page;       /* first page number in dimm */
 308         unsigned long last_page;        /* last page number in dimm */
 309         unsigned long page_mask;        /* used for interleaving -
 310                                          * 0UL for non intlv
 311                                          */
 312         u32 nr_pages;           /* number of pages in csrow */
 313         u32 grain;              /* granularity of reported error in bytes */
 314         int csrow_idx;          /* the chip-select row */
 315         enum dev_type dtype;    /* memory device type */
 316         u32 ue_count;           /* Uncorrectable Errors for this csrow */
 317         u32 ce_count;           /* Correctable Errors for this csrow */
 318         enum mem_type mtype;    /* memory csrow type */
 319         enum edac_type edac_mode;       /* EDAC mode for this csrow */
 320         struct mem_ctl_info *mci;       /* the parent */
 321
 322         struct kobject kobj;    /* sysfs kobject for this csrow */
 323
 324         /* channel information for this csrow */
 325         u32 nr_channels;
 326         struct channel_info *channels;
 327 };
 328
 329 struct mcidev_sysfs_group {
 330         const char *name;                               /* group name */
 331         struct mcidev_sysfs_attribute *mcidev_attr;     /* group attributes */
 332 };
 333
 334 struct mcidev_sysfs_group_kobj {
 335         struct list_head list;          /* list for all instances within a mc */
 336
 337         struct kobject kobj;            /* kobj for the group */
 338
 339         struct mcidev_sysfs_group *grp; /* group description table */
 340         struct mem_ctl_info *mci;       /* the parent */
 341 };
 342
 343 /* mcidev_sysfs_attribute structure
 344  *      used for driver sysfs attributes and in mem_ctl_info
 345  *      sysfs top level entries
 346  */
 347 struct mcidev_sysfs_attribute {
 348         /* It should use either attr or grp */
 349         struct attribute attr;
 350         struct mcidev_sysfs_group *grp; /* Points to a group of attributes */
 351
 352         /* Ops for show/store values at the attribute - not used on group */
 353         ssize_t (*show)(struct mem_ctl_info *,char *);
 354         ssize_t (*store)(struct mem_ctl_info *, const char *,size_t);
 355 };
 356
 357 /* MEMORY controller information structure
 358  */
 359 struct mem_ctl_info {
 360         struct list_head link;  /* for global list of mem_ctl_info structs */
 361
 362         struct module *owner;   /* Module owner of this control struct */
 363
 364         unsigned long mtype_cap;        /* memory types supported by mc */
 365         unsigned long edac_ctl_cap;     /* Mem controller EDAC capabilities */
 366         unsigned long edac_cap; /* configuration capabilities - this is
 367                                  * closely related to edac_ctl_cap.  The
 368                                  * difference is that the controller may be
 369                                  * capable of s4ecd4ed which would be listed
 370                                  * in edac_ctl_cap, but if channels aren't
 371                                  * capable of s4ecd4ed then the edac_cap would
 372                                  * not have that capability.
 373                                  */
 374         unsigned long scrub_cap;        /* chipset scrub capabilities */
 375         enum scrub_type scrub_mode;     /* current scrub mode */
 376
 377         /* Translates sdram memory scrub rate given in bytes/sec to the
 378            internal representation and configures whatever else needs
 379            to be configured.
 380          */
 381         int (*set_sdram_scrub_rate) (struct mem_ctl_info * mci, u32 bw);
 382
 383         /* Get the current sdram memory scrub rate from the internal
 384            representation and converts it to the closest matching
 385            bandwith in bytes/sec.
 386          */
 387         int (*get_sdram_scrub_rate) (struct mem_ctl_info * mci, u32 * bw);
 388
 389
 390         /* pointer to edac checking routine */
 391         void (*edac_check) (struct mem_ctl_info * mci);
 392
 393         /*
 394          * Remaps memory pages: controller pages to physical pages.
 395          * For most MC's, this will be NULL.
 396          */
 397         /* FIXME - why not send the phys page to begin with? */
 398         unsigned long (*ctl_page_to_phys) (struct mem_ctl_info * mci,
 399                                            unsigned long page);
 400         int mc_idx;
 401         int nr_csrows;
 402         struct csrow_info *csrows;
 403         /*
 404          * FIXME - what about controllers on other busses? - IDs must be
 405          * unique.  dev pointer should be sufficiently unique, but
 406          * BUS:SLOT.FUNC numbers may not be unique.
 407          */
 408         struct device *dev;
 409         const char *mod_name;
 410         const char *mod_ver;
 411         const char *ctl_name;
 412         const char *dev_name;
 413         char proc_name[MC_PROC_NAME_MAX_LEN + 1];
 414         void *pvt_info;
 415         u32 ue_noinfo_count;    /* Uncorrectable Errors w/o info */
 416         u32 ce_noinfo_count;    /* Correctable Errors w/o info */
 417         u32 ue_count;           /* Total Uncorrectable Errors for this MC */
 418         u32 ce_count;           /* Total Correctable Errors for this MC */
 419         unsigned long start_time;       /* mci load start time (in jiffies) */
 420
 421         /* this stuff is for safe removal of mc devices from global list while
 422          * NMI handlers may be traversing list
 423          */
 424         struct rcu_head rcu;
 425         struct completion complete;
 426
 427         /* edac sysfs device control */
 428         struct kobject edac_mci_kobj;
 429
 430         /* list for all grp instances within a mc */
 431         struct list_head grp_kobj_list;
 432
 433         /* Additional top controller level attributes, but specified
 434          * by the low level driver.
 435          *
 436          * Set by the low level driver to provide attributes at the
 437          * controller level, same level as 'ue_count' and 'ce_count' above.
 438          * An array of structures, NULL terminated
 439          *
 440          * If attributes are desired, then set to array of attributes
 441          * If no attributes are desired, leave NULL
 442          */
 443         struct mcidev_sysfs_attribute *mc_driver_sysfs_attributes;
 444
 445         /* work struct for this MC */
 446         struct delayed_work work;
 447
 448         /* the internal state of this controller instance */
 449         int op_state;
 450 };
 451
 452 /*
 453  * The following are the structures to provide for a generic
 454  * or abstract 'edac_device'. This set of structures and the
 455  * code that implements the APIs for the same, provide for
 456  * registering EDAC type devices which are NOT standard memory.
 457  *
 458  * CPU caches (L1 and L2)
 459  * DMA engines
 460  * Core CPU swithces
 461  * Fabric switch units
 462  * PCIe interface controllers
 463  * other EDAC/ECC type devices that can be monitored for
 464  * errors, etc.
 465  *
 466  * It allows for a 2 level set of hiearchry. For example:
 467  *
 468  * cache could be composed of L1, L2 and L3 levels of cache.
 469  * Each CPU core would have its own L1 cache, while sharing
 470  * L2 and maybe L3 caches.
 471  *
 472  * View them arranged, via the sysfs presentation:
 473  * /sys/devices/system/edac/..
 474  *
 475  *      mc/             <existing memory device directory>
 476  *      cpu/cpu0/..     <L1 and L2 block directory>
 477  *              /L1-cache/ce_count
 478  *                       /ue_count
 479  *              /L2-cache/ce_count
 480  *                       /ue_count
 481  *      cpu/cpu1/..     <L1 and L2 block directory>
 482  *              /L1-cache/ce_count
 483  *                       /ue_count
 484  *              /L2-cache/ce_count
 485  *                       /ue_count
 486  *      ...
 487  *
 488  *      the L1 and L2 directories would be "edac_device_block's"
 489  */
 490
 491 struct edac_device_counter {
 492         u32 ue_count;
 493         u32 ce_count;
 494 };
 495
 496 /* forward reference */
 497 struct edac_device_ctl_info;
 498 struct edac_device_block;
 499
 500 /* edac_dev_sysfs_attribute structure
 501  *      used for driver sysfs attributes in mem_ctl_info
 502  *      for extra controls and attributes:
 503  *              like high level error Injection controls
 504  */
 505 struct edac_dev_sysfs_attribute {
 506         struct attribute attr;
 507         ssize_t (*show)(struct edac_device_ctl_info *, char *);
 508         ssize_t (*store)(struct edac_device_ctl_info *, const char *, size_t);
 509 };
 510
 511 /* edac_dev_sysfs_block_attribute structure
 512  *
 513  *      used in leaf 'block' nodes for adding controls/attributes
 514  *
 515  *      each block in each instance of the containing control structure
 516  *      can have an array of the following. The show and store functions
 517  *      will be filled in with the show/store function in the
 518  *      low level driver.
 519  *
 520  *      The 'value' field will be the actual value field used for
 521  *      counting
 522  */
 523 struct edac_dev_sysfs_block_attribute {
 524         struct attribute attr;
 525         ssize_t (*show)(struct kobject *, struct attribute *, char *);
 526         ssize_t (*store)(struct kobject *, struct attribute *,
 527                         const char *, size_t);
 528         struct edac_device_block *block;
 529
 530         unsigned int value;
 531 };
 532
 533 /* device block control structure */
 534 struct edac_device_block {
 535         struct edac_device_instance *instance;  /* Up Pointer */
 536         char name[EDAC_DEVICE_NAME_LEN + 1];
 537
 538         struct edac_device_counter counters;    /* basic UE and CE counters */
 539
 540         int nr_attribs;         /* how many attributes */
 541
 542         /* this block's attributes, could be NULL */
 543         struct edac_dev_sysfs_block_attribute *block_attributes;
 544
 545         /* edac sysfs device control */
 546         struct kobject kobj;
 547 };
 548
 549 /* device instance control structure */
 550 struct edac_device_instance {
 551         struct edac_device_ctl_info *ctl;       /* Up pointer */
 552         char name[EDAC_DEVICE_NAME_LEN + 4];
 553
 554         struct edac_device_counter counters;    /* instance counters */
 555
 556         u32 nr_blocks;          /* how many blocks */
 557         struct edac_device_block *blocks;       /* block array */
 558
 559         /* edac sysfs device control */
 560         struct kobject kobj;
 561 };
 562
 563
 564 /*
 565  * Abstract edac_device control info structure
 566  *
 567  */
 568 struct edac_device_ctl_info {
 569         /* for global list of edac_device_ctl_info structs */
 570         struct list_head link;
 571
 572         struct module *owner;   /* Module owner of this control struct */
 573
 574         int dev_idx;
 575
 576         /* Per instance controls for this edac_device */
 577         int log_ue;             /* boolean for logging UEs */
 578         int log_ce;             /* boolean for logging CEs */
 579         int panic_on_ue;        /* boolean for panic'ing on an UE */
 580         unsigned poll_msec;     /* number of milliseconds to poll interval */
 581         unsigned long delay;    /* number of jiffies for poll_msec */
 582
 583         /* Additional top controller level attributes, but specified
 584          * by the low level driver.
 585          *
 586          * Set by the low level driver to provide attributes at the
 587          * controller level, same level as 'ue_count' and 'ce_count' above.
 588          * An array of structures, NULL terminated
 589          *
 590          * If attributes are desired, then set to array of attributes
 591          * If no attributes are desired, leave NULL
 592          */
 593         struct edac_dev_sysfs_attribute *sysfs_attributes;
 594
 595         /* pointer to main 'edac' class in sysfs */
 596         struct sysdev_class *edac_class;
 597
 598         /* the internal state of this controller instance */
 599         int op_state;
 600         /* work struct for this instance */
 601         struct delayed_work work;
 602
 603         /* pointer to edac polling checking routine:
 604          *      If NOT NULL: points to polling check routine
 605          *      If NULL: Then assumes INTERRUPT operation, where
 606          *              MC driver will receive events
 607          */
 608         void (*edac_check) (struct edac_device_ctl_info * edac_dev);
 609
 610         struct device *dev;     /* pointer to device structure */
 611
 612         const char *mod_name;   /* module name */
 613         const char *ctl_name;   /* edac controller  name */
 614         const char *dev_name;   /* pci/platform/etc... name */
 615
 616         void *pvt_info;         /* pointer to 'private driver' info */
 617
 618         unsigned long start_time;       /* edac_device load start time (jiffies) */
 619
 620         /* these are for safe removal of mc devices from global list while
 621          * NMI handlers may be traversing list
 622          */
 623         struct rcu_head rcu;
 624         struct completion removal_complete;
 625
 626         /* sysfs top name under 'edac' directory
 627          * and instance name:
 628          *      cpu/cpu0/...
 629          *      cpu/cpu1/...
 630          *      cpu/cpu2/...
 631          *      ...
 632          */
 633         char name[EDAC_DEVICE_NAME_LEN + 1];
 634
 635         /* Number of instances supported on this control structure
 636          * and the array of those instances
 637          */
 638         u32 nr_instances;
 639         struct edac_device_instance *instances;
 640
 641         /* Event counters for the this whole EDAC Device */
 642         struct edac_device_counter counters;
 643
 644         /* edac sysfs device control for the 'name'
 645          * device this structure controls
 646          */
 647         struct kobject kobj;
 648 };
 649
 650 /* To get from the instance's wq to the beginning of the ctl structure */
 651 #define to_edac_mem_ctl_work(w) \
 652                 container_of(w, struct mem_ctl_info, work)
 653
 654 #define to_edac_device_ctl_work(w) \
 655                 container_of(w,struct edac_device_ctl_info,work)
 656
 657 /*
 658  * The alloc() and free() functions for the 'edac_device' control info
 659  * structure. A MC driver will allocate one of these for each edac_device
 660  * it is going to control/register with the EDAC CORE.
 661  */
 662 extern struct edac_device_ctl_info *edac_device_alloc_ctl_info(
 663                 unsigned sizeof_private,
 664                 char *edac_device_name, unsigned nr_instances,
 665                 char *edac_block_name, unsigned nr_blocks,
 666                 unsigned offset_value,
 667                 struct edac_dev_sysfs_block_attribute *block_attributes,
 668                 unsigned nr_attribs,
 669                 int device_index);
 670
 671 /* The offset value can be:
 672  *      -1 indicating no offset value
 673  *      0 for zero-based block numbers
 674  *      1 for 1-based block number
 675  *      other for other-based block number
 676  */
 677 #define BLOCK_OFFSET_VALUE_OFF  ((unsigned) -1)
 678
 679 extern void edac_device_free_ctl_info(struct edac_device_ctl_info *ctl_info);
 680
 681 #ifdef CONFIG_PCI
 682
 683 struct edac_pci_counter {
 684         atomic_t pe_count;
 685         atomic_t npe_count;
 686 };
 687
 688 /*
 689  * Abstract edac_pci control info structure
 690  *
 691  */
 692 struct edac_pci_ctl_info {
 693         /* for global list of edac_pci_ctl_info structs */
 694         struct list_head link;
 695
 696         int pci_idx;
 697
 698         struct sysdev_class *edac_class;        /* pointer to class */
 699
 700         /* the internal state of this controller instance */
 701         int op_state;
 702         /* work struct for this instance */
 703         struct delayed_work work;
 704
 705         /* pointer to edac polling checking routine:
 706          *      If NOT NULL: points to polling check routine
 707          *      If NULL: Then assumes INTERRUPT operation, where
 708          *              MC driver will receive events
 709          */
 710         void (*edac_check) (struct edac_pci_ctl_info * edac_dev);
 711
 712         struct device *dev;     /* pointer to device structure */
 713
 714         const char *mod_name;   /* module name */
 715         const char *ctl_name;   /* edac controller  name */
 716         const char *dev_name;   /* pci/platform/etc... name */
 717
 718         void *pvt_info;         /* pointer to 'private driver' info */
 719
 720         unsigned long start_time;       /* edac_pci load start time (jiffies) */
 721
 722         /* these are for safe removal of devices from global list while
 723          * NMI handlers may be traversing list
 724          */
 725         struct rcu_head rcu;
 726         struct completion complete;
 727
 728         /* sysfs top name under 'edac' directory
 729          * and instance name:
 730          *      cpu/cpu0/...
 731          *      cpu/cpu1/...
 732          *      cpu/cpu2/...
 733          *      ...
 734          */
 735         char name[EDAC_DEVICE_NAME_LEN + 1];
 736
 737         /* Event counters for the this whole EDAC Device */
 738         struct edac_pci_counter counters;
 739
 740         /* edac sysfs device control for the 'name'
 741          * device this structure controls
 742          */
 743         struct kobject kobj;
 744         struct completion kobj_complete;
 745 };
 746
 747 #define to_edac_pci_ctl_work(w) \
 748                 container_of(w, struct edac_pci_ctl_info,work)
 749
 750 /* write all or some bits in a byte-register*/
 751 static inline void pci_write_bits8(struct pci_dev *pdev, int offset, u8 value,
 752                                    u8 mask)
 753 {
 754         if (mask != 0xff) {
 755                 u8 buf;
 756
 757                 pci_read_config_byte(pdev, offset, &buf);
 758                 value &= mask;
 759                 buf &= ~mask;
 760                 value |= buf;
 761         }
 762
 763         pci_write_config_byte(pdev, offset, value);
 764 }
 765
 766 /* write all or some bits in a word-register*/
 767 static inline void pci_write_bits16(struct pci_dev *pdev, int offset,
 768                                     u16 value, u16 mask)
 769 {
 770         if (mask != 0xffff) {
 771                 u16 buf;
 772
 773                 pci_read_config_word(pdev, offset, &buf);
 774                 value &= mask;
 775                 buf &= ~mask;
 776                 value |= buf;
 777         }
 778
 779         pci_write_config_word(pdev, offset, value);
 780 }
 781
 782 /*
 783  * pci_write_bits32
 784  *
 785  * edac local routine to do pci_write_config_dword, but adds
 786  * a mask parameter. If mask is all ones, ignore the mask.
 787  * Otherwise utilize the mask to isolate specified bits
 788  *
 789  * write all or some bits in a dword-register
 790  */
 791 static inline void pci_write_bits32(struct pci_dev *pdev, int offset,
 792                                     u32 value, u32 mask)
 793 {
 794         if (mask != 0xffffffff) {
 795                 u32 buf;
 796
 797                 pci_read_config_dword(pdev, offset, &buf);
 798                 value &= mask;
 799                 buf &= ~mask;
 800                 value |= buf;
 801         }
 802
 803         pci_write_config_dword(pdev, offset, value);
 804 }
 805
 806 #endif                          /* CONFIG_PCI */
 807
 808 extern struct mem_ctl_info *edac_mc_alloc(unsigned sz_pvt, unsigned nr_csrows,
 809                                           unsigned nr_chans, int edac_index);
 810 extern int edac_mc_add_mc(struct mem_ctl_info *mci);
 811 extern void edac_mc_free(struct mem_ctl_info *mci);
 812 extern struct mem_ctl_info *edac_mc_find(int idx);
 813 extern struct mem_ctl_info *edac_mc_del_mc(struct device *dev);
 814 extern int edac_mc_find_csrow_by_page(struct mem_ctl_info *mci,
 815                                       unsigned long page);
 816
 817 /*
 818  * The no info errors are used when error overflows are reported.
 819  * There are a limited number of error logging registers that can
 820  * be exausted.  When all registers are exhausted and an additional
 821  * error occurs then an error overflow register records that an
 822  * error occured and the type of error, but doesn't have any
 823  * further information.  The ce/ue versions make for cleaner
 824  * reporting logic and function interface - reduces conditional
 825  * statement clutter and extra function arguments.
 826  */
 827 extern void edac_mc_handle_ce(struct mem_ctl_info *mci,
 828                               unsigned long page_frame_number,
 829                               unsigned long offset_in_page,
 830                               unsigned long syndrome, int row, int channel,
 831                               const char *msg);
 832 extern void edac_mc_handle_ce_no_info(struct mem_ctl_info *mci,
 833                                       const char *msg);
 834 extern void edac_mc_handle_ue(struct mem_ctl_info *mci,
 835                               unsigned long page_frame_number,
 836                               unsigned long offset_in_page, int row,
 837                               const char *msg);
 838 extern void edac_mc_handle_ue_no_info(struct mem_ctl_info *mci,
 839                                       const char *msg);
 840 extern void edac_mc_handle_fbd_ue(struct mem_ctl_info *mci, unsigned int csrow,
 841                                   unsigned int channel0, unsigned int channel1,
 842                                   char *msg);
 843 extern void edac_mc_handle_fbd_ce(struct mem_ctl_info *mci, unsigned int csrow,
 844                                   unsigned int channel, char *msg);
 845
 846 /*
 847  * edac_device APIs
 848  */
 849 extern int edac_device_add_device(struct edac_device_ctl_info *edac_dev);
 850 extern struct edac_device_ctl_info *edac_device_del_device(struct device *dev);
 851 extern void edac_device_handle_ue(struct edac_device_ctl_info *edac_dev,
 852                                 int inst_nr, int block_nr, const char *msg);
 853 extern void edac_device_handle_ce(struct edac_device_ctl_info *edac_dev,
 854                                 int inst_nr, int block_nr, const char *msg);
 855 extern int edac_device_alloc_index(void);
 856
 857 /*
 858  * edac_pci APIs
 859  */
 860 extern struct edac_pci_ctl_info *edac_pci_alloc_ctl_info(unsigned int sz_pvt,
 861                                 const char *edac_pci_name);
 862
 863 extern void edac_pci_free_ctl_info(struct edac_pci_ctl_info *pci);
 864
 865 extern void edac_pci_reset_delay_period(struct edac_pci_ctl_info *pci,
 866                                 unsigned long value);
 867
 868 extern int edac_pci_alloc_index(void);
 869 extern int edac_pci_add_device(struct edac_pci_ctl_info *pci, int edac_idx);
 870 extern struct edac_pci_ctl_info *edac_pci_del_device(struct device *dev);
 871
 872 extern struct edac_pci_ctl_info *edac_pci_create_generic_ctl(
 873                                 struct device *dev,
 874                                 const char *mod_name);
 875
 876 extern void edac_pci_release_generic_ctl(struct edac_pci_ctl_info *pci);
 877 extern int edac_pci_create_sysfs(struct edac_pci_ctl_info *pci);
 878 extern void edac_pci_remove_sysfs(struct edac_pci_ctl_info *pci);
 879
 880 /*
 881  * edac misc APIs
 882  */
 883 extern char *edac_op_state_to_string(int op_state);
 884
 885 #endif                          /* _EDAC_CORE_H_ */