arch/arm/mach-ns9xxx/board-a9m9750dev.c

   1 /*
   2  * arch/arm/mach-ns9xxx/board-a9m9750dev.c
   3  *
   4  * Copyright (C) 2006,2007 by Digi International Inc.
   5  * All rights reserved.
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License version 2 as published by
   9  * the Free Software Foundation.
  10  */
  11 #include <linux/irq.h>
  12
  13 #include <asm/mach/map.h>
  14 #include <asm/gpio.h>
  15
  16 #include <asm/arch-ns9xxx/board.h>
  17 #include <asm/arch-ns9xxx/regs-sys.h>
  18 #include <asm/arch-ns9xxx/regs-mem.h>
  19 #include <asm/arch-ns9xxx/regs-bbu.h>
  20 #include <asm/arch-ns9xxx/regs-board-a9m9750dev.h>
  21
  22 #include "board-a9m9750dev.h"
  23
  24 static struct map_desc board_a9m9750dev_io_desc[] __initdata = {
  25         { /* FPGA on CS0 */
  26                 .virtual = io_p2v(NS9XXX_CSxSTAT_PHYS(0)),
  27                 .pfn = __phys_to_pfn(NS9XXX_CSxSTAT_PHYS(0)),
  28                 .length = NS9XXX_CS0STAT_LENGTH,
  29                 .type = MT_DEVICE,
  30         },
  31 };
  32
  33 void __init board_a9m9750dev_map_io(void)
  34 {
  35         iotable_init(board_a9m9750dev_io_desc,
  36                      ARRAY_SIZE(board_a9m9750dev_io_desc));
  37 }
  38
  39 static void a9m9750dev_fpga_ack_irq(unsigned int irq)
  40 {
  41         /* nothing */
  42 }
  43
  44 static void a9m9750dev_fpga_mask_irq(unsigned int irq)
  45 {
  46         u8 ier;
  47
  48         ier = __raw_readb(FPGA_IER);
  49
  50         ier &= ~(1 << (irq - FPGA_IRQ(0)));
  51
  52         __raw_writeb(ier, FPGA_IER);
  53 }
  54
  55 static void a9m9750dev_fpga_maskack_irq(unsigned int irq)
  56 {
  57         a9m9750dev_fpga_mask_irq(irq);
  58         a9m9750dev_fpga_ack_irq(irq);
  59 }
  60
  61 static void a9m9750dev_fpga_unmask_irq(unsigned int irq)
  62 {
  63         u8 ier;
  64
  65         ier = __raw_readb(FPGA_IER);
  66
  67         ier |= 1 << (irq - FPGA_IRQ(0));
  68
  69         __raw_writeb(ier, FPGA_IER);
  70 }
  71
  72 static struct irq_chip a9m9750dev_fpga_chip = {
  73         .ack            = a9m9750dev_fpga_ack_irq,
  74         .mask           = a9m9750dev_fpga_mask_irq,
  75         .mask_ack       = a9m9750dev_fpga_maskack_irq,
  76         .unmask         = a9m9750dev_fpga_unmask_irq,
  77 };
  78
  79 static void a9m9750dev_fpga_demux_handler(unsigned int irq,
  80                 struct irq_desc *desc)
  81 {
  82         u8 stat = __raw_readb(FPGA_ISR);
  83
  84         desc->chip->mask_ack(irq);
  85
  86         while (stat != 0) {
  87                 int irqno = fls(stat) - 1;
  88                 struct irq_desc *fpgadesc;
  89
  90                 stat &= ~(1 << irqno);
  91
  92                 fpgadesc = irq_desc + FPGA_IRQ(irqno);
  93
  94                 desc_handle_irq(FPGA_IRQ(irqno), fpgadesc);
  95         }
  96
  97         desc->chip->unmask(irq);
  98 }
  99
 100 void __init board_a9m9750dev_init_irq(void)
 101 {
 102         u32 eic;
 103         int i;
 104
 105         if (gpio_request(11, "board a9m9750dev extirq2") == 0)
 106                 ns9xxx_gpio_configure(11, 0, 1);
 107         else
 108                 printk(KERN_ERR "%s: cannot get gpio 11 for IRQ_EXT2\n",
 109                                 __func__);
 110
 111         for (i = FPGA_IRQ(0); i <= FPGA_IRQ(7); ++i) {
 112                 set_irq_chip(i, &a9m9750dev_fpga_chip);
 113                 set_irq_handler(i, handle_level_irq);
 114                 set_irq_flags(i, IRQF_VALID);
 115         }
 116
 117         /* IRQ_EXT2: level sensitive + active low */
 118         eic = __raw_readl(SYS_EIC(2));
 119         REGSET(eic, SYS_EIC, PLTY, AL);
 120         REGSET(eic, SYS_EIC, LVEDG, LEVEL);
 121         __raw_writel(eic, SYS_EIC(2));
 122
 123         set_irq_chained_handler(IRQ_EXT2,
 124                         a9m9750dev_fpga_demux_handler);
 125 }
 126
 127 void __init board_a9m9750dev_init_machine(void)
 128 {
 129         u32 reg;
 130
 131         /* setup static CS0: memory base ... */
 132         reg = __raw_readl(SYS_SMCSSMB(0));
 133         REGSETIM(reg, SYS_SMCSSMB, CSxB, NS9XXX_CSxSTAT_PHYS(0) >> 12);
 134         __raw_writel(reg, SYS_SMCSSMB(0));
 135
 136         /* ... and mask */
 137         reg = __raw_readl(SYS_SMCSSMM(0));
 138         REGSETIM(reg, SYS_SMCSSMM, CSxM, 0xfffff);
 139         REGSET(reg, SYS_SMCSSMM, CSEx, EN);
 140         __raw_writel(reg, SYS_SMCSSMM(0));
 141
 142         /* setup static CS0: memory configuration */
 143         reg = __raw_readl(MEM_SMC(0));
 144         REGSET(reg, MEM_SMC, PSMC, OFF);
 145         REGSET(reg, MEM_SMC, BSMC, OFF);
 146         REGSET(reg, MEM_SMC, EW, OFF);
 147         REGSET(reg, MEM_SMC, PB, 1);
 148         REGSET(reg, MEM_SMC, PC, AL);
 149         REGSET(reg, MEM_SMC, PM, DIS);
 150         REGSET(reg, MEM_SMC, MW, 8);
 151         __raw_writel(reg, MEM_SMC(0));
 152
 153         /* setup static CS0: timing */
 154         __raw_writel(0x2, MEM_SMWED(0));
 155         __raw_writel(0x2, MEM_SMOED(0));
 156         __raw_writel(0x6, MEM_SMRD(0));
 157         __raw_writel(0x6, MEM_SMWD(0));
 158 }