2 * Copyright 2005 Stephane Marchesin
3 * Copyright 2008 Stuart Bennett
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
26 #include <linux/swab.h>
27 #include <linux/slab.h>
30 #include "drm_sarea.h"
31 #include "drm_crtc_helper.h"
32 #include <linux/vgaarb.h>
33 #include <linux/vga_switcheroo.h>
35 #include "nouveau_drv.h"
36 #include <nouveau_drm.h>
37 #include "nouveau_fbcon.h"
38 #include "nouveau_pm.h"
39 #include "nv04_display.h"
40 #include "nv50_display.h"
41 #include "nouveau_acpi.h"
43 static void nouveau_stub_takedown(struct drm_device
*dev
) {}
44 static int nouveau_stub_init(struct drm_device
*dev
) { return 0; }
46 static int nouveau_init_engine_ptrs(struct drm_device
*dev
)
48 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
49 struct nouveau_engine
*engine
= &dev_priv
->engine
;
51 switch (dev_priv
->chipset
& 0xf0) {
53 engine
->display
.early_init
= nv04_display_early_init
;
54 engine
->display
.late_takedown
= nv04_display_late_takedown
;
55 engine
->display
.create
= nv04_display_create
;
56 engine
->display
.destroy
= nv04_display_destroy
;
57 engine
->display
.init
= nv04_display_init
;
58 engine
->display
.fini
= nv04_display_fini
;
59 engine
->pm
.clocks_get
= nv04_pm_clocks_get
;
60 engine
->pm
.clocks_pre
= nv04_pm_clocks_pre
;
61 engine
->pm
.clocks_set
= nv04_pm_clocks_set
;
64 engine
->display
.early_init
= nv04_display_early_init
;
65 engine
->display
.late_takedown
= nv04_display_late_takedown
;
66 engine
->display
.create
= nv04_display_create
;
67 engine
->display
.destroy
= nv04_display_destroy
;
68 engine
->display
.init
= nv04_display_init
;
69 engine
->display
.fini
= nv04_display_fini
;
70 engine
->pm
.clocks_get
= nv04_pm_clocks_get
;
71 engine
->pm
.clocks_pre
= nv04_pm_clocks_pre
;
72 engine
->pm
.clocks_set
= nv04_pm_clocks_set
;
75 engine
->display
.early_init
= nv04_display_early_init
;
76 engine
->display
.late_takedown
= nv04_display_late_takedown
;
77 engine
->display
.create
= nv04_display_create
;
78 engine
->display
.destroy
= nv04_display_destroy
;
79 engine
->display
.init
= nv04_display_init
;
80 engine
->display
.fini
= nv04_display_fini
;
81 engine
->pm
.clocks_get
= nv04_pm_clocks_get
;
82 engine
->pm
.clocks_pre
= nv04_pm_clocks_pre
;
83 engine
->pm
.clocks_set
= nv04_pm_clocks_set
;
86 engine
->display
.early_init
= nv04_display_early_init
;
87 engine
->display
.late_takedown
= nv04_display_late_takedown
;
88 engine
->display
.create
= nv04_display_create
;
89 engine
->display
.destroy
= nv04_display_destroy
;
90 engine
->display
.init
= nv04_display_init
;
91 engine
->display
.fini
= nv04_display_fini
;
92 engine
->pm
.clocks_get
= nv04_pm_clocks_get
;
93 engine
->pm
.clocks_pre
= nv04_pm_clocks_pre
;
94 engine
->pm
.clocks_set
= nv04_pm_clocks_set
;
95 engine
->pm
.voltage_get
= nouveau_voltage_gpio_get
;
96 engine
->pm
.voltage_set
= nouveau_voltage_gpio_set
;
100 engine
->display
.early_init
= nv04_display_early_init
;
101 engine
->display
.late_takedown
= nv04_display_late_takedown
;
102 engine
->display
.create
= nv04_display_create
;
103 engine
->display
.destroy
= nv04_display_destroy
;
104 engine
->display
.init
= nv04_display_init
;
105 engine
->display
.fini
= nv04_display_fini
;
106 engine
->pm
.clocks_get
= nv40_pm_clocks_get
;
107 engine
->pm
.clocks_pre
= nv40_pm_clocks_pre
;
108 engine
->pm
.clocks_set
= nv40_pm_clocks_set
;
109 engine
->pm
.voltage_get
= nouveau_voltage_gpio_get
;
110 engine
->pm
.voltage_set
= nouveau_voltage_gpio_set
;
111 engine
->pm
.temp_get
= nv40_temp_get
;
112 engine
->pm
.pwm_get
= nv40_pm_pwm_get
;
113 engine
->pm
.pwm_set
= nv40_pm_pwm_set
;
116 case 0x80: /* gotta love NVIDIA's consistency.. */
119 engine
->display
.early_init
= nv50_display_early_init
;
120 engine
->display
.late_takedown
= nv50_display_late_takedown
;
121 engine
->display
.create
= nv50_display_create
;
122 engine
->display
.destroy
= nv50_display_destroy
;
123 engine
->display
.init
= nv50_display_init
;
124 engine
->display
.fini
= nv50_display_fini
;
125 switch (dev_priv
->chipset
) {
136 engine
->pm
.clocks_get
= nv50_pm_clocks_get
;
137 engine
->pm
.clocks_pre
= nv50_pm_clocks_pre
;
138 engine
->pm
.clocks_set
= nv50_pm_clocks_set
;
141 engine
->pm
.clocks_get
= nva3_pm_clocks_get
;
142 engine
->pm
.clocks_pre
= nva3_pm_clocks_pre
;
143 engine
->pm
.clocks_set
= nva3_pm_clocks_set
;
146 engine
->pm
.voltage_get
= nouveau_voltage_gpio_get
;
147 engine
->pm
.voltage_set
= nouveau_voltage_gpio_set
;
148 if (dev_priv
->chipset
>= 0x84)
149 engine
->pm
.temp_get
= nv84_temp_get
;
151 engine
->pm
.temp_get
= nv40_temp_get
;
152 engine
->pm
.pwm_get
= nv50_pm_pwm_get
;
153 engine
->pm
.pwm_set
= nv50_pm_pwm_set
;
156 engine
->display
.early_init
= nv50_display_early_init
;
157 engine
->display
.late_takedown
= nv50_display_late_takedown
;
158 engine
->display
.create
= nv50_display_create
;
159 engine
->display
.destroy
= nv50_display_destroy
;
160 engine
->display
.init
= nv50_display_init
;
161 engine
->display
.fini
= nv50_display_fini
;
162 engine
->pm
.temp_get
= nv84_temp_get
;
163 engine
->pm
.clocks_get
= nvc0_pm_clocks_get
;
164 engine
->pm
.clocks_pre
= nvc0_pm_clocks_pre
;
165 engine
->pm
.clocks_set
= nvc0_pm_clocks_set
;
166 engine
->pm
.voltage_get
= nouveau_voltage_gpio_get
;
167 engine
->pm
.voltage_set
= nouveau_voltage_gpio_set
;
168 engine
->pm
.pwm_get
= nv50_pm_pwm_get
;
169 engine
->pm
.pwm_set
= nv50_pm_pwm_set
;
172 engine
->display
.early_init
= nouveau_stub_init
;
173 engine
->display
.late_takedown
= nouveau_stub_takedown
;
174 engine
->display
.create
= nvd0_display_create
;
175 engine
->display
.destroy
= nvd0_display_destroy
;
176 engine
->display
.init
= nvd0_display_init
;
177 engine
->display
.fini
= nvd0_display_fini
;
178 engine
->pm
.temp_get
= nv84_temp_get
;
179 engine
->pm
.clocks_get
= nvc0_pm_clocks_get
;
180 engine
->pm
.clocks_pre
= nvc0_pm_clocks_pre
;
181 engine
->pm
.clocks_set
= nvc0_pm_clocks_set
;
182 engine
->pm
.voltage_get
= nouveau_voltage_gpio_get
;
183 engine
->pm
.voltage_set
= nouveau_voltage_gpio_set
;
186 engine
->display
.early_init
= nouveau_stub_init
;
187 engine
->display
.late_takedown
= nouveau_stub_takedown
;
188 engine
->display
.create
= nvd0_display_create
;
189 engine
->display
.destroy
= nvd0_display_destroy
;
190 engine
->display
.init
= nvd0_display_init
;
191 engine
->display
.fini
= nvd0_display_fini
;
194 NV_ERROR(dev
, "NV%02x unsupported\n", dev_priv
->chipset
);
199 if (nouveau_modeset
== 2) {
200 engine
->display
.early_init
= nouveau_stub_init
;
201 engine
->display
.late_takedown
= nouveau_stub_takedown
;
202 engine
->display
.create
= nouveau_stub_init
;
203 engine
->display
.init
= nouveau_stub_init
;
204 engine
->display
.destroy
= nouveau_stub_takedown
;
211 nouveau_vga_set_decode(void *priv
, bool state
)
213 struct drm_device
*dev
= priv
;
214 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
216 if (dev_priv
->chipset
>= 0x40)
217 nv_wr32(dev
, 0x88054, state
);
219 nv_wr32(dev
, 0x1854, state
);
222 return VGA_RSRC_LEGACY_IO
| VGA_RSRC_LEGACY_MEM
|
223 VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
225 return VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
228 static void nouveau_switcheroo_set_state(struct pci_dev
*pdev
,
229 enum vga_switcheroo_state state
)
231 struct drm_device
*dev
= pci_get_drvdata(pdev
);
232 pm_message_t pmm
= { .event
= PM_EVENT_SUSPEND
};
233 if (state
== VGA_SWITCHEROO_ON
) {
234 printk(KERN_ERR
"VGA switcheroo: switched nouveau on\n");
235 dev
->switch_power_state
= DRM_SWITCH_POWER_CHANGING
;
236 nouveau_pci_resume(pdev
);
237 drm_kms_helper_poll_enable(dev
);
238 dev
->switch_power_state
= DRM_SWITCH_POWER_ON
;
240 printk(KERN_ERR
"VGA switcheroo: switched nouveau off\n");
241 dev
->switch_power_state
= DRM_SWITCH_POWER_CHANGING
;
242 drm_kms_helper_poll_disable(dev
);
243 nouveau_switcheroo_optimus_dsm();
244 nouveau_pci_suspend(pdev
, pmm
);
245 dev
->switch_power_state
= DRM_SWITCH_POWER_OFF
;
249 static void nouveau_switcheroo_reprobe(struct pci_dev
*pdev
)
251 struct drm_device
*dev
= pci_get_drvdata(pdev
);
252 nouveau_fbcon_output_poll_changed(dev
);
255 static bool nouveau_switcheroo_can_switch(struct pci_dev
*pdev
)
257 struct drm_device
*dev
= pci_get_drvdata(pdev
);
260 spin_lock(&dev
->count_lock
);
261 can_switch
= (dev
->open_count
== 0);
262 spin_unlock(&dev
->count_lock
);
266 static const struct vga_switcheroo_client_ops nouveau_switcheroo_ops
= {
267 .set_gpu_state
= nouveau_switcheroo_set_state
,
268 .reprobe
= nouveau_switcheroo_reprobe
,
269 .can_switch
= nouveau_switcheroo_can_switch
,
273 nouveau_card_init(struct drm_device
*dev
)
275 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
276 struct nouveau_engine
*engine
;
279 vga_client_register(dev
->pdev
, dev
, NULL
, nouveau_vga_set_decode
);
280 vga_switcheroo_register_client(dev
->pdev
, &nouveau_switcheroo_ops
);
282 /* Initialise internal driver API hooks */
283 ret
= nouveau_init_engine_ptrs(dev
);
286 engine
= &dev_priv
->engine
;
287 spin_lock_init(&dev_priv
->context_switch_lock
);
289 /* Make the CRTCs and I2C buses accessible */
290 ret
= engine
->display
.early_init(dev
);
294 /* Parse BIOS tables / Run init tables if card not POSTed */
295 ret
= nouveau_bios_init(dev
);
297 goto out_display_early
;
299 /* workaround an odd issue on nvc1 by disabling the device's
300 * nosnoop capability. hopefully won't cause issues until a
301 * better fix is found - assuming there is one...
303 if (dev_priv
->chipset
== 0xc1) {
304 nv_mask(dev
, 0x00088080, 0x00000800, 0x00000000);
307 ret
= nouveau_irq_init(dev
);
311 ret
= nouveau_display_create(dev
);
315 nouveau_backlight_init(dev
);
316 nouveau_pm_init(dev
);
318 if (dev
->mode_config
.num_crtc
) {
319 ret
= nouveau_display_init(dev
);
327 nouveau_pm_fini(dev
);
328 nouveau_backlight_exit(dev
);
329 nouveau_display_destroy(dev
);
331 nouveau_irq_fini(dev
);
333 nouveau_bios_takedown(dev
);
335 engine
->display
.late_takedown(dev
);
337 vga_switcheroo_unregister_client(dev
->pdev
);
338 vga_client_register(dev
->pdev
, NULL
, NULL
, NULL
);
342 static void nouveau_card_takedown(struct drm_device
*dev
)
344 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
345 struct nouveau_engine
*engine
= &dev_priv
->engine
;
347 if (dev
->mode_config
.num_crtc
)
348 nouveau_display_fini(dev
);
350 nouveau_pm_fini(dev
);
351 nouveau_backlight_exit(dev
);
352 nouveau_display_destroy(dev
);
354 nouveau_bios_takedown(dev
);
355 engine
->display
.late_takedown(dev
);
357 nouveau_irq_fini(dev
);
359 vga_switcheroo_unregister_client(dev
->pdev
);
360 vga_client_register(dev
->pdev
, NULL
, NULL
, NULL
);
363 /* first module load, setup the mmio/fb mapping */
364 /* KMS: we need mmio at load time, not when the first drm client opens. */
365 int nouveau_firstopen(struct drm_device
*dev
)
370 /* if we have an OF card, copy vbios to RAMIN */
371 static void nouveau_OF_copy_vbios_to_ramin(struct drm_device
*dev
)
373 #if defined(__powerpc__)
375 const uint32_t *bios
;
376 struct device_node
*dn
= pci_device_to_OF_node(dev
->pdev
);
378 NV_INFO(dev
, "Unable to get the OF node\n");
382 bios
= of_get_property(dn
, "NVDA,BMP", &size
);
384 for (i
= 0; i
< size
; i
+= 4)
385 nv_wi32(dev
, i
, bios
[i
/4]);
386 NV_INFO(dev
, "OF bios successfully copied (%d bytes)\n", size
);
388 NV_INFO(dev
, "Unable to get the OF bios\n");
393 int nouveau_load(struct drm_device
*dev
, unsigned long flags
)
395 struct drm_nouveau_private
*dev_priv
;
396 uint32_t reg0
= ~0, strap
;
399 dev_priv
= kzalloc(sizeof(*dev_priv
), GFP_KERNEL
);
404 dev_priv
->newpriv
= dev
->dev_private
;
405 dev
->dev_private
= dev_priv
;
408 NV_DEBUG(dev
, "vendor: 0x%X device: 0x%X class: 0x%X\n",
409 dev
->pci_vendor
, dev
->pci_device
, dev
->pdev
->class);
411 /* determine chipset and derive architecture from it */
412 reg0
= nv_rd32(dev
, NV03_PMC_BOOT_0
);
413 if ((reg0
& 0x0f000000) > 0) {
414 dev_priv
->chipset
= (reg0
& 0xff00000) >> 20;
415 switch (dev_priv
->chipset
& 0xf0) {
419 dev_priv
->card_type
= dev_priv
->chipset
& 0xf0;
423 dev_priv
->card_type
= NV_40
;
429 dev_priv
->card_type
= NV_50
;
432 dev_priv
->card_type
= NV_C0
;
435 dev_priv
->card_type
= NV_D0
;
438 dev_priv
->card_type
= NV_E0
;
444 if ((reg0
& 0xff00fff0) == 0x20004000) {
445 if (reg0
& 0x00f00000)
446 dev_priv
->chipset
= 0x05;
448 dev_priv
->chipset
= 0x04;
449 dev_priv
->card_type
= NV_04
;
452 if (!dev_priv
->card_type
) {
453 NV_ERROR(dev
, "unsupported chipset 0x%08x\n", reg0
);
458 NV_INFO(dev
, "Detected an NV%02x generation card (0x%08x)\n",
459 dev_priv
->card_type
, reg0
);
461 /* determine frequency of timing crystal */
462 strap
= nv_rd32(dev
, 0x101000);
463 if ( dev_priv
->chipset
< 0x17 ||
464 (dev_priv
->chipset
>= 0x20 && dev_priv
->chipset
<= 0x25))
470 case 0x00000000: dev_priv
->crystal
= 13500; break;
471 case 0x00000040: dev_priv
->crystal
= 14318; break;
472 case 0x00400000: dev_priv
->crystal
= 27000; break;
473 case 0x00400040: dev_priv
->crystal
= 25000; break;
476 NV_DEBUG(dev
, "crystal freq: %dKHz\n", dev_priv
->crystal
);
478 nouveau_OF_copy_vbios_to_ramin(dev
);
480 /* For kernel modesetting, init card now and bring up fbcon */
481 ret
= nouveau_card_init(dev
);
488 dev
->dev_private
= dev_priv
->newpriv
;
494 void nouveau_lastclose(struct drm_device
*dev
)
496 vga_switcheroo_process_delayed_switch();
499 int nouveau_unload(struct drm_device
*dev
)
501 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
503 nouveau_card_takedown(dev
);
505 dev
->dev_private
= dev_priv
->newpriv
;